Circuit configuration and circuit control method

Abstract

The application provides a circuit structure and a circuit control method, and relates to the technical field of circuits.The circuit structure comprises a first power branch, a second power branch, a load resistor and a control structure;the first power branch and the second power branch are connected in parallel, the input end of the parallelly-formed circuit is a first end, the output end of the parallelly-formed circuit is a second end, and a power resistor is arranged in the second power branch;the first end of the load resistor is connected to the output end of the parallelly-formed circuit, the second end of the load resistor is grounded, and the first power branch, the second power branch and the load resistor are electrically connected to the control structure;the control structure is used for collecting the output voltage of the second end and controlling the on-off of the first power branch and the second power branch.Through the circuit structure, the protection effect on the latch-up effect can be improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a circuit structure and circuit control method. Background Technology

[0002] Because charged particles in the space radiation environment have high energy, they can penetrate the surface of device chips and reach below the depletion layer. Therefore, charged particles in space, including heavy ions and protons, can form single-event latch-up (SEL) trigger signals in many places on the chip surface, causing the SEL phenomenon. Studies have found that for satellites in orbit, protons are the main cause of SELs.

[0003] Latch-up creates a low-impedance path between power supply (VDD) and ground (GND), triggering a large current that can cause permanent chip damage (burnout). This is a positive feedback mechanism; once triggered, the large current will continue even after external interference disappears. Latch-up can cause a sharp increase in current, a sudden drop in power supply voltage, and chip malfunction. In aerospace engineering, a power-off restart is typically used to prevent this.

[0004] In related technologies, because it is impossible to detect whether the latch-up effect has disappeared, during a power-off restart, the latch-up effect may persist, causing the power to be shut off again. This results in continuous switching of the circuit on and off, ultimately damaging the equipment and failing to provide protection. Therefore, latch-up protection methods in related technologies suffer from poor protection effectiveness. Summary of the Invention

[0005] This application provides a circuit structure and circuit control method to solve the problem of poor protection effect of latch-up protection methods.

[0006] In a first aspect, embodiments of this application provide a circuit structure, which includes: a first power branch, a second power branch, a load resistor, and a control structure; The first power branch and the second power branch are connected in parallel, and the input terminal of the parallel line is the first terminal, the output terminal of the parallel line is the second terminal, and a power resistor is provided in the second power branch; The first end of the load resistor is connected to the output end of the parallel circuit, the second end of the load resistor is grounded, and the first power branch, the second power branch and the load resistor are all electrically connected to the control structure. The control structure is used to acquire the output voltage of the second terminal, and to control the first power branch to connect and the second power branch to disconnect when the output voltage is within a preset voltage range, and to control the first power branch to disconnect and the second power branch to connect when the output voltage is not within the preset voltage range.

[0007] Optionally, the circuit structure further includes a current sampling resistor, the two ends of which are respectively connected to the power supply and the first terminal, and are electrically connected to the control structure; The control structure is also used to acquire the sampling current of the current sampling resistor, to control the first power branch to connect and the second power branch to disconnect when the sampling current is within a preset current range and the output voltage is within a preset voltage range, and to control the first power branch to disconnect and the second power branch to connect when the sampling current is not within the preset current range and the output voltage is not within the preset voltage range.

[0008] Optionally, the control structure includes a current detection circuit, a first comparator, an inverter, a second comparator, and logic gates; The current detection circuit is electrically connected to the current sampling resistor and the input terminal of the first comparator, respectively, and the current detection circuit is used to detect the sampling current. The output terminal of the first comparator is electrically connected to the input terminal of the inverter and the input terminal of the logic gate, respectively. The output terminal of the inverter is electrically connected to the input terminal of the logic gate, and the output terminal of the logic gate is electrically connected to the first power branch and the second power branch, respectively. The second comparator is electrically connected to the load resistor and the input terminal of the logic gate, respectively, and is used to detect the output voltage; The logic gate includes a first working state and a second working state; When the sampling current is within the preset current range and the output voltage is within the preset voltage range, the first signal output by the first comparator is high, the second signal output by the inverter is low, the third signal output by the second comparator is high, the first control signal output by the logic gate to the first power branch is high, and the second control signal output by the logic gate to the second power branch is low, the logic gate is in the first working state. In the second operating state, when the sampling current is not within the preset current range and the output voltage is not within the preset voltage range, the first signal is low, the second signal is high, the third signal is low, the first control signal is low, and the second control signal is high, the logic gate is in the second operating state.

[0009] Optionally, the current sampling circuit includes a first operational amplifier and a feedback resistor; The current input terminal of the current sampling resistor is connected to the positive input terminal of the first operational amplifier, and the current output terminal of the current sampling resistor is connected to the negative input terminal of the first operational amplifier. The feedback resistor is connected to the output terminal of the first operational amplifier and the negative input terminal of the first operational amplifier; The output of the first operational amplifier is connected to the first comparator.

[0010] Optionally, the current sampling circuit further includes a first branch resistor and a second branch resistor; The first branch resistor is connected between the current input terminal of the current sampling resistor and the positive input terminal of the first operational amplifier, and the second branch resistor is connected between the current output terminal of the current sampling resistor and the negative input terminal of the first operational amplifier.

[0011] Optionally, the first comparator includes a second operational amplifier and a third operational amplifier; The output terminal of the first operational amplifier is connected to the negative input terminal of the second operational amplifier, and the output terminal of the first operational amplifier is connected to the positive input terminal of the third operational amplifier; The output of the second operational amplifier is connected to the input of the logic gate; The output of the third operational amplifier is connected to the input of the logic gate.

[0012] Optionally, the first comparator further includes: a third branch resistor and a fourth branch resistor; The output terminal of the current sampling resistor is connected to the negative input terminal of the second operational amplifier through the third branch resistor, and the output terminal of the current sampling resistor is connected to the positive input terminal of the third operational amplifier through the fourth branch resistor.

[0013] Optionally, the first comparator further includes: a first protection resistor and a second protection resistor; The output of the second operational amplifier is connected to the logic gate through the first protection resistor; The output of the third operational amplifier is connected to the logic gate through the second protection resistor.

[0014] Optionally, the first power branch includes a first semiconductor field-effect transistor (MOSFET), a first transistor, a first diode, a first bias resistor, a first voltage divider resistor, and a second voltage divider resistor; The source of the first MOSFET is connected to the first terminal, and the two ends of the first diode are connected to the drain of the first MOSFET and the second terminal, respectively; the first voltage divider resistor and the second voltage divider resistor are connected in series, the gate of the first MOSFET is connected to the first voltage divider resistor, one end of the first bias resistor is connected to the first terminal, and the other end of the first bias resistor is connected between the first voltage divider resistor and the second voltage divider resistor; The second voltage divider resistor is connected to the collector of the first transistor, the emitter of the first transistor is grounded, and the base of the first transistor is connected to the control structure.

[0015] Secondly, embodiments of this application also provide a circuit control method, applied to the circuit structure described in any one of the first aspects, the circuit control method comprising: Collect the output voltage of the second terminal in the circuit structure; When the output voltage is within a preset voltage range, the first power branch is connected and the second power branch is disconnected. If the output voltage is not within the preset voltage range, the first power branch is disconnected and the second power branch is connected.

[0016] In the technical solution provided by this application, the output voltage is continuously monitored by a control structure. The magnitude of the output voltage reflects the resistance of the circuit, thereby indicating whether the latch-up effect has disappeared. If the output voltage returns to a preset voltage range when the second power branch is connected and the first power branch is disconnected, it indicates that the circuit resistance has returned to normal, meaning the latch-up effect has disappeared. At this point, the first power branch can be reconnected to the power supply, and the second power branch can be disconnected. This avoids the situation in related technologies where frequent circuit switching due to the inability to monitor whether the latch-up effect has disappeared can damage the circuit. Therefore, the circuit structure of this application has a stronger protection against the latch-up effect. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of the circuit structure provided in the embodiments of this application; Figure 2 This is a schematic diagram of the current detection circuit and the first comparator provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of the first power branch, the second power branch, and the second comparator provided in the embodiments of this application; Figure 4 This is a schematic flowchart of the circuit control method provided in the embodiments of this application.

[0019] Figure label: 1. First power branch; 2. Second power branch; 31. Current detection circuit; 32. First comparator; 33. Inverter; 34. Second comparator; 35. Logic gate; 4. Load resistor; Rs, current sampling resistor; R58, power resistor; R50, feedback resistor; U3A, first operational amplifier; U7A, second operational amplifier; U8A, third operational amplifier; R51, first branch resistor; R52, second branch resistor; R24, third branch resistor; R19, fourth branch resistor; R25, first protection resistor; R26, second protection resistor; Q14, first MOSFET; Q15, first transistor; D2, first diode; R40, first bias resistor; R41, first voltage divider resistor; R42, second voltage divider resistor. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] This application provides a circuit structure.

[0022] Please refer to Figures 1 to 4 The circuit structure includes a first power branch 1, a second power branch 2, a load resistor 4, and a control structure.

[0023] like Figure 1 As shown, the first power branch 1 and the second power branch 2 are connected in parallel, and the input terminal of the parallel circuit is the first terminal, and the output terminal of the parallel circuit is the second terminal. The first terminal is connected to the power supply, and the power supply input voltage is denoted as Vin.

[0024] like Figure 3 As shown, the difference between the second power branch 2 and the first power branch 1 is that the second power branch 2 is equipped with a power resistor R58, which serves a protective function.

[0025] The protective function of power resistor R58 is explained as follows: Under normal circuit structure conditions, the first power branch 1 is turned on and the second power branch 2 is turned off, and the current in the first power branch 1 is normal. In the event of a SEL (Self-Effect Latch-Up), the latch-up effect creates a low-impedance path between the power supply (VDD) and ground (GND). If the first power branch 1 remains conducting, the circuit may burn out due to excessive current. In the event of a SEL, if the first power branch 1 is disconnected and the second power branch 2 is conducting, the power resistor R58 in the second power branch 2 increases the circuit impedance, effectively reducing the current and preventing the circuit from burning out due to excessive current.

[0026] like Figure 1 As shown, the first end of the load resistor 4 is connected to the output end of the parallel circuit, the second end of the load resistor 4 is grounded, and the first power branch 1, the second power branch 2 and the load resistor 4 are all electrically connected to the control structure.

[0027] The control structure is used to acquire the output voltage (denoted as Vout) of the second terminal, and to control the first power branch 1 to be connected and the second power branch 2 to be disconnected when the output voltage is within a preset voltage range, and to control the first power branch 1 to be disconnected and the second power branch 2 to be connected when the output voltage is not within the preset voltage range.

[0028] The output voltage reflects the current in the circuit. When the output voltage is within the preset voltage range, it indicates that the current in the circuit is also normal. In this case, the first power branch 1 is normally connected, and the protection function of the second power branch 2 is not required; the second power branch 2 is disconnected. Conversely, when the output voltage is not within the preset voltage range, such as when a latch-up phenomenon occurs, the current in the circuit increases, and the corresponding output voltage also increases and exceeds the preset voltage range. In this case, the second power branch 2 is switched on, the first power branch 1 is disconnected, and the power resistor R58 in the second power branch 2 provides protection. It should be noted that when the output voltage is not within the preset voltage range, after switching to the second power branch 2, the output voltage will rise, but it will still not return to the preset voltage range until the latch-up effect disappears and the output voltage increases further before returning to the preset voltage range. At this point, the second power branch 2 is disconnected again, and the first power branch 1 is connected.

[0029] In addition, the logic for the change in output voltage is explained as follows: Understandably, the power supply has internal resistance. When a latch-up effect occurs in the circuit, it is equivalent to a short circuit. The current increases, which leads to an increase in voltage drop. This means that the internal resistance of the power supply diverts most of the voltage, resulting in a decrease in the output voltage. Conversely, when the external resistance of the power supply increases, the external resistance can divert more voltage, resulting in an increase in the output voltage.

[0030] In the circuit structure of this application, the output voltage is continuously monitored by a control structure. The magnitude of the output voltage reflects the resistance of the circuit, thereby indicating whether the latch-up effect has disappeared. When the second power branch 2 is connected and the first power branch 1 is disconnected, if the output voltage returns to the preset voltage range, it indicates that the circuit resistance has returned to its normal value, meaning the latch-up effect has disappeared. At this point, the first power branch 1 can be reconnected to the power supply, and the second power branch 2 can be disconnected. This avoids the situation in related technologies where frequent circuit switching due to the inability to monitor whether the latch-up effect has disappeared can damage the circuit. Therefore, the circuit structure of this application has a stronger protection against the latch-up effect.

[0031] Optionally, the circuit structure also includes a current sampling resistor Rs, the two ends of which are connected to the power supply and the first terminal, respectively, and are electrically connected to the control structure. The control structure is also used to acquire the sampling current of the current sampling resistor Rs, to control the first power branch 1 to be connected and the second power branch 2 to be disconnected when the sampling current is within a preset current range and the output voltage is within a preset voltage range, and to control the first power branch 1 to be disconnected and the second power branch 2 to be connected when the sampling current is not within a preset current range and the output voltage is not within a preset voltage range.

[0032] like Figure 1 As shown, a current sampling resistor Rs is also set between the power supply and the first terminal. The current sampling resistor Rs mainly serves two purposes: firstly, it increases the resistance in the circuit, which provides a certain degree of protection for the circuit; secondly, by detecting the current through the current sampling resistor Rs, it is equivalent to sampling the current of the entire circuit to obtain the sampled current.

[0033] By combining the sampled current and output voltage, more accurate control can be achieved over the first power branch 1 and the second power branch 2. When there is no latch-up effect in the circuit structure, and the sampled current is within the preset current range, the output voltage will also be within the preset voltage range. At this time, the control structure controls the first power branch 1 to be connected and the second power branch 2 to be disconnected. When latch-up occurs, the resistance in the circuit decreases, the sampled current increases, exceeding the preset current range, resulting in an increased voltage drop. This is equivalent to the internal resistance of the power supply diverting most of the voltage, causing the output voltage to decrease and fall below the preset voltage range. At this time, the control structure disconnects the first power branch 1 and connects the second power branch 2. The power resistor R58 in the second power branch 2 acts as a protection mechanism. Subsequently, the output voltage will increase slightly due to the effect of the power resistor R58, but it still does not return to the preset voltage range until the latch-up effect disappears and the output voltage returns to the preset voltage range. Then, the control structure connects the first power branch 1 and disconnects the second power branch 2, and the circuit structure operates normally.

[0034] In this embodiment, the on / off state of the first power branch 1 and the second power branch 2 is controlled by combining the magnitude of the sampled current. A fluctuation range of the circuit current (sampled current) (i.e., a preset current range) is set. When the sampled current is not within the preset current range, the power branch is adjusted. The method of this application realizes the linkage control of current and voltage under dual conditions. Compared with the single reference control method in related technologies, which shuts off the power supply whenever a large current occurs in the circuit, it can more comprehensively reflect the system operating status, avoid malfunctions, make the control more accurate, and ensure the stability of circuit operation.

[0035] Optionally, the control structure includes a current detection circuit 31, a first comparator 32, an inverter 33, a second comparator 34, and a logic gate 35; The current detection circuit 31 is electrically connected to the current sampling resistor Rs and the input terminal of the first comparator 32, respectively. The current detection circuit 31 is used to detect the sampling current. The output of the first comparator 32 is electrically connected to the input of the inverter 33 and the input of the logic gate 35, respectively. The output of the inverter 33 is electrically connected to the input of the logic gate 35, and the output of the logic gate 35 is electrically connected to the first power branch 1 and the second power branch 2, respectively. The second comparator 34 is electrically connected to the load resistor 4 and the input terminal of the logic gate 35 respectively. The second comparator 34 is used to detect the output voltage. Logic gate 35 includes a first operating state and a second operating state; When the sampling current is within the preset current range and the output voltage is within the preset voltage range, the first signal output by the first comparator 32 is high, the second signal output by the inverter 33 is low, the third signal output by the second comparator 34 is high, the first control signal output by the logic gate 35 to the first power branch 1 is high, and the second control signal output by the logic gate 35 to the second power branch 2 is low, the logic gate 35 is in the first working state. In the second operating state, when the sampling current is not within the preset current range and the output voltage is not within the preset voltage range, the first signal is low, the second signal is high, the third signal is low, the first control signal is low, and the second control signal is high, the logic gate 35 is in the second operating state.

[0036] like Figure 1 As shown, the detection terminal of the current detection circuit 31 is electrically connected to the current sampling resistor Rs to detect the sampling current. The signal output terminal of the current detection circuit 31 is electrically connected to the input terminal of the first comparator 32 to input the acquired signal related to the sampling current into the first comparator 32.

[0037] The output of the first comparator 32 is connected to the input of the inverter 33 to input a level signal to the inverter 33; and the output of the first comparator 32 is connected to the first input of the logic gate 35 to input a level signal from the first comparator 32 to the logic gate 35. The level signal from the first comparator 32 input to the logic gate 35 is denoted as EN1.

[0038] The output of inverter 33 is connected to the second input of logic gate 35, which is used to input the level signal of inverter 33 to logic gate 35. The level signal of inverter 33 input to logic gate 35 is denoted as EN2, and EN2 is the inverted signal of EN1.

[0039] The input terminal of the second comparator 34 is connected between the second terminal and the load resistor 4. The input terminal of the second comparator 34 is connected to the third input terminal of the logic gate 35. The second comparator 34 is used to acquire the output voltage, output a level signal according to the output voltage, and input the level signal to the logic gate 35. The level signal input from the second comparator 34 to the logic gate 35 is denoted as EN3.

[0040] The logic gate 35 includes a first output terminal and a second output terminal. The first output terminal is electrically connected to the first power branch 1 and is used to output a first control signal S1 to control the on / off state of the first power branch 1. The second output terminal is electrically connected to the second power branch 2 and is used to output a second control signal S2 to control the on / off state of the second power branch 2.

[0041] Logic gate 35 includes a first operating state and a second operating state, wherein the first operating state is: The current detection circuit 31 detects that the sampled current I is within the preset current range (Imin<I<Imax), and inputs the sampled current signal to the first comparator 32. At this time, EN1 output by the first comparator 32 is at a high level, EN2 is an inverted signal of EN1, and EN2 is at a low level; at the same time, the output voltage Vout detected by the second comparator 34 is within the preset voltage range, and EN3 output by the second comparator 34 is at a high level; the logic gate 35 receives the high-level EN1, the low-level EN2, and the high-level EN3, the logic gate 35 is in the first working state, outputs the first control signal S1 at a high level and the second control signal S2 at a low level, so as to control the first power branch 1 to be connected and the second power branch 2 to be disconnected.

[0042] The current detection circuit 31 detects that the sampled current I is not within the preset current range (I>Imax or I<Imin), and inputs the sampled current signal to the first comparator 32. At this time, EN1 output by the first comparator 32 is at a low level, EN2 is an inverted signal of EN1, and EN2 is at a high level; at the same time, the output voltage Vout detected by the second comparator 34 is not within the preset voltage range, and EN3 output by the second comparator 34 is at a low level; the logic gate 35 receives the low-level EN1, the high-level EN2, and the low-level EN3, the logic gate 35 is in the second working state, outputs the second control signal S2 at a high level and the first control signal S1 at a low level, so as to control the first power branch 1 to be disconnected and the second power branch 2 to be connected. It should be noted that when the first power branch 1 is controlled to be disconnected and the second power branch 2 to be connected, the output voltage Vout and the sampled current I will return to a safe area that ensures the circuit is not damaged, but do not return to the preset voltage range and the preset current range. In this process, the second comparator 34 continuously detects the voltage Vout. When it is detected that Vout is a normal value (indicating that the fault causing the circuit problem is resolved), EN3 changes from a low level to a high level; at this time, S1 is at a high level, S2 is at a low level, and the logic gate 35 returns to the first working state; the first power branch 1 is turned on, the second power branch 2 is disconnected, and the power supply works normally.

[0043] In the present application, the entire control structure is only composed of the current detection circuit 31, the first comparator 32, the inverter 33, the second comparator 34 and the logic gate 35, all of which are conventional analog / digital devices, no MCU or complex software logic is required, and the scheme of using pure hardware comparators and the logic gate 35 has a response time at the nanosecond to microsecond level, which is much faster than the software control scheme, and can quickly cut off or switch at the moment of fault occurrence, so as to effectively protect power devices.

[0044] Optionally, the current sampling circuit includes a first operational amplifier U3A and a feedback resistor R50; The current input terminal of the current sampling resistor Rs is connected to the positive input terminal of the first operational amplifier U3A, and the current output terminal of the current sampling resistor Rs is connected to the negative input terminal of the first operational amplifier U3A. The feedback resistor R50 is connected to the output terminal of the first operational amplifier U3A and the negative input terminal of the first operational amplifier U3A; The output of the first operational amplifier U3A is connected to the first comparator 32.

[0045] like Figure 2 As shown, the current sampling circuit includes a first operational amplifier U3A and a feedback resistor R50. The two ends of the current sampling resistor Rs are respectively connected to the two input terminals of the first operational amplifier U3A, which is used to input the sampling circuit signal into the first operational amplifier U3A, so that the first operational amplifier U3A can output the sampled current.

[0046] Feedback resistor R50 is connected to the output terminal and the negative input terminal of the first operational amplifier U3A. The feedback resistor R50 and the first operational amplifier U3A together form a negative feedback loop, which converts the current signal flowing through the current sampling resistor Rs into a voltage signal proportional to the sampling current and outputs it to the first comparator 32, realizing the linear conversion from current to voltage. The conversion ratio can be flexibly configured by adjusting the resistance value of the feedback resistor R50, thereby realizing high-precision, low-impedance detection of the load current.

[0047] The first operational amplifier U3A can be a TLC2722. Understandably, in this embodiment, the sampling current of the current sampling resistor Rs is represented by a voltage signal. The current sampling signal output by the first operational amplifier U3A is actually a voltage Vcomp. The voltage Vcomp is output as signal EN1 by the first comparator 32.

[0048] In this embodiment, by setting a feedback resistor R50, the negative feedback virtual short characteristic of the operational amplifier is used to convert the weak current signal flowing through the sampling resistor into a voltage signal with sufficient amplitude and accurate proportion. This achieves high-precision and low-noise detection of the current without affecting the normal operation of the circuit under test.

[0049] Optionally, the current sampling circuit also includes a first branch resistor R51 and a second branch resistor R52; The first branch resistor R51 is connected between the current input terminal of the current sampling resistor Rs and the positive input terminal of the first operational amplifier U3A, and the second branch resistor R52 is connected between the current output terminal of the current sampling resistor Rs and the negative input terminal of the first operational amplifier U3A.

[0050] like Figure 2As shown, the current input terminal of the current sampling resistor Rs is connected to the positive input terminal of the first operational amplifier U3A through the first branch resistor R51, and the current output terminal of the current sampling resistor Rs is connected to the negative input terminal of the first operational amplifier U3A through the second branch resistor R52. The first branch resistor R51 and the second branch resistor R52, on the one hand, limit abnormal current flow into the input terminal of the first operational amplifier U3A, protecting the operational amplifier from damage; on the other hand, they work with the parasitic capacitance at the input terminal of the operational amplifier to form a low-pass filter network, suppressing high-frequency interference and improving the stability of the current detection signal.

[0051] Through the structure of this embodiment, overcurrent protection and high-frequency noise suppression at the input of the operational amplifier are achieved without changing the basic detection function of the current sampling circuit, thereby improving the anti-interference capability and reliability of the current detection circuit 31, without the need to add any additional components.

[0052] Optionally, the first comparator 32 includes a second operational amplifier U7A and a third operational amplifier U8A; The output of the first operational amplifier U3A is connected to the negative input of the second operational amplifier U7A, and the output of the first operational amplifier U3A is connected to the positive input of the third operational amplifier U8A. The output of the second operational amplifier U7A is connected to the input of logic gate 35; The output of the third operational amplifier U8A is connected to the input of logic gate 35.

[0053] like Figure 2 As shown, in this embodiment, the first comparator 32 includes a second operational amplifier U7A and a third operational amplifier U8A. The negative input of the second operational amplifier U7A is connected to the output of the first operational amplifier U3A, and the positive input of the second operational amplifier U7A is connected to the first reference voltage (the voltage corresponding to the lower threshold current of the preset current range). The positive input of the third operational amplifier U8A is connected to the output of the first operational amplifier U3A, and the negative input of the third operational amplifier U8A is connected to the reference voltage (the voltage corresponding to the upper threshold current of the preset current range). The second operational amplifier U7A and the third operational amplifier U8A compare the output voltage of the first operational amplifier U3A with different reference voltages, and output EN1, which reflects whether the sampled current is within the preset current range.

[0054] Among them, the second operational amplifier U7A and the third operational amplifier U8A can be LM2900.

[0055] In this embodiment, a window comparator structure is constructed by setting the second and third operational amplifiers U8A. It can not only detect whether the current exceeds the limit, but also monitor the lower limit of the current simultaneously. Compared with a single threshold comparison scheme, it can more accurately define the effective operating range of the sampled current, avoiding misjudging current signals in edge states as abnormal, and ensuring the accuracy of control decisions.

[0056] Optionally, the first comparator 32 further includes: a third branch resistor R24 ​​and a fourth branch resistor R19; The output of the current sampling resistor Rs is connected to the negative input of the second operational amplifier U7A through the third branch resistor R24, and the output of the current sampling resistor Rs is connected to the positive input of the third operational amplifier U8A through the fourth branch resistor R19.

[0057] like Figure 2 As shown, in this embodiment, the third branch resistor R24 ​​is connected between the output terminal of the current sampling resistor Rs and the negative input terminal of the second operational amplifier U7A, and the fourth branch resistor R19 is connected between the output terminal of the current sampling resistor Rs and the positive input terminal of the third operational amplifier U8A. The third branch resistor R24 ​​and the fourth branch resistor R19 serve the same purpose: to limit the current flowing into the input terminals of the comparators (second and third operational amplifiers U8A) when abnormalities occur in the circuit (such as voltage spikes or power fluctuations), preventing the internal electrostatic protection diodes of the operational amplifiers from being damaged, thus protecting the comparator circuit from damage and improving the reliability of the circuit.

[0058] Optionally, the first comparator 32 further includes: a first protection resistor R25 and a second protection resistor R26; The output of the second operational amplifier U7A is connected to logic gate 35 through the first protection resistor R25; The output of the third operational amplifier U8A is connected to logic gate 35 through the second protection resistor R26.

[0059] like Figure 2 As shown, in this embodiment, the first protection resistor R25 is connected between the output of the second operational amplifier U7A and the logic gate 35, and the second protection resistor R26 is connected between the output of the third operational amplifier U8A and the logic gate 35. If a fault occurs inside the logic gate 35, or if an abnormal voltage occurs at the input (e.g., electrostatic discharge, ESD), a large current may be momentarily absorbed at the input of the logic gate 35. In this case, the first protection resistor R25 and the second protection resistor R26 act as current limiters, preventing excessive current from flowing out of the operational amplifier, thereby protecting the operational amplifier from burnout or damage and further improving the reliability of the circuit.

[0060] Optionally, the first power branch 1 includes a first semiconductor field-effect transistor (MOSFET), a first transistor Q15, a first diode D2, a first bias resistor R40, a first voltage divider resistor R41, and a second voltage divider resistor R42. The source of the first MOSFET Q14 is connected to the first terminal, and the two ends of the first diode D2 are connected to the drain and the second terminal of the first MOSFET Q14, respectively. The first voltage divider resistor R41 and the second voltage divider resistor R42 are connected in series. The gate of the first MOSFET Q14 is connected to the first voltage divider resistor R41. One end of the first bias resistor R40 is connected to the first terminal, and the other end of the first bias resistor R40 is connected between the first voltage divider resistor R41 and the second voltage divider resistor R42. The second voltage divider resistor R42 is connected to the collector of the first transistor Q15, the emitter of the first transistor Q15 is grounded, and the base of the first transistor Q15 is connected to the control structure.

[0061] like Figure 3 As shown, the first power switch receives S1. Under normal circuit operation, S1 is at a high level, the first transistor Q15 is turned on, and the gate of the first MOSFET Q14 is pulled to a low potential, so that the first MOSFET Q14 is turned on and the current flows from Vin to Vout.

[0062] When a latch-up effect occurs in the circuit structure, S1 is at a low level, the first transistor Q15 is cut off, the first MOSFET Q14 is pulled up by the first bias resistor R40, and the first MOSFET Q14 is turned off.

[0063] Among them, the first voltage divider resistor R41 and the second voltage divider resistor R42 play the roles of current limiting and gate protection. The pull-down speed of the first transistor Q15 to the gate of the first MOSFET Q14 can be adjusted by adjusting the size of the first voltage divider resistor R41 and the second voltage divider resistor R42.

[0064] The first diode D2 is used to prevent reverse current from flowing between Vout and Vin, thus providing protection.

[0065] It should be noted that, as Figure 3 As shown, the structure of the second power branch 2 is similar to that of the first power branch 1. The difference is that the second power branch 2 also includes a power resistor R58, which is connected between the first diode D2 and the second terminal.

[0066] This application also provides a circuit control method, applied to... Figures 1-3 In the circuit structure, such as Figure 4 As shown, the circuit control method includes the following steps: Step 101: Acquire the output voltage of the second terminal in the circuit structure; Step 102: When the output voltage is within a preset voltage range, control the first power branch to connect and the second power branch to disconnect. Step 103: If the output voltage is not within the preset voltage range, control the first power branch to disconnect and the second power branch to connect.

[0067] In this embodiment, the magnitude of the acquired output voltage reflects the resistance of the circuit, thereby indicating whether the latch-up effect has disappeared. If the output voltage returns to a preset voltage range when the second power branch is connected and the first power branch is disconnected, it indicates that the circuit resistance has returned to its normal value, meaning the latch-up effect has disappeared. At this point, the first power branch can be reconnected to the power supply, and the second power branch can be disconnected. This avoids the situation in related technologies where frequent circuit switching due to the inability to monitor the disappearance of the latch-up effect can damage the circuit. Furthermore, in this embodiment, software logic is used to control the on / off state of the first and second power branches, improving control accuracy.

[0068] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit structure, characterized in that, The circuit structure includes: a first power branch, a second power branch, a load resistor, and a control structure; The first power branch and the second power branch are connected in parallel, and the input terminal of the parallel line is the first terminal, the output terminal of the parallel line is the second terminal, and a power resistor is provided in the second power branch; The first end of the load resistor is connected to the output end of the parallel circuit, the second end of the load resistor is grounded, and the first power branch, the second power branch and the load resistor are all electrically connected to the control structure. The control structure is used to acquire the output voltage of the second terminal, and to control the first power branch to connect and the second power branch to disconnect when the output voltage is within a preset voltage range, and to control the first power branch to disconnect and the second power branch to connect when the output voltage is not within the preset voltage range.

2. The circuit structure according to claim 1, characterized in that, The circuit structure further includes a current sampling resistor, the two ends of which are respectively connected to the power supply and the first end, and are electrically connected to the control structure. The control structure is also used to acquire the sampling current of the current sampling resistor, to control the first power branch to connect and the second power branch to disconnect when the sampling current is within a preset current range and the output voltage is within a preset voltage range, and to control the first power branch to disconnect and the second power branch to connect when the sampling current is not within the preset current range and the output voltage is not within the preset voltage range.

3. The circuit structure according to claim 2, characterized in that, The control structure includes a current detection circuit, a first comparator, an inverter, a second comparator, and logic gates; The current detection circuit is electrically connected to the current sampling resistor and the input terminal of the first comparator, respectively, and the current detection circuit is used to detect the sampling current. The output terminal of the first comparator is electrically connected to the input terminal of the inverter and the input terminal of the logic gate, respectively. The output terminal of the inverter is electrically connected to the input terminal of the logic gate, and the output terminal of the logic gate is electrically connected to the first power branch and the second power branch, respectively. The second comparator is electrically connected to the load resistor and the input terminal of the logic gate, respectively, and is used to detect the output voltage; The logic gate includes a first working state and a second working state; When the sampling current is within the preset current range and the output voltage is within the preset voltage range, the first signal output by the first comparator is high, the second signal output by the inverter is low, the third signal output by the second comparator is high, the first control signal output by the logic gate to the first power branch is high, and the second control signal output by the logic gate to the second power branch is low, the logic gate is in the first working state. In the second operating state, when the sampling current is not within the preset current range and the output voltage is not within the preset voltage range, the first signal is low, the second signal is high, the third signal is low, the first control signal is low, and the second control signal is high, the logic gate is in the second operating state.

4. The circuit structure according to claim 3, characterized in that, The current sampling circuit includes a first operational amplifier and a feedback resistor; The current input terminal of the current sampling resistor is connected to the positive input terminal of the first operational amplifier, and the current output terminal of the current sampling resistor is connected to the negative input terminal of the first operational amplifier. The feedback resistor is connected to the output terminal of the first operational amplifier and the negative input terminal of the first operational amplifier; The output of the first operational amplifier is connected to the first comparator.

5. The circuit structure according to claim 4, characterized in that, The current sampling circuit also includes a first branch resistor and a second branch resistor. The first branch resistor is connected between the current input terminal of the current sampling resistor and the positive input terminal of the first operational amplifier, and the second branch resistor is connected between the current output terminal of the current sampling resistor and the negative input terminal of the first operational amplifier.

6. The circuit structure according to claim 3, characterized in that, The first comparator includes a second operational amplifier and a third operational amplifier; The output terminal of the first operational amplifier is connected to the negative input terminal of the second operational amplifier, and the output terminal of the first operational amplifier is connected to the positive input terminal of the third operational amplifier; The output of the second operational amplifier is connected to the input of the logic gate; The output of the third operational amplifier is connected to the input of the logic gate.

7. The circuit structure according to claim 6, characterized in that, The first comparator further includes: a third branch resistor and a fourth branch resistor; The output terminal of the current sampling resistor is connected to the negative input terminal of the second operational amplifier through the third branch resistor, and the output terminal of the current sampling resistor is connected to the positive input terminal of the third operational amplifier through the fourth branch resistor.

8. The circuit structure according to claim 6, characterized in that, The first comparator further includes: a first protection resistor and a second protection resistor; The output of the second operational amplifier is connected to the logic gate through the first protection resistor; The output of the third operational amplifier is connected to the logic gate through the second protection resistor.

9. The circuit structure according to any one of claims 1 to 8, characterized in that, The first power branch includes a first semiconductor field-effect transistor (MOSFET), a first transistor, a first diode, a first bias resistor, a first voltage divider resistor, and a second voltage divider resistor; The source of the first MOSFET is connected to the first terminal, and the two ends of the first diode are connected to the drain of the first MOSFET and the second terminal, respectively; the first voltage divider resistor and the second voltage divider resistor are connected in series, the gate of the first MOSFET is connected to the first voltage divider resistor, one end of the first bias resistor is connected to the first terminal, and the other end of the first bias resistor is connected between the first voltage divider resistor and the second voltage divider resistor; The second voltage divider resistor is connected to the collector of the first transistor, the emitter of the first transistor is grounded, and the base of the first transistor is connected to the control structure.

10. A circuit control method, characterized in that, The method, applied to the circuit structure of any one of claims 1 to 9, comprises: Collect the output voltage of the second terminal in the circuit structure; When the output voltage is within a preset voltage range, the first power branch is connected and the second power branch is disconnected. If the output voltage is not within the preset voltage range, the first power branch is disconnected and the second power branch is connected.

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