A jfet mosfet hybrid half bridge power module

Abstract

The application provides a JFET MOSFET hybrid half-bridge power module, and relates to the technical field of power semiconductor packaging, which comprises a copper-clad ceramic substrate, a patterned copper layer of which comprises a positive copper area, a midpoint copper area, an upper source copper area and a negative sink copper area. The positive copper area is provided with a plurality of SiC MOSFET chips; the midpoint copper area is provided with a plurality of SiC JFET chips and SiC Schottky barrier diode chips; and the upper source copper area is connected to the midpoint copper area through a plurality of jumper bonding wires. The midpoint copper area comprises an upper bearing area, a lower bearing area and a communication part, and the negative sink copper area and the lower gate copper area respectively extend to the interval region between the two bearing areas. The module is beneficial to reducing the detour and intersection of the lower bridge arm power connection and the gate connection, and improving the regularity of the internal interconnection layout.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor packaging technology, and more particularly to a JFET MOSFET hybrid half-bridge power module. Background Technology

[0002] JFET / MOSFET hybrid half-bridge power modules can be applied to power conversion scenarios such as electric drive systems for new energy vehicles, energy storage converters, photovoltaic inverters, and industrial power supplies. These power modules typically use MOSFETs in the upper bridge arm and JFETs and freewheeling diodes in the lower bridge arm to meet the power conversion requirements under high voltage, high frequency, and high current conditions. To improve the module's current carrying capacity, the power devices in the bridge arm are usually arranged in parallel using multiple chips, and the corresponding power and control connections are formed through patterned copper layers, bonding wires, and lead-out structures on a copper-clad ceramic substrate.

[0003] In a JFET / MOSFET hybrid half-bridge, the lower bridge arm simultaneously houses the JFET chip, the freewheeling diode chip, and the gate control connection structure of the JFET. The power and control connection requirements of these different chips are concentrated in a limited substrate area. When arranging chips and copper layers in existing modules, if the relative positions of the power connection area and the gate control connection area of ​​the lower bridge arm are not considered, local bonding wires may become circuitous, intersecting, or concentrated, leading to mutual interference between power and control connections. This is detrimental to the compact arrangement of the internal interconnect structure and operational stability of the module.

[0004] Therefore, how to rationally arrange the power chip, freewheeling device and corresponding copper layer connection area for the lower bridge arm structure of JFET MOSFET hybrid half-bridge in order to improve the interconnection organization inside the lower bridge arm has become a technical problem that needs to be solved in this field. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, the technical problem to be solved by this invention is to propose a JFETMOSFET hybrid half-bridge power module, which adopts the following technical solution: This invention provides a JFET MOSFET hybrid half-bridge power module, including a copper-clad ceramic substrate, wherein the patterned copper layer of the copper-clad ceramic substrate includes a positive copper region, a midpoint copper region, an upper source copper region, and a negative sink copper region. Multiple normally-off SiC MOSFET chips are disposed on the aforementioned positive copper region. The drain of each SiC MOSFET chip is electrically connected to the aforementioned positive copper region, and the source is electrically connected to the aforementioned upper source copper region. Multiple normally-connected SiC JFET chips and multiple SiC Schottky barrier diode chips are disposed on the aforementioned midpoint copper region. The drain of each of the aforementioned SiC JFET chips and the cathode of each of the aforementioned SiC Schottky barrier diode chips are electrically connected to the aforementioned midpoint copper region. The source of each of the above-mentioned SiC JFET chips and the anode of each of the above-mentioned SiC Schottky barrier diode chips are electrically connected to the above-mentioned negative copper sink region. The aforementioned source copper region and the aforementioned midpoint copper region are electrically connected by multiple bridging bonding wires so that the aforementioned source copper region and the midpoint copper region together form an AC output node.

[0006] In the above technical solution, the positive copper region, upper source copper region, midpoint copper region, and negative sink copper region correspond to different power nodes in the hybrid half-bridge. Multiple SiC MOSFET chips are disposed on the positive copper region, allowing their drains to be connected via the positive copper region. Multiple SiC JFET chips and multiple SiC Schottky barrier diode chips are jointly disposed on the midpoint copper region, allowing the drains of the SiC JFET chips and the cathodes of the SiC Schottky barrier diode chips to be connected to the AC output node on the chip carrier side. The sources of the SiC JFET chips and the anodes of the SiC Schottky barrier diode chips are connected via the negative sink copper region. The upper source copper region is electrically connected to the midpoint copper region via multiple bridging bonding wires, allowing the source side of the upper bridge arm SiC MOSFET chip to be connected to the AC output node. By using the copper area allocation and chip connection relationship described above, the upper bridge arm MOSFET, lower bridge arm JFET and freewheeling diode can be laid out according to the corresponding electrical nodes, reducing cross wiring between different power nodes, and forming a more concentrated connection structure between the lower bridge arm switching branch and the freewheeling branch on the AC output node side, which is beneficial to improving the interconnection organization relationship inside the module.

[0007] As a further improvement, the number of the aforementioned SiC MOSFET chips is four, the number of the aforementioned SiC JFET chips is four, and the number of the aforementioned SiC Schottky barrier diode chips is four.

[0008] In the above technical solution, by setting four SiC MOSFET chips, four SiC JFET chips, and four SiC Schottky barrier diode chips respectively, multiple chips can jointly bear the current path of the corresponding bridge arm, and provide a basis for the partitioned arrangement between different chip groups. This quantity setting is a specific setting method for adapting the power level and internal space of the module in this embodiment, which is conducive to achieving a balance between current carrying requirements, chip placement space, and internal connection structure.

[0009] As a further improvement, the four SiC MOSFET chips mentioned above are arranged in two rows and two columns along two intersecting directions.

[0010] In the above technical solution, four SiC MOSFET chips are arranged in two rows and two columns, forming a relatively concentrated chip array on the positive copper region. This arrangement facilitates the connection of the source terminals of each SiC MOSFET chip towards the upper source copper region. This layout helps to reduce the occupied area of ​​the upper bridge arm chip group and reserves space for multiple bridging bonding connection positions between the upper source copper region and the midpoint copper region.

[0011] As a further improvement, the aforementioned midpoint copper region includes an upper bearing region, a lower bearing region, and a connecting portion connecting the upper bearing region and the lower bearing region. An interval region is formed between the upper bearing region and the lower bearing region except for the connecting portion. Two SiC Schottky barrier diode chips are disposed on the upper side of the upper bearing region and two SiC JFET chips are disposed on the lower side. Two SiC JFET chips are disposed on the upper side of the lower bearing region and two SiC Schottky barrier diode chips are disposed on the lower side.

[0012] In the above technical solution, both the upper and lower carrier regions are used to support SiC JFET chips and SiC Schottky barrier diode chips, and are electrically connected through a connecting portion, so that the drain of each SiC JFET chip and the cathode of each SiC Schottky barrier diode chip are connected to the midpoint copper region. In the upper carrier region, the SiC Schottky barrier diode chip is located on the upper side and the SiC JFET chip is located on the lower side, and in the lower carrier region, the SiC JFET chip is located on the upper side and the SiC Schottky barrier diode chip is located on the lower side, thus forming a symmetrical arrangement with corresponding upper and lower sides. This arrangement allows the upper and lower sets of SiC JFET chips and SiC Schottky barrier diode chips to be arranged adjacent to the corresponding negative sink connection region and gate connection region, respectively, so that the bonding line lengths from each chip to the corresponding copper region tend to be similar, which helps to reduce the differences in local connection paths and parasitic parameters between different parallel chips, and improves the regularity of the internal connection structure of the lower bridge arm.

[0013] As a further improvement, the aforementioned negative copper region includes a middle extension, an upper extension, and a lower extension. The middle extension is located within the aforementioned interval region. The upper extension extends to the side of the upper bearing region opposite to the lower bearing region, and the lower extension extends to the side of the lower bearing region opposite to the upper bearing region. The middle extension, the upper extension, and the lower extension are interconnected. The aforementioned patterned copper layer also includes a lower gate copper region, which is located within the aforementioned interval region and is insulated from the aforementioned middle extension.

[0014] In the above technical solution, the upper, middle, and lower extensions of the negative copper sink region extend to the outer side of the upper carrier region, between the upper and lower carrier regions, and the outer side of the lower carrier region, respectively. This allows the source of the SiC JFET chip and the anode of the SiC Schottky barrier diode chip, located at different positions, to connect to the adjacent negative copper sink region. Simultaneously, the lower gate copper region is disposed within the gap between the upper and lower carrier regions and is insulated from the middle extension, spatially partitioning the JFET gate connection region with the negative copper sink connection regions corresponding to the JFET source and SBD anode. This reduces the likelihood of power bonding connections and gate bonding connections circling around the chipset periphery and lowers the risk of crossover, overlap, or concentrated arrangement of different bonding lines.

[0015] As a further improvement, the lower gate copper region is electrically connected to the gate of the SiCJFET chip located in the upper and lower carrier regions, respectively.

[0016] In the above technical solution, the lower gate copper region is electrically connected to the gates of the SiC JFET chips in both the upper and lower carrier regions, enabling multiple SiC JFET chips to receive gate control signals through the same independent copper region. Since the lower gate copper region is located between the two carrier regions, its connection distance to the upper and lower groups of SiC JFET chips is short, which helps reduce the detour of the gate connection path and keeps the gate control connection separate from the power connection formed by the negative sink copper region.

[0017] As a further improvement, the first ends of the plurality of the aforementioned bridging bonding wires are respectively connected to at least two spaced connection positions in the aforementioned source copper region, and the second ends of the plurality of the aforementioned bridging bonding wires are respectively connected to at least two spaced connection positions in the aforementioned midpoint copper region.

[0018] In the above technical solution, multiple bridging bonding lines are connected at different locations between the upper source copper region and the midpoint copper region, allowing the sources of multiple SiC MOSFET chips to be connected to the midpoint copper region from multiple locations after converging through the upper source copper region. Compared to a method that only bridging connections at a single location, this structure helps avoid excessive concentration of connections between the upper source copper region and the midpoint copper region, and improves the consistency of connection paths from different SiC MOSFET chips to the AC output node.

[0019] Further improvements include a heat dissipation substrate and a package housing; the copper-clad ceramic substrate includes a ceramic insulating layer, a patterned copper layer on the upper side of the ceramic insulating layer, and a bottom copper layer on the lower side of the ceramic insulating layer, the bottom copper layer being bonded to the heat dissipation substrate; the package housing and the heat dissipation substrate cooperate to form a package cavity, and the copper-clad ceramic substrate, SiC MOSFET chip, SiC JFET chip, and SiC Schottky barrier diode chip are all disposed in the package cavity.

[0020] In the above technical solution, the copper-clad ceramic substrate achieves electrical isolation between different copper areas through a ceramic insulating layer, and is bonded to the heat dissipation substrate through a bottom copper layer, providing a path for heat transfer downwards for each power chip. The package shell and the heat dissipation substrate cooperate to form a package cavity, which can encapsulate and protect the copper-clad ceramic substrate, power chips, and internal bonding connections, thereby improving the stability and applicability of the module's internal structure. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the overall structure of the present invention; Figure 2 This is a schematic diagram of the copper layer layout structure of the present invention; Figure 3 This is a schematic diagram of the layout structure of the copper sink area and the negative copper sink area in this invention; Figure 4 This is the circuit topology diagram of the present invention.

[0023] Figure label: 1-Copper-clad ceramic substrate; 2-Positive copper region; 3-Midpoint copper region; 4-Upper source copper region; 5-Negative sink copper region; 6-Lower gate copper region; 7-SiC MOSFET chip; 8-SiC JFET chip; 9-SiC Schottky barrier diode chip; 31-Upper bearing area; 32-Lower bearing area; 33-Connecting part; 34-Interval area. Detailed Implementation

[0024] To facilitate understanding by those skilled in the art, the structure of the present invention will now be described in further detail with reference to the accompanying drawings: The present invention will be further described below with reference to specific embodiments. It should be understood that the following embodiments are used to illustrate the technical solutions of the present invention, so that those skilled in the art can understand and implement the present invention. The number, size, shape, relative position and connection method of each component can be adjusted according to the module's rated voltage, rated current, chip specifications, package size and application scenario. As long as the corresponding electrical connection relationship and layout relationship can be achieved, they can all be used as implementation methods of the present invention.

[0025] like Figures 1-4As shown, this invention provides a JFET / MOSFET hybrid half-bridge power module. This power module is used to construct a half-bridge power conversion unit and can be applied in new energy vehicle drives, energy storage converters, photovoltaic inverters, industrial power supplies, and other power conversion equipment. The power module includes a copper-clad ceramic substrate 1, multiple power chips disposed on the copper-clad ceramic substrate 1, a heat dissipation substrate, and a package housing. The copper-clad ceramic substrate 1 supports the power chips and forms the internal electrical connection paths of the module. The heat dissipation substrate absorbs the heat generated by the power chips during operation and conducts heat. The package housing encapsulates and protects the copper-clad ceramic substrate 1, the power chips, and the internal connection structures.

[0026] The copper-clad ceramic substrate 1 includes a ceramic insulating layer, a patterned copper layer disposed on the upper side of the ceramic insulating layer, and a bottom copper layer disposed on the lower side of the ceramic insulating layer. The ceramic insulating layer can be made of aluminum nitride ceramic, silicon nitride ceramic, alumina ceramic, or other insulating and thermally conductive materials suitable for power modules. The patterned copper layer forms multiple mutually insulated copper regions by dividing the upper copper layer, with different copper regions undertaking the connection functions of different power nodes or control nodes. The bottom copper layer is attached to the heat dissipation substrate, allowing the heat generated by the power chip to be transferred to the heat dissipation substrate through the back of the chip, the patterned copper layer, the ceramic insulating layer, and the bottom copper layer.

[0027] like Figures 1-2 As shown, in this embodiment, the patterned copper layer includes a positive copper region 2, a midpoint copper region 3, an upper source copper region 4, and a negative sink copper region 5. Electrical insulation intervals are maintained between the positive copper region 2, the midpoint copper region 3, the upper source copper region 4, and the negative sink copper region 5 to prevent unintended conduction between different power nodes. The positive copper region 2 is used to connect the drain side of the upper bridge arm SiC MOSFET chip 7, the midpoint copper region 3 is used to form the AC output node of the half-bridge, the negative sink copper region 5 is used to connect the source side of the lower bridge arm SiC JFET chip 8 and the anode side of the SiC Schottky barrier diode chip 9, and the upper source copper region 4 is used to collect the source side of the SiC MOSFET chip 7.

[0028] The above structure is formed and realized as follows Figure 4 The circuit topology shown is a hybrid half-bridge power circuit, in which SiC MOSFET chip 7 forms the upper bridge arm, SiC JFET chip 8 forms the lower bridge arm switching branch, and SiC Schottky barrier diode chip 9 forms the freewheeling branch connected in parallel with the lower bridge arm switching branch. Specifically, positive copper region 2 corresponds to the positive DC side node, upper source copper region 4 and midpoint copper region 3 correspond to the AC output node, and negative sink copper region 5 corresponds to the negative DC side node.

[0029] like Figure 2As shown, multiple normally-off SiC MOSFET chips 7 are disposed on the positive copper region 2. In this embodiment, the SiC MOSFET chip 7 adopts a back-drain structure, with the back drain connected to the positive copper region 2 via a conductive connection layer. Source and gate pads are formed on the front side of the chip. The conductive connection layer can be a sintered silver layer, a solder layer, or other conductive connection materials suitable for chip mounting. The drains of multiple SiC MOSFET chips 7 are connected to the positive copper region 2, enabling the multiple SiC MOSFET chips 7 to be connected in parallel to form an upper bridge arm switching unit. The source of each SiC MOSFET chip 7 is connected to the upper source copper region 4 via bonding wires or other conductive connection structures. The upper source copper region 4 is used to collect the source currents of the multiple SiC MOSFET chips 7.

[0030] In this embodiment, there are four SiC MOSFET chips 7. The four SiC MOSFET chips 7 are arranged in a two-row, two-column array along two intersecting directions and are concentrated on one side of the copper-clad ceramic substrate 1. The two intersecting directions can be the vertical and horizontal directions from a top-down view of the module. The two-row, two-column array arrangement of the four SiC MOSFET chips 7 allows each chip to form a relatively compact upper bridge arm chip group on the positive copper region 2, and enables the chip source pads to be distributed towards the upper source copper region 4. The upper source copper region 4 is located in the adjacent area of ​​the SiC MOSFET chip group 7, allowing the source of each SiC MOSFET chip 7 to be connected to the upper source copper region 4 via a shorter bonding path.

[0031] like Figure 2 As shown, the upper source copper region 4 and the midpoint copper region 3 are electrically connected by multiple bridging bonding wires. One end of each bridging bonding wire is connected to the upper source copper region 4, and the other end is connected to the midpoint copper region 3, so that the upper source copper region 4 and the midpoint copper region 3 together constitute the AC output node. The AC output node is connected to the source side of the upper bridge arm SiC MOSFET chip 7, and also to the drain side of the lower bridge arm SiC JFET chip 8 and the cathode side of the SiC Schottky barrier diode chip 9, thereby forming the midpoint of the bridge arm in the hybrid half-bridge.

[0032] In one specific embodiment, the first ends of multiple bridging bonding wires are connected to at least two spaced-apart connection positions in the upper source copper region 4, and the second ends of the multiple bridging bonding wires are connected to at least two spaced-apart connection positions in the midpoint copper region 3. The upper source copper region 4 can extend along the edge direction of the SiC MOSFET chip group 7, and the midpoint copper region 3 has multiple bonding points set at positions opposite to the upper source copper region 4, so that multiple groups of bridging bonding wires can form connections at different positions. After the multiple bridging bonding wires are distributed, the source currents of multiple SiC MOSFET chips 7 can be collected through the upper source copper region 4 and then connected to the midpoint copper region 3 from multiple positions, which helps to avoid the connection between the upper source copper region 4 and the midpoint copper region 3 being concentrated in a single local area. The local connection paths from different SiC MOSFET chips 7 to the AC output node also tend to be close, which helps to reduce the connection path differences between the parallel SiC MOSFET chips 7.

[0033] like Figures 2-3 As shown, multiple normally-conducting SiC JFET chips 8 and multiple SiC Schottky barrier diode chips 9 are disposed on the midpoint copper region 3. The SiC JFET chip 8 adopts a back-drain structure, with its back drain connected to the midpoint copper region 3, and source and gate pads formed on the front side of the chip. The cathode side of the SiC Schottky barrier diode chip 9 is connected to the midpoint copper region 3, and its anode side is led out through the front electrode. By connecting the drain of the SiC JFET chip 8 and the cathode of the SiC Schottky barrier diode chip 9 to the midpoint copper region 3, the lower bridge arm switching branch and the freewheeling branch converge to the same AC output node at the midpoint side.

[0034] like Figure 3 As shown, in this embodiment, there are four SiC JFET chips 8 and four SiC Schottky barrier diode chips 9. All four SiC JFET chips 8 and four SiC Schottky barrier diode chips 9 are mounted on the midpoint copper region 3. The midpoint copper region 3 forms a continuous conductive area, allowing the drains of each SiC JFET chip 8 and the cathodes of each SiC Schottky barrier diode chip 9 to be directly connected on the back side of the chip. By having the midpoint copper region 3 jointly support the SiC JFET chips 8 and SiC Schottky barrier diode chips 9, the need for separate connection structures between the lower bridge arm switching branch and the freewheeling branch on the AC output node side can be reduced, keeping the midpoint connection area compact.

[0035] like Figure 3As shown, the midpoint copper region 3 includes an upper carrier region 31, a lower carrier region 32, and a connecting portion 33 connecting the upper carrier region 31 and the lower carrier region 32. Both the upper carrier region 31 and the lower carrier region 32 are used to carry the SiC JFET chip 8 and the SiC Schottky barrier diode chip 9. The connecting portion 33 connects the upper carrier region 31 and the lower carrier region 32, making the upper carrier region 31 and the lower carrier region 32 constitute the same midpoint copper region 3. A gap region 34 is formed between the upper carrier region 31 and the lower carrier region 32, excluding the connecting portion 33. The gap region 34 can be used to arrange the intermediate extension of the negative sink copper region 5, the lower gate copper region 6, and the corresponding bonding connection areas.

[0036] In this embodiment, two SiC Schottky barrier diode chips 9 are disposed on the upper side of the upper carrier region 31, and two SiC JFET chips 8 are disposed on the lower side of the upper carrier region 31. The two SiC Schottky barrier diode chips 9 are arranged side by side in the left-right direction, and the two SiC JFET chips 8 are also arranged side by side in the left-right direction. Two SiC JFET chips 8 are disposed on the upper side of the lower carrier region 32, and two SiC Schottky barrier diode chips 9 are disposed on the lower side of the lower carrier region 32. The two SiC JFET chips 8 in the lower carrier region 32 are arranged side by side in the left-right direction, and the two SiC Schottky barrier diode chips 9 in the lower carrier region 32 are also arranged side by side in the left-right direction.

[0037] like Figure 3 As shown, the chips in the upper carrier region 31 and the lower carrier region 32 are arranged in an inverted configuration, corresponding vertically. In the upper carrier region 31, the SiC Schottky barrier diode chip 9 is located near the upper side of the module, and the SiC JFET chip 8 is located near the spacing region 34. In the lower carrier region 32, the SiC JFET chip 8 is located near the spacing region 34, and the SiC Schottky barrier diode chip 9 is located near the lower side of the module. This arrangement ensures that the two sets of SiC JFET chips 8 and SiC Schottky barrier diode chips 9 are distributed towards the spacing region 34 and their corresponding outer regions, allowing the source, anode, and gate connections of each chip to be positioned close together.

[0038] like Figure 2 As shown, the negative copper sink region 5 is used to connect the source of the SiC JFET chip 8 and the anode of the SiC Schottky barrier diode chip 9. The source of each SiC JFET chip 8 is connected to the negative copper sink region 5 via bonding wires, and the anode of each SiC Schottky barrier diode chip 9 is also connected to the negative copper sink region 5 via bonding wires. The negative copper sink region 5 forms the negative-side bus region of the lower bridge arm, allowing the other electrodes of the SiC JFET chip 8 and the SiC Schottky barrier diode chip 9, other than the midpoint side, to be connected to the negative-side power node.

[0039] like Figures 2-3As shown, the negative copper sink region 5 includes a middle extension, an upper extension, and a lower extension. The middle extension is located within the interval region 34 between the upper bearing region 31 and the lower bearing region 32. The upper extension extends to the side of the upper bearing region 31 opposite to the lower bearing region 32, and the lower extension extends to the side of the lower bearing region 32 opposite to the upper bearing region 31. The middle extension, the upper extension, and the lower extension are interconnected, forming a continuous negative copper sink region 5.

[0040] like Figure 3 As shown, the upper extension is located outside the upper carrier region 31 and can serve as a proximity connection region between the anode of the SiC Schottky barrier diode chip 9 and the source of the SiC JFET chip 8 in the upper carrier region 31. The middle extension is located between the upper carrier region 31 and the lower carrier region 32 and can provide a negative-side connection point for the SiC JFET chip 8 near the spacing region 34. The lower extension is located outside the lower carrier region 32 and can serve as a proximity connection region between the anode of the SiC Schottky barrier diode chip 9 and the source of the SiC JFET chip 8 in the lower carrier region 32. By extending the negative copper sink region 5 to the outside of the upper carrier region 31, between the upper carrier region 31 and the lower carrier region 32, and outside the lower carrier region 32, the sources of the SiC JFET chip 8 and the anodes of the SiC Schottky barrier diode chip 9 at different locations can be bonded to the closer negative copper sink region 5.

[0041] In practical implementation, the bonding wires between the source of the SiC JFET chip 8 and the negative copper sink region 5, and the bonding wires between the anode of the SiC Schottky barrier diode chip 9 and the negative copper sink region 5, can be connected to the middle extension, upper extension, or lower extension respectively, depending on the location of each chip. Since the negative copper sink region 5 forms connectable areas near the upper carrier region 31, lower carrier region 32, and interval region 34, the bonding wire lengths from each parallel branch to the negative copper sink region 5 tend to be similar, which helps reduce the differences in local connection paths and parasitic parameters between different branches. The multi-directional extension of the negative copper sink region 5 also reduces the number of bonding wires that bypass the chipset periphery, maintaining a relatively regular layout of the internal connections of the lower bridge arm.

[0042] like Figures 2-3 As shown, the patterned copper layer also includes a lower gate copper region 6. The lower gate copper region 6 is located within the gap region 34 between the upper carrier region 31 and the lower carrier region 32, and is insulated from the intermediate extension of the negative sink copper region 5. An insulating gap is maintained between the lower gate copper region 6 and the intermediate extension, allowing the lower gate copper region 6 to form an independent control connection region, without electrical connection to the negative sink copper region 5. The lower gate copper region 6 can be formed using the same copper layer material as the other patterned copper regions, or a relatively smaller copper region area can be used depending on the control current requirements.

[0043] The lower gate copper region 6 is electrically connected to the gates of the SiC JFET chips 8 located in the upper carrier region 31 and the lower carrier region 32, respectively. In this embodiment, the gates of all four SiC JFET chips 8 are connected to the lower gate copper region 6 through corresponding bonding lines, enabling the four SiC JFET chips 8 to receive gate control signals through the same control copper region. The lower gate copper region 6 is located between the two carrier regions, allowing the SiC JFET chips 8 in the upper carrier region 31 and the lower carrier region 32 to be gate-bonded towards the spacer region 34.

[0044] like Figures 2-3 As shown, the intermediate extension and the lower gate copper region 6 are both arranged within the spacer region 34, but they are kept insulated from each other. The intermediate extension serves as the negative-side busbar for the source of the SiC JFET chip 8 and the anode of the SiC Schottky barrier diode chip 9, while the lower gate copper region 6 serves as the control connection for the gate of the SiC JFET chip 8. By placing the negative busbar connection region and the gate connection region at different positions within the spacer region 34, the power bonding connection and the gate bonding connection can be arranged in separate sections on the plane. The SiC JFET chip 8 located in the upper carrier region 31 and the lower carrier region 32 can be connected to the adjacent intermediate extension, upper extension, lower extension, and lower gate copper region 6, respectively, which helps to reduce the risk of power bonding lines and gate bonding lines crossing, overlapping, or being locally concentrated.

[0045] In one embodiment, the lower gate copper region 6 can be connected to an external JFET driving circuit via a separate lead-out structure. The lead-out structure can be a terminal disposed on the copper-clad ceramic substrate 1, a bonding wire structure connected to an auxiliary copper region, or other conductive structure capable of transmitting gate control signals. The specific connection between the lower gate copper region 6 and the external driving circuit can be configured according to the module packaging structure and application requirements. The lower gate copper region 6 maintains electrical isolation from the negative sink copper region 5, allowing the JFET gate control signal to be applied independently relative to the negative sink node on the JFET source side.

[0046] It should be understood that the patterned copper layer can also include multiple auxiliary copper regions. These auxiliary copper regions maintain an insulating distance from the positive copper region 2, the midpoint copper region 3, the upper source copper region 4, the negative sink copper region 5, and the lower gate copper region 6. Some auxiliary copper regions can be connected to corresponding chip electrodes, control copper regions, or detection nodes via bonding wires, while others can be connected to each other via copper clips or other conductive connectors. The auxiliary copper regions can be used to extract drive signals, detection signals, sampling signals, or test signals. The number, location, and connections of the auxiliary copper regions can be adjusted according to the module's drive requirements, test requirements, and protection requirements.

[0047] In the above embodiments, multiple vertical leads can also be provided on the copper-clad ceramic substrate 1. The vertical leads can be fixed to corresponding copper areas or auxiliary copper areas and led outwards from the package housing. The vertical leads can be used to connect to external drive circuits, detection circuits, control circuits, or other module interfaces. Different leads can be connected to the positive copper area 2, the midpoint copper area 3, the upper source copper area 4, the negative sink copper area 5, the lower gate copper area 6, or the auxiliary copper area, respectively. Since the definitions of module terminals may differ in different application scenarios, the specific electrical functions of each lead can be configured according to the requirements of the external circuit.

[0048] A heat dissipation substrate is disposed below the copper-clad ceramic substrate 1. The bottom copper layer is bonded to the heat dissipation substrate, forming a top-to-bottom heat conduction path on the copper-clad ceramic substrate 1. The heat dissipation substrate can be a copper substrate, an aluminum substrate, a copper alloy substrate, or other metal substrates with good thermal conductivity. A thermally conductive connection layer can be provided between the copper-clad ceramic substrate 1 and the heat dissipation substrate. The thermally conductive connection layer can be a solder layer, a sintering layer, a thermally conductive adhesive layer, or other thermally conductive connection materials suitable for power module assembly. Through the bonding of the bottom copper layer to the heat dissipation substrate, the heat generated during the operation of the SiC MOSFET chip 7, the SiC JFET chip 8, and the SiC Schottky barrier diode chip 9 can be transferred to the heat dissipation substrate via the copper-clad ceramic substrate 1.

[0049] The package housing and the heat dissipation substrate cooperate to form a package cavity. The copper-clad ceramic substrate 1, SiC MOSFET chip 7, SiC JFET chip 8, SiC Schottky barrier diode chip 9, bonding wires, auxiliary copper areas, and related lead-out structures are all disposed within the package cavity. The package housing can be formed of insulating material, and the package cavity can be filled with insulating encapsulation material. The insulating encapsulation material can be epoxy resin, silicone gel, or other insulating materials suitable for power module packaging. The package housing protects the internal chips, bonding wires, and copper areas, and maintains the stability of the module's internal structure under vibration, temperature changes, and external environmental influences.

[0050] In this embodiment, the positive copper region 2, the upper source copper region 4, the midpoint copper region 3, and the negative sink copper region 5 respectively serve as the connection functions for different power nodes. The SiC MOSFET chip 7 constitutes the upper bridge arm switching unit, while the SiC JFET chip 8 and the SiC Schottky barrier diode chip 9 constitute the lower bridge arm switching and freewheeling unit. The drain of the SiC MOSFET chip 7 is connected via the positive copper region 2, and the source is connected via the upper source copper region 4 and a bonding wire to the midpoint copper region 3. The drain of the SiC JFET chip 8 and the cathode of the SiC Schottky barrier diode chip 9 are both connected to the midpoint copper region 3, and the source of the SiC JFET chip 8 and the anode of the SiC Schottky barrier diode chip 9 are both connected to the negative sink copper region 5. Thus, an internal electrical connection relationship corresponding to the hybrid half-bridge topology is formed on the copper-clad ceramic substrate 1.

[0051] By setting an upper carrier region 31, a lower carrier region 32, and a connecting portion 33 on the midpoint copper region 3, and by arranging the SiC JFET chip 8 and the SiC Schottky barrier diode chip 9 in reverse order within the upper carrier region 31 and the lower carrier region 32, the upper and lower sets of chips can be positioned close to their corresponding negative sink connection regions and gate connection regions, respectively. The negative sink copper region 5 extends to the outside of the upper carrier region 31, the spacing region 34, and the lower carrier region 32, while the lower gate copper region 6 is located within the spacing region 34, enabling power connections and gate connections of different chips to be completed within adjacent regions. The bonding line lengths from each chip to its corresponding copper region tend to be similar, which helps to reduce the differences in local connection paths and parasitic parameters between parallel branches, and makes the bonding connection layout within the module more regular.

[0052] This invention is not limited to the above embodiments. The specific outlines of the positive copper region 2, the midpoint copper region 3, the upper source copper region 4, the negative sink copper region 5, and the lower gate copper region 6 can be adjusted according to the chip size, the number of chips, the terminal position, and the package size. The number of SiC MOSFET chips 7, SiC JFET chips 8, and SiC Schottky barrier diode chips 9 can be increased or decreased according to the module's rated current. The shapes of the upper carrier region 31, the lower carrier region 32, and the connecting portion 33 can be adjusted according to the midpoint current path and the chip layout. The middle extension, upper extension, and lower extension of the negative sink copper region 5 can be bent, forked, widened, or other shapes suitable for forming adjacent bonding points. The lower gate copper region 6 can form a corresponding branch structure according to the gate position of the JFET chip, so that the gate of each SiC JFET chip 8 can be connected to the lower gate copper region 6.

[0053] In other embodiments, the source connection region of the upper bridge arm chipset can also adopt a partitioned form adapted to the lower bridge arm chipset. The positive copper region 2 can form multiple chip carrier regions according to the array position of the SiC MOSFET chips 7. The upper source copper region 4 can be arranged around or adjacent to the SiC MOSFET chips 7 group and connected to the midpoint copper region 3 through multiple bridging bonding lines. The gate of the SiC MOSFET chip 7 can also be led out through an independent gate copper region. The independent gate copper region and the upper source copper region 4 maintain an insulating distance, so that the source connection and gate connection of the SiC MOSFET chip 7 form relatively independent arrangement regions.

[0054] In other embodiments, the SiC Schottky barrier diode chip 9 can be configured with different area specifications or different quantities according to the module's reverse freewheeling capability requirements. The SiC JFET chip 8 can be configured with chips of the same specification or a combination of chips of different specifications according to the rated current of the lower bridge arm. The SiC MOSFET chip 7, SiC JFET chip 8, and SiC Schottky barrier diode chip 9 can be fixed on the copper-clad ceramic substrate 1 using silver sintering, solder mounting, transient liquid phase bonding, or other connection methods suitable for power semiconductor module packaging. The bonding wires can be formed using aluminum wire, copper wire, strip wire, or other conductive connectors suitable for internal interconnection of the power module.

[0055] The above embodiments are used to illustrate the technical concept of the present invention. For those skilled in the art, adjustments to the number of chips, the shape of the copper area, the bonding position, the lead-out structure, and the packaging structure, without departing from the concept of the present invention, can all be considered as embodiments of the present invention.

Claims

1. A JFET MOSFET hybrid half-bridge power module, characterized in that, The invention includes a copper-clad ceramic substrate, wherein the patterned copper layer of the copper-clad ceramic substrate includes a positive copper region, a midpoint copper region, an upper source copper region, and a negative sink copper region. Multiple normally-off SiC MOSFET chips are disposed on the positive copper region. The drain of each SiC MOSFET chip is electrically connected to the positive copper region, and the source is electrically connected to the upper source copper region. Multiple normally-connected SiC JFET chips and multiple SiC Schottky barrier diode chips are disposed on the midpoint copper region. The drain of each SiC JFET chip and the cathode of each SiC Schottky barrier diode chip are electrically connected to the midpoint copper region. The source of each SiC JFET chip and the anode of each SiC Schottky barrier diode chip are electrically connected to the negative copper sink region. The source copper region and the midpoint copper region are electrically connected by multiple bridging bonding wires so that the source copper region and the midpoint copper region together form an AC output node.

2. The JFET MOSFET hybrid half-bridge power module according to claim 1, characterized in that, The plurality of SiC MOSFET chips comprises four, the plurality of SiC JFET chips comprises four, and the plurality of SiC Schottky barrier diode chips comprises four.

3. The JFET MOSFET hybrid half-bridge power module according to claim 2, characterized in that, The four SiCMOSFET chips are arranged in two rows and two columns along two intersecting directions.

4. The JFET MOSFET hybrid half-bridge power module according to claim 1, characterized in that, The midpoint copper area includes an upper bearing area, a lower bearing area, and a connecting portion connecting the upper bearing area and the lower bearing area. An interval area is formed between the upper bearing area and the lower bearing area, except for the connecting portion. Two SiC Schottky barrier diode chips are disposed on the upper side of the upper bearing area, and two SiC JFET chips are disposed on the lower side. Two SiC JFET chips are disposed on the upper side of the lower bearing area, and two SiC Schottky barrier diode chips are disposed on the lower side.

5. The JFET MOSFET hybrid half-bridge power module according to claim 4, characterized in that, The negative copper sink area includes a middle extension, an upper extension, and a lower extension. The middle extension is located within the interval area. The upper extension extends to the side of the upper bearing area away from the lower bearing area. The lower extension extends to the side of the lower bearing area away from the upper bearing area. The middle extension, the upper extension, and the lower extension are interconnected. The patterned copper layer also includes a lower gate copper region, which is located within the spacing region and is insulated from the intermediate extension.

6. The JFET MOSFET hybrid half-bridge power module according to claim 5, characterized in that, The lower gate copper region is electrically connected to the gate of the SiC JFET chip located in the upper and lower carrier regions, respectively.

7. The JFET MOSFET hybrid half-bridge power module according to claim 1, characterized in that, The first ends of the plurality of bridging bonding wires are respectively connected to at least two spaced connection positions in the upper source copper region, and the second ends of the plurality of bridging bonding wires are respectively connected to at least two spaced connection positions in the midpoint copper region.

8. The JFET MOSFET hybrid half-bridge power module according to claim 1, characterized in that, It also includes a heat dissipation substrate and a packaging housing; The copper-clad ceramic substrate includes a ceramic insulating layer, a patterned copper layer on the upper side of the ceramic insulating layer, and a bottom copper layer on the lower side of the ceramic insulating layer, wherein the bottom copper layer is bonded to the heat dissipation substrate. The package housing and the heat dissipation substrate cooperate to form a package cavity, and the copper-clad ceramic substrate, SiC MOSFET chip, SiC JFET chip and SiC Schottky barrier diode chip are all disposed in the package cavity.

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