A control method and device of a digital power supply

Abstract

The application discloses a control method and device of a digital power supply, in the upper half cycle of a PWM period, a CLA is controlled to trigger a first analog-to-digital converter to collect an output signal, a first deviation amount of the output signal from a first set reference value is calculated, and a first loop operation is performed to obtain a first duty ratio adjustment amount; in the lower half cycle of the PWM period, a CPU is controlled to trigger a second analog-to-digital converter to collect the output signal, a second deviation amount of the output signal from a second set reference value is calculated, and a second loop operation is performed to obtain a second duty ratio adjustment amount; a final duty ratio adjustment amount is determined as the first duty ratio adjustment amount multiplied by a first duty ratio adjustment weight coefficient plus the second duty ratio adjustment amount multiplied by a second duty ratio adjustment weight coefficient; and the PWM driving output is updated according to the final duty ratio adjustment amount. Through double-core time-sharing staggered sampling, independent loop operation and weight fusion output, high-precision digital power supply control can be realized, and the demand of the digital power supply for high reliability and fast response under high dynamic conditions can be met.

Description

Technical Field

[0001] This invention relates to the field of power supply control technology, and in particular to a control method and device for a digital power supply. Background Technology

[0002] Currently, to achieve loop control and intelligent management of digital power supplies, microcontroller units (MCUs) or digital signal processors (DSPs) are often used as the control core. A common approach is to utilize the multi-core architecture of the DSP, for example, using the main central processing unit (CPU) to handle the outer voltage loop control, and cores such as control law accelerators (CLAs) to handle high-speed calculations in the inner current loop, thereby attempting to achieve multi-threaded intelligent and networked management.

[0003] However, early single-core or pseudo-multi-core solutions had inherent flaws in their analog-to-digital conversion (ADC) sampling mechanisms. Within a single switching cycle, the system often only performs ADC sampling once in the first half of the cycle, leaving energy transfer fluctuations in the second half of the cycle in a "blind zone." This prevents real-time monitoring and timely adjustment of the pulse-width modulation (PWM) loop compensation. This directly results in slow loop dynamic response and large switching ripple. More seriously, in a single-core architecture, the high-real-time "loop operation" shares processor resources with "multi-task events" such as communication and management. Because time-slice allocation is used instead of true hardware parallelism, if a task abnormally occupies the CPU for an extended period, it can easily lead to loop operation event congestion, preventing timely execution of closed-loop control. This not only causes output voltage / current oscillations but, in severe cases, can damage the power supply module and load due to overvoltage / overcurrent protection failure.

[0004] Therefore, existing technologies cannot simultaneously achieve accurate monitoring of both the first and second halves of the cycle and independent parallel processing of multiple tasks, and cannot meet the high reliability and fast response requirements of digital power supplies under highly dynamic operating conditions. Summary of the Invention

[0005] This invention provides a digital power supply control method and device. Through dual-core time-division interleaved sampling, independent loop operation and weighted fusion output, it can achieve high-precision digital power supply control and meet the requirements of digital power supply for high reliability and fast response under high dynamic operating conditions.

[0006] In a first aspect, embodiments of the present invention provide a digital power supply control method, implemented using a DSP, wherein the DSP includes a CPU and a CLA, forming a dual-core architecture, and the DSP integrates a first analog-to-digital converter and a second analog-to-digital converter. The control method for the digital power supply includes: During the first half of the PWM cycle, the CLA is controlled to trigger the first analog-to-digital converter to acquire the output signal, calculate the first deviation between it and the first set reference value, and perform the first loop operation to obtain the first duty cycle adjustment amount. In the second half of the PWM cycle, the CPU is controlled to trigger the second analog-to-digital converter to acquire the output signal, calculate the second deviation between the output signal and the second set reference value, and perform a second loop operation to obtain the second duty cycle adjustment amount. The final duty cycle adjustment amount is determined as: first duty cycle adjustment amount × first duty cycle adjustment weight coefficient + second duty cycle adjustment amount × second duty cycle adjustment weight coefficient; wherein, the sum of the first duty cycle adjustment weight coefficient and the second duty cycle adjustment weight coefficient is 100%. Update the PWM drive output based on the final duty cycle adjustment.

[0007] Optionally, the sampling trigger time of the first analog-to-digital converter and the sampling trigger time of the second analog-to-digital converter have a phase difference of 180° within a single PWM cycle.

[0008] Optionally, the default configuration for both the first duty cycle adjustment weighting coefficient and the second duty cycle adjustment weighting coefficient is 50%.

[0009] Optionally, the values ​​of the first duty cycle adjustment weight coefficient of the CLA and the second duty cycle adjustment weight coefficient of the CPU are set according to the current working state parameters of the system.

[0010] Optionally, the first loop operation is a current loop PI operation, and the second loop operation is a voltage loop PI operation; The CPU is used to perform voltage loop PI calculation to generate current instructions and transmit the current instructions to the CLA; when the CLA performs current loop PI calculation, it uses the current instructions as a set reference value.

[0011] Optionally, the CPU transmits the current command to the CLA via shared RAM or a communication interface.

[0012] Optionally, the CLA has an independent floating-point arithmetic unit and a dedicated data bus; The CLA independently completes the processes of ADC triggering, deviation calculation, PI calculation, and data writing during the first half of the PWM cycle.

[0013] Optionally, the control method for the digital power supply further includes: Real-time monitoring of the operating status of the CLA and the CPU; When an abnormality is detected in either the CLA or the CPU, the other is controlled to take over the current loop control task and independently output the duty cycle adjustment amount with a weighting coefficient of 100%.

[0014] In a second aspect, embodiments of the present invention also provide a control device for a digital power supply, used to execute the control method for a digital power supply described in the first aspect, comprising: The CLA control module is used to control the CLA to trigger the first analog-to-digital converter to acquire the output signal during the first half of the PWM cycle, calculate the first deviation between the signal and the set reference value, and perform the first loop operation to obtain the first duty cycle adjustment amount. The CPU control module is used to control the CPU to trigger the second analog-to-digital converter to acquire the output signal in the second half of the PWM cycle, calculate the second deviation between the signal and the set reference value, and perform a second loop operation to obtain the second duty cycle adjustment amount. The final duty cycle adjustment amount determination module is used to determine the final duty cycle adjustment amount as a first duty cycle adjustment amount × a first duty cycle adjustment weight coefficient + a second duty cycle adjustment amount × a second duty cycle adjustment weight coefficient; wherein, the sum of the first duty cycle adjustment weight coefficient and the second duty cycle adjustment weight coefficient is 100%; The drive output update module is used to update the PWM drive output according to the final duty cycle adjustment.

[0015] Optional, also includes: The operation status monitoring module is used to control the other to take over the current loop control task when an abnormal operation is detected in either the CLA or the CPU, and to independently output the duty cycle adjustment amount with a 100% weighting coefficient.

[0016] This invention utilizes a dual-core time-division interleaved sampling and weighted fusion mechanism in a DSP, enabling the two processing cores to independently complete sampling and loop operations at different times, thus avoiding competition for computing resources. By fusing the adjustment values ​​of the two cores through weighting coefficients, the invention fully utilizes the computing power of both cores while ensuring the consistency and stability of the final output. This achieves high-precision digital power supply control, meeting the high reliability and fast response requirements of digital power supplies under highly dynamic operating conditions.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a digital power supply control method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a digital power supply control device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of another digital power supply control device provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a flowchart illustrating a digital power supply control method according to an embodiment of the present invention. This embodiment is applicable to the control of a digital power supply loop. The method can be executed by a digital power supply control device, which can be implemented in hardware and / or software. The digital power supply control method is implemented using a DSP, which includes a CPU and a CLA, forming a dual-core architecture. The DSP integrates a first analog-to-digital converter and a second analog-to-digital converter.

[0023] refer to Figure 1 The method includes the following steps: S110. In the first half of the PWM cycle, control the CLA to trigger the first analog-to-digital converter to acquire the output signal, calculate the first deviation between it and the first set reference value, and perform the first loop operation to obtain the first duty cycle adjustment amount.

[0024] Specifically, the first half of the PWM cycle can be from when the PWM counter returns to zero until it reaches the midpoint of the cycle, and the first loop operation can be a PI operation or a PID operation. The CLA has a floating-point arithmetic unit and a dedicated data bus independent of the CPU, which can independently complete the entire process from ADC triggering and deviation calculation to loop operation without occupying CPU resources.

[0025] S120. In the second half of the PWM cycle, the control CPU triggers the second analog-to-digital converter to acquire the output signal, calculates the second deviation between the output signal and the second set reference value, and performs the second loop operation to obtain the second duty cycle adjustment.

[0026] Specifically, the second half of the PWM cycle can be from when the PWM counter reaches the midpoint of the cycle to when it returns to zero in the next cycle, and the second loop operation can be a PI operation or a PID operation.

[0027] S130. Determine the final duty cycle adjustment amount as: first duty cycle adjustment amount × first duty cycle adjustment weight coefficient + second duty cycle adjustment amount × second duty cycle adjustment weight coefficient; wherein, the sum of the first duty cycle adjustment weight coefficient and the second duty cycle adjustment weight coefficient is 100%.

[0028] Specifically, the system has a first duty cycle adjustment weight coefficient (denoted as A%, corresponding to CLA) and a second duty cycle adjustment weight coefficient (denoted as B%, corresponding to CPU), and A% + B% = 100%. The final duty cycle adjustment amount is calculated according to the following formula: Final duty cycle adjustment amount = First duty cycle adjustment amount × A% + Second duty cycle adjustment amount × B%. This formula linearly merges the duty cycle adjustment amounts obtained independently by CLA and CPU according to the preset weight ratio to obtain a unified final adjustment amount.

[0029] S140: Update the PWM drive output based on the final duty cycle adjustment.

[0030] Specifically, the calculated final duty cycle adjustment can be written into the PWM duty cycle register to adjust the on-time of the power switch, thereby updating the drive signal within one PWM cycle.

[0031] This embodiment utilizes the dual-core time-sharing sampling and independent operation of the DSP to avoid competition and conflict between the two operation cores for the same resource; by using weighting coefficients to linearly fuse the adjustment values ​​of the two cores, the operation results of the two cores can be reflected in the final output, which not only makes full use of the parallel processing capability of the dual cores, but also ensures the consistency and stability of the control output.

[0032] Optionally, based on the above embodiments, the sampling trigger time of the first analog-to-digital converter and the sampling trigger time of the second analog-to-digital converter have a phase difference of 180° within a single PWM cycle.

[0033] Specifically, the first analog-to-digital converter (ADC) can be triggered to sample at the peak of the PWM carrier wave (the peak point of the count), and the second ADC can be triggered to sample at the trough of the PWM carrier wave (the zero point of the count or another extreme point). Through this staggered configuration, the two ADCs sample once in the first half and once in the second half of the PWM cycle, achieving full cycle coverage. Since the current exhibits a triangular wave shape within a PWM cycle, the values ​​sampled at the peak and trough are located precisely at the two endpoints of the triangular wave. Averaging these two sampled values ​​effectively eliminates the sampling error introduced by switching ripple, obtaining current information closer to the true average value. This provides more accurate feedback data for subsequent loop calculations, allowing the controller to use higher control bandwidth without causing system oscillation.

[0034] This embodiment performs sampling once in the first half and once in the second half of the PWM cycle, achieving full cycle coverage. This effectively eliminates the interference of switching ripple on the sampled values, improves sampling accuracy, and thus provides more accurate feedback data for loop operation.

[0035] Optionally, in one embodiment, the default configuration of both the first duty cycle adjustment weighting coefficient and the second duty cycle adjustment weighting coefficient is 50%.

[0036] In this embodiment, the CLA and CPU contribute equally to the final output by default, and the system is in a balanced working state, which is suitable for most normal working conditions and simplifies the initial configuration process.

[0037] Optionally, in one embodiment, the values ​​of the first duty cycle adjustment weight coefficient of the CLA and the second duty cycle adjustment weight coefficient of the CPU are set according to the current operating state parameters of the system.

[0038] Specifically, based on operating status parameters, the system dynamically sets the values ​​of the first duty cycle adjustment weight coefficient A% for the CLA and the second duty cycle adjustment weight coefficient B% for the CPU through table lookup or preset algorithms. For example, under heavy load conditions, the system can increase the CPU's weight coefficient B%, allowing the voltage outer loop regulation to play a larger role in the final output; under light load conditions or conditions sensitive to output ripple, the CLA's weight coefficient A% can be increased, allowing the high-frequency current inner loop regulation to play a greater role. By dynamically adjusting the weight ratios, the system can adapt to different operating conditions and optimize control performance.

[0039] This embodiment can adaptively adjust the weight ratio of the dual cores in the control output according to the actual working conditions, and can maintain good control performance under different load conditions and operating environments.

[0040] Optionally, based on the above embodiments, the first loop operation is a current loop PI operation, and the second loop operation is a voltage loop PI operation; the CPU is used to execute the voltage loop PI operation to generate a current command and transmit the current command to the CLA; when the CLA executes the current loop PI operation, it uses the current command as a set reference value.

[0041] This embodiment assigns the high real-time requirement of the inner current loop to the CLA for execution, and the more strategic outer voltage loop to the CPU for execution. This achieves a reasonable division of labor between the inner and outer loops, ensuring the fast response of the current loop while freeing up computing power for the CPU to execute system management tasks.

[0042] Optionally, based on the above embodiments, the CPU transmits current commands to the CLA via shared RAM or a communication interface.

[0043] Specifically, the CPU can transmit the current command to the CLA via shared RAM, SPI interface, IPC interrupt, or register mapping area. When the CLA executes the inner current loop control, it uses the aforementioned current command as the first set reference value (i.e., the set current value), compares the actual current sampled by the first analog-to-digital converter with the current command, performs current loop PI calculation, and obtains the first duty cycle adjustment. This design of separating the inner and outer loops allows the high-frequency current loop to be executed in real time by the CLA, resulting in a fast response speed; while the low-frequency voltage loop is executed by the CPU, taking into account system-level strategy calculations and network communication functions.

[0044] This embodiment provides specific high-speed data interaction methods to ensure that current commands can be transmitted between the two cores with low latency, meeting the time requirements of real-time control.

[0045] Optionally, the CLA has an independent floating-point arithmetic unit and a dedicated data bus; the CLA independently completes the ADC triggering, deviation calculation, PI calculation and data writing process in the first half of the PWM cycle.

[0046] Specifically, during the first half of the PWM cycle, the CLA can independently complete the following processes: triggering the first analog-to-digital converter to start sampling; reading the conversion result of the first analog-to-digital converter; comparing the sampled result with the current command and calculating the deviation; performing PI calculation and updating the first duty cycle adjustment; and writing the calculation result into shared RAM or a designated register. The above process requires no CPU participation or intervention. During this time, the CPU can perform other tasks such as voltage loop calculations, communication protocol processing, and fault diagnosis. This hardware-level task isolation ensures the determinism and real-time performance of the inner current loop.

[0047] In this embodiment, the CLA can complete sampling and calculation tasks autonomously without relying on the CPU, ensuring the determinism and high real-time performance of the inner current loop, and will not be blocked by other CPU tasks.

[0048] Optionally, based on the above embodiments, the method further includes: real-time detection of the operating status of the CLA and the CPU; when an abnormal operation of either the CLA or the CPU is detected, controlling the other to take over the current loop control task and independently outputting the duty cycle adjustment amount with a weighting coefficient of 100%.

[0049] Specifically, the system monitors the operating status of the CLA and CPU in real time. When an abnormality is detected in either the CLA or the CPU, the system controls the other, which is operating normally, to take over all loop control tasks. The taking-over core independently outputs the duty cycle adjustment with a 100% weighting coefficient; that is, dual-core weight fusion is no longer performed, and a single normal core independently completes all control calculations. For example, when the CLA is abnormal, the CPU takes over the current loop control, at which point A%=0% and B%=100%; when the CPU is abnormal, the CLA takes over the voltage loop control or continues to operate with a preset safe current command, at which point A%=100% and B%=0%. This mechanism ensures that the system can maintain basic power supply functions even in the event of a single-core failure, improving system reliability.

[0050] In this embodiment, when either of the dual cores fails, the normally operating core can take over all control tasks, ensuring that the system can still maintain basic power supply in the fault state, thus improving the reliability and safety of the entire power system.

[0051] Figure 2 This is a schematic diagram of a control device for a digital power supply according to an embodiment of the present invention, used to execute the control method for the digital power supply described above. (Refer to...) Figure 2 The device includes: The CLA control module 210 is used to control the CLA to trigger the first analog-to-digital converter to acquire the output signal during the first half of the PWM cycle, calculate the first deviation between the signal and the set reference value, and perform the first loop operation to obtain the first duty cycle adjustment amount. The CPU control module 220 is used to control the CPU to trigger the second analog-to-digital converter to acquire the output signal in the second half of the PWM cycle, calculate the second deviation between the signal and the set reference value, and perform the second loop operation to obtain the second duty cycle adjustment amount. The final duty cycle adjustment amount determination module 230 is used to determine the final duty cycle adjustment amount as a first duty cycle adjustment amount × a first duty cycle adjustment weight coefficient + a second duty cycle adjustment amount × a second duty cycle adjustment weight coefficient; wherein, the sum of the first duty cycle adjustment weight coefficient and the second duty cycle adjustment weight coefficient is 100%; The drive output update module 240 is used to update the PWM drive output based on the final duty cycle adjustment.

[0052] Figure 3 This is a schematic diagram of another digital power supply control device provided in an embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 3 The device also includes: The operation status monitoring module 310 is used to control the other to take over the current loop control task when an abnormal operation of either the CLA or the CPU is detected, and to independently output the duty cycle adjustment amount with a 100% weighting coefficient.

[0053] The digital power supply control device provided in this embodiment of the invention can execute the digital power supply control method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method. For content not described in detail in the embodiments of the invention, please refer to the digital power supply control method provided in the above embodiments.

[0054] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0055] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for controlling a digital power supply, characterized in that, It is implemented using a DSP, which includes a CPU and a CLA, forming a dual-core architecture. The DSP integrates a first analog-to-digital converter and a second analog-to-digital converter. The control method for the digital power supply includes: During the first half of the PWM cycle, the CLA is controlled to trigger the first analog-to-digital converter to acquire the output signal, calculate the first deviation between it and the first set reference value, and perform the first loop operation to obtain the first duty cycle adjustment amount. In the second half of the PWM cycle, the CPU is controlled to trigger the second analog-to-digital converter to acquire the output signal, calculate the second deviation between the output signal and the second set reference value, and perform a second loop operation to obtain the second duty cycle adjustment amount. The final duty cycle adjustment amount is determined as: first duty cycle adjustment amount × first duty cycle adjustment weight coefficient + second duty cycle adjustment amount × second duty cycle adjustment weight coefficient; wherein, the sum of the first duty cycle adjustment weight coefficient and the second duty cycle adjustment weight coefficient is 100%. Update the PWM drive output based on the final duty cycle adjustment.

2. The control method for a digital power supply according to claim 1, characterized in that, The sampling trigger time of the first analog-to-digital converter and the sampling trigger time of the second analog-to-digital converter have a phase difference of 180° within a single PWM cycle.

3. The control method for a digital power supply according to claim 1, characterized in that, The default configuration for both the first duty cycle adjustment weighting coefficient and the second duty cycle adjustment weighting coefficient is 50%.

4. The control method for a digital power supply according to claim 1, characterized in that, The values ​​of the first duty cycle adjustment weight coefficient of the CLA and the second duty cycle adjustment weight coefficient of the CPU are set according to the current working state parameters of the system.

5. The control method for a digital power supply according to claim 1, characterized in that, The first loop operation is a current loop PI operation, and the second loop operation is a voltage loop PI operation; The CPU is used to perform voltage loop PI calculation to generate current instructions and transmit the current instructions to the CLA; when the CLA performs current loop PI calculation, it uses the current instructions as a set reference value.

6. The control method for a digital power supply according to claim 5, characterized in that, The CPU transmits the current command to the CLA via shared RAM or a communication interface.

7. The control method for a digital power supply according to claim 1, characterized in that, The CLA has an independent floating-point arithmetic unit and a dedicated data bus; The CLA independently completes the processes of ADC triggering, deviation calculation, PI calculation, and data writing during the first half of the PWM cycle.

8. The control method for a digital power supply according to claim 1, characterized in that, The control method for the digital power supply also includes: Real-time monitoring of the operating status of the CLA and the CPU; When an abnormality is detected in either the CLA or the CPU, the other is controlled to take over the current loop control task and independently output the duty cycle adjustment amount with a weighting coefficient of 100%.

9. A control device for a digital power supply, used to execute the control method for the digital power supply according to any one of claims 1-8, characterized in that, include: The CLA control module is used to control the CLA to trigger the first analog-to-digital converter to acquire the output signal during the first half of the PWM cycle, calculate the first deviation between the signal and the set reference value, and perform the first loop operation to obtain the first duty cycle adjustment amount. The CPU control module is used to control the CPU to trigger the second analog-to-digital converter to acquire the output signal in the second half of the PWM cycle, calculate the second deviation between the signal and the set reference value, and perform a second loop operation to obtain the second duty cycle adjustment amount. The final duty cycle adjustment amount determination module is used to determine the final duty cycle adjustment amount as a first duty cycle adjustment amount × a first duty cycle adjustment weight coefficient + a second duty cycle adjustment amount × a second duty cycle adjustment weight coefficient; wherein, the sum of the first duty cycle adjustment weight coefficient and the second duty cycle adjustment weight coefficient is 100%; The drive output update module is used to update the PWM drive output according to the final duty cycle adjustment.

10. The control device for a digital power supply according to claim 9, characterized in that, Also includes: The operation status monitoring module is used to control the other to take over the current loop control task when an abnormal operation is detected in either the CLA or the CPU, and to independently output the duty cycle adjustment amount with a 100% weighting coefficient.

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