High-power electric appliance chip hierarchical energy efficiency regulation and intelligent power supply optimization method

Abstract

The application relates to the technical field of chip power supply control, and discloses a large-power electric appliance chip hierarchical energy efficiency regulation and intelligent power supply optimization method, which comprises the following steps: collecting electromagnetic parameters such as voltage and actual inductance current and node temperature, extracting voltage change rate and current deviation, and integrating the voltage change rate and the current deviation into a state characteristic matrix; deducing impedance according to temperature and calculating weight, generating asymmetric phase current instructions and steady-state output duty cycles, and combining electromagnetic parameters to calculate dead time parameters; when it is determined that a computing power step occurs, locking the lowest temperature power supply phase as a target phase to calculate an asymmetric feedforward duty cycle, synthesizing a drive signal to cross-periodically inject a feedforward pulse; calculating a target phase cumulative volt-second product, cutting off the pulse when the magnetic core saturation threshold is reached, extracting a remaining compensation duty cycle, and writing the remaining compensation duty cycle into a secondary-low-temperature standby phase register according to a redirection time sequence to complete transfer injection. The application reduces switching loss and improves energy efficiency by taking into account steady-state thermal balance and extreme transient response.

Description

Technical Field

[0001] This invention relates to the field of chip power supply control technology, specifically to a method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips. Background Technology

[0002] High-power electrical appliances and high-performance computing devices experience a jump in computing power when performing computational tasks, causing transient changes in the power supply load of the core chip. Existing multi-phase chip power supply systems use symmetrical phase-shift interleaved control logic and configure fixed dead-time parameters in the controller. The control architecture instructs each power supply phase to share the steady-state load current equally. It does not incorporate the real-time physical node temperature differences of the underlying power devices and inductors into the feedback loop. Under conditions where there are objective differences in hardware heat dissipation, the symmetrical distribution of steady-state current causes the heat dissipation-limited power supply phases to continue to heat up, generating local hot spots and limiting the overall power supply efficiency of the device. When dealing with the output voltage drop caused by a leap in computing power, the current control mechanism extends the conduction time of the drive pulse across cycles to output compensation charge. The continuous conduction with a long duty cycle directly increases the cumulative time of the inductor's forward voltage drop. In designs lacking a dynamic monitoring mechanism for the core saturation boundary, the inductor element exceeds the physical threshold of the saturation volt-second product and loses its inductive reactance. The resulting surge in short-circuit current directly causes overload damage to the underlying power hardware. At the same time, the fixed dead time setting deviates from the actual operating conditions of the power transistor's equivalent parasitic capacitance charging and discharging characteristics over a wide load range, causing the drive half-bridge to perform switching operations in a non-zero voltage state, generating unnecessary switching power losses and reducing the overall energy efficiency ratio of the high-power chip power supply system. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical chips, which solves the problems faced by chip power supply systems under computing power leaps, such as local hot spots caused by symmetrical distribution, core saturation caused by large-span compensation, and switching losses caused by fixed dead zones.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips, comprising the following steps: Electromagnetic operating parameters including input voltage, output voltage, and actual inductance current of the power supply phase, as well as physical node temperature, are collected. The output voltage change rate and current deviation in the electromagnetic operating parameters are extracted and integrated with the physical node temperature into a state feature matrix. Extract the physical node temperature to derive the actual impedance and calculate the smooth operation weight, thereby generating the asymmetric phase current command and steady-state output duty cycle; extract the input voltage and actual inductor current to calculate the dead time parameter; When a computing power step occurs, the power supply phase with the lowest physical node temperature is locked as the target phase, and the asymmetric feedforward duty cycle is calculated by combining the output voltage change rate and current deviation. Based on the steady-state output duty cycle, dead time parameters, and asymmetric feedforward duty cycle, multiple asymmetric pulse width modulation drive signals are synthesized to inject corresponding asymmetric feedforward duty cycle pulses into the target phase. Calculate the cumulative volt-second product of the target phase. When the cumulative volt-second product reaches the threshold, cut off the asymmetric feedforward duty cycle pulse, extract the remaining compensation duty cycle, and locate the power supply phase with the second lowest physical node temperature as the backup phase to generate the redirection timing. The remaining compensation duty cycle is written into the register of the spare phase according to the redirection timing, and the multi-channel asymmetric pulse width modulation drive signal is updated and injected into the spare phase.

[0005] This invention integrates electromagnetic operating parameters and physical node temperature. When a computing power jump occurs, it prioritizes the use of the power supply phase with the lowest temperature for feedforward injection. By monitoring the volt-second product and truncating the pulse at the saturation threshold, the remaining compensation amount is redirected to the second lowest temperature phase. This completes transient energy compensation while avoiding single inductor saturation and thermal stress concentration.

[0006] Furthermore, the output voltage change rate and current deviation are extracted from the electromagnetic operating parameters, including the following steps: The input voltage, output voltage, total load current, and actual inductor current of each power supply phase of the current hardware circuit are synchronously collected during the microsecond-level high-speed electromagnetic sampling period as electromagnetic operation parameters. Record the output voltage of the current sampling period and the output voltage of the previous sampling period and calculate the difference between the two. Divide the difference by the time span of the switching cycle to calculate the output voltage change rate. A sliding time window is established in the internal memory, and the total load current of multiple historical sampling periods in the sliding time window is extracted. The arithmetic mean of all total load currents is calculated as the average load current. The current deviation is obtained by subtracting the average load current from the total load current of the current period.

[0007] The current deviation is calculated by combining a sliding time window with the arithmetic mean, high-frequency switching noise is filtered out, and the step amplitude of the actual load is quantified, providing an accurate data source for transient determination.

[0008] Furthermore, the integration of the physical node temperature with the state feature matrix includes the following steps: The temperature of physical nodes is simultaneously acquired during millisecond-level low-speed thermodynamic sampling cycles; The acquired input voltage, output voltage, total load current, actual inductor current, and physical node temperature are clock-domain aligned according to the time sequence. The aligned input voltage, output voltage, total load current, actual inductor current, physical node temperature, output voltage change rate, and current deviation are extracted as state feature elements. All state feature elements are combined into a state feature matrix according to a preset dimensional order.

[0009] To address the time difference between electromagnetic high-frequency parameters and thermodynamic low-frequency parameters, clock domain alignment is used to synchronize sampling timing, thereby eliminating state observation errors caused by asynchronous data.

[0010] Furthermore, the actual impedance is derived by extracting the physical node temperature and the smoothing operation weight is calculated. The steps include: An impedance mapping model is established, which superimposes the nominal impedance value of the inductor coil at the nominal operating temperature with the impedance increment obtained from the temperature change corresponding to the physical node temperature, and then derives the actual impedance. Calculate the proportion of the reciprocal of the actual impedance of each power supply phase in the sum of the reciprocals of the actual impedances of all power supply phases, and generate the original current allocation weights; The original current allocation weights are input into a digital low-pass filter to perform time-scale decoupling operations. Combined with the smoothing weights of the previous discrete time step, the smoothing weights corresponding to each power supply in the current discrete time step are output.

[0011] A model is constructed by utilizing the characteristic of inductor impedance changing with temperature, and combined with digital filtering to process weight allocation, to achieve dynamic load balancing of each power supply phase based on thermal distribution.

[0012] Furthermore, the step of generating the asymmetric phase current command and steady-state output duty cycle accordingly includes: The voltage compensation outer loop calculates the reference duty cycle based on the difference between the output voltage and the target reference voltage. The asymmetrical phase current command is calculated by multiplying the total load current by the smooth operation weight. The bias duty cycle is calculated using the difference between the asymmetrical phase current command and the actual inductor current through the current compensation inner loop. The steady-state output duty cycle is generated by performing an arithmetic superposition operation on the base duty cycle and the bias duty cycle.

[0013] A dual closed-loop control architecture is constructed, which superimposes the outer loop reference duty cycle with the inner loop bias duty cycle based on thermal weight, so that the current of each power supply phase is asymmetrically distributed according to the corresponding heat dissipation capacity under steady-state conditions.

[0014] Furthermore, the dead time parameters are calculated by extracting the input voltage and the actual inductor current. The steps include: Extract the drain-source equivalent parasitic capacitance parameters of the upper and lower bridge arm power switching transistors in the driving half-bridge, and determine the equivalent parasitic capacitance by combining the additional parasitic capacitance of the switching node. A constant current charge-discharge equation for the equivalent parasitic capacitance is constructed by combining the input voltage, and the total charge transfer is obtained by multiplying the equivalent parasitic capacitance by the input voltage. The theoretical optimal dead time is obtained by dividing the total charge transfer by the actual inductor current of the corresponding power supply phase. The theoretical optimal dead time is then multiplied by the operating clock frequency and rounded down to obtain the dead time register count value as the dead time parameter.

[0015] Based on the charging and discharging characteristics of the parasitic capacitance of the power switching device, and combined with the inductor current, the charge transfer time is calculated to achieve adaptive tuning of the dead time and reduce the commutation loss of the power bridge arm.

[0016] Furthermore, when a computing power step occurs, based on the output voltage change rate and the current deviation, the power supply phase with the lowest physical node temperature in the state feature matrix is ​​identified as the target phase. The asymmetric feedforward duty cycle is calculated using the input voltage, the output voltage, and the preset nominal inductance value. The steps include: When the output voltage change rate shows a negative drop and its absolute value is greater than the preset voltage drop rate threshold, and the current deviation shows a positive sudden change and its value is greater than the preset current amplitude change threshold, it is determined that a load surge type computing power step has occurred. After determining that a computing power step has occurred, the physical node temperature in the state feature matrix is ​​retrieved, the lowest power supply phase is locked as the target phase, and the pulse width required for cross-cycle injection is calculated by combining the nominal inductance value, current deviation, input voltage, output voltage and the set switching cycle time span, and the asymmetric feedforward duty cycle is output. The asymmetric feedforward duty cycle is written into the register corresponding to the target, and the driving half-bridge of the target phase is turned on to generate the corresponding asymmetric feedforward duty cycle pulse.

[0017] Step events are identified by using both voltage and current change characteristics, and the compensation pulse width is directly calculated based on the current circuit parameters to improve the transient response speed of the system.

[0018] Further, the cumulative volt-second product of the target phase is calculated, and the asymmetric feedforward duty cycle pulse is truncated when the cumulative volt-second product reaches a threshold. The steps include: The difference between the input voltage and the output voltage is calculated as the inductor forward voltage drop. The cumulative volt-second product is calculated by multiplying the inductor forward voltage drop by the real-time conduction time of the target phase driven half-bridge. The threshold is obtained by multiplying the core cross-sectional area, the number of coil turns, and the constant saturation magnetic induction. When the accumulated volt-second product reaches the threshold, a saturation defense protection signal is output, and the power switching transistor of the target phase is turned off by the pulse truncation command, thereby trunculating the asymmetric feedforward duty cycle pulse.

[0019] The saturation threshold is calculated based on the physical structure parameters of the inductor core. The single pulse injection amount is monitored by the volt-second product, and the pulse is cut off at the saturation critical point to prevent the inductor from being damaged by deep saturation.

[0020] Furthermore, the remaining compensation duty cycle is extracted, and the power supply phase with the second lowest temperature at the physical node is identified as the spare phase to generate a redirection timing sequence. The steps include: The actual executed duty cycle is derived by recording the executed conduction time corresponding to the instant the pulse is cut off. The remaining compensation duty cycle that has not been released is calculated by subtracting the actual executed duty cycle from the asymmetric feedforward duty cycle. After removing the target phase that is currently experiencing pulse interruption, retrieve the physical node temperature of the remaining power supply phases and extract the power supply phase with the lowest current temperature as the backup phase; The redirection timing is generated according to the following rules: the original steady-state interleaved conduction time of the backup phase channel is forcibly suspended, and the conduction command is immediately triggered to the backup phase channel at the moment when the target phase pulse is cut off, taking the moment as the starting point; and the remaining compensation duty cycle is written into the corresponding register of the backup phase according to the redirection timing to complete the redirection injection.

[0021] After the target phase pulse is truncated, the unreleased duty cycle fraction is calculated and transferred to the next lowest temperature power supply phase to ensure the integrity of the compensation energy and disperse the thermal stress of the device.

[0022] Furthermore, after writing the remaining compensation duty cycle into the corresponding spare register according to the redirection timing to complete the redirection injection, the steps also include: When the redirection injection operation is completed and the current deviation falls back to within the preset current amplitude change threshold, a control switching command is sent to the underlying control logic to switch back to the synchronous interleaved operation mode. Extract the difference between the output voltage recorded in the state feature matrix and the set target reference voltage, and divide the target reference voltage by the input voltage to obtain the theoretical steady-state duty cycle; The initial reset value of the integral accumulator register of the proportional-integral regulator is obtained by subtracting the product of the difference between the target reference voltage and the output voltage and the proportional coefficient of the proportional-integral regulator in the voltage compensation outer loop from the theoretical steady-state duty cycle. Write the initial reset value to the integral accumulator register and clear the values ​​of the current compensation inner loop bias integral accumulator registers corresponding to all power supplies to zero.

[0023] When the system switches back to steady-state mode after transient compensation, the initial value of the outer loop proportional-integral regulator is reset and the inner loop bias integral is cleared to eliminate the integral term deviation generated by the feedforward process and prevent overshoot of the output voltage.

[0024] This invention provides a method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips. It has the following beneficial effects: 1. This invention derives the actual impedance by collecting the temperature of physical nodes and calculates the smooth operation weight, generating a steady-state output duty cycle and asymmetric phase current command. At the same time, the asymmetric phase current command is substituted into the timing physical model containing the equivalent parasitic capacitance parameters of the driving half-bridge switching nodes to calculate the dead time. This changes the power supply redundancy and energy waste caused by the fixed symmetrical power supply of traditional high-power electrical appliances, enabling each power supply phase to perform adaptive energy efficiency adjustment based on the real-time thermodynamic state and the charging and discharging characteristics of the underlying parasitic parameters, reducing the non-zero voltage turn-on loss of the system and improving the overall equipment energy efficiency ratio.

[0025] 2. This invention determines the occurrence of a computing power step when the output voltage change rate and current deviation meet a preset threshold condition, suspends the steady-state interleaving logic, and locks the power supply phase with the lowest physical node temperature as the target phase to inject an asymmetric feedforward duty cycle pulse across cycles. When dealing with the transient load surge of high-power chips, the instantaneous compensation charge is forcibly directed to the physical path with the largest current heat dissipation margin, taking into account both the transient voltage recovery rate and the thermal balance between power supply phases, and avoiding the problem of local hot spot deterioration.

[0026] 3. This invention monitors the cumulative volt-second product of the target phase in real time and cuts off the drive pulse when the volt-second product threshold of the magnetic core saturation is reached. The remaining unreleased compensation duty cycle is extracted and transferred to the standby phase with the second lowest physical node temperature according to the redirection timing. At the same time, when switching back to the synchronous interleaved operation mode, the initial integral value of the feedback regulator is reset according to the real-time input and output voltage. Under the premise of adhering to the physical bottom line of preventing hard saturation of magnetic components, the transient compensation energy is fully output, and the secondary voltage overshoot fluctuation during the controller operation mode switching process is eliminated. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the system timing interaction of the present invention; Figure 2 This is a schematic diagram of the method flow according to an embodiment of the present invention; Figure 3 This is a timing interaction diagram for data acquisition and state feature matrix construction of the underlying control logic and parameter acquisition modules of this invention. Figure 4 The timing interaction diagram for the actual impedance inverse proportional mapping and asymmetric duty cycle allocation of the thermal equalization scheduling module of the present invention. Figure 5The timing reconstruction module of this invention calculates the optimal dead time and configures the timing interaction diagram of the underlying hardware; Figure 6 The timing interaction diagram for triggering transient intervention and performing cross-cycle pulse injection by the feedforward intervention module of the present invention; Figure 7 The timing interaction diagram for the boundary defense module of this invention performing core saturation defense and transient energy route redirection; Figure 8 The timing interaction diagram for the smooth transfer of control and integrator parameter reconstruction of the signal synthesis and steady-state takeover module of the present invention is shown below. Figure 9 This is a schematic diagram of the global time-frequency energy distribution of the multiphase DC-DC converter of the present invention during the entire process of implementing transient feedforward intervention and steady-state recovery. Detailed Implementation

[0028] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] See appendix Figure 1 This invention provides a high-power electrical appliance chip-based graded energy efficiency regulation and intelligent power supply optimization system, the system comprising: The parameter acquisition module synchronously acquires the input voltage, output voltage, total load current, and actual inductance current of each power supply phase during the high-speed electromagnetic sampling cycle, and synchronously acquires the physical node temperature of each power supply phase during the low-speed thermodynamic sampling cycle.

[0030] The matrix construction module extracts the output voltage change rate and current deviation from the data collected in the high-speed electromagnetic sampling cycle, uses the output voltage change rate and current deviation as orthogonal feature parameters, and encapsulates and integrates the orthogonal feature parameters with the physical node temperature collected in the low-speed thermodynamic sampling cycle into a state feature matrix.

[0031] The thermal equalization scheduling module extracts the physical node temperature from the state feature matrix to establish a mapping model and derives the actual impedance of each power supply phase inductor. It calculates the original current allocation weight based on the actual impedance, inputs the original current allocation weight into a digital low-pass filter to perform time-scale decoupling operation to obtain the smooth operation weight, and generates the asymmetric phase current command and the corresponding steady-state output duty cycle of each power supply based on the smooth operation weight.

[0032] The timing reconstruction module reads the asymmetric phase current command to establish a timing physical model and calculates the charging and discharging time of the equivalent parasitic capacitance of the driving half-bridge switching node. Based on the charging and discharging time of the equivalent parasitic capacitance of the driving half-bridge switching node, it dynamically adjusts and reconstructs the dead time parameters corresponding to each power supply phase driving half-bridge.

[0033] The feedforward intervention module extracts the output voltage change rate and current deviation from the state feature matrix and executes threshold condition comparison logic. When the output voltage change rate and current deviation simultaneously meet the preset threshold conditions, the power supply phase with the lowest physical node temperature is locked as the target phase, and asymmetric feedforward duty cycle pulses are injected into the target phase across cycles.

[0034] The boundary defense module initiates integration operations and calculates the cumulative volt-second product corresponding to the target in real time during the process of the feedforward intervention module injecting asymmetric feedforward duty cycle pulses into the target phase. When the cumulative volt-second product reaches the set volt-second product threshold for core saturation, the driving pulse corresponding to the target is cut off. The remaining unreleased compensation duty cycle is extracted to generate a redirection timing sequence, and the remaining compensation duty cycle is redirected and injected into the spare phase with the second lowest physical node temperature according to the redirection timing sequence.

[0035] The signal synthesis and steady-state takeover module receives the steady-state output duty cycle generated by the thermal equalization scheduling module, the dead-time parameters output by the timing reconstruction module, the asymmetric feedforward duty cycle output by the feedforward intervention module, and the residual compensation duty cycle and redirection timing output by the boundary defense module. It writes the steady-state output duty cycle of each power supply phase into the comparator register of the corresponding power supply phase and writes the dead-time parameters of each power supply phase into the dead-time register of the corresponding driving half-bridge. When a computing power step occurs, it replaces the control data in the comparator register of the target phase with the asymmetric feedforward duty cycle. The digital pulse width modulation peripheral performs carrier comparison and dead-time insertion processing based on the global time base counter, the control data in each comparator register, and the dead-time parameters in each dead-time register, generating multiple asymmetric pulse width modulation drive signals. Each asymmetric pulse width modulation drive signal is then output to the corresponding power supply phase drive half-bridge. The asymmetric pulse width modulation drive signal of the target phase channel is used to control the target phase to output asymmetric feedforward duty cycle pulses across cycles. After the boundary defense module generates the remaining compensation duty cycle and redirection timing, the remaining compensation duty cycle is written into the corresponding spare comparator register according to the redirection timing. This causes the digital pulse width modulation peripheral to update the multi-channel asymmetric pulse width modulation drive signal corresponding to the spare phase channel, and outputs the updated multi-channel asymmetric pulse width modulation drive signal to the corresponding spare drive half-bridge. The drive half-bridges corresponding to each power supply and the power switching transistors controlled by the drive half-bridges together constitute the external hardware power stage. After the transient intervention ends, a control switching instruction is issued to the underlying control logic, and a reset initial value is written to the integral accumulation register of the proportional-integral regulator of the voltage compensation outer loop. The values ​​of the bias integral accumulation registers of the current compensation inner loop corresponding to all power supplies are cleared to zero.

[0036] See appendix Figure 2 This invention provides a method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips, the method comprising the following steps: S1 divides the sampling period into microsecond-level and millisecond-level sampling periods in the underlying control logic, respectively collects the electromagnetic operating parameters and physical node temperature of the multiphase DC-DC converter, extracts the orthogonal features of voltage and current, and integrates the heterogeneous data to construct a state feature matrix. S2, extract the physical node temperature from the state feature matrix, calculate the actual impedance of each power supply phase under the current physical node temperature through the impedance mapping model, calculate the original current allocation weight based on the actual impedance, input the original current allocation weight into the digital low-pass filter to perform time-scale decoupling operation to obtain the smooth operation weight, combine the smooth operation weight to generate the asymmetric phase current command and output the steady-state output duty cycle corresponding to each power supply that has evolved smoothly. S3 receives the asymmetric phase current command, substitutes the asymmetric phase current command into the timing physical model of the underlying hardware switching node, calculates the theoretical optimal dead time for the charging and discharging time of the equivalent parasitic capacitance of the driving half-bridge switching node of each power supply phase, converts the theoretical optimal dead time into a dead time register count value, and writes the dead time register count value as a dead time parameter into the dead time register corresponding to each power supply phase driving half-bridge. S4. Extract the output voltage change rate and current deviation in the state feature matrix and perform numerical comparison with the preset voltage drop rate threshold and the preset current amplitude change threshold, respectively, and perform a logical AND operation. When the logical AND operation result indicates that a computing power step occurs, retrieve the current physical node temperature distribution, suspend the symmetrical phase shift clock sequence, calculate the asymmetric feedforward duty cycle required to inject the power supply phase with the lowest physical node temperature across cycles, synthesize multiple asymmetric pulse width modulation drive signals based on the steady-state output duty cycle, dead time parameters, and asymmetric feedforward duty cycle, and output the drive signals to the drive half bridge corresponding to the target to inject asymmetric feedforward duty cycle pulses into the target phase to perform charge feedforward compensation. S5, during the injection of asymmetric feedforward duty cycle pulses, the internal digital integrator is simultaneously started to accumulate the positive volt-second product across the inductor. When the accumulated volt-second product reaches the set volt-second product threshold for core saturation, the drive pulse corresponding to the target is cut off. The remaining unreleased compensation duty cycle is calculated and a redirection timing sequence is generated. The remaining compensation duty cycle is written into the corresponding comparator register of the second lowest physical node temperature according to the redirection timing sequence. This causes the digital pulse width modulation peripheral to update the multi-channel asymmetric pulse width modulation drive signal corresponding to the backup phase channel. The updated multi-channel asymmetric pulse width modulation drive signal is then output to the corresponding backup drive half-bridge to complete the redirection injection. S6, under transient conditions, the digital pulse width modulation peripheral writes the asymmetric feedforward duty cycle into the comparator register corresponding to the target to generate the target phase channel drive signal in the multi-channel asymmetric pulse width modulation drive signal; after the drive pulse of the target phase is truncated, the remaining compensation duty cycle is written into the spare corresponding comparator register according to the redirection timing to update the spare phase channel drive signal in the multi-channel asymmetric pulse width modulation drive signal. After the transient event termination condition is triggered, the register flags of the feedforward intervention module and the boundary defense module are cleared, control is switched back to the synchronous interleaved operation mode, and the initial reset value is written to the integral accumulation register of the proportional-integral regulator of the voltage compensation outer loop. The values ​​of the bias integral accumulation registers of the current compensation inner loop corresponding to all power supplies are cleared to zero.

[0037] See appendix Figure 3 In a specific implementation, step S1 of the present invention includes the following steps: S11, the underlying control logic uses the switching frequency of the multiphase DC-DC converter as a reference to set a high-speed electromagnetic sampling period in the microsecond range. The switching frequency of the multiphase DC-DC converter ranges from 300kHz to 1MHz. The high-speed electromagnetic sampling period built into the underlying control logic ranges from 1μs to 3.3μs. At the beginning of each switching cycle of the multiphase DC-DC converter, the parameter acquisition module synchronously acquires the input voltage, output voltage, total load current, and actual inductor current of each active power supply phase of the current hardware circuit through the analog-to-digital converter. The trigger timing settings of the analog-to-digital converter and the design of the analog signal conditioning circuit are configured in accordance with the digital signal processor peripheral manual.

[0038] S12, the matrix construction module performs processing operations on the data acquired in the high-speed electromagnetic sampling cycle and extracts the output voltage change rate as the first orthogonal feature parameter. The underlying control logic records the output voltage of the current sampling cycle and the output voltage of the previous sampling cycle and calculates the difference between the output voltage of the current sampling cycle and the output voltage of the previous sampling cycle. The underlying control logic divides the difference between the output voltage of the current sampling cycle and the output voltage of the previous sampling cycle by the time span of the switching cycle of the multiphase DC-DC converter to obtain the output voltage change rate. The time span of the switching cycle of the multiphase DC-DC converter is determined by the reciprocal of the switching frequency of the multiphase DC-DC converter. The underlying control logic generates an electrical parameter reference for the transient fluctuation of the total load through differential operation of two consecutive sampling cycles.

[0039] S13, the matrix construction module establishes a fixed-length sliding time window in the internal memory and extracts the total load current of multiple historical sampling periods in the sliding time window. The depth of the sliding time window is set to four to sixteen consecutive sampling points based on the time constant of the electromagnetic feedback main loop. The matrix construction module calculates the arithmetic mean of all total load currents in the sliding time window as the average load current. The matrix construction module subtracts the average load current from the total load current of the current period to obtain the current deviation. The matrix construction module uses the current deviation as the second orthogonal feature parameter and performs dual feature verification by combining the output voltage change rate and the current deviation.

[0040] S14, the underlying control logic sets a millisecond-level low-speed thermodynamic sampling period with a longer time span. The value range of the low-speed thermodynamic sampling period is 5ms to 50ms. The parameter acquisition module uses thermistors arranged at the bottom of the inductors of each power supply phase or temperature sensors integrated inside the intelligent power stage to synchronously acquire the physical node temperature of each power supply phase when the low-speed thermodynamic sampling period is triggered. The underlying control logic adopts an asynchronous sampling method to separate the acquisition of high-frequency electromagnetic data and low-frequency temperature data.

[0041] S15, the matrix construction module performs clock domain alignment operation on the heterogeneous electrical data acquired in the high-speed electromagnetic sampling cycle and the physical node temperature acquired in the low-speed thermodynamic sampling cycle according to the time occurrence sequence. In the microsecond-level period interval where the physical node temperature does not trigger a physical update, the underlying control logic maintains the register value of the physical node temperature constant through the zero-order hold module. The matrix construction module extracts the input voltage, output voltage, total load current, output voltage change rate, current deviation, actual inductor current of each power supply phase, and physical node temperature of each power supply phase as state feature elements. All state feature elements are combined into a multidimensional data set according to the preset dimension order. The multidimensional data set is combined into a state feature matrix containing global operating condition information.

[0042] See appendix Figure 4In a specific implementation, step S2 of the present invention includes the following steps: S21, the thermal equilibrium scheduling module extracts the physical node temperatures from the state feature matrix to establish an impedance mapping model. This model superimposes the nominal impedance value of the inductor coil at its nominal operating temperature onto the impedance increment corresponding to temperature changes. The nominal operating temperature range set internally by the underlying control logic is 20℃ to 30℃. When the conductive material inside the inductor coil is high-purity copper, the corresponding temperature coefficient of resistance ranges from 0.00385℃. -1 Up to 0.00405℃ -1 The thermal equalization scheduling module calculates the actual impedance of each power supply phase at the current physical node temperature based on the impedance mapping model. The formula for calculating the actual impedance is: ; In the formula, For the first The actual impedance of each power supply phase; This is the nominal impedance of the inductor at its nominal operating temperature; The temperature coefficient of resistance of the conductive material inside the inductor coil; For the first Temperature of the physical node corresponding to each power supply; The nominal operating temperature set internally by the system; This refers to the phase number of the independently powered phase in a multiphase DC-DC converter.

[0043] S22, the thermal equalization scheduling module receives the actual impedance of each power supply phase and performs asymmetric scheduling operations. The underlying control logic establishes an inverse proportional mapping mechanism between the current allocation weight of each power supply phase and the actual impedance. The thermal equalization scheduling module calculates the proportion of the reciprocal of the actual impedance of each power supply phase in the sum of the reciprocals of the actual impedances of all power supply phases and generates the original current allocation weight. The formula for calculating the original current allocation weight is: ; In the formula, For the first The original current allocation weights for each power supply phase; For the first The actual impedance of each power supply phase; For the first The actual impedance of each power supply phase; The total number of independent power supply phases within a multiphase DC-DC converter; The step index for performing the global impedance reciprocal summation operation; This refers to the phase number of the independently powered phase in a multiphase DC-DC converter.

[0044] S23, the thermal equalization scheduling module inputs the original current allocation weights into the digital low-pass filter to perform time-scale decoupling operations. The underlying control logic performs low-pass filtering smoothing operations on the control signal step amplitude caused by the low-speed thermodynamic loop data update in the microsecond-level electromagnetic loop. The operating clock of the digital low-pass filter is synchronized with the low-speed thermodynamic sampling period, i.e., discrete time step. The iteration is performed in millisecond intervals. The smoothing coefficient set in the digital low-pass filter ranges from 0.05 to 0.20. The thermal equalization scheduling module combines the smoothing weight of the previous discrete time step to output the smoothing weight of each power supply phase in the current discrete time step. The calculation formula for the smoothing weight is as follows: ; In the formula, For the current discrete time step ; For the previous discrete time step Smooth operation weight of each power supply phase; For the current discrete time step The original current allocation weights for each power supply phase; This is the filtering smoothing coefficient set in the digital low-pass filter; The discrete-time step index for the underlying digital control algorithm; This refers to the phase number of the independently powered phase in a multiphase DC-DC converter.

[0045] S24, the voltage compensation outer loop of the multiphase DC-DC converter outputs the reference duty cycle based on the difference between the output voltage and the target reference voltage. The thermal balance scheduling module multiplies the total load current with the smooth operation weight to calculate the asymmetrical phase current command for each power supply phase. The current compensation inner loop of the multiphase DC-DC converter calculates the bias duty cycle that acts independently on the corresponding power supply phase based on the difference between the asymmetrical phase current command and the actual inductor current of the corresponding power supply phase. The thermal balance scheduling module performs an arithmetic superposition operation on the reference duty cycle and the bias duty cycle to generate the steady-state output duty cycle for each power supply phase. The proportional-integral regulator parameters of the voltage compensation outer loop and the current compensation inner loop are configured in combination with control theory. The thermal balance scheduling module performs an arithmetic superposition operation to merge the voltage regulation data and the current distribution data into a control command.

[0046] See appendix Figure 5 In a specific implementation, step S3 of the present invention includes the following steps: S31, the timing reconstruction module receives the asymmetric phase current command allocated by the thermal equalization scheduling module and establishes a timing physical model. The underlying control logic extracts the drain-source equivalent parasitic capacitance parameters of the upper and lower bridge arm power switching transistors in each power supply phase, and superimposes the drain-source equivalent parasitic capacitance of the upper and lower bridge arm power switching transistors, as well as the additional parasitic capacitance of the driving half-bridge switching node, to obtain the equivalent parasitic capacitance of the driving half-bridge switching node of the corresponding power supply phase. Among them, the additional parasitic capacitance includes the parasitic capacitance of the printed circuit board traces and the parasitic capacitance of the inductor pins, which are obtained by extracting parasitic parameters through finite element electromagnetic simulation software, or set according to the empirical values ​​of the circuit hardware. S32, the timing reconstruction module calculates the optimal dead time for zero-voltage turn-on of each power supply phase in the multi-phase DC-DC converter based on the timing physical model. The timing reconstruction module directly eliminates the energy loss caused by the heat generation of the power switching transistor and the energy loss caused by the dead time error by accurately closing the parasitic capacitance charging and discharging cycle. The underlying control logic uses the input voltage as the voltage amplitude boundary crossed by the equivalent parasitic capacitance of the driving half-bridge switching node during the charging and discharging process. The value range of the equivalent parasitic capacitance of the driving half-bridge switching node is 0.2nF to 1.5nF, and the theoretical optimal dead time ranges from 15ns to 80ns. The timing reconstruction module multiplies the equivalent parasitic capacitance Csw of the driving half-bridge switching node with the input voltage to obtain the total charge transfer amount, and divides the total charge transfer amount by the actual inductor current of the corresponding power supply phase to obtain the theoretical optimal dead time. The timing reconstruction module sets a lower current safety threshold and a dead time safety limit range within the timing physical model. When the sampled actual inductor current is lower than the lower current safety threshold, the timing reconstruction module locks the dead time of the corresponding power supply phase to the upper limit extreme value of the dead time safety limit range. The theoretically optimal dead time is calculated using the following formula: ; In the formula, For the first The theoretically optimal dead time for driving a half-bridge in a power supply phase to achieve zero-voltage turn-on; ; The input voltage is recorded in the state feature matrix; For the first The actual inductor current flowing through each power supply phase; This refers to the phase number of the independently powered phase in a multiphase DC-DC converter.

[0047] S33, the timing reconstruction module obtains the theoretical optimal dead time of all power supply phases of the multiphase DC-DC converter and sends the data to the underlying hardware registers. The underlying control logic obtains the operating clock frequency of the internal digital pulse width modulation peripheral. The timing reconstruction module multiplies the theoretical optimal dead time by the operating clock frequency and performs a floor operation to obtain a dimensionless dead time register count value as the dead time parameter. The timing reconstruction module writes the count values ​​of each dead time register into the dead time register corresponding to each power supply phase drive half-bridge through the underlying data bus. The multiphase DC-DC converter synchronously changes the switching timing of the underlying hardware according to the data write operation results. The bit width of the dead time register in the digital pulse width modulation peripheral is configured according to application requirements.

[0048] See appendix Figure 6 In a specific implementation, step S4 of the present invention includes the following steps: S41, the feedforward intervention module extracts the output voltage change rate and current deviation in the state feature matrix in real time and performs a logical AND operation. The feedforward intervention module compares the output voltage change rate with the preset voltage drop rate threshold and the current deviation with the preset current amplitude change threshold. When the output voltage change rate shows a negative drop and its absolute value is greater than the voltage drop rate threshold, and the current deviation shows a positive sudden change and its value is greater than the current amplitude change threshold, the feedforward intervention module determines that the underlying hardware circuit has experienced a load surge-type computing power step. The voltage drop rate threshold is set according to the voltage tolerance window boundary of the power supply load, and the current amplitude change threshold is set according to the transient power consumption specification of the power supply load. The preset voltage drop rate threshold ranges from 0.5mV / μs to 3.5mV / μs, and the preset current amplitude change threshold ranges from 15A to 50A.

[0049] S42, after the feedforward intervention module determines that a computing power step has occurred in the underlying hardware circuit, it starts the target phase locking program. The feedforward intervention module traverses and retrieves the physical node temperature of each power supply phase recorded in the state feature matrix. The feedforward intervention module extracts the power supply phase with the lowest physical node temperature as the target phase through a numerical comparison algorithm. The feedforward intervention module generates a transient intervention trigger signal containing the target phase identifier and sends the transient intervention trigger signal to the underlying control logic. In this embodiment, the asymmetric feedforward duty cycle refers to the control parameter written into the comparator register corresponding to the target phase, used to limit the conduction time of the target phase drive half-bridge; the asymmetric feedforward duty cycle pulse refers to the actual pulse signal output by the target phase drive half-bridge according to the asymmetric feedforward duty cycle. The residual compensation duty cycle refers to the control parameter written into the comparator register corresponding to the spare phase, used to limit the conduction time of the spare phase redirection compensation.

[0050] S43, the feedforward intervention module receives the transient intervention trigger signal and calculates the charge feedforward compensation amount based on the physical parameters of the underlying hardware circuit. The nominal physical inductance value of the corresponding inductor element in all power supply phases in the active or alternative states ranges from 150nH to 470nH. The feedforward intervention module calculates the pulse width required for cross-cycle injection of the asymmetric feedforward duty cycle pulse based on the nominal physical inductance value of the target phase and the current deviation. The feedforward intervention module establishes a mapping equation between the inductor magnetization rate and the amount of compensation charge. The feedforward intervention module outputs the asymmetric feedforward duty cycle based on the mapping equation. The formula for calculating the asymmetric feedforward duty cycle is: ; In the formula, This refers to the asymmetric feedforward duty cycle injected across cycles into the comparator register corresponding to the target. The physical nominal inductance value of the inductor corresponding to the power supply phase that is locked as the target phase; The current deviation is recorded in the state feature matrix; The input voltage is recorded in the state feature matrix; The output voltage recorded in the state feature matrix; The switching cycle time span set for the operation of digital pulse width modulation peripherals.

[0051] S44, after the feedforward intervention module obtains the asymmetric feedforward duty cycle, it performs the operation of injecting the asymmetric feedforward duty cycle pulse into the target phase across cycles. The underlying control logic suspends the original symmetric phase shift clock sequence set by the digital pulse width modulation peripheral. The feedforward intervention module shields the phase interleaving waiting time of the steady-state clock cycle. The feedforward intervention module writes the asymmetric feedforward duty cycle as comparator control data into the comparator register corresponding to the target. The digital pulse width modulation peripheral updates the target phase channel drive signal in the multi-channel asymmetric pulse width modulation drive signal according to the asymmetric feedforward duty cycle, and outputs the target phase channel drive signal to the drive half-bridge of the target phase. The drive half-bridge of the target phase conducts according to the written asymmetric feedforward duty cycle and outputs the asymmetric feedforward duty cycle pulse.

[0052] See appendix Figure 7 In a specific implementation, step S5 of the present invention includes the following steps: S51, during the process of receiving asymmetric feedforward duty cycle pulse injection in the target phase, the boundary defense module starts the internal digital integrator to observe the positive volt-second product across the inductor of the target phase. The boundary defense module extracts the input voltage and output voltage from the state feature matrix and calculates the difference between the input voltage and the output voltage as the positive voltage drop of the inductor. The boundary defense module captures the rising edge interrupt flag of the corresponding channel of the target phase in the digital pulse width modulation peripheral as the start time, and multiplies the positive voltage drop of the inductor with the real-time conduction time of the target phase driving half bridge from the start time of cross-cycle injection to calculate the cumulative volt-second product of the target phase.

[0053] S52, the boundary defense module establishes a volt-second product threshold model for inductor core saturation by combining the physical material properties and structural parameters of the inductor element. The underlying control logic extracts the core cross-sectional area, number of coil turns, and saturation magnetic flux density constant from the power inductor datasheet as physical reference parameters. When the inductor core material is ferrite or a soft magnetic alloy, the corresponding saturation magnetic flux density constant ranges from 0.35T to 0.65T. The volt-second product threshold for core saturation, which is composed of the product of multiple physical reference parameters, ranges from 2.5V·μs to 8.0V·μs. The boundary defense module uses the product of the physical reference parameters as the volt-second product threshold for core saturation. The boundary defense module performs a numerical comparison between the cumulative volt-second product calculated in real time and the volt-second product threshold for core saturation, and outputs a saturation defense protection signal to the digital pulse width modulation peripheral when the cumulative volt-second product reaches the volt-second product threshold for core saturation.

[0054] S53, after outputting the saturation defense protection signal, the boundary defense module uses the underlying hardware time-limit comparator to issue a pulse truncation command. The digital pulse width modulation peripheral resets the corresponding drive register of the target and turns off the power switching transistor of the target phase according to the pulse truncation command. The underlying control logic synchronously records the executed conduction time at the instant of pulse truncation and divides the executed conduction time by the time span of the switching cycle set when the digital pulse width modulation peripheral is working to obtain the actual executed duty cycle. The boundary defense module subtracts the actual executed duty cycle from the asymmetric feedforward duty cycle calculated by the feedforward intervention module to obtain the remaining compensation duty cycle. The formula for calculating the remaining compensation duty cycle is: ; In the formula, The remaining compensation duty cycle corresponding to the energy not fully released after the target phase is truncated; This refers to the asymmetric feedforward duty cycle injected across cycles into the comparator register corresponding to the target. The target phase has already been turned on at the instant the saturation defense protection signal is triggered; The switching cycle time span set for the operation of digital pulse width modulation peripherals.

[0055] S54, after obtaining the remaining compensation duty cycle, the boundary defense module starts the transient energy routing redirection program. The boundary defense module reads the physical node temperature vector of each power supply phase in the state feature matrix and removes the target phase that is currently experiencing pulse truncation. Among the remaining power supply phases, the boundary defense module extracts the power supply phase with the lowest current physical node temperature as the backup phase with the second lowest physical node temperature through numerical comparison. The boundary defense module generates the redirection timing sequence and writes the remaining compensation duty cycle into the corresponding comparator register of the backup phase according to the redirection timing sequence. This enables the digital pulse width modulation peripheral to update the backup phase channel drive signal in the multi-channel asymmetric pulse width modulation drive signal according to the remaining compensation duty cycle in the corresponding comparator register of the backup phase. The updated backup phase channel drive signal is then output to the corresponding backup drive half-bridge according to the redirection timing sequence, thus completing the redirection injection. When all power supply phases trigger the saturation defense protection signal, the underlying control logic suspends the transient energy routing redirection program and throws a global hardware overload interrupt prompt.

[0056] See appendix Figure 8 In a specific implementation, step S6 of the present invention includes the following steps: S61, when the boundary defense module completes all transient energy routing redirection operations and the current deviation in the state feature matrix falls back to within the preset current amplitude change threshold, the signal synthesis and steady-state takeover module initiates the smooth handover procedure. The signal synthesis and steady-state takeover module issues a control switching instruction to the underlying control logic. The underlying control logic releases the suspended state of the symmetrical phase-shift clock sequence of the digital pulse width modulation peripheral according to the control switching instruction. The global time base counter inside the digital pulse width modulation peripheral aligns the corresponding drive half-bridge reference carrier phase according to the clock synchronization signal. The operating architecture of the multiphase DC-DC converter switches from asynchronous cross-cycle intervention mode to synchronous interleaved operation mode according to the smooth handover procedure.

[0057] S62, when the signal synthesis and steady-state takeover module switches to the synchronous interleaved operation mode, it extracts the output voltage recorded in the state feature matrix. The signal synthesis and steady-state takeover module then starts the underlying integrator parameter reconstruction program. The target reference voltage for the high-power electrical chip is in the range of 0.6V to 1.5V, and the proportional coefficient of the proportional-integral regulator inside the voltage compensation outer loop is in the range of 0.02 to 0.18. The signal synthesis and steady-state takeover module divides the set target reference voltage by the input voltage recorded in the state feature matrix to obtain the theoretical steady-state duty cycle. The signal synthesis and steady-state takeover module subtracts the product of the difference between the target reference voltage and the output voltage and the proportional coefficient of the voltage compensation outer loop from the theoretical steady-state duty cycle to obtain the reset initial value of the integral accumulator register of the proportional-integral regulator in the voltage compensation outer loop. The formula for calculating the reset initial value is: ; In the formula, This is the initial value to be reset for the internal integral accumulation register of the voltage compensation outer loop during the instantaneous switch from asynchronous intervention back to steady-state interleaved operation; The theoretical steady-state duty cycle is derived based on the feedforward derivation of the macroscopic input-output ratio of the actual power supply network. This refers to the proportional coefficient of the proportional-integral regulator in the voltage compensation outer loop; The target reference voltage set by the underlying control logic for the output closed-loop feedback; The output voltage is recorded in the state feature matrix.

[0058] S63, the signal synthesis and steady-state takeover module resets the initial value and writes it into the integral accumulator register of the proportional-integral regulator of the voltage compensation outer loop via the data bus. The signal synthesis and steady-state takeover module simultaneously clears the values ​​of the bias integral accumulator registers of the current compensation inner loop corresponding to all power supplies. The voltage compensation outer loop and the current compensation inner loop combine the updated values ​​of each integral accumulator register to take over the generation logic of the steady-state output duty cycle of the multiphase DC-DC converter. The underlying control logic continues to maintain a microsecond-level high-speed electromagnetic sampling period and a millisecond-level low-speed thermodynamic sampling period based on the preset hardware switching frequency. The high-power electrical chip graded energy efficiency regulation and intelligent power supply optimization system enters a digital closed-loop control process that combines steady-state thermal balance distribution and transient boundary defense.

[0059] See attached document Figure 9 To aid in understanding the technical solution of this invention, the following is an application example of a method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips: Under steady-state operation, the parameter acquisition module synchronously acquires electromagnetic parameters and the physical node temperature of each power supply phase. The thermal equalization scheduling module derives the actual impedance of each power supply phase based on the physical node temperature distribution of each power supply phase. The thermal equalization scheduling module adjusts the original current allocation weight of each power supply phase based on the actual impedance. The thermal equalization scheduling module inputs the original current allocation weight into the digital low-pass filter to perform time-scale decoupling operation and generate the steady-state output duty cycle corresponding to each power supply. The timing reconstruction module reads the asymmetric phase current command and calculates the theoretical optimal dead time corresponding to each power supply by combining the equivalent parasitic capacitance parameters of the driving half-bridge switching node. The timing reconstruction module converts the theoretical optimal dead time into dead time parameters and writes them into the dead time register corresponding to the driving half-bridge of each power supply phase. When a step change in the total load current causes a change in the output voltage, the feedforward intervention module extracts the output voltage change rate and current deviation. When both the output voltage change rate and current deviation simultaneously exceed a preset threshold, the feedforward intervention module determines that a computing power step has occurred in the underlying hardware circuit. After determining that a computing power step has occurred in the underlying hardware circuit, the feedforward intervention module suspends the symmetrical phase-shift clock sequence corresponding to the digital pulse width modulation peripheral. The feedforward intervention module retrieves the physical node temperature vector and locks the power supply phase with the lowest current physical node temperature as the target phase. The feedforward intervention module masks the phase interleaving wait time of the steady-state clock cycle and... The asymmetric feedforward duty cycle value is calculated by combining the physical nominal inductance value of the target phase with the current deviation. The feedforward intervention module writes the asymmetric feedforward duty cycle value across cycles into the comparator register corresponding to the target. The digital pulse width modulation peripheral updates the target phase channel drive signal in the multi-channel asymmetric pulse width modulation drive signal according to the asymmetric feedforward duty cycle in the target phase comparator register, the dead time parameter corresponding to the target, and the carrier count value of the global time base counter. The target phase channel drive signal is then output to the drive half-bridge corresponding to the target to trigger the asymmetric feedforward duty cycle pulse. During the asymmetric feedforward duty cycle pulse injection process of the target phase, the boundary defense module activates a digital integrator to accumulate the cumulative volt-second product across the inductor of the target phase. When the cumulative volt-second product of the target phase reaches the set volt-second product threshold for core saturation, the boundary defense module issues a pulse truncation command using a low-level hardware time comparator. The digital pulse width modulation peripheral shuts down the power switching transistor of the target phase and truncates the corresponding drive pulse according to the pulse truncation command. The boundary defense module subtracts the actual executed duty cycle from the asymmetric feedforward duty cycle calculated by the feedforward intervention module to obtain the remaining compensation duty cycle. The boundary defense module then activates transient energy... The routing redirection procedure removes the target phase where pulse truncation occurs from the physical node temperature vector. The boundary defense module extracts the power supply phase with the lowest physical node temperature among the remaining power supply phases as the backup phase through numerical comparison. The boundary defense module generates the redirection timing sequence and writes the remaining compensation duty cycle into the corresponding comparator register of the backup phase according to the redirection timing sequence. The digital pulse width modulation peripheral generates the backup phase channel drive signal according to the updated backup phase comparator register data and outputs the backup phase channel drive signal to the corresponding backup drive half-bridge according to the redirection timing sequence to complete the redirection injection of the remaining compensation duty cycle. When the boundary defense module completes the redirection injection operation and the current deviation falls back to within the preset current amplitude change threshold, the signal synthesis and steady-state takeover module issues a control switching command to the underlying control logic. The underlying control logic releases the suspended state of the symmetrical phase-shift clock sequence and uses the global time base counter to align the reference carrier phase corresponding to each power supply. The system operating architecture switches from asynchronous cross-cycle intervention mode to synchronous interleaved operation mode. When switching to synchronous interleaved operation mode, the signal synthesis and steady-state takeover module extracts the input voltage and target reference voltage to derive the theoretical steady-state duty cycle. The signal synthesis and steady-state takeover module uses the theoretical steady-state duty cycle combined with the proportional coefficient of the proportional-integral regulator to derive the reset initial value of the integral accumulator register. The signal synthesis and steady-state takeover module writes the reset initial value to the integral accumulator register of the proportional-integral regulator of the voltage compensation outer loop. The signal synthesis and steady-state takeover module simultaneously clears the values ​​of the bias integral accumulator registers of the current compensation inner loop corresponding to all power supplies to zero. The high-power electrical chip graded energy efficiency regulation and intelligent power supply optimization system resumes the execution of the steady-state closed-loop control process.

[0060] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can omit, substitute, and modify the details of the above methods and systems in various ways without departing from the principles and essence of the present invention. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result using substantially the same method falls within the scope of the present invention.

Claims

1. A method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips, characterized in that, The method includes the following steps: Electromagnetic operating parameters including input voltage, output voltage, and actual inductance current of the power supply phase, as well as physical node temperature, are collected. The output voltage change rate and current deviation in the electromagnetic operating parameters are extracted and integrated with the physical node temperature into a state feature matrix. Extract the physical node temperature to derive the actual impedance and calculate the smooth operation weight, thereby generating the asymmetric phase current command and steady-state output duty cycle; extract the input voltage and the actual inductor current to calculate the dead time parameter. When a computing power step occurs, based on the output voltage change rate and the current deviation, the power supply phase with the lowest physical node temperature in the state feature matrix is ​​locked as the target phase. The asymmetric feedforward duty cycle is calculated based on the input voltage, the output voltage, and the preset nominal inductance value. Based on the steady-state output duty cycle, the dead time parameter, and the asymmetric feedforward duty cycle, a multi-channel asymmetric pulse width modulation drive signal is synthesized to inject the corresponding asymmetric feedforward duty cycle pulse into the target phase. Calculate the cumulative volt-second product of the target phase, and when the cumulative volt-second product reaches the threshold, truncate the asymmetric feedforward duty cycle pulse, extract the remaining compensation duty cycle, and locate the power supply phase with the second lowest temperature of the physical node as the spare phase to generate the redirection timing. The remaining compensation duty cycle is written into the register of the spare phase according to the redirection timing, and the multi-channel asymmetric pulse width modulation drive signal is updated to be injected into the spare phase.

2. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 1, characterized in that, The steps for extracting the output voltage change rate and current deviation from the electromagnetic operating parameters include: The input voltage, output voltage, total load current, and actual inductor current of each power supply phase of the current hardware circuit are synchronously collected during a high-speed electromagnetic sampling period at the microsecond level as electromagnetic operating parameters. Record the output voltage of the current sampling period and the output voltage of the previous sampling period and calculate the difference between the two. Divide the difference by the time span of the switching cycle to calculate the output voltage change rate. A sliding time window is established in the internal memory, and the total load current of multiple historical sampling periods in the sliding time window is extracted. The arithmetic mean of all the total load currents is calculated as the average load current. The current deviation is obtained by subtracting the average load current from the total load current of the current period.

3. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 2, characterized in that, The steps include integrating the physical node temperature into a state feature matrix: The temperature of the physical node is simultaneously acquired during a low-speed thermodynamic sampling period on the order of milliseconds. The acquired input voltage, output voltage, total load current, actual inductor current, and physical node temperature are clock-domain aligned according to the time sequence. The aligned input voltage, output voltage, total load current, actual inductor current, physical node temperature, output voltage change rate, and current deviation are extracted as state feature elements, and all state feature elements are combined into the state feature matrix according to a preset dimensional order.

4. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 3, characterized in that, The steps for extracting the physical node temperature to derive the actual impedance and calculating the smoothing operation weights include: An impedance mapping model is established, which superimposes the nominal impedance value of the inductor coil at the nominal operating temperature with the impedance increment obtained from the temperature change corresponding to the physical node temperature, and derives the actual impedance. Calculate the proportion of the reciprocal of the actual impedance of each power supply phase in the sum of the reciprocals of the actual impedances of all power supply phases and generate the original current allocation weights; The original current allocation weights are input into a digital low-pass filter to perform time-scale decoupling operations. Combined with the smoothing operation weights of the previous discrete time step, the smoothing operation weights corresponding to each power supply in the current discrete time step are output.

5. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 4, characterized in that, The steps for generating the asymmetric phase current command and steady-state output duty cycle accordingly include: The voltage compensation outer loop calculates the reference duty cycle based on the difference between the output voltage and the target reference voltage. The asymmetric phase current command is calculated by multiplying the total load current by the smooth operation weight. The bias duty cycle is calculated using the difference between the asymmetrical phase current command and the actual inductor current through the current compensation inner loop. The steady-state output duty cycle is generated by performing an arithmetic superposition operation on the reference duty cycle and the bias duty cycle.

6. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 5, characterized in that, The steps for extracting the input voltage and the actual inductor current to calculate the dead time parameters include: Extract the drain-source equivalent parasitic capacitance parameters of the upper and lower bridge arm power switching transistors in the driving half-bridge, and determine the equivalent parasitic capacitance by combining the additional parasitic capacitance of the switching node. A constant current charge-discharge equation for the equivalent parasitic capacitance is constructed based on the input voltage, and the total charge transfer is obtained by multiplying the equivalent parasitic capacitance by the input voltage. The theoretical optimal dead time is obtained by dividing the total charge transfer amount by the actual inductor current of the corresponding power supply phase. The theoretical optimal dead time is then multiplied by the operating clock frequency and rounded down to obtain the dead time register count value as the dead time parameter.

7. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 6, characterized in that, When a computing power step occurs, based on the output voltage change rate and the current deviation, the power supply phase with the lowest physical node temperature in the state feature matrix is ​​identified as the target phase. The asymmetric feedforward duty cycle is calculated using the input voltage, the output voltage, and the preset nominal inductance value. The steps include: When the output voltage change rate shows a negative drop and its absolute value is greater than a preset voltage drop rate threshold, and the current deviation shows a positive sudden change and its value is greater than a preset current amplitude change threshold, it is determined that a load surge type computing power step has occurred. After determining that the computing power step has occurred, the physical node temperature in the state feature matrix is ​​retrieved, the lowest power supply phase is locked as the target phase, and the pulse width required for cross-cycle injection is calculated by combining the nominal inductance value, the current deviation, the input voltage, the output voltage and the set switching cycle time span, and the asymmetric feedforward duty cycle is output. The asymmetric feedforward duty cycle is written into the register corresponding to the target, and the driving half-bridge of the target phase is controlled to turn on to generate the corresponding asymmetric feedforward duty cycle pulse.

8. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 7, characterized in that, Calculating the cumulative volt-second product of the target phase, and truncating the asymmetric feedforward duty cycle pulse when the cumulative volt-second product reaches a threshold, includes the following steps: The difference between the input voltage and the output voltage is calculated as the inductor forward voltage drop. The inductor forward voltage drop is multiplied by the real-time conduction time of the target phase driven half-bridge to calculate the cumulative volt-second product. The threshold is obtained by multiplying the cross-sectional area of ​​the magnetic core, the number of coil turns, and the constant saturation magnetic induction. When the accumulated volt-second product reaches the threshold, a saturation defense protection signal is output, and the power switching transistor of the target phase is turned off by a pulse truncation command, thereby trunculating the asymmetric feedforward duty cycle pulse.

9. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 8, characterized in that, The steps include: extracting the remaining compensation duty cycle and identifying the power supply phase with the second lowest temperature at the physical node as the spare phase to generate a redirection timing sequence. The actual executed duty cycle is derived by recording the executed conduction time corresponding to the instant the pulse is cut off. The remaining compensation duty cycle that has not been released is calculated by subtracting the actual executed duty cycle from the asymmetric feedforward duty cycle. After removing the target phase that is currently experiencing pulse interruption, retrieve the physical node temperature of the remaining power supply phases, and extract the power supply phase with the lowest current temperature as the backup phase; The redirection timing is generated according to the following rules: the original steady-state interleaved conduction time of the backup phase channel is forcibly suspended, and the conduction command is immediately triggered to the backup phase channel at the moment when the target phase pulse is cut off, taking the moment as the starting point; and the remaining compensation duty cycle is written into the corresponding register of the backup phase according to the redirection timing to complete the redirection injection.

10. The method for graded energy efficiency regulation and intelligent power supply optimization of high-power electrical appliance chips according to claim 9, characterized in that, After writing the remaining compensation duty cycle into the corresponding spare register according to the redirection timing to complete the redirection injection, the steps further include: When the redirection injection operation is completed and the current deviation falls back to within the preset current amplitude change threshold, a control switching command is sent to the underlying control logic to switch back to the synchronous interleaved operation mode. Extract the difference between the output voltage and the set target reference voltage recorded in the state feature matrix, and divide the target reference voltage by the input voltage to obtain the theoretical steady-state duty cycle; The initial reset value of the integral accumulator register of the proportional-integral regulator is obtained by subtracting the product of the difference between the target reference voltage and the output voltage and the proportional coefficient of the proportional-integral regulator in the voltage compensation outer loop from the theoretical steady-state duty cycle. Write the initial reset value to the integral accumulator register, and clear the values ​​of the current compensation inner loop bias integral accumulator registers corresponding to all power supplies to zero.

Images