A control method and device for suppressing narrow pulses of a three-level inverter

Abstract

The application discloses a control method and device for inhibiting narrow pulses of a three-level inverter. The method comprises the following steps: obtaining a reference voltage vector, calculating basic small vector action time T1 and effective vector action time T2 and T3, and correcting based on error integral of the last period; identifying narrow pulses of T1, executing zero setting or processing of widening to minimum reliable pulse width, distributing time difference according to original proportion of T2 and T3 to maintain the direction of the resultant vector; generating seven-segment SVPWM comparison value or gate driving signal according to the processed time and midpoint balance factor; calculating the difference between ideal action time and final output action time and updating error integral for compensation in the next period. The device comprises functional modules for realizing the above method. The application can inhibit narrow pulses while maintaining the direction of output voltage vector, compensating for volt-second error and taking into account the midpoint potential adjustment ability.

Description

Technical Field

[0001] This invention relates to the technical field of inverter modulation control, and in particular to a control method and apparatus for suppressing narrow pulses in a three-level inverter. Background Technology

[0002] Three-level inverters are widely used in high-voltage, high-power motor drive systems due to their advantages such as small output voltage step, good harmonic performance, and low voltage stress on power devices. In space vector pulse width modulation (SVPWM) control, a hardware dead time is required to avoid bridge arm shoot-through. Simultaneously, power devices are limited by their physical characteristics, with minimum reliable turn-on and turn-off times. Under conditions such as low speed, light load, and low modulation ratio, the vector action time calculated by the SVPWM algorithm may be too short, resulting in a final output pulse width smaller than the minimum reliable pulse width allowed by the power device, i.e., a narrow pulse. Narrow pulses cannot be reliably executed by the power device, causing the actual output voltage to deviate from the command value, leading to problems such as increased current harmonics, commutation overvoltage, and increased stress on the power device.

[0003] For a three-level inverter, redundant small vectors not only participate in the synthesis of the reference voltage vector, but also play a role in midpoint potential regulation. If the duration of the small vector that generates the narrow pulse is directly deleted, although the narrow pulse can be eliminated, the corresponding volt-second area will be lost, causing the amplitude and direction of the synthesized vector to deviate, and the midpoint potential regulation capability will be lost. If the narrow pulse is simply widened and the corresponding time is deducted from other effective vectors, the original vector's action ratio may be changed, causing the synthesized vector's direction to shift and affecting the output current waveform quality. In addition, when the reference voltage vector crosses the sector boundary, the bridge arm mapping relationship of each vector changes, and simple cross-cycle compensation or pulse shifting strategies may cause incorrect time allocation. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the existing technology, the purpose of this invention is to solve the technical problem that it is difficult to simultaneously suppress narrow pulses, maintain the output voltage vector direction, and adjust the midpoint potential. This invention provides a control method and device for suppressing narrow pulses in a three-level inverter, which can eliminate narrow pulses, maintain the synthesized vector direction, compensate for volt-second errors, and protect the midpoint potential adjustment capability.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A control method for suppressing narrow pulses in a three-level inverter includes the following steps:

[0007] 1) Obtain the reference voltage vector for the current PWM cycle, determine the large and small sectors where the reference voltage vector is located, and calculate the duration T1 of the basic small vector and the durations T2 and T3 of the two effective vectors;

[0008] 2) Based on the Sigma-Delta error integral value saved in the previous PWM cycle, T1, T2 and T3 are corrected to obtain the target action time of this cycle;

[0009] 3) Perform narrow pulse identification on T1. When T1 is in the preset narrow pulse range, perform zeroing or widening to the minimum reliable pulse width on T1 to obtain the basic small vector action time T1′.

[0010] 4) Calculate the time difference ΔPool=T1−T1′ generated by the process, and allocate the time difference to T2 and T3 according to the original ratio of T2 and T3 to obtain T2′ and T3′;

[0011] 5) Generate a seven-segment SVPWM comparison value or gate drive signal based on T1′, T2′, T3′ and the midpoint balance factor k;

[0012] 6) Calculate the difference between T1, T2, T3 obtained in step 1) and the final output T1′, T2′, T3′, update the Sigma-Delta error integral and save it for compensation in the next PWM cycle.

[0013] In this way, by acquiring the reference voltage vector and calculating the basic small vector action time T1 and the effective vector action times T2 and T3, the error integral amount saved in the previous cycle is used to correct the above times before narrow pulse identification. Only T1 is zeroed or widened, eliminating the conditions for narrow pulse generation from the source. The time difference generated by the processing is distributed according to the original ratio of T2 and T3, so that the ratio of T2 to T3 remains unchanged, thereby maintaining the direction of spatial vector synthesis determined by T2 and T3, avoiding the problems of output voltage vector direction deviation and current harmonic increase caused by narrow pulse processing. By calculating the difference between the ideal action time and the final output action time and updating the error integral amount for the next cycle compensation, the volt-second error of this cycle is not lost, achieving accurate volt-second balance in the average sense of multiple PWM cycles. Finally, a seven-segment SVPWM comparison value or gate drive signal is generated, which suppresses narrow pulses while taking into account the accuracy of output voltage vector direction and volt-second error compensation.

[0014] Furthermore, the correction described in step 2) includes:

[0015] When a change in the number of the triangular region formed by the combination of large and small sectors is detected, the Sigma-Delta error integral value saved in the previous PWM cycle is cleared.

[0016] When the triangular region number formed by the combination of large and small sectors is detected to be unchanged, the Sigma-Delta error integral amount saved in the previous PWM cycle is superimposed on T1, T2, and T3.

[0017] In this way, the processing avoids the error integral of the old sector being incorrectly applied to the new sector due to changes in the mapping relationship of each vector bridge arm during sector switching, thus ensuring the accuracy of error compensation during cross-sector switching.

[0018] Furthermore, in step 3), when T1 is greater than zero and less than the preset minimum basic vector action time, it is determined that T1 is in the preset narrow pulse interval;

[0019] If T1 is less than the preset zero threshold, then T1 is set to zero;

[0020] If T1 is greater than or equal to the preset zero threshold, then T1 will be expanded to the preset minimum base vector action time;

[0021] The preset zero threshold is less than the preset minimum base vector action time.

[0022] In this way, by comparing T1 with the preset minimum base vector action time to determine whether it is in a narrow pulse range, and further distinguishing between zeroing and widening processing according to the preset zero threshold, where the zeroing threshold is less than the minimum base vector action time; this distinction process allows T1 to be directly zeroed to completely eliminate the narrow pulse when it is too small and widening cannot be reliably executed; when T1 is a narrow pulse but can be reliably executed after widening, the vector action is retained, thereby minimizing the impact on the output voltage waveform within safety constraints.

[0023] Furthermore, a hysteresis loop is introduced during the narrow pulse identification of T1 in step 3):

[0024] When T1 enters the preset narrow pulse interval from the decreasing direction, the first preset zero threshold is used for judgment;

[0025] When T1 exits the preset narrow pulse interval from the increasing direction, the second preset zero threshold is used for judgment;

[0026] The second preset zero threshold is greater than the first preset zero threshold.

[0027] In this way, the hysteresis mechanism prevents T1 from frequently switching between zeroing and broadening modes due to small disturbances near the threshold boundary, thus enhancing the stability and engineering practicality of the control.

[0028] Furthermore, step 4) involves allocating the time difference to T2 and T3 according to the original ratio of T2 to T3, including:

[0029] When T2+T3 is non-zero, T2 and T3 are corrected according to T2′=T2+ΔPool×T2 / (T2+T3) and T3′=T3+ΔPool×T3 / (T2+T3);

[0030] When T2+T3 is zero, ΔPool is allocated entirely to the non-zero term in either T2 or T3;

[0031] When T2′ or T3′ becomes negative after proportional allocation, the item with the negative value is set to zero, the other item absorbs the entire ΔPool, and the value after absorption is limited to ensure that it does not exceed the remaining available time.

[0032] In this way, the ratio of T2 to T3 remains strictly constant, thereby maintaining the direction of spatial vector synthesis determined by T2 and T3. Only the vector amplitude is slightly adjusted, minimizing the impact of narrow pulse processing on the output current waveform quality. Boundary processing covers the time allocation requirements under extreme operating conditions, ensuring that the ΔPool allocation logic can be executed correctly under various operating conditions and will not cause output voltage runaway due to allocation overflow.

[0033] Furthermore, after step 4), the process also includes: normalizing T1′, T2′, and T3′ so that the sum of the three is equal to the PWM period; in step 6), the Sigma-Delta error integral is updated by using the difference between the target action time before normalization and the output action time after normalization as the error increment, which is carried over to the next PWM period for compensation.

[0034] In this way, the normalization process ensures that the sum of the final output T1′, T2′, and T3′ is strictly equal to the PWM period Ts, guaranteeing that the output duty cycle does not exceed 1 and avoiding modulation failure due to time overflow. The time compression caused by normalization is automatically recovered through the Sigma-Delta error integration mechanism. When updating the error integration, the difference between the target action time before normalization and the output action time after normalization is used as the error increment and carried over to the next PWM cycle for compensation. This achieves complete volt-second balance in a multi-cycle average sense, and the volt-second area of ​​normalization compression is not lost.

[0035] Further, the update of the Sigma-Delta error integral in step 6) is performed according to the following formula:

[0036] errTx(k+1)=sat[Tx_ideal(k)+errTx(k)−Tx_output(k)]

[0037] Where x∈{1,2,3}, Tx_ideal(k) is the ideal action time before narrow pulse processing in the k-th PWM cycle, Tx_output(k) is the final output action time in the k-th PWM cycle, errTx(k) is the Sigma-Delta error integral stored in the k-th PWM cycle, and sat[·] is the anti-saturation limiting function.

[0038] In this way, the formula records the historical volt-second error of each vector by independent integration in three channels, and prevents the integral from being too large by limiting the amplitude, so that each vector can independently obtain accurate error compensation in subsequent cycles, and finally achieve complete volt-second balance in the average sense of multiple PWM cycles.

[0039] Further, in step 5), the midpoint balance factor k is obtained in the following way:

[0040] Obtain the original adjustment factor k_in output by the midpoint balance controller;

[0041] Based on the processed basic small vector action time T1′, the pulse widths of the two types of single-sided small vectors in the seven-segment SVPWM are pre-calculated as T01=(1+k_in)×T1′ / 4 and T02=(1−k_in)×T1′ / 4;

[0042] When T01 or T02 is non-zero and less than the minimum single-sided pulse width limit, if k_in is positive, the midpoint balance factor k_out of the final output will be clamped to +1; if k_in is negative, k_out will be clamped to -1.

[0043] When both T01 and T02 are zero or both are greater than or equal to the minimum single-sided pulse width limit, k_out = k_in is maintained.

[0044] When T1′ is zero, set k_out to zero;

[0045] k_out serves as the midpoint balancing factor k, and k_out is only used to generate the SVPWM comparison value for the current PWM cycle.

[0046] In this way, the clamping protection retains the midpoint potential regulation capability to the maximum extent within the safety constraints of the power device, while avoiding controller integral saturation or regulation oscillation caused by k_out feedback.

[0047] Furthermore, the three-level inverter is a midpoint clamped three-level inverter or a T-type three-level inverter.

[0048] In this way, the control method is clearly applicable to midpoint clamped three-level inverters or T-type three-level inverters. Both of these topologies have the functions of split DC bus, midpoint potential and redundant small vector distribution, which can fully implement all the steps of this method and achieve the corresponding technical effects.

[0049] The present invention also includes a control device for suppressing narrow pulses in a three-level inverter, comprising a reference voltage input module, a sector detection module, a vector time calculation module, a narrow pulse identification module, a time difference allocation module, a Sigma-Delta error integration module, a midpoint balance constraint module, and a PWM output module; each module is configured to execute the control method described above.

[0050] Compared with the prior art, the present invention has the following advantages:

[0051] 1. The control method for suppressing narrow pulses in a three-level inverter described in this invention only performs narrow pulse identification and zeroing or widening processing on the basic small vector T1, eliminating narrow pulses from the source; the generated time difference is allocated according to the original ratio of T2 and T3, keeping the ratio of the action time of the two vectors unchanged, thereby maintaining the direction of spatial vector synthesis and avoiding output voltage direction deviation and current waveform distortion caused by narrow pulse processing.

[0052] 2. The control method for suppressing narrow pulses in a three-level inverter described in this invention calculates the difference between the ideal action time and the final output action time, and uses an error integration mechanism to carry over the volt-second error of the current cycle to subsequent PWM cycles for compensation. This restores the vector average volt-second balance across multiple PWM cycle scales, reducing the impact of narrow pulse processing on the long-term accuracy of the output voltage.

[0053] 3. The control method for suppressing narrow pulses in a three-level inverter described in this invention pre-calculates the midpoint balance factor k. When continuous distribution will generate non-zero narrow pulses, k is clamped to +1 or -1 to cancel the corresponding side pulse. Within the safety constraint boundary of the power device, the adjustment capability of the midpoint potential is preserved to the maximum extent, thereby achieving coordinated control of narrow pulse suppression and midpoint balance. Attached Figure Description

[0054] To make the purpose, technical solution, and advantages of the invention clearer, the invention will now be described in further detail with reference to the accompanying drawings:

[0055] Figure 1 This is a schematic diagram of the three-level inverter system described in the embodiment;

[0056] Figure 2 This is an overall flowchart of the control method described in the embodiment;

[0057] Figure 3 This is a schematic diagram illustrating the preprocessing of narrow pulses in the embodiment;

[0058] Figure 4 This is a schematic diagram of the k-factor allocation relationship after narrow pulse preprocessing in the embodiment. Detailed Implementation

[0059] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0061] Example 1:

[0062] Please see Figure 1 The figure illustrates the structure of a three-level inverter system applicable to the control method described in this embodiment. The three-level inverter includes a first capacitor C1 and a second capacitor C2 connected in series between the positive terminal P and the negative terminal N of the DC bus, and the connection point of the two capacitors constitutes the midpoint O. Three-phase bridge arms are connected in parallel between the P terminal, the O terminal and the N terminal, and each phase bridge arm includes multiple power switching devices and corresponding freewheeling diodes. The three-level inverter can be a midpoint clamped three-level inverter, a T-type three-level inverter, or other three-level topology structures with split DC bus, midpoint potential and redundant small vector distribution functions.

[0063] Please see Figure 2 The control method for suppressing narrow pulses in a three-level inverter according to the present invention includes the following steps:

[0064] 1) Obtain the reference voltage vector and determine the sector;

[0065] This method is executed by the inverter's controller (e.g., DSP or FPGA), which receives a reference voltage vector command from the motor drive upper-level control algorithm (e.g., vector control). This vector is defined by the components Vα and Vβ in the α-β coordinate system. Based on the magnitude and phase relationship of Vα and Vβ, the large sector number N (N takes the value 1 to 6) and the small sector number n (n takes the value 1 to 6 or other subdivision values) of the current reference voltage vector are determined.

[0066] Large and small sectors combine to form a unique triangular region number; when the triangular region number changes compared to the previous PWM cycle, the Sigma-Delta error integral value saved in the previous cycle is cleared; when the triangular region number does not change, the Sigma-Delta error integral value is retained for later superposition.

[0067] The Sigma-Delta error integration refers to an error compensation mechanism that accumulates the difference between the ideal action time and the final output action time of the current PWM cycle, and feeds back and superimposes the difference to the action time of subsequent PWM cycles, whose working principle is similar to the error feedback loop in a Sigma-Delta modulator.

[0068] 2) Calculate the ideal vector action times T1, T2, and T3;

[0069] The ideal action time of each vector is calculated using the volt-second balance principle according to the vector combination corresponding to the triangular region where the reference voltage vector is located; wherein, the action time of the basic small vector is denoted as T1, and the action times of the other two active vectors participating in the synthesis of the reference voltage vector are denoted as T2 and T3 respectively; T1 corresponds to the total action time of the basic small vectors distributed at the start, end and middle positions of the switching sequence in the seven-segment SVPWM.

[0070] 3) Superimpose the Sigma-Delta error integration amount;

[0071] The Sigma-Delta error integration amounts errT1, errT2, and errT3 of the three vectors respectively calculated and saved in the previous PWM cycle are superimposed on the corresponding ideal action times T1, T2, and T3 of the current cycle to obtain the target action time of the current cycle; this superimposition operation enables the historical volt-second error to be compensated in the current cycle.

[0072] 4) Narrow pulse identification and processing for the basic small vector action time T1;

[0073] As shown in Figure 3 , the target action time T1 obtained in step S3 is compared with a preset narrow pulse interval, where the upper bound of the preset narrow pulse interval is the preset minimum basic vector action time T_min, and the lower bound is zero; the specific operations are as follows:

[0074] When T1 is greater than zero and less than T_min, it is determined to be in a narrow pulse state;

[0075] Further, T1 is compared with the preset zero-setting threshold T_th: if T1 < T_th, a zero-setting process is performed on T1, so that T1′=0; if T1 ≥ T_th, a widening process is performed on T1, so that T1′=T_min; wherein the preset zero-setting threshold T_th is less than the preset minimum basic vector action time T_min.

[0076] When T1 is not less than T_min, no narrow pulse processing is required, and T1′ remains as T1.

[0077] As a preferred option, a hysteresis mechanism can be introduced into the above judgment logic: when T1 decreases from a larger value and enters the narrow pulse interval, the first zero threshold T_th1 is used for judgment; when T1 increases from a smaller value and exits the narrow pulse interval, the second zero threshold T_th2 is used for judgment, T_th2=T_th1+ΔT_hys; ΔT_hys is the preset hysteresis width. This hysteresis mechanism can effectively prevent T1 from frequently switching modes due to small disturbances near the threshold boundary.

[0078] 5) Calculate the time difference ΔPool and allocate it proportionally;

[0079] Calculate the time difference ΔPool=T1−T1′ between the action time of the basic small vector before and after narrow pulse processing;

[0080] When ΔPool is positive, it means that T1 is set to zero or shortened to release allocable time; when ΔPool is negative, it means that T1 is widened and needs to borrow time from other vectors.

[0081] The goal of this step is to allocate ΔPool to T2 and T3;

[0082] When T2+T3 is not zero, the distribution is made according to the original ratio of T2 and T3: T2′=T2+ΔPool×T2 / (T2+T3), T3′=T3+ΔPool×T3 / (T2+T3);

[0083] This proportional allocation method keeps the ratio of T2 to T3 constant, thereby maintaining the direction of the spatial vector synthesis determined by T2 and T3, with only a slight adjustment in amplitude. This design minimizes the impact of narrow pulse processing on the direction of the output voltage vector, which helps maintain the quality of the output current waveform.

[0084] When T2+T3 is zero, ΔPool is allocated to the non-zero term in T2 or T3. When T2′ or T3′ becomes negative after proportional allocation, the term with the negative value is set to zero, and the other term absorbs all ΔPool according to its original time as a proportion of T2+T3, and the absorbed value is limited to ensure that it does not exceed the remaining available time in the PWM cycle.

[0085] 6) Narrow pulse protection with midpoint balance factor k;

[0086] After completing the T1 narrow pulse preprocessing and ΔPool allocation, the processed basic small vector action time T1′ is obtained; the midpoint balance controller independently calculates and outputs the original adjustment factor k_in based on the midpoint capacitor voltage deviation and phase current direction;

[0087] like Figure 4As shown, narrow pulse protection is performed before using k_in to generate the PWM compare value:

[0088] First, pre-calculate the two types of single-sided small vector pulse widths in the seven-segment SVPWM: T01=(1+k_in)×T1′ / 4, T02=(1−k_in)×T1′ / 4; then, determine the midpoint balance factor k_out of the final output based on the pre-calculation results.

[0089] When either T01 or T02 is non-zero and less than the minimum single-sided pulse width limit T_pulse_min, it indicates that using k_in would result in an unreliable narrow pulse on one side. In this case, if k_in is positive, k_out is clamped to +1, canceling the pulse on the T02 side; if k_in is negative, k_out is clamped to -1, canceling the pulse on the T01 side. This clamping operation eliminates narrow pulses while maintaining the maximum pulse width on the side that is not canceled, thereby maximizing the regulation effect of the midpoint potential within the safety constraint boundary.

[0090] When both T01 and T02 are zero or not less than T_pulse_min, it means that the allocation of k_in will not generate narrow pulses, and k_out = k_in is kept, thus fully preserving the adjustment intention of the midpoint balance controller.

[0091] When T1′ is zero, the basic small vector does not participate in the work of this cycle, so let k_out be zero.

[0092] It should be noted that k_out is only used to replace k_in to generate the SVPWM comparison value for this PWM cycle, and does not feed back to the state update stage of the midpoint balance controller; this means that the midpoint balance controller always "senses" its own output k_in, and will not produce integral saturation or regulation oscillation due to the forced clamping of the pulse level.

[0093] 7) Generate and output the SVPWM comparison value;

[0094] Based on the final determined basic small vector action time T1′, effective vector action times T2′ and T3′, and midpoint balance factor k_out, the PWM comparison values ​​of each phase bridge arm are generated according to the switching sequence rules of the seven-segment SVPWM, written into the timer comparison register, and gate drive signals are generated to control the on / off state of the power switching devices.

[0095] 8) Update the Sigma-Delta error integral;

[0096] Calculate the difference between the ideal action time and the final output action time of each of the three vectors in this cycle, and update the Sigma-Delta error integral: errTx(k+1)=sat[Tx_ideal(k)+errTx(k)−Tx_output(k)];

[0097] Where x∈{1,2,3}, Tx_ideal(k) is the ideal action time before narrow pulse processing calculated by step S2 in the k-th PWM cycle, Tx_output(k) is the final output action time determined by steps 5) and 6) in the k-th PWM cycle, errTx(k) is the Sigma-Delta error integral amount saved in the k-th PWM cycle, errTx(k+1) is the updated Sigma-Delta error integral amount, and sat[·] is the anti-saturation limiting function, used to prevent the integral amount from being too large and exceeding the reasonable range.

[0098] The updated three Sigma-Delta error integrals are saved and superimposed on the ideal action time of the corresponding vector in step S3 of the next PWM cycle. Through this Sigma-Delta error integration mechanism, the volt-second error of this cycle is not lost, but is gradually compensated in subsequent cycles, thereby achieving accurate volt-second balance in the average sense of multiple PWM cycles.

[0099] 9) Execute in a loop;

[0100] Return to step 1) and proceed to the processing flow of the next PWM cycle; the above steps are executed once or twice in each PWM switching cycle.

[0101] Example 2:

[0102] This embodiment provides a control device for eliminating narrow pulses in a three-level inverter. The device includes a reference voltage input module, a sector detection module, a vector time calculation module, a narrow pulse identification module, a time difference allocation module, a Sigma-Delta error integration module, a midpoint balance constraint module, and a PWM output module.

[0103] The reference voltage input module receives the reference voltage vector command output by the upper-level control algorithm; the sector detection module determines the current large or small sector based on the reference voltage vector; the vector time calculation module calculates the ideal basic small vector action time T1 and the effective vector action times T2 and T3, and superimposes the Sigma-Delta error integral to obtain the target action time; the narrow pulse identification module identifies narrow pulses in T1 and performs zeroing or widening to the minimum reliable pulse width; the time difference allocation module calculates the time difference ΔPool and allocates it proportionally to T2 and T3; the midpoint balance constraint module obtains the original adjustment factor k_in output by the midpoint balance controller, performs single-sided pulse width pre-calculation based on T1′, and clamps k_out to +1 or −1 when necessary; the Sigma-Delta error integral module calculates the difference between the ideal action time and the final output action time and updates the Sigma-Delta error integral; the PWM output module generates a seven-segment SVPWM comparison value or gate drive signal based on T1′, T2′, T3′ and k_out.

[0104] The functions of the above modules correspond to the detailed description of steps 1) to 9) in Embodiment 1, and will not be repeated here; the above modules can be implemented by microcontrollers, digital signal processors, FPGAs, application-specific integrated circuits or combinations thereof.

[0105] In summary, this invention eliminates the conditions for narrow pulse generation at their source by identifying and zeroing or widening only the basic small vector action time T1; it maintains the direction of the synthesized vector by distributing the time difference according to the original ratio of T2 to T3; it achieves precise volt-second balance across multiple PWM cycle scales by carrying over the volt-second error of the current cycle to subsequent cycles through an error integration mechanism; and it maximizes the adjustment capability of the midpoint potential within the safety constraints of power devices by pre-calculating the midpoint balance factor k and providing endpoint clamping protection. The synergistic effect of these techniques effectively solves the problem of simultaneously addressing narrow pulse suppression, vector direction maintenance, volt-second error compensation, and midpoint potential adjustment.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A control method for suppressing narrow pulses in a three-level inverter, characterized in that: Includes the following steps: 1) Obtain the reference voltage vector for the current PWM cycle, determine the large and small sectors where the reference voltage vector is located, and calculate the duration T1 of the basic small vector and the durations T2 and T3 of the two effective vectors; 2) Based on the Sigma-Delta error integral value saved in the previous PWM cycle, T1, T2 and T3 are corrected to obtain the target action time of this cycle; 3) Perform narrow pulse identification on T1. When T1 is in the preset narrow pulse range, perform zeroing or widening to the minimum reliable pulse width on T1 to obtain the basic small vector action time T1′. 4) Calculate the time difference ΔPool=T1−T1′ generated by the process, and allocate the time difference to T2 and T3 according to the original ratio of T2 and T3 to obtain T2′ and T3′; 5) Generate a seven-segment SVPWM comparison value or gate drive signal based on T1′, T2′, T3′ and the midpoint balance factor k; 6) Calculate the difference between T1, T2, T3 obtained in step 1) and the final output T1′, T2′, T3′, update the Sigma-Delta error integral and save it for compensation in the next PWM cycle.

2. The control method for suppressing narrow pulses in a three-level inverter according to claim 1, characterized in that: The corrections described in step 2) include: When a change in the number of the triangular region formed by the combination of large and small sectors is detected, the Sigma-Delta error integral value saved in the previous PWM cycle is cleared. When the triangular region number formed by the combination of large and small sectors is detected to be unchanged, the Sigma-Delta error integral amount saved in the previous PWM cycle is superimposed on T1, T2, and T3.

3. The control method for suppressing narrow pulses in a three-level inverter according to claim 1, characterized in that: In step 3), when T1 is greater than zero and less than the preset minimum base vector action time, it is determined that T1 is in the preset narrow pulse interval; If T1 is less than the preset zero threshold, then T1 is set to zero; If T1 is greater than or equal to the preset zero threshold, then T1 will be expanded to the preset minimum base vector action time; The preset zero threshold is less than the preset minimum base vector action time.

4. The control method for suppressing narrow pulses in a three-level inverter according to claim 3, characterized in that: In step 3), a hysteresis loop is introduced during the narrow pulse identification of T1: When T1 enters the preset narrow pulse interval from the decreasing direction, the first preset zero threshold is used for judgment; When T1 exits the preset narrow pulse interval from the increasing direction, the second preset zero threshold is used for judgment; The second preset zero threshold is greater than the first preset zero threshold.

5. The control method for suppressing narrow pulses in a three-level inverter according to claim 1, characterized in that: Step 4) describes the operation of allocating the time difference to T2 and T3 according to the original ratio of T2 to T3, which includes: When T2+T3 is non-zero, T2 and T3 are corrected according to T2′=T2+ΔPool×T2 / (T2+T3) and T3′=T3+ΔPool×T3 / (T2+T3); When T2+T3 is zero, ΔPool is allocated entirely to the non-zero term in either T2 or T3; When T2′ or T3′ becomes negative after proportional allocation, the item with the negative value is set to zero, the other item absorbs the entire ΔPool, and the value after absorption is limited to ensure that it does not exceed the remaining available time.

6. The control method for suppressing narrow pulses in a three-level inverter according to claim 5, characterized in that: Step 4) is followed by: normalizing T1′, T2′, and T3′ so that the sum of the three is equal to the PWM period; in step 6), the Sigma-Delta error integral is updated by using the difference between the target action time before normalization and the output action time after normalization as the error increment, which is carried over to the next PWM period for compensation.

7. The control method for suppressing narrow pulses in a three-level inverter according to claim 1, characterized in that: The update of the Sigma-Delta error integral in step 6) is performed according to the following formula: errTx(k+1)=sat[Tx_ideal(k)+errTx(k)−Tx_output(k)] Where x∈{1,2,3}, Tx_ideal(k) is the ideal action time before narrow pulse processing in the k-th PWM cycle, Tx_output(k) is the final output action time in the k-th PWM cycle, errTx(k) is the Sigma-Delta error integral stored in the k-th PWM cycle, and sat[·] is the anti-saturation limiting function.

8. The control method for suppressing narrow pulses in a three-level inverter according to claim 1, characterized in that: In step 5), the midpoint balance factor k is obtained in the following way: Obtain the original adjustment factor k_in output by the midpoint balance controller; Based on the processed basic small vector action time T1′, the pulse widths of the two types of single-sided small vectors in the seven-segment SVPWM are pre-calculated as T01=(1+k_in)×T1′ / 4 and T02=(1−k_in)×T1′ / 4; When T01 or T02 is non-zero and less than the minimum single-sided pulse width limit, if k_in is positive, the midpoint balance factor k_out of the final output will be clamped to +1; if k_in is negative, k_out will be clamped to -1. When both T01 and T02 are zero or both are greater than or equal to the minimum single-sided pulse width limit, k_out = k_in is maintained. When T1′ is zero, set k_out to zero; k_out serves as the midpoint balancing factor k, and k_out is only used to generate the SVPWM comparison value for the current PWM cycle.

9. The control method according to claim 1, characterized in that, The three-level inverter is a midpoint clamped three-level inverter or a T-type three-level inverter.

10. A control device for suppressing narrow pulses in a three-level inverter, characterized in that: It includes a reference voltage input module, a sector detection module, a vector time calculation module, a narrow pulse identification module, a time difference allocation module, a Sigma-Delta error integration module, a midpoint balance constraint module, and a PWM output module; each module is configured to execute the control method as described in any one of claims 1-9.

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