Power supply chip, driving system and voltage processing method

Abstract

The present disclosure provides a power supply chip, a driving system and a voltage processing method, which can be applied to the technical field of power supply. The power supply chip can comprise: a control circuit; a dual-mode inverter, configured to work in a half-bridge inversion mode or a full-bridge inversion mode under the control of the control circuit, and to invert an input voltage received via an input voltage terminal in the half-bridge inversion mode or the full-bridge inversion mode to generate an oscillating power signal; a transformer, connected between the dual-mode inverter and a double-voltage three-output rectifier, and configured to transform the oscillating power signal into a transformed oscillating power signal; the double-voltage three-output rectifier, configured to rectify the transformed oscillating power signal under the control of the control circuit to generate a first positive voltage, a second positive voltage and a negative voltage; and a compensation circuit, configured to selectively compensate voltage fluctuation of the second positive voltage by using the first positive voltage or the negative voltage under the control of the control circuit in the case that the second positive voltage has voltage fluctuation.

Description

Technical Field

[0001] This disclosure relates to the field of power supply technology, specifically to a power chip, a drive system, and a voltage processing method. Background Technology

[0002] In applications such as motor drives, photovoltaic inverters, uninterruptible power supplies (UPS), and traction inverters for electric vehicles (EVs) and hybrid electric vehicles (EHVs), power devices such as insulated-gate bipolar transistors (IGBTs) and silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are widely used. Based on this, a drive system needs to be designed to control the conduction of these power devices. The drive system may include a power supply. To meet the power requirements of other devices in the drive system (such as the gate drivers used to control the conduction of the aforementioned power devices), this power supply needs to simultaneously output a relatively high positive voltage (e.g., 15V), a relatively low positive voltage (e.g., 5V), and a negative voltage (e.g., -5V). However, power supplies used to simultaneously output these three voltages in related drive systems often struggle to achieve a balance between low cost, high integration, high energy conversion efficiency, high compatibility, and high stability. Summary of the Invention

[0003] In view of this, the present disclosure provides a power supply chip, a driving system, and a voltage processing method.

[0004] One aspect of this disclosure provides a power chip for use in a drive system. The drive system includes a target power device and a gate driver and a monitoring circuit electrically connected to the target power device. The power chip includes: a control circuit; a dual-mode inverter electrically connected to an input voltage terminal and the control circuit, for operating in half-bridge inverter mode or full-bridge inverter mode under the control of the control circuit, inverting the input voltage received via the input voltage terminal in half-bridge inverter mode or full-bridge inverter mode to generate an oscillating power signal; and a transformer connected between the dual-mode inverter and a double-voltage triple-output rectifier for transforming the oscillating power signal into a transformed oscillating power signal and outputting the transformed signal to the double-voltage triple-output rectifier. The oscillating power signal is used to transmit AC power between the dual-mode inverter and the double-voltage triple-output rectifier. The double-voltage triple-output rectifier is also electrically connected to the control circuit, the gate driver, and the monitoring circuit. Under the control of the control circuit, it rectifies the transformed oscillating power signal to generate a first positive voltage, a second positive voltage, and a negative voltage. The first positive voltage and the negative voltage are used to power the gate driver, and the second positive voltage is used to power the monitoring circuit. The compensation circuit is electrically connected to the double-voltage triple-output rectifier and the control circuit. Under the control of the control circuit, it selectively uses the first positive voltage or the negative voltage to compensate for the voltage fluctuation of the second positive voltage when there is a voltage fluctuation in the second positive voltage.

[0005] Another aspect of this disclosure provides a drive system comprising: a target power device, a gate driver electrically connected to the target power device, a monitoring circuit electrically connected to the target power device, and the aforementioned power chip.

[0006] Another aspect of this disclosure provides a voltage processing method, comprising: a dual-mode inverter operating in half-bridge inverter mode or full-bridge inverter mode under the control of a control circuit, wherein in half-bridge inverter mode or full-bridge inverter mode, an input voltage received via an input voltage terminal is inverted to generate an oscillating power signal; a transformer transforms the oscillating power signal; a double-voltage triple-output rectifier, under the control of the control circuit, rectifies the transformed oscillating power signal to generate a first positive voltage, a second positive voltage, and a negative voltage, wherein the first positive voltage and the negative voltage are used to power a gate driver, and the second positive voltage is used to power a monitoring circuit; and a compensation circuit, under the control of the control circuit, selectively uses the first positive voltage or the negative voltage to compensate for voltage fluctuations in the second positive voltage when voltage fluctuations exist in the second positive voltage; wherein the first positive voltage is higher than the second positive voltage.

[0007] According to embodiments of this disclosure, a driving circuit is provided. In this driving circuit, a dual-mode inverter can operate in half-bridge inverter mode or full-bridge inverter mode under the control of a control circuit, and can invert different input voltages into corresponding oscillation frequency signals in different inverter modes. A transformer can transform the oscillation frequency signals. A double-voltage three-output rectifier can rectify the transformed oscillation frequency signals corresponding to different input voltages under the control of the control circuit, generating a first positive voltage, a second positive voltage, and a negative voltage. A compensation circuit can selectively use the first positive voltage or the negative voltage to compensate for voltage fluctuations in the second positive voltage under the control of the control circuit. Thus, the double-voltage three-output rectifier of this disclosure can stably power the gate driver using a relatively high first positive voltage while stably powering low-voltage circuits such as the monitoring circuit using a relatively low second positive voltage, achieving stable three-level output including the negative voltage with minimal resource consumption. Therefore, the power chip of this disclosure has advantages such as high integration, high energy conversion efficiency, and high stability while consuming fewer manufacturing resources and thus having a low-cost advantage.

[0008] Furthermore, since the driving circuit of this embodiment is compatible with different input voltages, it can achieve high-efficiency energy transfer under input voltages such as 12V or 24V. Therefore, the power chip of this embodiment also has high compatibility with different input voltages. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings, which will be explained in conjunction with the drawings.

[0010] Figure 1 A schematic diagram of a drive system according to an embodiment of the present disclosure is shown.

[0011] Figure 2 A schematic diagram of a power supply chip according to an embodiment of the present disclosure is shown.

[0012] Figure 3 A schematic diagram of a power supply chip according to another embodiment of the present disclosure is shown.

[0013] Figure 4 A schematic diagram of a first mode according to an embodiment of the present disclosure is shown.

[0014] Figure 5 A schematic diagram of a second mode according to an embodiment of the present disclosure is shown.

[0015] Figure 6 A schematic diagram of a third mode according to an embodiment of the present disclosure is shown.

[0016] Figure 7 A schematic diagram of a fourth mode according to an embodiment of the present disclosure is shown.

[0017] Figure 8 The diagram schematically illustrates the waveform of the output voltage when switching modes in a first manner according to an embodiment of the present disclosure.

[0018] Figure 9 The diagram schematically illustrates the waveform of the output voltage when switching modes in a second manner according to an embodiment of the present disclosure.

[0019] Figure 10 A schematic diagram of a drive system according to another embodiment of the present disclosure is shown.

[0020] Figure 11 A schematic diagram of a voltage processing method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0021] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0023] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0024] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0025] In applications such as motor drives, photovoltaic inverters, uninterruptible power supplies (UPS), electric vehicles (EVs), and traction inverters for hybrid vehicles (EHVs), a large number of power devices such as insulated gate bipolar transistors (IGBTs) and silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFETs) are required.

[0026] On the one hand, the voltage required for these power devices to turn on is usually above 15V in order to make the on-resistance small enough and thus obtain ideal switching characteristics. Therefore, a bias voltage of about 15V is required for the gate driver of IGBT and SiC MOSFET.

[0027] On the other hand, due to Miller crosstalk and quiescent current, the gate driver needs to provide a -5V bias voltage when the power device is turned off to avoid false turn-on caused by crosstalk and reduce quiescent current. Furthermore, to prevent power device failure under extreme conditions such as overload and short circuit, the gate driver also needs to be equipped with a series of monitoring circuits and signal feedback circuits with fast response capabilities. These circuits are typically powered by a 5V low-voltage power supply. Therefore, the power supply used to power the gate driver needs to have 15V, 5V, and -5V voltage rails. These voltage rails are usually powered by the low-voltage side. Since the aforementioned bias power supply is connected between the low-voltage side and the high-voltage side where the power device is located, without isolation, it will affect the normal operation of sensitive equipment on the low-voltage side and threaten personal safety.

[0028] Based on this, to achieve the aforementioned multiple voltage rails, some solutions typically require two or more isolated power supplies or other switching power supplies for the gate driver power supply system. This not only increases the overall system cost but also hinders system integration. Furthermore, electric vehicles have two different power supply requirements on the low-voltage side: 12V and 24V. Therefore, it is usually necessary to manufacture various models of isolated power supplies to meet these different voltage requirements.

[0029] For example, in some solutions based on isolated power supplies, two independent isolated power supplies are required to provide sufficient voltage rails, resulting in higher system costs and greater structural complexity. Non-isolated power supplies are less expensive than isolated power supplies, leading to the development of other solutions. In other solutions based on non-isolated power supplies, replacing low-voltage isolated power supplies with non-isolated power supplies (such as low-dropout linear regulators or switching power supplies) can reduce system costs.

[0030] While this solution eliminates the need for a low-voltage isolated power supply, it still requires an additional non-isolated power supply. Whether using a low-dropout linear regulator or a switching power supply, both lead to increased system cost and reduced integration; furthermore, the additional power supply stage increases system power losses. In addition, this type of solution includes various high-voltage isolated power supplies to accommodate different input voltages.

[0031] In another set of designs, the power supply can only provide a 15V positive voltage and a -5V negative voltage, but cannot provide a 5V positive voltage. In yet another set of designs, dual outputs of 15V positive voltage and 5V positive voltage can be achieved, but the 15V positive voltage and 5V positive voltage share the same ground plane, and a negative voltage output cannot be provided to meet the negative voltage requirements of the gate driver; moreover, this rectifier requires six power transistors, increasing the cost of the circuit.

[0032] Based on the above, since the power supply used to power the gate driver in related technologies cannot achieve a stable output of three voltages: 15V positive, 5V positive, and -5V negative, the drive system based on the gate driver requires additional power supply devices to power the digital isolator and monitoring circuit, which increases the cost of the drive system. Furthermore, a single power supply is difficult to simultaneously support 12V and 24V voltage inputs.

[0033] In view of this, embodiments of this disclosure propose a drive system including a gate driver. The drive system also includes a single-transformer, three-output power supply chip based on a double-rectifier topology. This power supply chip can simultaneously achieve stable outputs including a 15V positive voltage, a 5V positive voltage, and a -5V negative voltage to power the gate driver and low-voltage circuitry. Furthermore, the power supply chip can employ a dual-mode inverter to be compatible with different input voltages, achieving high-efficiency energy transfer at both 12V and 24V input levels.

[0034] Figure 1 A schematic diagram of a drive system according to an embodiment of the present disclosure is shown.

[0035] like Figure 1 As shown, the driving system of this embodiment may include a power supply chip, a gate driver, and a monitoring circuit.

[0036] In this embodiment, the gate driver and monitoring circuitry can be electrically connected to the target power device. For example, the gate driver can be electrically connected to the gate of the target power device to control the turn-on or turn-off of the target power device under the control of a drive signal. For example, the target power device may include an N-type IGBT, but it should be understood that the target power device in this embodiment may also include other power devices, which will not be elaborated here. The monitoring circuitry can be connected to the source or drain of the target power device to monitor the current flowing through the target power device to avoid short circuits or overload conditions.

[0037] The input voltage terminal of the power supply chip can be used to receive input voltage. The first output terminal of the power supply chip can be electrically connected to the first power supply terminal of the gate driver. The third output terminal of the power supply chip can be electrically connected to the second power supply terminal of the gate driver. The second output terminal of the power supply chip can be electrically connected to the power supply terminal of the monitoring circuit. Furthermore, the monitoring circuit can also be connected to ground, which will not be elaborated further.

[0038] For example, the power supply chip can process the input voltage, outputting a first positive voltage via a first output terminal, a second positive voltage via a second output terminal, and a negative voltage via a third output terminal. The first positive and negative voltages can be used to power the gate driver. The second positive voltage can be used to power the monitoring circuit. For example, the first positive voltage could be 15V. The second positive voltage could be 5V. The negative voltage could be -5V.

[0039] In some embodiments, the second positive voltage can also power other devices in the drive system. For example, the drive system in this disclosure embodiment may further include a digital isolator, which can be used to transmit drive signals and monitoring signals between the low-voltage battery side and the high-voltage battery side. The power supply terminal of the digital isolator can be electrically connected to the second output terminal of the power chip so that the second positive voltage powers the digital isolator.

[0040] In this embodiment, the power chip is also compatible with different input voltages, such as 12V and 24V input voltages. The following description, in conjunction with the accompanying drawings, provides a detailed explanation.

[0041] Figure 2 A schematic diagram of a power supply chip according to an embodiment of the present disclosure is shown.

[0042] like Figure 2As shown, the power chip in this embodiment may include a control circuit, a dual-mode inverter, a transformer, and a double-voltage triple-output rectifier.

[0043] A dual-mode inverter can be electrically connected to the input voltage terminal and the control circuit. Under the control of the mode control signal of the control circuit, the dual-mode inverter can operate in either half-bridge inverter mode or full-bridge inverter mode. Thus, in either half-bridge or full-bridge inverter mode, the dual-mode inverter can receive a DC input voltage via the input voltage terminal and invert the input voltage to generate a differential oscillating power signal.

[0044] For example, with an input voltage of, for example, 12V, the dual-mode inverter can operate in half-bridge inverter mode. With an input voltage of, for example, 24V, the dual-mode inverter can operate in full-bridge inverter mode. That is, when the input voltage is low, the output voltage is close to twice the input voltage, and the power supply chip requires high gain, the dual-mode inverter operates in full-bridge inverter mode; when the power supply chip input level is high, the output voltage is close to the input voltage, and the power supply chip requires low gain, the dual-mode inverter can operate in half-bridge inverter mode, thus enabling the power supply chip to be compatible with different input levels. For example, the dual-mode inverter can be used to achieve two inverter levels: 12V to 20V and 24V to 20V, but it is not limited to these. Taking 12V to 20V as an example, the 20V can be based on the voltage difference between a first positive voltage and a negative voltage. Other cases are similar and will not be elaborated further.

[0045] The transformer is electrically connected to both the dual-mode inverter and the double-voltage triple-output rectifier. In this way, the transformer can transform the oscillating power signal into a transformed oscillating power signal and output the transformed oscillating power signal to the double-voltage triple-output rectifier to transmit AC power between the dual-mode inverter and the double-voltage triple-output rectifier.

[0046] The double-voltage triple-output rectifier can also be electrically connected to a control circuit, a gate driver, and a monitoring circuit. The double-voltage triple-output rectifier receives a transformed oscillating power signal from a transformer and, under the control of the rectification control signal of the control circuit, rectifies the transformed oscillating power signal to generate a first positive voltage, a second positive voltage, and a negative voltage. The first positive voltage, the second positive voltage, and the negative voltage can be DC voltages. For example, the double-voltage triple-output rectifier has a first output terminal, a second output terminal, and a third output terminal. The first and third output terminals are electrically connected to the first and second voltage terminals of the gate driver, respectively, and the second output terminal is electrically connected to the voltage terminal of the monitoring circuit. The first output terminal is used to output the first positive voltage, the second output terminal is used to output the second positive voltage, and the third output terminal is used to output the negative voltage.

[0047] However, in the above-described scheme, since low-voltage circuits such as monitoring circuits and digital isolators, which operate at lower voltages, require stronger power supply stability compared to gate drivers operating at higher voltages, the power chip in this embodiment may further include a compensation circuit. The compensation circuit may be electrically connected to a double-voltage triple-output rectifier and a control circuit. When voltage fluctuations exist in the second positive voltage, the compensation circuit, under the control of a compensation control signal from the control circuit, can selectively use either a first positive voltage or a negative voltage to compensate for the voltage fluctuations in the second positive voltage. For example, if the second positive voltage is higher than a predetermined value (e.g., 5V), the compensation circuit can use a negative voltage to compensate for the second positive voltage. If the second positive voltage is lower than a predetermined value (e.g., 5V), the compensation circuit can use the first positive voltage to compensate for the second positive voltage. In this way, the second positive voltage can be stabilized with less resource consumption, achieving a balance between the stability of the second positive voltage and resource consumption.

[0048] Based on this, in the embodiments of this disclosure, the dual-mode inverter can operate in half-bridge inverter mode or full-bridge inverter mode under the control of the control circuit, and can invert different input voltages into corresponding oscillation frequency signals in different inverter modes. A transformer can transform the oscillation frequency signals. A double-voltage three-output rectifier can rectify the transformed oscillation frequency signals corresponding to different input voltages under the control of the control circuit, generating a first positive voltage, a second positive voltage, and a negative voltage. A compensation circuit can selectively use the first positive voltage or the negative voltage to compensate for voltage fluctuations in the second positive voltage under the control of the control circuit. Thus, the double-voltage three-output rectifier of this disclosure can stably power the gate driver using a relatively high first positive voltage while stably powering low-voltage circuits such as the monitoring circuit using a relatively low second positive voltage, achieving stable three-level output including the negative voltage with minimal resource consumption. Therefore, the power chip of this disclosure has advantages such as high integration, high energy conversion efficiency, and high stability, while consuming fewer manufacturing resources and thus having a low-cost advantage.

[0049] Furthermore, since the driving circuit of this embodiment is compatible with different input voltages, it can achieve high-efficiency energy transfer under input voltages such as 12V or 24V. Therefore, the power chip of this embodiment also has high compatibility with different input voltages.

[0050] Figure 3 A schematic diagram of a power supply chip according to another embodiment of the present disclosure is shown.

[0051] like Figure 3 As shown, the power chip in this embodiment may include a dual-mode inverter, a transformer, and a double-voltage triple-output rectifier.

[0052] In this embodiment, the control circuit further includes a transmitter controller and a receiver controller. The transmitter controller can be used to control the dual-mode inverter. The receiver controller can be used to control the double-voltage triple-output rectifier.

[0053] The transformer may include a primary coil L1 and a secondary coil L2 coupled to each other. The primary positive terminal VPP and the primary negative terminal VPN of the primary coil L1 are electrically connected to a dual-mode inverter to receive an oscillating power signal and can couple the oscillating power signal to the secondary coil L2 to transform the oscillating power signal into a transformed oscillating power signal.

[0054] A dual-mode inverter may include a first inverter power device M11, a second inverter power device M12, a third inverter power device M13, and a fourth inverter power device M14. For example, the first inverter power device M11, the second inverter power device M12, the third inverter power device M13, and the fourth inverter power device M14 can be used as switches to achieve DC voltage to AC voltage inversion. It should be noted that... Figure 3 The first inverter power device M11, the second inverter power device M12, the third inverter power device M13, and the fourth inverter power device M14 are shown using N-type field-effect transistors. However, it should be understood that at least one of the first inverter power device M11, the second inverter power device M12, the third inverter power device M13, and the fourth inverter power device M14 can also be implemented based on a P-type field-effect transistor, which will not be elaborated here. In addition, in some embodiments, they can also be implemented as diodes, which will not be elaborated here.

[0055] The first terminal of the first inverter power device M11 is electrically connected to the input voltage terminal. The second terminal of the first inverter power device M11 is electrically connected to the primary positive terminal VPP. The control terminal of the first inverter power device M11 is electrically connected to the transmitter controller. The first terminal of the second inverter power device M12 is electrically connected to the input voltage terminal. The second terminal of the second inverter power device M12 is electrically connected to the primary negative terminal VPN. The control terminal of the second inverter power device M12 is electrically connected to the transmitter controller.

[0056] The first terminal of the third inverter power device M13 is electrically connected to the primary positive terminal VPP. The second terminal of the third inverter power device M13 is electrically connected to ground GND. The control terminal of the third inverter power device M13 is electrically connected to the transmitter controller.

[0057] The first terminal of the fourth inverter power device M14 is electrically connected to the primary negative terminal VPN. The second terminal of the fourth inverter power device M14 is electrically connected to ground GND. The control terminal of the fourth inverter power device M14 is electrically connected to the transmitter controller.

[0058] In some embodiments, the input voltage VIN may fall within a first voltage range or a second voltage range different from the first voltage range. For example, the first voltage range may be a voltage range lower than the second voltage range. Based on this, the transmitter controller may, in response to detecting that the input voltage VIN falls within the first voltage range (e.g., the input voltage VIN is 12V), control the first inverter power device M11 and the third inverter power device M13 to alternately conduct, or control the second inverter power device M12 and the fourth inverter power device M14 to alternately conduct, so that the dual-mode inverter operates in half-bridge inverter mode. For example, in half-bridge inverter mode, the fourth inverter power device M14 of the dual-mode inverter may remain constantly on, the second inverter power device M12 may remain constantly off, and the first inverter power device M11 and the third inverter power device M13 may alternately conduct.

[0059] The transmitter controller can also respond to the detection that the input voltage VIN belongs to the second voltage range (e.g., the input voltage VIN is 24V) by controlling the first inverter power device M11 and the fourth inverter power device M14 to simultaneously conduct during the first inverter period and simultaneously turn off during the second inverter period via a mode control signal. It also controls the second inverter power device M12 and the third inverter power device M13 to simultaneously turn off during the first inverter period and simultaneously conduct during the second inverter period, so that the dual-mode inverter operates in full-bridge inverter mode. It should be understood that the first inverter period and the second inverter period represent two different periods.

[0060] In this embodiment, both the half-bridge inverter mode and the full-bridge inverter mode can invert the voltage difference (i.e., the oscillation power signal) across the primary coil L1 into an AC voltage (i.e., the transformed oscillation power signal). Furthermore, the peak AC voltage generated in the half-bridge inverter mode is half that in the full-bridge inverter mode.

[0061] In some embodiments, the double-voltage triple-output rectifier may include a first rectifier power device M21, a second rectifier power device M22, a third rectifier power device M23, a fourth rectifier power device M24, a first capacitor CL1, a second capacitor CL2, and a third capacitor CL3. The first capacitor CL1, the second capacitor CL2, and the third capacitor CL3 may be load capacitors. In this embodiment, the power chip can generate three regulated outputs, including a negative voltage VE, with high conversion efficiency. Furthermore, the double-voltage triple-output rectifier only requires four power devices to achieve rectification, reducing the resources required for the drive system of the gate driver and exhibiting high integration.

[0062] The first terminal of the first rectifier power device M21 is electrically connected to the positive secondary terminal VSP of the secondary coil L2, the second terminal of the first rectifier power device M21 is electrically connected to the first output terminal of the double voltage triple output rectifier, and the control terminal of the first rectifier power device M21 is electrically connected to the receiver controller.

[0063] The first terminal of the second rectifier power device M22 is electrically connected to the secondary negative terminal VSN of the secondary coil L2, the second terminal of the second rectifier power device M22 is electrically connected to the second output terminal of the double voltage triple output rectifier, and the control terminal of the second rectifier power device M22 is electrically connected to the receiver controller.

[0064] The first terminal of the third rectifier power device M23 is electrically connected to the secondary negative terminal VSN, the second terminal of the third rectifier power device M23 is electrically connected to ground GND, and the control terminal of the third rectifier power device M23 is electrically connected to the receiver controller.

[0065] The first terminal of the fourth rectifier power device M24 is electrically connected to the secondary positive terminal VSP, the second terminal of the fourth rectifier power device M24 is electrically connected to the third output terminal, and the control terminal of the fourth rectifier power device M24 is electrically connected to the receiver controller.

[0066] The first capacitor CL1 is electrically connected between the second terminal of the first rectifier power device M21 and the second terminal of the third rectifier power device M23.

[0067] The second capacitor CL2 is electrically connected between the second terminal of the second rectifier power device M22 and the second terminal of the third rectifier power device M23.

[0068] The third capacitor CL3 is electrically connected between the second terminal of the third rectifier power device M23 and the second terminal of the fourth rectifier power device M24.

[0069] Based on this, the double-voltage triple-output rectifier is equivalent to two voltage doublers. The gain of the double-voltage triple-output rectifier is twice that of the full-bridge rectifier. Therefore, when the dual-mode inverter operates in full-bridge inverter mode, the power chip can convert 24V to 20V.

[0070] The receiver controller can control the conduction of the first rectifier power device M21, the second rectifier power device M22, the third rectifier power device M23, and the fourth rectifier power device M24 to charge the first capacitor CL1, the second capacitor CL2, and the third capacitor CL3. The first positive voltage V1 is output through the first output terminal of the double voltage triple output rectifier via the charged first capacitor CL1, the second positive voltage V2 is output through the second output terminal of the double voltage triple output rectifier via the charged second capacitor CL2, and the negative voltage VE is output through the third output terminal of the double voltage triple output rectifier via the charged third capacitor CL3.

[0071] In some embodiments, the first rectifier power device M21, the second rectifier power device M22, the third rectifier power device M23, and the fourth rectifier power device M24 can be used as switches. It should be noted that, in Figure 3 The diagram illustrates a first rectifier power device M21, a second rectifier power device M22, a third rectifier power device M23, and a fourth rectifier power device M24 using N-type field-effect transistors. However, it should be understood that at least one of these devices is also implemented based on a P-type field-effect transistor, which will not be elaborated upon here. Furthermore, in some embodiments, at least one of these devices can also be implemented as a diode, which will not be elaborated upon here either.

[0072] The receiver controller can also monitor the first positive voltage V1, the second positive voltage V2, and the negative voltage VE, and generate feedback signals to control the power produced by the dual-mode inverter.

[0073] In embodiments of this disclosure, the drive system may further include a digital isolator connected between the transmitter controller and the output controller. The digital isolator is used to transmit the feedback signal back to the transmitter controller.

[0074] The transmitter controller can output mode control signals to drive the power devices in the dual-mode inverter based on the feedback signal from the digital isolator, thereby controlling the dual-mode inverter to perform inversion or cease operation. The transmitter controller can also control the dual-mode inverter to operate in full-bridge inverter mode or half-bridge inverter mode.

[0075] In this embodiment, the power chip may further include a first coupling capacitor C1 and a second coupling capacitor C2. The primary positive terminal VPP of the transformer can be connected via the first coupling capacitor C1 to the second terminal of the first inverter power device M11 and the first terminal of the third inverter power device M13 (i.e., the midpoint of the bridge arm formed by the first inverter power device M11 and the third inverter power device M13). The first coupling capacitor C1 can be used together with the transformer to form a resonant network (e.g., an LLC resonant network) to reduce higher harmonic components, thereby improving conversion efficiency, achieving zero-voltage turn-on, and increasing the voltage gain of the system.

[0076] The negative secondary terminal VSN of the transformer can be connected to the first terminal of the second rectifier power device M22 and the first terminal of the third rectifier power device M23 via the second coupling capacitor C2. The second coupling capacitor C2 carries the DC level, ensuring volt-second balance of the secondary coil L2 under any first positive voltage V1, second positive voltage V2, and negative voltage VE, thus achieving decoupling of the three outputs. Furthermore, the second coupling capacitor C2 can resonate with the secondary coil L2 of the transformer, thereby reducing self-circulating current and lowering losses.

[0077] In some embodiments, the receiver controller may include a first pulse width modulation circuit, a second pulse width modulation circuit, a receiver control unit, and an encoder. The first pulse width modulation circuit monitors a first positive voltage V1 and determines how much power V1 requires, thereby outputting a first duty cycle signal. The second pulse width modulation circuit monitors a second positive voltage V2 and determines how much power V2 requires, thereby outputting a second duty cycle signal. The receiver control unit determines the mode of the double-voltage triple-output rectifier based on the first and second duty cycle signals and outputs rectification control signals to drive the power devices in the double-voltage triple-output rectifier. The encoder encodes the first and second duty cycle signals to obtain the aforementioned feedback signal and transmits the feedback signal to a digital isolator.

[0078] For example, the receiver controller can control the double-voltage triple-output rectifier to be in a first mode, a second mode, a third mode, and a fourth mode, and control the duration of the double-voltage triple-output rectifier in the first mode, the second mode, the third mode, and the fourth mode, so that the charged first capacitor CL1 outputs a first positive voltage V1 through the first output terminal of the double-voltage triple-output rectifier, the charged second capacitor CL2 outputs a second positive voltage V2 through the second output terminal of the double-voltage triple-output rectifier, and the charged third capacitor CL3 outputs a negative voltage VE through the third output terminal of the double-voltage triple-output rectifier.

[0079] Specifically, for ease of understanding, the two time periods are defined here based on the current flow direction of the secondary coil L2. For example, the time period in which the AC current (also called the resonant current) of the secondary coil L2 flows from the positive terminal VSP to the negative terminal VSN is defined as the first time period, and the time period in which the AC current of the secondary coil L2 flows from the negative terminal VSN to the positive terminal VSP is defined as the second time period. In this embodiment, the first and second time periods are equal, that is, the positive and negative half-cycles of the AC current are completely symmetrical. The following is combined with... Figures 4-7 A detailed explanation will follow. It is important to note that... Figures 4-6 middle, I 2+ This can represent the current flowing from the secondary coil L2 to the positive terminal VSP. 2-This can represent the current flowing from the secondary coil L2 to the negative terminal VSN. Φ1 can represent the phase corresponding to the positive half-cycle of the alternating current. Φ2 can represent the phase corresponding to the negative half-cycle of the alternating current, which will not be elaborated here.

[0080] Figure 4 A schematic diagram of a first mode according to an embodiment of the present disclosure is shown. Figure 4 As shown, in the first mode, the receiver controller can: during a first time period, control the first rectifier power device M21 and the third power rectifier to be turned off, while the second rectifier power device M22 and the fourth power rectifier to be turned on, to charge the second capacitor CL2 and the third capacitor CL3; during a second time period, control the first rectifier power device M21 and the third power rectifier to be turned on, while the second rectifier power device M22 and the fourth power rectifier to be turned off, to charge the first capacitor CL1. Thus, in the first mode, the double-voltage triple-output rectifier charges the first capacitor CL1, the second capacitor CL2, and the third capacitor CL3 simultaneously with the same charging current. Since the positive and negative half-cycles of the AC current are completely symmetrical, the charging current for the first capacitor CL1, the second capacitor CL2, and the third capacitor CL3 is exactly the same. Based on this, in the first mode, the first capacitor CL1, the second capacitor CL2, and the third capacitor CL3 are all charged.

[0081] Figure 5 A schematic diagram of a second mode according to an embodiment of the present disclosure is shown. Figure 5 As shown, the receiver controller can operate in the second mode as follows: During the first time period, it controls the first rectifier power device M21 to be off and the fourth rectifier power device M24 to be on; during the second time period, it controls the fourth rectifier power device M24 to be off and the first rectifier power device M21 to be on; during both the first and second time periods, it controls the second power rectifier device to be off and the third power rectifier device to be on. Thus, during the first time period, the double-voltage triple-output rectifier can charge the third capacitor CL3, and during the second time period, it can charge the first capacitor CL1. Since the positive and negative half-cycles of the AC current are completely symmetrical, the charging current for the first capacitor CL1 and the third capacitor CL3 is exactly the same.

[0082] Figure 6 A schematic diagram illustrating a third mode according to an embodiment of this disclosure is shown. Figure 6As shown, the receiver controller can operate in the third mode as follows: During the first time period, it controls the second rectifier power device M22 to be on and the third rectifier power device M23 to be off; during the second time period, it controls the third rectifier power device M23 to be on and the second rectifier power device M22 to be off; during both the first and second time periods, it controls the first rectifier power device M21 and the fourth rectifier power device M24 to be on. During the first time period, the double-voltage triple-output rectifier can charge the second capacitor CL2 and the third capacitor CL3. During the second time period, the double-voltage triple-output rectifier can discharge the third capacitor CL3. Because the positive and negative half-cycles of the AC current are completely symmetrical, the third capacitor CL3 will neither be charged nor discharged after the positive and negative half-cycles.

[0083] Figure 7 A schematic diagram illustrating a fourth mode according to an embodiment of the present disclosure is shown. Figure 7 As shown, the receiver controller can operate in the fourth mode: during the first and second time periods, it controls the first rectifier power device M21, the third rectifier power device M23, and the fourth rectifier power device M24 to be turned off. In the fourth mode, the dual-mode inverter may not operate, and no power is transmitted to the double-voltage triple-output rectifier. Furthermore, the first inverter power device M11, the second inverter power device M12, the third inverter power device M13, and the fourth inverter power device M14 are all turned off, and the first capacitor CL1, the second capacitor CL2, and the third capacitor CL3 will not be charged.

[0084] Based on this, in this power chip, by controlling the timing of the first, second, third, and fourth modes through a control circuit, and controlling the power obtained by the first capacitor CL1, the second capacitor CL2, and the third capacitor CL3, voltage regulation of the first positive voltage V1, the second positive voltage V2, and the negative voltage VE can be achieved. Since the gate driver (e.g., a bipolar load gate driver) requires the same current from the first positive voltage V1 and the negative voltage VE, and the double-voltage triple-output rectifier also provides the same current to the first positive voltage V1 and the negative voltage VE in the first and second modes, it naturally ensures that the required power and the actual power received are the same for the first positive voltage V1 and the negative voltage VE, thus achieving load balancing of the first positive voltage V1 and the negative voltage VE. If, in addition to bipolar loads like the aforementioned gate driver, there are other unipolar loads that only require the output current of the first positive voltage V1 and the negative voltage VE, a voltage regulator can be introduced into the voltage chip to achieve load balancing.

[0085] Figure 8 The diagram schematically illustrates the waveform of the output voltage when switching modes in a first manner according to an embodiment of the present disclosure. Figure 9The diagram schematically illustrates the waveform of the output voltage when switching modes in a second manner according to an embodiment of the present disclosure. Here, t represents time.

[0086] for Figure 8 As shown, the first positive voltage V1 and the negative voltage VE can be used to power a bipolar load, and the second positive voltage V2 can be used to power a unipolar load alone, where the unipolar load current is greater than that of the bipolar load. In the first mode, the power chip can power the first, second, and third capacitors, causing the voltages stored in the first, second, and third capacitors to rise. After the voltages of the first, second, and third capacitors rise for a period of time, that is, after the first positive voltage V1 and the second positive voltage V2 rise for a period of time while the negative voltage VE drops for a period of time, the power chip enters the third mode. In the third mode, the second positive voltage V2 continues to rise while the first positive voltage V1 and the negative voltage VE begin to decrease due to the power consumption of the load. After the second positive voltage V2 rises for a fixed period of time, the power chip enters the fourth mode. In the fourth mode, the first positive voltage V1, the second positive voltage V2, and the negative voltage VE begin to decrease due to the power consumption of the load. After decreasing for a period of time, the power chip re-enters the first mode to charge the first, second, and third capacitors.

[0087] for Figure 9 As shown, the first positive voltage V1 and the negative voltage VE can be used to power both ends of a bipolar load, while the second positive voltage V2 can be used to power a unipolar load alone, where the bipolar load current is greater than that of the unipolar load. In the first mode, the power chip can power the first, second, and third capacitors, causing the voltages stored in the first, second, and third capacitors to rise. After the voltages of the first, second, and third capacitors have risen for a period of time, that is, after the first positive voltage V1 and the second positive voltage V2 have risen for a period of time while the negative voltage VE has fallen for a period of time, the power chip enters the second mode. In the second mode, the first positive voltage V1 and the negative voltage VE continue to rise, while the second positive voltage V2 begins to fall due to the power consumption of the load. After the first positive voltage V1 and the negative voltage VE have risen for a fixed period of time, the power chip enters the fourth mode. In the fourth mode, the first positive voltage V1, the negative voltage VE, and the second positive voltage V2 begin to fall due to the power consumption of the load. After falling for a period of time, the power chip re-enters the first mode to charge the first, second, and third capacitors.

[0088] In this embodiment, by precisely controlling the rise and fall times of the first mode, second mode, third mode, and fourth mode, it can be ensured that the first positive voltage V1, the negative voltage VE, and the second positive voltage V2 are controlled within a certain range, thus ensuring stable power supply to both bipolar and unipolar loads. The unipolar load may include low-voltage circuits such as the aforementioned monitoring circuit.

[0089] Furthermore, in some embodiments, the compensation control signal may include a first compensation control signal and a second compensation control signal. The receiver controller may generate the first compensation control signal in response to detecting that the second positive voltage V2 is less than a predetermined voltage (e.g., 5V), and generate the second compensation control signal in response to detecting that the second positive voltage V2 is greater than or equal to the predetermined voltage.

[0090] The compensation circuit can be electrically connected to the first, second, and third output terminals of the double-voltage triple-output rectifier and the receiver controller. Thus, under the control of a first compensation control signal, the compensation circuit can partially open the conductive path between the first and second output terminals, and electrically isolate the second and third output terminals, to compensate for voltage fluctuations in the second positive voltage V2 using the first positive voltage V1. Furthermore, under the control of a second compensation control signal, the compensation circuit can also partially open the conductive path between the second and third output terminals, and electrically isolate the first and second output terminals, to compensate for voltage fluctuations in the second positive voltage V2 using the negative voltage VE. The following is combined with... Figure 10 The specific structure of the compensation circuit is explained.

[0091] Figure 10 A schematic diagram of a drive system according to another embodiment of the present disclosure is shown.

[0092] like Figure 10 As shown, the compensation circuit may include a first current-limiting switch and a second current-limiting switch. The receiver controller may also include a compensation control unit.

[0093] The first terminal of the first current-limiting switch is electrically connected to the first output terminal of the double-voltage triple-output rectifier, and the second terminal of the first current-limiting switch is electrically connected to the second output terminal of the double-voltage triple-output rectifier. The control terminal of the first current-limiting switch is electrically connected to the receiver controller (e.g., a compensation control unit). Thus, the first current-limiting switch can close under the control of a first compensation control signal to partially open the conductive path between the first and second output terminals, and open under the control of a second compensation control signal to electrically isolate the first and second output terminals.

[0094] The first terminal of the second current-limiting switch is electrically connected to the second output terminal of the double-voltage triple-output rectifier, and the second terminal of the second current-limiting switch is electrically connected to the third output terminal of the double-voltage triple-output rectifier. The control terminal of the second current-limiting switch is electrically connected to the receiver controller (e.g., a compensation control unit). Thus, the second current-limiting switch can close under the control of the second compensation control signal to partially open the conductive path between the second and third output terminals, and open under the control of the first compensation control signal to electrically isolate the second and third output terminals.

[0095] In some embodiments, the first current-limiting switch may be implemented based on an N-type field-effect transistor or a P-type field-effect transistor. The second current-limiting switch may be implemented based on an N-type field-effect transistor or a P-type field-effect transistor.

[0096] Furthermore, in some embodiments, the first current-limiting switch and the second current-limiting switch can be implemented based on the same type of transistor. For example, when the first and second current-limiting switches are N-type field-effect transistors, the drain of the first current-limiting switch can be connected to the first output terminal, the source of the first current-limiting switch can be connected to the second output terminal, the source of the second current-limiting switch can be connected to the second output terminal, and the drain of the second current-limiting switch can be connected to the third output terminal. The gates of the first and second current-limiting switches can be connected to a compensation control unit.

[0097] In this embodiment, the compensation control unit may include an inverter and a comparator. The gate of the first current-limiting switch may be connected to the output of the inverter, and the input of the inverter may be connected to the output of the comparator. The gate of the second current-limiting switch may be directly connected to the output of the comparator.

[0098] The comparator's first input can be connected to the second output of a double-voltage triple-output rectifier to receive a second positive voltage, and its second input can be connected to a predetermined voltage terminal to receive a predetermined voltage. Thus, when the second positive voltage is greater than the predetermined voltage, the comparator outputs a first compensation control signal (e.g., a low level "0"). This first compensation control signal, after passing through an inverter, inverts to control the first current-limiting switch to at least partially conduct, thereby compensating for the second positive voltage with the first positive voltage. Simultaneously, the first compensation control signal can directly control the second current-limiting switch to turn off, electrically isolating the second and third output terminals from each other.

[0099] When the second positive voltage is less than a predetermined voltage, the comparator can output a second compensation control signal (e.g., a high level "1"). This second compensation control signal can directly control the second current-limiting switch to at least partially conduct, thereby compensating for the second positive voltage with the negative voltage. Simultaneously, after passing through an inverter, the inverted second compensation control signal can also control the second current-limiting switch to at least partially conduct, thereby compensating for the second positive voltage with the negative voltage.

[0100] Based on this, for the special power requirements of the low-voltage circuit in the drive system of this disclosure embodiment, in this disclosure embodiment, only a small amount of resources are needed to manufacture the above-mentioned compensation circuit and the above-mentioned compensation control unit. The first positive voltage and negative voltage generated by the power chip itself can be used to stabilize and compensate the second positive voltage generated by the power chip itself. The stability of the second positive voltage is achieved with only a small amount of resources, thus meeting the power requirements of the low-voltage circuit.

[0101] Figure 11 A schematic diagram of a voltage processing method according to an embodiment of the present disclosure is shown.

[0102] like Figure 11 As shown, the voltage processing method of this embodiment may include operations S1110 to S1140.

[0103] When operating S1110, the dual-mode inverter operates in half-bridge inverter mode or full-bridge inverter mode under the control of the control circuit. In half-bridge inverter mode or full-bridge inverter mode, the input voltage received through the input voltage terminal is inverted to generate an oscillating power signal.

[0104] When operating S1120, the transformer transforms the oscillation power signal.

[0105] When operating S1130, the double-voltage triple-output rectifier, under the control of the control circuit, rectifies the transformed oscillating power signal to generate a first positive voltage, a second positive voltage, and a negative voltage.

[0106] In operation S1140, when there is voltage fluctuation in the second positive voltage, the compensation circuit selectively uses the first positive voltage or the negative voltage to compensate for the voltage fluctuation of the second positive voltage under the control of the control circuit.

[0107] It should be understood that the voltage processing method of this disclosure is not limited to operations S1110 to S1140 mentioned herein. In this disclosure, the voltage processing method may also include other operations. For details, please refer to the operations performed by the aforementioned power chip, which will not be elaborated here.

[0108] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0109] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A power chip for use in a drive system, the drive system including a target power device and a gate driver and a monitoring circuit electrically connected to the target power device; The power supply chip includes: Control circuit; A dual-mode inverter is electrically connected to the input voltage terminal and the control circuit. It is used to operate in half-bridge inverter mode or full-bridge inverter mode under the control of the control circuit. In half-bridge inverter mode or full-bridge inverter mode, it inverts the input voltage received through the input voltage terminal to generate an oscillating power signal. The transformer, connected between the dual-mode inverter and the double-voltage triple-output rectifier, is used to transform the oscillating power signal into a transformed oscillating power signal and output the transformed oscillating power signal to the double-voltage triple-output rectifier to transmit AC power between the dual-mode inverter and the double-voltage triple-output rectifier. The double-voltage triple-output rectifier is also electrically connected to the control circuit, the gate driver, and the monitoring circuit. Under the control of the control circuit, it is used to rectify the transformed oscillating power signal to generate a first positive voltage, a second positive voltage, and a negative voltage. The first positive voltage and the negative voltage are used to power the gate driver, and the second positive voltage is used to power the monitoring circuit. The compensation circuit, electrically connected to the double-voltage triple-output rectifier and the control circuit, is used to selectively compensate for the voltage fluctuation of the second positive voltage using either the first positive voltage or the negative voltage under the control of the control circuit, in the event of voltage fluctuation in the second positive voltage.

2. The power chip according to claim 1, wherein, The control circuit includes a receiver controller, which is configured to generate a first compensation control signal in response to detecting that the second positive voltage is less than a predetermined voltage, and to generate a second compensation control signal in response to detecting that the second positive voltage is greater than or equal to the predetermined voltage. The double-voltage triple-output rectifier has a first output terminal, a second output terminal, and a third output terminal. The first output terminal and the third output terminal are electrically connected to the first voltage terminal and the second voltage terminal of the gate driver, respectively. The second output terminal is electrically connected to the voltage terminal of the monitoring circuit. The first output terminal is used to output the first positive voltage, the second output terminal is used to output the second positive voltage, and the third output terminal is used to output the negative voltage. The compensation circuit is electrically connected to the first output terminal, the second output terminal, and the third output terminal of the double-voltage triple-output rectifier, as well as the receiver controller, and is used for: Under the control of the first compensation control signal, the conductive channel between the first output terminal and the second output terminal is partially turned on, and the second output terminal and the third output terminal are electrically isolated, so as to use the first positive voltage to compensate for the voltage fluctuation of the second positive voltage; Under the control of the second compensation control signal, the conductive channel between the second output terminal and the third output terminal is partially turned on, and the first output terminal and the second output terminal are electrically isolated, so as to use the negative voltage to compensate for the voltage fluctuation of the second positive voltage.

3. The power chip according to claim 2, wherein, The compensation circuit includes: The first current limiting switch has a first terminal electrically connected to the first output terminal of the double voltage triple output rectifier, a second terminal electrically connected to the second output terminal of the double voltage triple output rectifier, and a control terminal electrically connected to the receiver controller. It is used to close under the control of the first compensation control signal to partially conduct the conductive channel between the first output terminal and the second output terminal, and to open under the control of the second compensation control signal to electrically isolate the first output terminal and the second output terminal. The second current-limiting switch has a first terminal electrically connected to the second output terminal of the double-voltage triple-output rectifier, a second terminal electrically connected to the third output terminal of the double-voltage triple-output rectifier, and a control terminal electrically connected to the receiver controller. It is used to close under the control of the second compensation control signal to partially conduct the conductive channel between the second output terminal and the third output terminal, and to open under the control of the first compensation control signal to electrically isolate the second output terminal and the third output terminal.

4. The power chip according to claim 2 or 3, wherein, The transformer includes a primary coil and a secondary coil coupled to each other. The primary positive terminal and the primary negative terminal of the primary coil are electrically connected to the dual-mode inverter to receive the oscillating power signal. The double-voltage triple-output rectifier includes: The first rectifier power device has a first terminal electrically connected to the secondary positive terminal of the secondary coil, a second terminal electrically connected to the first output terminal of the double voltage triple output rectifier, and a control terminal electrically connected to the receiver controller. The second rectifier power device has a first terminal electrically connected to the negative secondary terminal of the secondary coil, a second terminal electrically connected to the second output terminal of the double-voltage triple-output rectifier, and a control terminal electrically connected to the receiver controller. The third rectifier power device has a first terminal electrically connected to the secondary negative terminal, a second terminal electrically connected to ground, and a control terminal electrically connected to the receiver controller. The fourth rectifier power device has a first terminal electrically connected to the secondary positive terminal, a second terminal electrically connected to the third output terminal, and a control terminal electrically connected to the receiving terminal controller. The first capacitor is connected between the second terminal of the first rectifier power device and the second terminal of the third rectifier power device; The second capacitor is connected between the second terminal of the second rectifier power device and the second terminal of the third rectifier power device; The third capacitor is connected between the second terminal of the third rectifier power device and the second terminal of the fourth rectifier power device; The receiver controller is further configured to charge the first capacitor, the second capacitor, and the third capacitor by controlling the conduction of the first rectifier power device, the second rectifier power device, the third rectifier power device, and the fourth rectifier power device, so that the first positive voltage is output through the first output terminal of the double voltage triple output rectifier via the charged first capacitor, the second positive voltage is output through the second output terminal of the double voltage triple output rectifier via the charged second capacitor, and the negative voltage is output through the third output terminal of the double voltage triple output rectifier via the charged third capacitor.

5. The power chip according to claim 4, wherein, The receiver controller is also configured to control the double-voltage triple-output rectifier to be in a first mode, a second mode, a third mode, and a fourth mode, and to control the duration of the double-voltage triple-output rectifier in the first mode, the second mode, the third mode, and the fourth mode, so that the first capacitor after charging outputs the first positive voltage through the first output terminal of the double-voltage triple-output rectifier, the second capacitor after charging outputs the second positive voltage through the second output terminal of the double-voltage triple-output rectifier, and the third capacitor after charging outputs the negative voltage through the third output terminal of the double-voltage triple-output rectifier.

6. The power chip according to claim 5, wherein, The receiver controller is also used for, In the first mode: during a first time period when the direction of AC current flow in the secondary coil is from the positive terminal to the negative terminal, the first and third power rectifier devices are controlled to be turned off, while the second and fourth power rectifier devices are turned on; during a second time period when the direction of AC current flow in the secondary coil is from the negative terminal to the positive terminal, the first and third power rectifier devices are controlled to be turned on, while the second and fourth power rectifier devices are turned off. In the second mode: during the first time period, the first rectifier power device is controlled to be turned off and the fourth rectifier power device is turned on; during the second time period, the fourth rectifier power device is controlled to be turned off and the first rectifier power device is turned on; during the first time period and the second time period, the second power rectifier device is controlled to be turned off and the third power rectifier device is controlled to be turned on. In the third mode: during the first time period, the second rectifier power device is turned on and the third rectifier power device is turned off; during the second time period, the third rectifier power device is turned on and the second rectifier power device is turned off; during the first time period and the second time period, the first rectifier power device and the fourth rectifier power device are turned on. In the fourth mode: during the first time period and the second time period, the first rectifier power device, the third rectifier power device and the fourth rectifier power device are controlled to be turned off.

7. The power chip according to claim 4, wherein, The control circuit also includes a transmitter controller; The dual-mode inverter includes: The first inverter power device has a first terminal electrically connected to the input voltage terminal, a second terminal electrically connected to the primary positive terminal, and a control terminal electrically connected to the transmitter controller. The second inverter power device has a first terminal electrically connected to the input voltage terminal, a second terminal electrically connected to the primary negative terminal, and a control terminal electrically connected to the transmitter controller. The third inverter power device has a first terminal electrically connected to the primary positive terminal, a second terminal electrically connected to ground, and a control terminal electrically connected to the transmitter controller. The fourth inverter power device has its first terminal electrically connected to the primary negative terminal, its second terminal connected to ground, and its control terminal electrically connected to the transmitter controller.

8. The power chip according to claim 7, wherein, The transmitter controller is also used for: In response to detecting that the input voltage belongs to a first voltage range, the first inverter power device and the third inverter power device are controlled to be turned on alternately, or the second inverter power device and the fourth inverter power device are controlled to be turned on alternately, so that the dual-mode inverter operates in the half-bridge inverter mode; In response to detecting that the input voltage belongs to the second voltage range, the first inverter power device and the fourth inverter power device are controlled to be turned on simultaneously during the first inverter period and turned off simultaneously during the second inverter period. The second inverter power device and the third inverter power device are controlled to be turned off simultaneously during the first inverter period and turned on simultaneously during the second inverter period, so that the dual-mode inverter operates in the full-bridge inverter mode.

9. A drive system, comprising: The target power device, the gate driver electrically connected to the target power device, the monitoring circuit electrically connected to the target power device, and the power chip according to any one of claims 1 to 8.

10. A voltage processing method, applied to a power supply chip as described in any one of claims 1 to 8, the voltage processing method comprising: The dual-mode inverter operates in half-bridge inverter mode or full-bridge inverter mode under the control of the control circuit. In half-bridge inverter mode or full-bridge inverter mode, it inverts the input voltage received through the input voltage terminal to generate an oscillating power signal. The transformer transforms the oscillating power signal; Under the control of the control circuit, the double-voltage triple-output rectifier rectifies the transformed oscillation power signal to generate a first positive voltage, a second positive voltage, and a negative voltage. The first positive voltage and the negative voltage are used to power the gate driver, and the second positive voltage is used to power the monitoring circuit. When there is voltage fluctuation in the second positive voltage, the compensation circuit, under the control of the control circuit, selectively uses the first positive voltage or the negative voltage to compensate for the voltage fluctuation of the second positive voltage. Wherein, the first positive voltage is higher than the second positive voltage.

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