Power supply circuit and control method thereof

Abstract

The application provides a power supply circuit and a control method thereof. The power supply circuit comprises a power supply port, a load port, an H-bridge circuit, a detection module and a control circuit. The H-bridge circuit comprises a first bridge arm and a second bridge arm. The first bridge arm and the second bridge arm are both heterogeneous bridge arms composed of a switching MOS tube and a power adjusting tube. The detection module is used for detecting a current detection signal. The control circuit is used for receiving the current detection signal, outputting a PWM driving signal of a target frequency to the switching MOS tube in the H-bridge circuit, and outputting a continuous adjusting driving signal of the target frequency to the power adjusting tube in the H-bridge circuit based on the current detection signal and a target current amplitude, so that the H-bridge circuit outputs a pulse current with the target frequency and the target current amplitude to a load connected to the load port. The power supply circuit provided by the application can balance the dynamic commutation capability and the steady-state low ripple performance, and realize high-fidelity pulse current output.

Description

Technical Field

[0001] This application relates to the field of electroplating power supply technology, and in particular to a power supply circuit and its control method. Background Technology

[0002] As electronic components move towards higher density and miniaturization, the manufacturing process of printed circuit boards (PCBs) is becoming increasingly complex. In particular, the through-hole plating and high aspect ratio processes of high-end PCBs place extremely stringent requirements on pulse plating power supplies. An ideal pulse plating power supply should possess characteristics such as steep pulse edges, rapid switching between forward and reverse currents, extremely low steady-state output ripple, and high current control precision to ensure plating uniformity, consistent copper thickness in holes, and overall board quality.

[0003] Currently, the industry widely adopts the isomorphic H-bridge topology of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) as the core conversion structure of pulse electroplating power supplies. This topology utilizes the fast switching characteristics of MOSFETs to achieve high response speeds, meeting basic high-frequency pulse output requirements. However, in practical applications, the full-bridge structure inevitably generates parasitic oscillations during full-domain high-frequency modulation, resulting in severe ripple glitches at the output, causing pulse waveform distortion. To suppress such interference, existing technologies typically require adding large-capacity filter capacitors at the front end of the power supply and connecting a series reactor at the rear end, significantly increasing the overall size of the device and hindering system integration and miniaturization design.

[0004] Therefore, how to effectively suppress parasitic oscillations and output ripples in the H-bridge topology without relying on large-volume filter components, while maintaining pulse edge steepness and current switching speed, and improving sampling accuracy and waveform fidelity, has become a pressing technical challenge in the field of PCB pulse electroplating power supplies. Summary of the Invention

[0005] In view of this, the main purpose of this application is to propose a power supply circuit and its control method, which aims to solve the problem of severe ripple and spikes in the output current of existing electroplating power supplies.

[0006] To achieve the above objectives, a first aspect of this application provides a power supply circuit, the power supply circuit comprising: The power supply port includes a positive terminal and a negative terminal for receiving DC power. Load port, used for electrical connection to the load; An H-bridge circuit includes a first bridge arm and a second bridge arm. The first bridge arm includes a first upper bridge arm switch and a first lower bridge arm switch electrically connected between the positive and negative terminals of the power supply port. The second bridge arm includes a second upper bridge arm switch and a second lower bridge arm switch electrically connected between the positive and negative terminals of the power supply port. The midpoint of the first bridge arm and the second bridge arm is electrically connected to the load port. The first upper bridge arm switch and the second upper bridge arm switch are power regulation transistors, and the first lower bridge arm switch and the second lower bridge arm switch are switching MOSFETs; alternatively, the first upper bridge arm switch and the second upper bridge arm switch are switching MOSFETs, and the first lower bridge arm switch and the second lower bridge arm switch are power regulation transistors. A detection module, electrically connected to the load port, is used to detect the current output from the load port to the load and obtain a corresponding current detection signal; and The control circuit is electrically connected to the control terminal of the switching transistor in the H-bridge circuit and the detection module, respectively. The control circuit is used to acquire the target frequency and the target current amplitude, receive the current detection signal output by the detection module, and output a PWM drive signal with the target frequency to the switching MOSFET in the H-bridge circuit. Based on the current detection signal and the target current amplitude, the control circuit outputs a continuously adjusting drive signal with the target frequency to the power adjustment transistor in the H-bridge circuit, so that the H-bridge circuit converts the received DC power into electrical energy and outputs a pulse current with the target frequency and the target current amplitude to the load connected to the load port. The amplitude of the continuously adjusting drive signal is related to the target current amplitude.

[0007] The power supply circuit provided in this application offers a heterogeneous H-bridge circuit with asymmetrical upper and lower arms. The two arms utilize a hybrid power loop composed of switching MOSFETs and power regulation transistors. A control circuit outputs a PWM drive signal with a target frequency to the switching MOSFETs in the H-bridge circuit, and a continuously adjusting drive signal with the target frequency to the power regulation transistors in the H-bridge circuit, based on a current detection signal and a target current amplitude. This enables the H-bridge circuit to convert the received DC power into electrical energy and output a pulse current with the target frequency and amplitude to the load connected to the load port. On one hand, the switching MOSFETs, with their fast switching speed and rapid commutation response, primarily handle the commutation of positive and negative currents in the circuit. This allows for rapid switching of the pulse current polarity, ensuring a steep pulse current edge without tail distortion. On the other hand, the power regulation transistors, with their excellent linear regulation characteristics, smooth conduction current, and controllable steady-state voltage drop, can effectively cancel high-frequency glitches caused by switching noise and parasitic oscillations in real time, compressing current ripple and achieving low-ripple steady-state output and high-precision dynamic adjustment. Therefore, the power supply circuit provided in this application embodiment combines the high-speed characteristics of switching MOSFETs with the linear advantages of power regulation transistors. It can achieve high-fidelity pulse current output without the need for large-capacity filtering devices, thus balancing dynamic commutation capability and steady-state low ripple performance.

[0008] In some embodiments, the power regulating transistor includes at least one of a transistor and a linearly regulated MOSFET.

[0009] In some embodiments, the control circuit includes: The controller is electrically connected to the detection module and the control terminal of the switching MOSFET in the H-bridge circuit. The controller is used to acquire the target frequency and target current amplitude, receive the current detection signal output by the detection module, output a PWM drive signal with the target frequency to the switching MOSFET in the H-bridge circuit, and generate a current inner loop reference signal based on the current detection signal and the target current amplitude using a current outer loop control algorithm. The inner current loop circuit is electrically connected to the controller, the detection module, and the control terminal of the power adjustment transistor in the H-bridge circuit, respectively. It is used to receive the inner current loop reference signal and the current detection signal, and to perform negative feedback adjustment on the inner current loop reference signal based on the current detection signal to obtain the continuous adjustment drive signal, and to output the continuous adjustment drive signal to the control terminal of the power adjustment transistor in the H-bridge circuit.

[0010] In some embodiments, the controller obtains a current setpoint based on the target current amplitude, subtracts the feedback current value corresponding to the current detection signal from the current setpoint to obtain a current deviation value, and performs PI processing on the current deviation value to obtain the current inner loop reference signal.

[0011] In some embodiments, the detection module is further configured to detect the temperature of the power regulation transistor in the H-bridge circuit, obtain a temperature detection signal, and output the temperature detection signal to the controller; The controller obtains a current compensation offset value based on the current detection signal and the temperature detection signal, and obtains the current setpoint value based on the current compensation offset value and the target current amplitude.

[0012] In some embodiments, the controller determines the corresponding current compensation offset value by linear piecewise fitting based on the current detection signal, the temperature detection signal, and a preset mapping table; wherein, the mapping table defines the linear relationship between the current compensation offset value and the temperature value corresponding to the temperature detection signal and the current value corresponding to the current detection signal within multiple temperature value intervals and multiple current value intervals.

[0013] In some embodiments, the detection module is used to detect the current output from the load port to the load according to a preset detection cycle; The controller is used to calculate the current setpoint at the current moment according to the following formula: Iref(k)=Iset+ΔIcomp[Ttemp,Ifb(k)]; Where Iref(k) is the current given value at the current moment, Iset is the target current amplitude, ΔIcomp[Ttemp,Ifb(k)] is the current compensation offset value at the current moment, Ttemp is the temperature value corresponding to the temperature detection signal at the current moment, and Ifb(k) is the current value corresponding to the current detection signal at the current moment.

[0014] In some embodiments, the controller is configured to calculate the signal amplitude of the current inner loop reference signal at the current moment according to the following formula: u(k)=Kp×[e(k)-e(k-1)]+Ki×e(k)+u(k-1); e(k) = Iref(k) Ifb(k); e(k-1)=Iref(k-1) Ifb(k-1); Where u(k) is the signal amplitude of the current inner loop reference signal at the current moment, Kp is the proportional coefficient, Ki is the integral coefficient, e(k) is the current deviation value at the current moment, e(k-1) is the current deviation value at the previous detection moment, u(k-1) is the signal amplitude of the current inner loop reference signal at the previous detection moment, Iref(k-1) is the current setpoint value at the previous detection moment, and Ifb(k-1) is the current value corresponding to the current detection signal at the previous detection moment.

[0015] In some embodiments, the inner current loop circuit includes: An operational amplifier is provided, wherein the non-inverting input terminal of the operational amplifier is electrically connected to the controller for receiving the current inner loop reference signal output by the controller, the inverting input terminal of the operational amplifier is electrically connected to the detection module for receiving the current detection signal output by the detection module, and the output terminal of the operational amplifier is electrically connected to the control terminal of the power adjustment transistor in the H-bridge circuit for outputting a corresponding continuous adjustment drive signal to the power adjustment transistor. Phase compensation resistor; A phase compensation capacitor, connected in series with the phase compensation resistor, is connected between the inverting input and output terminals of the operational amplifier; and The filter capacitor is electrically connected between the inverting input and output terminals of the operational amplifier.

[0016] A second aspect of this application also provides a control method for a power supply circuit, the control method being applied to the power supply circuit described in the first aspect above, the control method comprising: Obtain the target frequency and target current amplitude; The current output from the load port to the load is detected to obtain the corresponding current detection signal; The H-bridge circuit outputs a PWM drive signal with a frequency of the target frequency to the switching MOSFET in the H-bridge circuit, and based on the current detection signal and the target current amplitude, outputs a continuous adjustment drive signal with a frequency of the target frequency to the power adjustment transistor in the H-bridge circuit, so that the H-bridge circuit converts the received DC power into electrical energy and outputs a pulse current with a frequency of the target frequency and an amplitude of the target current amplitude to the load connected to the load port. The amplitude of the continuously adjusting drive signal is related to the amplitude of the target current.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] Figure 1This is a schematic diagram of the power supply circuit provided in an embodiment of this application; Figure 2 for Figure 1 The timing diagram of the drive signals for the power supply circuit shown; Figure 3 for Figure 1 The waveform diagram of the pulse current output by the power supply circuit is shown. Figure 4 A flowchart of a power supply circuit control method provided in an embodiment of this application.

[0019] The annotations in the attached figures are explained as follows: Power supply circuit 1; Load 2; Power supply port 10; Positive terminal 11; Negative terminal 12; Load port 20; First terminal 21; Second terminal 22; H-bridge circuit 30; First bridge arm 31; Second bridge arm 32; Detection module 40; Control circuit 50; Controller 51; Current inner loop circuit 52; First current inner loop circuit 521; Second current inner loop circuit 522; First switching MOSFET Q1; Second switching MOSFET Q2; First transistor Q3; Second transistor Q4; Current detection signal FB; First isolated gate driver chip U3; Second isolated gate driver chip U4; First current inner loop reference signal A1; Second current inner loop reference signal A2; First PWM drive signal PWM1; Second PWM drive signal PWM2; First operational amplifier U1; First phase compensation resistor R1; First phase compensation capacitor C1; First filter capacitor C2; Second operational amplifier U2; Second phase compensation resistor R2; Second phase compensation capacitor C3; Second filter capacitor C4.

[0020] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0021] In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0022] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0023] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] The various embodiments of this application can be combined arbitrarily to achieve different technical effects.

[0025] As electronic components move towards higher density and miniaturization, the manufacturing process of printed circuit boards (PCBs) is becoming increasingly complex. In particular, the through-hole plating and high aspect ratio processes of high-end PCBs place extremely stringent requirements on pulse plating power supplies. An ideal pulse plating power supply should possess characteristics such as steep pulse edges, rapid switching between forward and reverse currents, extremely low steady-state output ripple, and high current control precision to ensure plating uniformity, consistent copper thickness in holes, and overall board quality.

[0026] Currently, the industry widely adopts the isomorphic H-bridge topology of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) as the core conversion structure of pulse electroplating power supplies. This topology utilizes the fast switching characteristics of MOSFETs to achieve high response speeds, meeting basic high-frequency pulse output requirements. However, in practical applications, the full-bridge structure inevitably generates parasitic oscillations during full-domain high-frequency modulation, resulting in severe ripple glitches at the output, causing pulse waveform distortion. To suppress such interference, existing technologies typically require adding large-capacity filter capacitors at the front end of the power supply and connecting a series reactor at the rear end, significantly increasing the overall size of the device and hindering system integration and miniaturization design.

[0027] More importantly, the introduction of high-frequency noise degrades the accuracy of current sampling and further exacerbates pulse waveform distortion. This makes it difficult to guarantee the precise ratio of forward and reverse pulses, directly affecting the control of electroplating process parameters. In actual production, defects such as uneven plating, thin copper holes, and even localized burning of the board surface caused by pulse waveform distortion frequently occur, severely restricting the yield improvement of high-reliability PCB products.

[0028] Therefore, how to effectively suppress parasitic oscillations and output ripples in the H-bridge topology without relying on large-volume filter components, while maintaining pulse edge steepness and current switching speed, and improving sampling accuracy and waveform fidelity, has become a pressing technical challenge in the field of PCB pulse electroplating power supplies.

[0029] In view of this, embodiments of this application provide a power supply circuit. Please refer to... Figure 1 , Figure 1 This is a schematic diagram of the power supply circuit provided in an embodiment of this application.

[0030] like Figure 1 As shown, the power supply circuit 1 includes a power port 10, a load port 20, an H-bridge circuit 30, a detection module 40, and a control circuit 50.

[0031] The power port 10 includes a positive terminal 11 and a negative terminal 12 for receiving DC power.

[0032] The load port 20 includes a first end 21 and a second end 22 for electrical connection with the load 2.

[0033] The H-bridge circuit 30 includes a first bridge arm 31 and a second bridge arm 32. The first bridge arm 31 includes a first upper bridge arm switch and a first lower bridge arm switch electrically connected between the positive terminal 11 and the negative terminal 12 of the power supply port 10. The second bridge arm 32 includes a second upper bridge arm switch and a second lower bridge arm switch electrically connected between the positive terminal 11 and the negative terminal 12 of the power supply port 10. The midpoint of the first bridge arm 31 is electrically connected to the first end 21 of the load port 20, and the midpoint of the second bridge arm 32 is electrically connected to the second end 22 of the load port 20.

[0034] Wherein, the first upper bridge arm switch and the second upper bridge arm switch are power regulators, and the first lower bridge arm switch and the second lower bridge arm switch are switching MOSFETs; or, the first upper bridge arm switch and the second upper bridge arm switch are switching MOSFETs, and the first lower bridge arm switch and the second lower bridge arm switch are power regulators. The power regulator includes at least one of a transistor and a linearly adjustable MOSFET.

[0035] Among them, a switching MOSFET refers to a power MOSFET that operates in switching mode. Its gate receives a PWM drive signal with a fixed amplitude, and it mainly alternates between the cutoff region and the fully on region during operation. A linearly regulated MOSFET refers to a power MOSFET that operates in the linearly regulated region (i.e., the saturation region / constant current region). Its gate receives a continuously variable drive signal with an amplitude that changes with feedback. By adjusting the gate-source voltage Vgs, the drain current Id is continuously controlled to achieve precise regulation of the output voltage or current. For example, such as... Figure 1 As shown, the first upper bridge arm switch includes a first switching MOSFET Q1, the second upper bridge arm switch includes a second switching MOSFET Q2, the first lower bridge arm switch includes a first transistor Q3, and the second lower bridge arm switch includes a second transistor Q4.

[0036] The detection module 40 includes a current sensor, which is electrically connected to the load port 20. The detection module 40 detects the current output from the load port 20 to the load through the current sensor and obtains the corresponding current detection signal FB.

[0037] The control circuit 50 is electrically connected to the control terminal of the switching transistor in the H-bridge circuit 30 and the detection module 40, respectively. The control circuit 50 is used to acquire the target frequency and the target current amplitude, receive the current detection signal FB output by the detection module 40, and output a PWM drive signal with the target frequency to the switching MOS transistor in the H-bridge circuit 30. Based on the current detection signal FB and the target current amplitude, it outputs a continuous adjustment drive signal with the target frequency to the power adjustment transistor in the H-bridge circuit 30, so that the H-bridge circuit 30 converts the received DC power into electrical energy and outputs a pulse current with the target frequency and the target current amplitude to the load 2 connected to the load port 20.

[0038] The amplitude of the continuously adjusting drive signal is related to the amplitude of the target current.

[0039] The power supply circuit 1 can be used in an electroplating power supply, and the load 2 can be an electroplating device.

[0040] The target frequency and the target current amplitude can be freely configured through the human-machine interface.

[0041] The power supply circuit 1 provided in this application embodiment provides a heterogeneous H-bridge circuit 30 with asymmetrical upper and lower bridge arms. The two bridge arms are composed of a hybrid power loop using switching MOSFETs and power adjustment transistors. The control circuit 50 outputs a PWM drive signal with a target frequency to the switching MOSFETs in the H-bridge circuit 30, and a continuously adjusting drive signal with a target frequency to the power adjustment transistors in the H-bridge circuit 30 based on the current detection signal FB and the target current amplitude. This enables the H-bridge circuit 30 to convert the received DC power into electrical energy and output a pulse current with a target frequency and an amplitude of the target current to the load 2 connected to the load port 20. On the one hand, since the switching MOSFETs have the characteristics of fast switching speed and rapid commutation response, they mainly undertake the task of commutating the positive and negative currents of the circuit. In this way, the polarity of the pulse current can be switched quickly, ensuring that the pulse current edge is steep and without tail distortion. On the other hand, since the power regulator has the advantages of excellent linear regulation characteristics, smooth conduction current, and controllable steady-state voltage drop, it can cancel high-frequency glitches caused by switching noise and parasitic oscillations in real time, compress current ripple, and achieve low-ripple steady-state output and high-precision dynamic regulation. Therefore, the power supply circuit 1 provided in this application embodiment combines the high-speed characteristics of the switching MOSFET with the linear advantages of the power regulator, and can achieve both dynamic commutation capability and steady-state low-ripple performance without the need for large-capacity filtering devices, thus realizing high-fidelity pulse current output.

[0042] In some embodiments of this application, the control circuit 50 includes a controller 51 and a current inner loop circuit 52.

[0043] The controller 51 is electrically connected to the control terminals of the switching MOSFETs (i.e., the first switching MOSFET Q1 and the second switching MOSFET Q2) in the detection module 40 and the H-bridge circuit 30. The controller 51 is used to acquire the target frequency and the target current amplitude, receive the current detection signal FB output by the detection module 40, output a PWM drive signal with the target frequency to the switching MOSFETs in the H-bridge circuit 30, and generate a current inner loop reference signal based on the current detection signal FB and the target current amplitude through a current outer loop control algorithm.

[0044] The inner current loop circuit 52 is electrically connected to the controller 51, the detection module 40, and the control terminals of the power adjustment transistors (i.e., the first transistor Q3 and the second transistor Q4) in the H-bridge circuit 30. The inner current loop circuit 52 receives the inner current loop reference signal output by the controller 51 and the current detection signal FB output by the detection module 40. Based on the current detection signal FB, the inner current loop circuit 52 performs negative feedback adjustment on the inner current loop reference signal to obtain the continuous adjustment drive signal, and outputs the continuous adjustment drive signal to the control terminal of the power adjustment transistor in the H-bridge circuit 30.

[0045] Specifically, such as Figure 2 As shown, the PWM drive signals output by the controller 51 include a first PWM drive signal PWM1 output to the gate of the first switching MOSFET Q1 and a second PWM drive signal PWM2 output to the gate of the second switching MOSFET Q2. The current inner loop reference signals output by the controller 51 include a first current inner loop reference signal A1 and a second current inner loop reference signal A2. The first PWM drive signal PWM1 and the second PWM drive signal PWM2 are complementary (i.e., substantially out of phase), the first current inner loop reference signal A1 and the second current inner loop reference signal A2 are complementary, and the phase of the first PWM drive signal PWM1 is the same as the phase of the second current inner loop reference signal A2.

[0046] The current inner loop circuit 52 includes a first current inner loop circuit 521 and a second current inner loop circuit 522. The first current inner loop circuit 521 is electrically connected to the controller 51, the first transistor Q3, and the detection module 40, respectively. Based on the current detection signal FB, the first current inner loop circuit 521 performs negative feedback adjustment on the first current inner loop reference signal A1 output by the controller 51 to obtain a first continuous adjustment drive signal, and outputs the first continuous adjustment drive signal to the base of the first transistor Q3.

[0047] The second current inner loop circuit 522 is electrically connected to the controller 51, the second transistor Q4, and the detection module 40, respectively. Based on the current detection signal FB, the second current inner loop circuit 522 performs negative feedback adjustment on the second current inner loop reference signal A2 output by the controller 51 to obtain the second continuous adjustment drive signal, and outputs the second continuous adjustment drive signal to the base of the second transistor Q4.

[0048] Please refer to the following: Figures 1-3 During operation, the power supply circuit 1 cycles through a positive pulse phase and a negative pulse phase. During the positive pulse phase, the first switching MOSFET Q1 and the second transistor Q4 are turned on, while the second switching MOSFET Q2 and the first transistor Q3 are turned off. During the negative pulse phase, the second switching MOSFET Q2 and the first transistor Q3 are turned on, while the first switching MOSFET Q1 and the second transistor Q4 are turned off.

[0049] Thus, the controller 51, based on the same timer and the target frequency of the positive and negative pulses, uses a timing allocation algorithm to uniformly allocate the turn-on and turn-off times of the two drive signals of the H-bridge circuit 30. This ensures that the obtained PWM drive signal and the current inner loop reference signal are synchronized in timing, preventing direct connection between the positive and negative terminals of the H-bridge circuit 30 and adapting to high-speed commutation timing requirements. Furthermore, the use of a software current outer loop + hardware current inner loop nested dual closed-loop control architecture enables the functional decomposition and time-division collaborative operation of the switching MOSFET and power regulation transistor. During the pulse commutation phase, the current outer loop can correct the output current deviation in real time and dynamically generate the current inner loop reference signal, providing a precise reference for the current inner loop. This allows for real-time correction of current overshoot, suppression of commutation shocks, and guarantees overall current accuracy while eliminating static errors. During the steady-state pulse phase, the hardware inner loop can acquire the current detection signal FB output by the detection module 40 in real time and quickly compare the current detection signal FB with the current inner loop reference signal output by the current outer loop. This allows for dynamic correction of the linear operating point of the power regulator. In this way, the hardware inner loop is fully responsible for fine current control, continuously reducing ripple, optimizing current smoothness, and filtering out high-frequency noise. Furthermore, since the hardware inner loop has strong instantaneous anti-interference capability, it can effectively improve the consistency of pulse current. Therefore, when the power supply circuit 1 is applied to an electroplating power supply, it can reduce plating color difference and thin copper hole defects, making it suitable for high-end PCB high aspect ratio precision pulse electroplating conditions.

[0050] In some embodiments of this application, the controller 51 includes a control chip and a digital-to-analog converter (DAC). The DAC converts the first current inner loop reference signal A1 and the second current inner loop reference signal A2 output by the control chip from digital signals into analog signals (e.g., analog signals of 0-3V, where 3V corresponds to the maximum current value) and then outputs them to the first current inner loop circuit 521 and the second current inner loop circuit 522. The control chip may include, but is not limited to: a microcontroller unit (MCU), an ARM-based processor (ARM, Advanced RISC Machine), a digital signal processor (DSP), a field-programmable gate array (FPGA), a microprocessor unit (MPU), a system-on-chip (SOC), a programmable logic controller (PLC), and an application-specific integrated circuit (ASIC). For example, the control chip can be a high-performance STM32G4xxx series chip with a sampling frequency of up to 4MHz, which can provide high signal-to-noise ratio raw data for closed-loop operation.

[0051] In some embodiments of this application, the power supply circuit 1 further includes a first isolated gate driver chip U3 and a second isolated gate driver chip U4. The first isolated gate driver chip U3 is electrically connected between the controller 51 and the gate of the first switching MOSFET Q1, and the second isolated gate driver chip U4 is electrically connected between the controller 51 and the gate of the second switching MOSFET Q2. The first isolated gate driver chip U3 and the second isolated gate driver chip U4 are used to isolate and amplify the PWM drive signal output by the controller 51 into a strong gate drive signal sufficient for fast switching of the high-voltage power transistor. The first isolated gate driver chip U3 and the second isolated gate driver chip U4 are both selected as low propagation delay, high-speed isolated driver chips to minimize the transmission timing error introduced by the isolation link, ensure the synchronization of the switching actions of each bridge arm, and meet the fast commutation timing requirements of the power devices. The controller 51 can also pre-compensate the phase difference through software based on the fixed propagation delay of the first isolated gate driver chip U3 and the second isolated gate driver chip U4 to offset the timing offset caused by the isolated drive, ensuring the fast commutation synchronization of the switching MOSFET.

[0052] In some embodiments of this application, the first current inner loop reference signal A1 and the second current inner loop reference signal A2 are voltage signals. The controller 51 obtains a current setpoint based on the target current amplitude, subtracts the feedback current value corresponding to the current detection signal FB from the current setpoint to obtain a current deviation value, performs PI processing on the current deviation value to obtain a reference voltage value, and generates a first current inner loop reference signal A1 and a second current inner loop reference signal A2 with an amplitude of the reference voltage value and a frequency of the target frequency.

[0053] Thus, the software current outer loop uses a floating-point PI adjustment algorithm to achieve linear constant current drive of the power regulator, ensuring that the power regulator's conduction state is stable and the current is continuous without sudden changes.

[0054] In some embodiments of this application, the detection module 40 further includes a temperature sensor. The detection module 40 detects the temperature of the power adjustment transistor (i.e., the first transistor Q3 and / or the second transistor Q4) in the H-bridge circuit 30 through the temperature sensor, obtains a temperature detection signal, and outputs the temperature detection signal to the controller 51.

[0055] The controller 51 obtains a current compensation offset value based on the current detection signal FB and the temperature detection signal, and obtains the current setpoint value based on the current compensation offset value and the target current amplitude.

[0056] Since the voltage difference Vbe and β parameter between the base and emitter of a transistor will drift with temperature and operating current, the current compensation offset value obtained based on the transistor's current and temperature can be used to compensate the transistor's drive signal. This can offset the current deviation caused by the nonlinearity of the transistor device in real time, greatly widen the operating temperature range, and improve the accuracy of linear constant current control under all operating conditions.

[0057] In some embodiments of this application, the controller 51 determines the corresponding current compensation offset value through a linear piecewise fitting method based on the current detection signal FB, the temperature detection signal, and a preset mapping table. The mapping table defines the linear relationship between the current compensation offset value and the temperature value corresponding to the temperature detection signal and the current value corresponding to the current detection signal FB within multiple temperature value intervals and multiple current value intervals.

[0058] The detection module 40 is used to detect the current output from the load port 20 to the load according to a preset detection cycle.

[0059] The controller 51 is used to calculate the current setpoint at the current moment according to the following formula: Iref(k)=Iset+ΔIcomp[Ttemp,Ifb(k)]; Where Iref(k) is the current given value at the current moment, Iset is the target current amplitude, ΔIcomp[Ttemp,Ifb(k)] is the current compensation offset value at the current moment, Ttemp is the temperature value corresponding to the temperature detection signal at the current moment, and Ifb(k) is the current value corresponding to the current detection signal FB at the current moment.

[0060] Thus, by acquiring the actual circuit current and the operating temperature of the power regulating tube in real time through the detection module 40, and by pre-storing multiple sets of linear piecewise fitting coefficients corresponding to different temperature and current conditions in the controller 51, a complete compensation algorithm logic is constructed. The real-time temperature and sampled current can be used as input variables, and the current compensation offset ΔIcomp[Ttemp,Ifb(k)] can be obtained through piecewise linear operation, thereby completing the compensation of the transistor's drive signal and eliminating the current deviation caused by the nonlinearity of the transistor device.

[0061] In some embodiments of this application, the controller 51 is used to calculate the signal amplitude of the current inner loop reference signal at the current moment according to the following formula: u(k)=Kp×[e(k)-e(k-1)]+Ki×e(k)+u(k-1); e(k) = Iref(k) Ifb(k); e(k-1)=Iref(k-1) Ifb(k-1); Where u(k) is the signal amplitude of the current inner loop reference signal at the current moment, Kp is the proportional coefficient, Ki is the integral coefficient, e(k) is the current deviation value at the current moment, e(k-1) is the current deviation value at the previous detection moment, u(k-1) is the signal amplitude of the current inner loop reference signal at the previous detection moment, Iref(k-1) is the current setpoint value at the previous detection moment, and Ifb(k-1) is the current value corresponding to the current detection signal FB at the previous detection moment.

[0062] Thus, based on the signal amplitude of the current inner loop reference signal at the previous detection moment, the signal amplitude of the current inner loop reference signal at the current moment is obtained by using an incremental floating-point PI algorithm, retaining the historical output state, which can achieve continuous and non-abrupt load current regulation.

[0063] In some embodiments of this application, the inner current loop circuit 52 includes an operational amplifier, a phase compensation resistor, a phase compensation capacitor, and a filter capacitor.

[0064] The non-inverting input of the operational amplifier is electrically connected to the controller 51 to receive the current inner loop reference signal output by the controller 51. The inverting input of the operational amplifier is electrically connected to the detection module 40 to receive the current detection signal FB output by the detection module 40. The output of the operational amplifier is electrically connected to the control terminal of the power adjustment transistor in the H-bridge circuit 30 to output a corresponding continuous adjustment drive signal to the power adjustment transistor.

[0065] The phase compensation capacitor and the phase compensation resistor are connected in series between the inverting input and output of the operational amplifier.

[0066] The filter capacitor is electrically connected between the inverting input terminal and the output terminal of the operational amplifier.

[0067] Specifically, such as Figure 1 As shown, the first current inner loop circuit 521 includes a first operational amplifier U1, a first phase compensation resistor R1, a first phase compensation capacitor C1, and a first filter capacitor C2.

[0068] The first operational amplifier U1 has its non-inverting input terminal electrically connected to the controller 51 to receive the first current inner loop reference signal A1 output by the controller 51. The first operational amplifier U1 has its inverting input terminal electrically connected to the detection module 40 to receive the current detection signal FB output by the detection module 40. The first operational amplifier U1 has its output terminal electrically connected to the base of the first transistor Q3. The first operational amplifier U1 is used to output a first continuous adjustment drive signal to the first transistor Q3.

[0069] The first phase compensation capacitor C1 and the first phase compensation resistor R1 are connected in series between the inverting input terminal and the output terminal of the first operational amplifier U1.

[0070] The first filter capacitor C2 is electrically connected between the inverting input terminal and the output terminal of the first operational amplifier U1.

[0071] Similarly, the second current inner loop circuit 522 includes a second operational amplifier U2, a second phase compensation resistor R2, a second phase compensation capacitor C3, and a second filter capacitor C4.

[0072] The non-inverting input of the second operational amplifier U2 is electrically connected to the controller 51 to receive the second current inner loop reference signal A2 output by the controller 51. The inverting input of the second operational amplifier U2 is electrically connected to the detection module 40 to receive the current detection signal FB output by the detection module 40. The output of the second operational amplifier U2 is electrically connected to the base of the second transistor Q4, and the second operational amplifier U2 is used to output a second continuous adjustment drive signal to the second transistor Q4.

[0073] The second phase compensation capacitor C3 and the second phase compensation resistor R2 are connected in series between the inverting input terminal and the output terminal of the second operational amplifier U2.

[0074] The second filter capacitor C4 is electrically connected between the inverting input terminal and the output terminal of the second operational amplifier U2.

[0075] The operational amplifier amplifies the difference between the set voltage (i.e., the voltage corresponding to the current inner loop reference signal) and the sampling feedback voltage (i.e., the voltage corresponding to the current detection signal FB), and outputs a continuous adjustment drive signal to the corresponding transistor. By dynamically adjusting the transistor's on-state voltage drop through the negative feedback mechanism, the pulse current output by the loop can be quickly stabilized.

[0076] The phase compensation resistor and phase compensation capacitor are connected in series to form a Miller phase compensation network, which is connected between the output terminal and the inverting input terminal of the operational amplifier. This network can correct the loop phase margin and eliminate closed-loop self-excited oscillation.

[0077] The filter capacitor is connected in parallel to the input side of the operational amplifier, which can filter out high-frequency noise in the current detection signal FB, ensuring the steady-state constant current accuracy and dynamic response stability of the analog inner loop.

[0078] Thus, the inner current loop circuit is constructed entirely of analog hardware, achieving a response speed at the microsecond level. The operational amplifier amplifies the differential error between the set voltage and the sampled feedback voltage, generating a continuously adjusting drive signal sent to the base of the transistor. This dynamically adjusts the transistor's base current and voltage drop, effectively offsetting current drift caused by fluctuations in input voltage and load impedance, ultimately achieving a high-precision, high-stability linear constant current drive output.

[0079] Please see Figure 4 , Figure 4 A flowchart illustrating a control method for a power supply circuit provided in an embodiment of this application. Based on the same concept, this application also provides a control method for a power supply circuit, which is applied to the power supply circuit 1 described in any of the preceding embodiments. The control method includes the following steps S1 to S3.

[0080] Step S1: Obtain the target frequency and target current amplitude; Step S2: Detect the current output from the load port 20 to the load and obtain the corresponding current detection signal FB; Step S3: Output a PWM drive signal with the target frequency to the switching MOS transistor in the H-bridge circuit 30, and output a continuous adjustment drive signal with the target frequency to the power adjustment transistor in the H-bridge circuit 30 based on the current detection signal FB and the target current amplitude, so that the H-bridge circuit 30 performs power conversion on the received DC power and outputs a pulse current with the target frequency and the target current amplitude to the load connected to the load port 20.

[0081] The amplitude of the continuously adjusting drive signal is related to the amplitude of the target current.

[0082] It should be noted that the control method of the power supply circuit corresponds to the aforementioned power supply circuit 1. For a more detailed description, please refer to the contents of the various embodiments of the aforementioned power supply circuit 1, which will not be repeated here.

[0083] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0084] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0085] In summary, the above description is merely an embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the disclosure of this application should be included within the scope of protection of this application.

Claims

1. A power supply circuit, characterized in that, The power supply circuit includes: The power supply port includes a positive terminal and a negative terminal for receiving DC power. Load port, used for electrical connection to the load; An H-bridge circuit includes a first bridge arm and a second bridge arm. The first bridge arm includes a first upper bridge arm switch and a first lower bridge arm switch electrically connected between the positive and negative terminals of the power supply port. The second bridge arm includes a second upper bridge arm switch and a second lower bridge arm switch electrically connected between the positive and negative terminals of the power supply port. The midpoint of the first bridge arm and the second bridge arm is electrically connected to the load port. The first upper bridge arm switch and the second upper bridge arm switch are power regulation transistors, and the first lower bridge arm switch and the second lower bridge arm switch are switching MOSFETs; alternatively, the first upper bridge arm switch and the second upper bridge arm switch are switching MOSFETs, and the first lower bridge arm switch and the second lower bridge arm switch are power regulation transistors. A detection module, electrically connected to the load port, is used to detect the current output from the load port to the load and obtain a corresponding current detection signal; and The control circuit is electrically connected to the control terminal of the switching transistor in the H-bridge circuit and the detection module, respectively. The control circuit is used to acquire the target frequency and the target current amplitude, receive the current detection signal output by the detection module, and output a PWM drive signal with the target frequency to the switching MOSFET in the H-bridge circuit. Based on the current detection signal and the target current amplitude, the control circuit outputs a continuously adjusting drive signal with the target frequency to the power adjustment transistor in the H-bridge circuit, so that the H-bridge circuit converts the received DC power into electrical energy and outputs a pulse current with the target frequency and the target current amplitude to the load connected to the load port. The amplitude of the continuously adjusting drive signal is related to the target current amplitude.

2. The power supply circuit as described in claim 1, characterized in that, The power regulation transistor includes at least one of a transistor and a linearly regulated MOSFET.

3. The power supply circuit as described in claim 1, characterized in that, The control circuit includes: The controller is electrically connected to the detection module and the control terminal of the switching MOSFET in the H-bridge circuit. The controller is used to acquire the target frequency and target current amplitude, receive the current detection signal output by the detection module, output a PWM drive signal with the target frequency to the switching MOSFET in the H-bridge circuit, and generate a current inner loop reference signal based on the current detection signal and the target current amplitude using a current outer loop control algorithm. The inner current loop circuit is electrically connected to the controller, the detection module, and the control terminal of the power adjustment transistor in the H-bridge circuit, respectively. It is used to receive the inner current loop reference signal and the current detection signal, and to perform negative feedback adjustment on the inner current loop reference signal based on the current detection signal to obtain the continuous adjustment drive signal, and to output the continuous adjustment drive signal to the control terminal of the power adjustment transistor in the H-bridge circuit.

4. The power supply circuit as described in claim 3, characterized in that, The controller obtains a current setpoint based on the target current amplitude, subtracts the feedback current value corresponding to the current detection signal from the current setpoint to obtain a current deviation value, and performs PI processing on the current deviation value to obtain the current inner loop reference signal.

5. The power supply circuit as described in claim 4, characterized in that, The detection module is also used to detect the temperature of the power regulation transistor in the H-bridge circuit, obtain a temperature detection signal, and output the temperature detection signal to the controller; The controller obtains a current compensation offset value based on the current detection signal and the temperature detection signal, and obtains the current setpoint value based on the current compensation offset value and the target current amplitude.

6. The power supply circuit as described in claim 5, characterized in that, The controller determines the corresponding current compensation offset value by linear piecewise fitting based on the current detection signal, the temperature detection signal, and a preset mapping table; wherein, the mapping table defines the linear relationship between the current compensation offset value and the temperature value corresponding to the temperature detection signal and the current value corresponding to the current detection signal within multiple temperature value intervals and multiple current value intervals.

7. The power supply circuit as described in claim 6, characterized in that, The detection module is used to detect the current output from the load port to the load according to a preset detection cycle; The controller is used to calculate the current setpoint at the current moment according to the following formula: Iref(k)=Iset+ΔIcomp[Ttemp,Ifb(k)]; Where Iref(k) is the current given value at the current moment, Iset is the target current amplitude, ΔIcomp[Ttemp,Ifb(k)] is the current compensation offset value at the current moment, Ttemp is the temperature value corresponding to the temperature detection signal at the current moment, and Ifb(k) is the current value corresponding to the current detection signal at the current moment.

8. The power supply circuit as described in claim 7, characterized in that, The controller is used to calculate the signal amplitude of the current inner loop reference signal at the current moment according to the following formula: u(k)=Kp×[e(k)-e(k-1)]+Ki×e(k)+u(k-1); e(k)=Iref(k) Ifb(k); e(k-1)=Iref(k-1) Ifb(k-1); Where u(k) is the signal amplitude of the current inner loop reference signal at the current moment, Kp is the proportional coefficient, Ki is the integral coefficient, e(k) is the current deviation value at the current moment, e(k-1) is the current deviation value at the previous detection moment, u(k-1) is the signal amplitude of the current inner loop reference signal at the previous detection moment, Iref(k-1) is the current setpoint value at the previous detection moment, and Ifb(k-1) is the current value corresponding to the current detection signal at the previous detection moment.

9. The power supply circuit as described in claim 3, characterized in that, The inner current loop circuit includes: An operational amplifier is provided, wherein the non-inverting input terminal of the operational amplifier is electrically connected to the controller for receiving the current inner loop reference signal output by the controller, the inverting input terminal of the operational amplifier is electrically connected to the detection module for receiving the current detection signal output by the detection module, and the output terminal of the operational amplifier is electrically connected to the control terminal of the power adjustment transistor in the H-bridge circuit for outputting a corresponding continuous adjustment drive signal to the power adjustment transistor. Phase compensation resistor; A phase compensation capacitor, connected in series with the phase compensation resistor, is connected between the inverting input and output terminals of the operational amplifier; and The filter capacitor is electrically connected between the inverting input and output terminals of the operational amplifier.

10. A control method for a power supply circuit, characterized in that, The control method is applied to the power supply circuit as described in any one of claims 1 to 9, and the control method includes: Obtain the target frequency and target current amplitude; The current output from the load port to the load is detected to obtain the corresponding current detection signal; The H-bridge circuit outputs a PWM drive signal with a frequency of the target frequency to the switching MOSFET in the H-bridge circuit, and based on the current detection signal and the target current amplitude, outputs a continuous adjustment drive signal with a frequency of the target frequency to the power adjustment transistor in the H-bridge circuit, so that the H-bridge circuit converts the received DC power into electrical energy and outputs a pulse current with a frequency of the target frequency and an amplitude of the target current amplitude to the load connected to the load port. The amplitude of the continuously adjusting drive signal is related to the amplitude of the target current.

Images