Modulation method of solid state transformer inverter stage and transformer

Abstract

The application discloses a modulation method of an inverter stage of a solid-state transformer and a transformer, and belongs to the field of multi-level transformers. The inverter stage is a three-phase cascaded H-bridge transformer, and each phase is composed of n voltage-type H-bridge sub-modules in series. The inverter stage further comprises a reference signal module and a control module. The reference signal module generates a phase voltage reference signal, and the control module generates a PWM pulse signal according to the reference signal to control the operating state of the transformer. The modulation method running in the control module is a direct modulation method based on adjacent voltage levels of a reference voltage. The application takes the positional relationship between the reference voltage and the adjacent voltage levels as the modulation basis, avoids coordinate transformation, trigonometric functions and irrational number operation, reduces the implementation difficulty of the high-level inverter stage transformer, and is helpful to the digital real-time modulation control and power level expansion of the solid-state transformer.

Description

Technical Field

[0001] This invention belongs to the field of multilevel converters, specifically relating to a modulation method and converter for the inverter stage of a solid-state transformer. Background Technology

[0002] With the continuous increase in the proportion of new energy sources, represented by wind and solar power, in end-use energy consumption, the trend of new energy gradually becoming the main energy source has become significant. Given the intermittent and fluctuating nature of new energy power generation, highly controllable power electronic devices have become an important technical means to achieve stable power conversion and regulation. Solid-state transformers achieve voltage conversion, electrical isolation, and bidirectional energy flow through power electronic conversion technology and high-frequency isolation technology. Their inverter stage is used to convert DC power into AC power. In high-voltage, high-power applications, due to the limitation of the voltage withstand capability of individual power semiconductor devices, the inverter stage of a solid-state transformer can usually adopt a cascaded structure, with multiple power units connected in series to share the output voltage and form a multi-level stepped voltage waveform.

[0003] Modulation strategy is fundamental to the operation of the inverter stage in a solid-state transformer, directly affecting the converter's dynamic response speed, output power quality, and other performance characteristics. Existing modulation methods for the inverter stage include space vector modulation, sinusoidal pulse width modulation, and nearest-nearest-level modulation, which typically require steps such as carrier comparison, coordinate transformation, region determination, sector location, or candidate state search. For inverter stages with high-level numbers, performing complex region location and screening of a large number of candidate states in each sampling period increases the computational burden on the digital controller and affects real-time implementation at higher switching frequencies, thereby impacting the power quality of the converter's output.

[0004] Therefore, it is necessary to provide a modulation method suitable for the inverter stage of a solid-state transformer, so that the controller can directly determine the state of the three-phase level participating in the synthesis and its duration of action within the sampling period based on the positional relationship between the three-phase reference voltage and adjacent levels, thereby reducing the computational complexity of modulation implementation. Summary of the Invention

[0005] The purpose of this invention is to provide a modulation method and converter for the inverter stage of a solid-state transformer. This addresses the problems of complex implementation, difficult switching state selection, and a sharp increase in computational load as the voltage level increases in traditional solid-state transformer inverter stage modulation methods.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] Step 1: The solid-state transformer inverter stage adopts a three-phase cascaded H-bridge converter. n The number of single-phase sub-modules in a three-phase cascaded H-bridge converter, and the output level range of the converter is [- n , n], obtain the converter a Mutually, b Harmony c Corresponding reference voltage , , : Due to the symmetry of the three-phase converter reference voltage, the three-phase reference voltage satisfies:

[0008] In the formula, , , It is within the output level range of a single phase of the converter.

[0009] Step two, for any phase According to the phase reference voltage Calculate the adjacent level Upper adjacent level and level margin Specifically: , , , , In the formula, floor( ) indicates not greater than The largest integer, ceil( ) indicates not less than The smallest integer. When hour, Located at integer level, ;when hour, Located between two adjacent integer levels, .

[0010] Step 3: Calculate the sum of the three-phase level margins. m : (4) Because the three-phase reference voltages are symmetrical, and , , All are integer levels, therefore m It is an integer; and since the level margin of each phase is within the range of [0,1), therefore m The value can be 0, 1 or 2.

[0011] The three-phase level margins are further arranged in order of magnitude as follows: (5) in p , q, r All from set The selection from the options represents the labels of the phases with the largest, second largest, and smallest level margins, respectively. When at least two level margins are equal, the selection is based on... a Mutually, b Mutually, c Phase sequence priority determination p , q , r The arrangement.

[0012] Step four, according to m The value of the switch state is used to construct the switch state. S The switching state has three components, representing the voltage levels of the three-phase output of the converter, and the duration of each switching state is also calculated. when m When =0, select the switch state. And make this state within a sampling period Internal effect.

[0013] when m When =1, let , , , Select three switch states: , , (6) The corresponding duration of action is: , , (7) when m When =2, let Select three three-phase synthesized level states: , , (8) The corresponding duration of action is: , , (9) From equations (7) and (9), it can be seen that, , , All are non-negative values.

[0014] Step 5, Limiting correction of switching states: Detect whether each phase component of all switching states participating in modulation exceeds [-] within one sampling period. n , n If all components are located in [- n ,n If any component of the switching state is greater than [a certain value], then no limiting correction will be performed; if any component of the switching state is greater than [a certain value], then no limiting correction will be performed. n Then the switch state is superimposed. y vectors If any component of the switch state is less than - n Then the state of the switch is superimposed. y vectors ;in, y To make the switch state satisfy [- n , n Output the minimum integer number of times the limit is reached; Step 6: Based on the duration of each switch state, within one sampling period... The internal switching states are time-division multiplexed to synthesize a reference voltage and complete modulation.

[0015] Compared with the prior art, the present invention has at least the following beneficial effects: First, the solid-state transformer inverter stage modulation method of the present invention uses the relative position of the reference voltage and the adjacent level as the modulation basis, without the need for Clark coordinate transformation, region number judgment, sector positioning or candidate state lookup table; Second, the state action time of the converter is directly obtained from the level margin difference, without involving trigonometric functions and irrational number operations; Third, the implementation steps of the converter operation are not limited by the size of the specific number of sub-modules inside the converter, which is convenient to extend to higher level numbers; Fourth, in the case where the reference voltage is at the boundary of integer level, it can degenerate into a synthesis method of single switch state, which is convenient for engineering implementation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following is a brief introduction to the drawings used in the prior art and embodiments. The following drawings are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 Inverter stage structure based on direct modulation of adjacent levels of reference voltage; Figure 2 Implementation steps flowchart; Figure 3 : A schematic diagram showing the relationship between the reference voltage and the lower adjacent voltage level, the upper adjacent voltage level, and the voltage margin; Figure 4 The output waveform diagram of the solid-state transformer inverter stage simulation using the method of this invention is shown below. Figure 4 (a) is a waveform diagram of the single-phase output level. Figure 4 (b) is a waveform diagram of line voltage. Detailed Implementation

[0018] To clearly illustrate the purpose, technical solution, and advantages of the present invention, the embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0019] In one specific embodiment, three-phase n Taking a cascaded H-bridge converter as an example, any phase of the converter is... n Composed of several voltage-type H-bridge modules connected in series, it can output 2 n +1 level. The level output range is [- n , n Inverter stage a , b , c Three-phase normalized reference voltage , , for:

[0020] In the formula, n The number of single-phase submodules. k The modulation coefficient, , This represents the angular frequency of the reference phase voltage. t The sampling time.

[0021] Assumption n =5, take , k =0.8, sampling period is The output level range of the cascaded H-bridge converter is [-5, 5]. At the sampling time... t =1 / 600 s At that time, the sampled three-phase reference voltage is: , ,

[0022] for a Phase, the lower adjacent level of reference voltage 4 is The upper adjacent level is The level margin is ;for b Phase, the lower adjacent level of the reference voltage 0 is The upper adjacent level is The level margin is ;for c Phase, the lower adjacent level of the reference voltage -4 is The upper adjacent level is The level margin is .

[0023] therefore, , , , m =0. According to m The rule for constructing a state with a value of 0 is to select a unique switch state:

[0024] Since all phase components of the switching state are within the range [-5, 5], no amplitude limiting correction is required. The duration of this switching state is equal to the sampling period. .

[0025] When sampling time t =1 / 400 s At that time, the sampled three-phase reference voltage is:

[0026] for a The lower adjacent level of the reference voltage is The upper adjacent level is The level margin is ;for b The lower adjacent level of the reference voltage is The upper adjacent level is The level margin is ;for c The lower adjacent level of the reference voltage is The upper adjacent level is The level margin is , .

[0027] because The relationship between the magnitudes of the three-phase level margins is as follows: ,Right now p = c , q = a , r = b .definition:

[0028] according to m From the rule for constructing the switch state with =1, we know that the three switch states involved in the synthesis are:

[0029] Since all phase components of the switching state are within [-5, 5], no limiting correction is required. The durations of the three states are as follows:

[0030]

[0031] Substituting into the level margin expression, we get:

[0032] In a sampling period Inside, , , The time-division composite reference voltage has the following application times: , , .

[0033] When sampling time t =1 / 1200 s At that time, the sampled three-phase reference voltage is:

[0034] for a The lower adjacent level of the reference voltage is The upper adjacent level is The level margin is ;for b The lower adjacent level of the reference voltage is The upper adjacent level is The level margin is ;for c The lower adjacent level of the reference voltage is The upper adjacent level is The level margin is , .

[0035] definition:

[0036] because , m =2. The relationship between the magnitudes of the three-phase level margins is as follows: ,Right now p = b , q = c , r = a .

[0037] according to m Given the switch state construction rule of =2, we know that the three switch states involved in the synthesis are:

[0038] Since all phase components of the switching state are within [-5, 5], no limiting correction is required. The durations of the three states are as follows:

[0039] Substituting into the level margin expression, we get:

[0040] In a sampling period Inside, , , The time-division composite reference voltage has the following application times: , , .

[0041] Figure 4 The number of single-phase submodules in the inverter stage is given. n =5. Sampling period =1 / 10000 s Modulation coefficient k The simulation output waveform obtained using the method of this invention when the value is 0.8, wherein... Figure 4 (a) is a waveform diagram of the single-phase output level. Figure 4 (b) is a waveform diagram of line voltage.

[0042] Finally, it should be noted that the above embodiments are only some embodiments of the present invention, and not all embodiments, used to illustrate the technical solutions of the present invention; those skilled in the art should understand that they can modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A converter with a solid-state transformer inverter stage, characterized in that, The inverter stage is a three-phase cascaded H-bridge converter, with each phase consisting of... n The inverter stage is composed of several voltage-source H-bridge inverter submodules connected in series. Each submodule contains four IGBTs, four diodes, and one DC voltage source. The diodes and IGBTs are connected in anti-parallel. The inverter stage also includes a reference signal module and a control module. The reference signal module generates the inverter stage voltage. a Mutually, b Harmony c Corresponding normalized reference voltage , , Among them, the three-phase reference voltage satisfies And it is located within the single-phase output level range of the converter [-n, n]. n It is a positive integer; The control module generates PWM pulse signals based on the reference signal to control the operating state of the converter. The modulation method used in the control module is a direct modulation method based on the adjacent level of the reference voltage.

2. A modulation method for a solid-state transformer inverter stage, characterized in that, Includes the following steps: Step 1: Sample the phase voltage reference signal; Step 2: For any phase The floor function is used for rounding down. Calculate the reference voltage for this phase. The next adjacent level Use the floor function ceil( Calculate the reference voltage for this phase. upper adjacent level , and by and The difference is used to calculate the level margin. : , , ;in, ;when When it is an integer level, and ;when When the level is not an integer, and ; Step 3: Calculate the sum of the three-phase level margins The three-phase level margins are arranged in order of magnitude as follows: ,in p , q , r All from set The numbers selected represent the phases with the largest, second largest, and smallest level margins, respectively. m The value can be 0, 1, or 2; Step Four: According to m The value of the switch state is used to construct the switch state. S The switching state has three components, representing the voltage levels of the three-phase output of the converter, and the duration of each switching state is also calculated. when m When =0, select the switch state. And make this state within a sampling period internal effect; when m When =1, let , , , Select three switch states: ， ， The corresponding duration of action is: ， ， when m When =2, let Select three three-phase synthesized level states: ， ， The corresponding duration of action is: ， ， Step 5: Limiting correction of switching states: Detect whether each phase component of all switching states participating in modulation exceeds [-] within one sampling period. n , n If all components are located in [- n , n If any component of the switching state is greater than [a certain value], then no limiting correction will be performed; if any component of the switching state is greater than [a certain value], then no limiting correction will be performed. n Then the switch state is superimposed. y vectors If any component of the switch state is less than - n Then the state of the switch is superimposed. y vectors ;in, y To make the switch state satisfy [- n , n Output the minimum integer number of times the limit is reached; Step Six: Based on the duration of each switch state, within one sampling period... The internal switching states are time-division multiplexed to synthesize a reference voltage and complete modulation.

3. The modulation method for a solid-state transformer inverter stage as described in claim 2, characterized in that, When at least two level margins are equal, according to a Mutually, b Mutually, c Phase sequence priority determination p , q , r The arrangement.

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