A start-up voltage output circuit and chip

Abstract

The embodiment of the application relates to the technical field of power management, and discloses a starting voltage output circuit and a chip, the starting voltage output circuit comprising: a control circuit and a charge pump circuit; the control circuit is connected with the charge pump circuit; the control circuit is configured to: output a first reference voltage to the charge pump circuit in a first time period, control the charge pump circuit to output an intermediate voltage; output a second reference voltage to the charge pump circuit in a second time period, control the charge pump circuit to output a starting voltage; the first time period and the second time period are continuous, and the second time period is located after the first time period; and the first reference voltage is less than the second reference voltage. The technical scheme of the application can shorten the time of the circuit from the sleep mode to the standby mode.

Description

Technical Field

[0001] This application relates to the field of power management technology, specifically to a startup voltage output circuit and chip. Background Technology

[0002] With the increasing demands for low power consumption and fast response in electronic devices, system-level power management technology has become a key aspect of integrated circuit design. To reduce standby power consumption, modern electronic devices typically support multiple low-power modes, among which sleep mode and standby mode are two main energy-saving states.

[0003] For example, current memory products can support hibernation mode. However, when the memory exits hibernation mode and enters standby mode, a bandgap reference voltage needs to be established first. Then, the charge pump builds up a startup voltage from zero potential. The established startup voltage is used to quickly respond to read and write operations on memory cells when switching from standby mode to active mode. The establishment time of the bandgap reference and the duration of the charge pump's startup voltage establishment directly determine the duration of exiting hibernation mode and entering standby mode. Summary of the Invention

[0004] This application provides a startup voltage output circuit and chip, which aims to shorten the startup voltage establishment time, thereby shortening the time for electronic devices to exit sleep mode and enter standby mode.

[0005] In a first aspect, embodiments of this application provide a startup voltage output circuit. This startup voltage output circuit includes a control circuit and a charge pump circuit. A first output terminal of the control circuit is connected to an input terminal of the charge pump circuit. The control circuit is configured to: provide a first reference voltage to the input terminal of the charge pump circuit during a first time period, controlling the charge pump circuit to output an intermediate voltage; and provide a second reference voltage to the input terminal of the charge pump circuit during a second time period, controlling the charge pump circuit to output a startup voltage. The first time period and the second time period are consecutive, with the second time period following the first time period; the first reference voltage is less than the second reference voltage, and the intermediate voltage is less than the startup voltage.

[0006] In this embodiment, the time for the charge pump circuit to establish the startup voltage is divided into two time periods, with the second reference voltage serving as a precise reference voltage for the charge pump circuit's output startup voltage. Since it takes time for the second reference voltage to establish from zero potential to a stable output voltage, during the first time period before the second reference voltage is fully established, the control circuit outputs a first reference voltage as the reference voltage for the charge pump circuit. This allows the charge pump circuit to start establishing a voltage based on a first reference voltage lower than the second voltage, generating an intermediate voltage lower than the startup voltage, even before the second reference voltage reaches a stable value. In the second time period after the second reference voltage is fully established, the control circuit outputs the second reference voltage as the reference voltage for the charge pump circuit, allowing the charge pump circuit to further establish a voltage based on the intermediate voltage, generating a startup voltage that meets the requirements.

[0007] The embodiments of this application make full use of the first time period before the second reference voltage stabilizes to pre-establish an intermediate voltage, so that the establishment of the start-up voltage does not need to start from zero potential, shortening the start-up voltage establishment time of the charge pump circuit, thereby shortening the time required for the electronic device to exit the hibernation mode and enter the standby mode.

[0008] In one possible implementation, the control circuit includes a voltage divider, a first voltage selector, a bandgap reference voltage source, and a pulse generator. The output of the voltage divider is connected to a first input of the first voltage selector to output a first reference voltage. The input of the bandgap reference voltage source receives a control signal, and its output is connected to a second input of the first voltage selector, generating a second reference voltage according to the control signal. The input of the pulse generator receives the control signal, and its output is connected to a control terminal of the first voltage selector, generating a pulse control signal according to the control signal. The output of the first voltage selector serves as the first output of the control circuit, and the first voltage selector is configured to provide either the first reference voltage or the second reference voltage to the input of the charge pump circuit according to the pulse control signal.

[0009] In this embodiment, after receiving the control signal, the bandgap reference voltage source begins to establish a second reference voltage and outputs it to the first voltage selector; the voltage divider, being connected to an external power supply, can output a stable first reference voltage to the first selector; after receiving the control signal, the pulse generator issues a pulse control signal to control the first voltage selector to provide the first reference voltage or the second reference voltage to the charge pump circuit, and the charge pump circuit establishes the intermediate voltage and the start-up voltage sequentially based on the reference voltage provided by the first voltage selector.

[0010] In one possible implementation, the pulse control signal includes a high-level signal and a low-level signal. A first voltage selector is configured to: provide a first reference voltage to the input of the charge pump circuit in response to the pulse control signal being a high-level signal; and provide a second reference voltage to the input of the charge pump circuit in response to the pulse control signal being a low-level signal. That is, the first voltage selector can provide the first reference voltage during a first time period after receiving the high-level signal, thereby enabling the charge pump circuit to establish an intermediate voltage based on zero potential; the first voltage selector can provide the second reference voltage during a second time period after receiving the low-level signal, thereby enabling the charge pump circuit to establish a startup voltage based on the intermediate voltage.

[0011] In one possible implementation, the duration of the high-level signal of the pulse control signal is related to the establishment time of the second reference voltage. Thus, during the duration of the high-level signal, i.e., during the establishment of the second reference voltage by the bandgap reference voltage source, the pulse control signal controls the first voltage selector to provide the first reference voltage to the charge pump circuit. After the high-level signal ends, i.e., from the completion of the second reference voltage establishment to the stable phase, the pulse control signal controls the first voltage selector to promptly switch to providing the second reference voltage to the charge pump circuit, ensuring that the time required for the output voltage of the charge pump circuit to establish from zero potential to the start-up voltage is minimized.

[0012] In one possible implementation, the voltage divider includes an enable terminal connected to the output terminal of the pulse generator. This allows the voltage divider to continuously output a stable first reference voltage while the pulse control signal is high, and to cease operation while the pulse control signal is low, thereby reducing power consumption in the circuit.

[0013] In one possible implementation, the charge pump circuit includes an operational amplifier, a charge pump, and a feedback loop. The non-inverting input of the operational amplifier is connected to the output of the feedback loop, the inverting input of the operational amplifier serves as the input of the charge pump circuit, the bias voltage input of the operational amplifier is connected to a bias voltage, and the output of the operational amplifier is connected to the input of the charge pump; the output of the charge pump is connected to the input of the feedback loop.

[0014] In this embodiment, the non-inverting input of the operational amplifier receives the feedback voltage from the feedback loop, and the inverting input receives either the first reference voltage or the second reference voltage output by the first voltage selector. The feedback voltage is the voltage output by the charge pump after passing through the feedback loop. By comparing the magnitude of the feedback voltage at the non-inverting input with the reference voltage at the inverting input, and connecting the bias voltage input of the operational amplifier to the bias voltage, closed-loop control of the charge pump's startup voltage can be achieved. This allows the charge pump to establish a stable intermediate voltage based on the first reference voltage and a stable startup voltage based on the second reference voltage.

[0015] In one possible implementation, the charge pump also includes an enable terminal for receiving a control signal. This allows the charge pump to start operating simultaneously with other devices in the startup voltage output circuit when a control signal is received, ensuring the shortest possible time for the charge pump to build up the startup voltage from zero potential. Simultaneously, the charge pump does not operate when no control signal is received, reducing power consumption in the circuit.

[0016] In one possible implementation, the second output terminal of the control circuit is connected to the bias voltage terminal of the operational amplifier. The control circuit also includes a bias voltage generator and a second voltage selector. The first input terminal of the second voltage selector is connected to the output terminal of the voltage divider; the input terminal of the bias voltage generator is connected to the output terminal of the bandgap reference voltage source, and the output terminal of the bias voltage generator is connected to the second input terminal of the second voltage selector. The bias voltage generator is configured to output a bias voltage based on a second reference voltage; the control terminal of the second voltage selector is connected to the output terminal of the pulse generator, and the output terminal of the second voltage selector serves as the second output terminal of the control circuit. Thus, under the control of a pulse control signal, the second voltage selector provides either a first reference voltage or a bias voltage to the charge pump circuit.

[0017] In one possible implementation, the second voltage selector is configured to: provide a first reference voltage to the bias voltage terminal of the operational amplifier in response to a high-level pulse control signal; and provide a bias voltage to the bias voltage terminal of the operational amplifier in response to a low-level pulse control signal.

[0018] In this embodiment, the output of the second voltage selector is controlled by a pulse control signal. During the duration of the high-level signal, the second voltage selector outputs a first reference voltage to provide a bias voltage for the operational amplifier; during the duration of the low-level signal, the second voltage selector outputs a bias voltage to provide a bias voltage for the operational amplifier, ensuring that the operational amplifier is always in normal working condition.

[0019] Secondly, embodiments of this application provide a chip. The chip includes a controller and a startup voltage output circuit as described in the first aspect. The controller is connected to the startup voltage output circuit and is configured to output a control signal to the startup voltage output circuit.

[0020] It should be understood that the technical effects of the second aspect can be referred to the first aspect, and the implementation methods of this application will not be described in detail here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual process of the product method or the actual timing of signals involved in the embodiments of this application.

[0022] Figure 1 This is a schematic diagram of the structure of a circuit for exiting sleep mode disclosed in an embodiment of this application; Figure 2 This is a waveform diagram illustrating the signal transmission from sleep mode to standby mode in an embodiment of this application. Figure 3 This is a schematic diagram of the structure of a startup voltage output circuit disclosed in an embodiment of this application; Figure 4 This is a waveform diagram illustrating the signal transmission of a startup voltage output circuit from sleep mode to standby mode according to an embodiment of this application. Figure 5 This is a schematic diagram of the structure of the first voltage divider disclosed in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the second voltage divider disclosed in the embodiments of this application; Figure 7 This is a schematic diagram of the third voltage divider disclosed in the embodiments of this application; Figure 8 This is a schematic diagram of the fourth voltage divider disclosed in the embodiments of this application; Figure 9 This is a schematic diagram of the structure of a chip disclosed in an embodiment of this application.

[0023] Explanation of reference numerals in the attached figures: 1. Exit Sleep Mode Circuit; 11. Bandgap Reference Voltage Source; 12. Delay Unit; 13. Bias Voltage Generator; 14. Charge Pump; 15. Feedback Loop; 16. Operational Amplifier; 2. Start-up Voltage Output Circuit; 20. Control Circuit; 201. Voltage Divider; 202. Pulse Generator; 203. First Voltage Selector; 204. Second Voltage Selector; 21. Charge Pump Circuit; 3. Chip; 30. Controller. Detailed Implementation

[0024] The embodiments of this application are described below with reference to the accompanying drawings.

[0025] The terms “first,” “second,” etc., are used for descriptive purposes only and have no sequential or technical meaning, nor should they be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0026] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0027] The term "electrical connection" refers to the flow of current or signal from one conductor to another. An electrical connection between A and B means that current or signal can flow from A to B and vice versa. This connection includes direct and indirect electrical connections. A direct electrical connection between A and B means that A and B are physically connected. An indirect electrical connection between A and B means that A and B are connected via C, where C can be at least one wire or device.

[0028] Non-volatile memory (such as NAND flash memory, NOR flash memory, etc.) and volatile memory (such as dynamic random access memory, DRAM) are widely integrated into various battery-powered portable electronic devices, such as smart wearable devices (watches, wristbands), wireless audio devices (true wireless earphones), IoT sensor nodes, and portable medical monitors. To reduce standby power consumption, these devices typically control the memory to enter a deep sleep mode during working intervals, and switch the memory from sleep mode to standby mode when data read / write operations are needed, thus quickly entering active mode.

[0029] This application provides a circuit for exiting sleep mode, such as... Figure 1 The circuit shown to exit sleep mode includes an inverter, a bandgap reference voltage source 11, a delay unit 12, an operational amplifier 16, a bias voltage generator 13, a charge pump 14, and a feedback loop 15.

[0030] The input terminal of the inverter is used to receive the sleep enable signal PD. The output terminal of the inverter is connected to the enable terminal of the bandgap reference voltage source 11 and the input terminal of the delay unit 12, respectively. The output terminal of the inverter is used to output the control signal PDB. The control signal PDB is out of phase with the sleep enable signal PD; that is, when the sleep enable signal PD is high, the control signal PDB is low, and when the sleep enable signal PD is low, the control signal PDB is high.

[0031] The bandgap reference voltage source 11 operates when the control signal PDB is high, generating a reference voltage signal VBG1. After receiving the reference voltage signal VBG1, the bias voltage generator 13 outputs a bias voltage VBIAS0 to the bias voltage terminal of the operational amplifier 16. The delay unit 12 delays the control signal PDB, outputting a rising edge delay signal DLY. For example, when the control signal PDB experiences a rising edge transition, the delay signal DLY may experience a rising edge transition some time after the rising edge transition of the control signal PDB; conversely, when the control signal PDB experiences a falling edge transition, the delay signal DLY may simultaneously experience a falling edge transition.

[0032] The enable terminal of charge pump 14 is connected to the output terminal of delayer 12. The output terminal of charge pump 14 is connected to the input terminal of feedback loop 15. The output terminal of feedback loop 15 is connected to the non-inverting input terminal of operational amplifier 16. The output terminal of bandgap reference voltage source 11 is connected to the inverting input terminal of operational amplifier 16. The output terminal of operational amplifier 16 is connected to the input terminal of charge pump 14. The bias voltage terminal of operational amplifier 16 is connected to the output terminal of bias voltage generator 13.

[0033] The charge pump 14 is used to operate when the delay signal DLY is high, thereby outputting a start-up voltage VPP based on the voltage at the output terminal of the operational amplifier 16. The voltage at the output terminal of the operational amplifier 16 is determined by the reference voltage signal VBG1 and the feedback voltage signal VFB. The feedback voltage signal VFB is obtained by the feedback loop 15 sampling the voltage signal output by the charge pump 14.

[0034] In some embodiments, the charge pump 14 is internally equipped with an inverter (the internal structure of the charge pump is not shown). The inverter inverts the output of the operational amplifier 16. When the feedback voltage signal VFB is greater than the reference voltage signal VBG1, the output of the operational amplifier 16 is positive, and the inverter inside the charge pump 14 converts it to a negative value, thereby stopping the clock pulse of the charge pump 14. When the feedback voltage signal VFB is less than the reference voltage signal VBG1, the output of the operational amplifier 16 is negative, and the inverter inside the charge pump 14 converts it to a positive value, thereby starting the clock pulse of the charge pump 14, thereby increasing the output voltage of the charge pump 14, thus maintaining the feedback voltage signal VFB equal to the reference voltage signal VBG1, that is, maintaining the stability of the output start-up voltage VPP of the charge pump 14.

[0035] Although not shown in the accompanying drawings, those skilled in the art will understand that in other embodiments, the inverter may also be provided independently of the charge pump 14, which is located between the output of the operational amplifier 16 and the input of the charge pump 14.

[0036] For example, a waveform diagram of the signal transmission in the exit sleep mode circuit is shown below. Figure 2 As shown, combined with Figure 1 The structure of the exit sleep mode circuit shown is as follows: The operation process of the exit sleep mode circuit is as follows: When an electronic device (e.g., memory) is in sleep mode, i.e. Figure 2 Before the first time period shown, an externally input high-level sleep enable signal PD is inverted by an inverter to obtain a low-level control signal PDB. After receiving the low-level control signal PDB from the inverter, the enable terminal of the bandgap reference voltage source 11 stops operating, and the reference voltage signal VBG1 remains low. After receiving the low-level control signal PDB from the inverter, the input terminal of the delay unit 12 outputs a low-level delay signal DLY to the enable terminal of the charge pump 14. At this time, the charge pump 14 also stops operating and outputs a low-level voltage signal, which is 0.

[0037] When an electronic device needs to exit sleep mode, that is Figure 2In the first time period shown, the sleep enable signal PD transitions from high to low, and after being inverted by the inverter, the control signal PDB transitions from low to high. Upon receiving the high-level control signal PDB, the enable terminal of the bandgap reference voltage source 11 begins to establish the reference voltage signal VBG1 (the reference voltage signal VBG1 gradually increases). When the reference voltage signal VBG1 begins to establish, the bias voltage generator 13 synchronously outputs the bias voltage VBIAS0 to the bias voltage terminal of the operational amplifier 16. A period of time after the control signal PDB transitions from low to high, the delay signal DLY output by the delay unit 12 also transitions from low to high.

[0038] When the delay signal DLY is high, that is Figure 2 In the second time period shown, the bandgap reference voltage source 11 establishes the reference voltage signal VBG1, and the bias voltage generator 13 also outputs a stable bias voltage VBIAS0 to the bias voltage terminal of the operational amplifier 16, enabling the operational amplifier 16 to operate normally. At this time, the enable terminal of the charge pump 14 receives a high-level delayed signal DLY, and the charge pump 14 starts to work, outputting a gradually increasing start-up voltage VPP. The feedback loop 15 takes the start-up voltage VPP output by the charge pump 14 as an input signal, processes it, and inputs a feedback voltage signal VFB to the non-inverting input terminal of the operational amplifier 16. By comparing the voltage magnitudes at the non-inverting and inverting input terminals of the operational amplifier 16, the charge pump 14 is able to output a stable start-up voltage VPP.

[0039] like Figure 2 As shown, the time required for the circuit to completely exit sleep mode and enter standby mode is limited by the duration of the bandgap reference voltage source 11 establishing the reference voltage signal VBG1 and the duration of the charge pump 14 establishing the startup voltage VPP, resulting in a relatively long time requirement. However, with the increasing demands for real-time response capabilities of devices, the time required for electronic devices to exit sleep mode and enter standby mode has become an obstacle restricting the performance of electronic devices.

[0040] To address the aforementioned problems, this application provides a startup voltage output circuit 2, which aims to shorten the time it takes for an electronic device to transition from sleep mode to standby mode. For example... Figure 3 As shown, the startup voltage output circuit 2 includes a control circuit 20 and a charge pump circuit 21, with the control circuit 20 connected to the charge pump circuit 21. The control circuit 20 includes a voltage divider 201, a bandgap reference voltage source 11, a pulse generator 202, a first voltage selector 203, a second voltage selector 204, and a bias voltage generator 13. The charge pump circuit 21 includes an operational amplifier 16, a charge pump 14, and a feedback loop 15.

[0041] The input terminal of voltage divider 201 is electrically connected to the external power supply VDD, the enable terminal of voltage divider 201 is electrically connected to the output terminal of pulse generator 202, and the output terminal of voltage divider 201 is electrically connected to the first input terminal of first voltage selector 203 and the first input terminal of second voltage selector 204, respectively.

[0042] The input terminal of the bandgap reference voltage source 11 is electrically connected to the control signal input terminal, the output terminal of the bandgap reference voltage source 11 is electrically connected to the second input terminal of the first voltage selector 203, the output terminal of the bandgap reference voltage source 11 is also electrically connected to the input terminal of the bias voltage generator 13, and the output terminal of the bias voltage generator 13 is electrically connected to the second input terminal of the second voltage selector 204.

[0043] The input terminal of pulse generator 202 is electrically connected to the control signal input terminal, and the output terminal of pulse generator 202 is electrically connected to the control terminals of the first voltage selector 203 and the second voltage selector 204, respectively. The inverting input terminal of operational amplifier 16 is electrically connected to the output terminal of the first voltage selector 203, the non-inverting input terminal of operational amplifier 16 is electrically connected to the output terminal of feedback loop 15, the output terminal of operational amplifier 16 is electrically connected to the input terminal of charge pump 14, and the bias voltage terminal of operational amplifier 16 is electrically connected to the output terminal of the second voltage selector 204. The output terminal of charge pump 14 is electrically connected to the input terminal of feedback loop 15, and charge pump 14 is electrically connected to the control signal input terminal.

[0044] It should be understood that, Figure 3 In the start-up voltage output circuit 2 shown, an inverter is also provided inside the charge pump 14. Of course, in other embodiments, the inverter can also be provided independently of the charge pump 14, which will not be described in detail here.

[0045] In some implementations, the control signal input terminal can receive a sleep enable signal PD via an inverter. The inverter is used to invert the input sleep enable signal PD and output a control signal PDB to the input terminal of the bandgap reference voltage source 11, the input terminal of the pulse generator 202, and the enable terminal of the charge pump 14.

[0046] like Figure 4 As shown, this application discloses a waveform diagram of signal transmission when a startup voltage output circuit enters standby mode from sleep mode. Based on this waveform diagram, combined with... Figure 3 The structure of the startup voltage output circuit 2 shown is illustrated, and its operation is as follows: When the startup voltage output circuit 2 is in sleep mode, that is Figure 4Before the first time period shown, an externally input high-level sleep enable signal PD is inverted by an inverter and then inputs a low-level control signal PDB to the enable terminals of the bandgap reference voltage source 11, pulse generator 202, and charge pump 14, respectively. After receiving the low-level control signal PDB, pulse generator 202 inputs a low-level pulse control signal PLS to the enable terminals of the first voltage selector 203, the second voltage selector 204, and the voltage divider 201. Voltage divider 201 inputs a low-level first reference voltage VREF0 to the first input terminal of the first voltage selector 203. Bandgap reference voltage source 11 inputs a low-level second reference voltage VBG2 to the input terminal of the first voltage selector 203. Bandgap reference voltage source 11 inputs a low-level second reference voltage VBG2 to the input terminal of the bias voltage generator 13. Charge pump 14 outputs a low-level voltage signal.

[0047] When the startup voltage output circuit 2 begins to establish the startup voltage, an externally input low-level sleep enable signal PD with a falling edge is inverted by an inverter and then inputs a high-level control signal PDB with a rising edge to the bandgap reference voltage source 11 and the pulse generator 202, respectively. Simultaneously, a high-level control signal PDB with a rising edge is also input to the enable terminal of the charge pump 14. After receiving the high-level control signal PDB with a rising edge, the bandgap reference voltage source 11 begins to establish the second reference voltage VBG2. After receiving the high-level control signal PDB with a rising edge, the pulse generator 202 inputs a pulse control signal PLS to the enable terminal of the voltage divider 201, the control terminal of the first voltage selector 203, and the control terminal of the second voltage selector 204.

[0048] Specifically, the pulse control signal PLS is divided into a high-level signal period and a low-level signal period. During the high-level pulse control signal PLS period, i.e. Figure 4 During the first time period shown, voltage divider 201 divides the voltage of external input VDD and outputs a first reference voltage VREF0 to first voltage selector 203. First voltage selector 203 selects the first reference voltage VREF0 at the first input terminal as the first selected output voltage VREF and inputs it to the inverting input terminal of operational amplifier 16.

[0049] The second voltage selector 204 also selects the first reference voltage VREF0 at the first input terminal as the second selected output voltage VBIAS2 and inputs it to the bias voltage terminal of the operational amplifier 16. After receiving the high-level control signal PDB at the rising edge, the enable terminal of the charge pump 14 starts to work and starts to output a voltage signal according to the output voltage of the operational amplifier 16, that is, it starts to establish an intermediate voltage. The voltage signal output by the charge pump 14 is processed by the feedback loop 15 and then inputs the feedback voltage signal VFB to the non-inverting input terminal of the operational amplifier 16.

[0050] During the low-level pulse control signal PLS period, i.e. Figure 4 During the second time period shown, voltage divider 201 stops outputting the first reference voltage VREF0, first voltage selector 203 selects the second reference voltage VBG2 output by bandgap reference voltage source 11 as the first selected output voltage VREF and inputs it to the inverting input terminal of operational amplifier 16, feedback loop 15 processes the voltage signal output by charge pump 14 and outputs feedback voltage signal VFB and inputs it to the non-inverting input terminal of operational amplifier 16, second voltage selector 204 selects the bias voltage VBIAS1 after the second reference voltage VBG2 is processed by bias voltage generator 13 as the second selected output voltage VBIAS2 and inputs it to the bias voltage terminal of operational amplifier 16.

[0051] The enable terminal of charge pump 14 continuously receives a high-level control signal PDB to maintain its operating mode, and outputs a voltage signal based on the voltage at the output terminal of operational amplifier 16, i.e., establishing a voltage from the intermediate voltage to the start-up voltage VPP. Operational amplifier 16 determines whether the voltage signal output by charge pump 14 reaches the start-up voltage VPP by comparing the voltage magnitudes at the non-inverting input terminal and the inverting input terminal.

[0052] Specifically, when the feedback voltage signal VFB is less than the second reference voltage VBG2, the voltage signal output by the charge pump 14 does not meet the high voltage requirement of the start-up voltage VPP, and the output voltage signal needs to be increased to continue to establish the start-up voltage VPP; when the feedback voltage signal VFB is greater than or equal to the second reference voltage VBG2, the voltage signal output by the charge pump 14 meets the high voltage requirement of the start-up voltage VPP, that is to say, the circuit has completed the establishment of the start-up voltage VPP.

[0053] In some examples, the duration of the high-level signal period of the pulse control signal PLS is related to the establishment time of the second reference voltage VBG2. When the second reference voltage VBG2 is in the establishment period, the pulse control signal PLS remains at a high level; when the second reference voltage VBG2 has completed establishment and reached a stable stage, the pulse control signal PLS enters a low-level signal period.

[0054] In some examples, the voltage VDD input to the voltage divider 201 is less than the circuit's startup voltage VPP to ensure that the first reference voltage VREF0 output by the voltage divider 201 is less than the second reference voltage VBG2 output by the bandgap reference voltage source 11. This, in turn, ensures that the voltage signal output by the charge pump 14 during the high-level pulse control signal period is less than the startup voltage VPP, thus ensuring that other loads in the electronic device are within a safe operating range.

[0055] like Figure 5As shown in the figure, this application discloses a schematic diagram of a first voltage divider. The voltage divider 201 includes a first transistor N1 and a resistor string; wherein the first transistor N1 is a negative channel metal-oxide-semiconductor field-effect transistor (NMOS), and the resistor string includes n resistors connected in series; that is, R1-R... n n is a positive integer greater than or equal to 2.

[0056] In this circuit, the gate of the first transistor N1 is connected to the output of the pulse generator 202 to receive the pulse control signal PLS. The drain of the first transistor N1 is connected to the first end of the resistor string, the second end of the resistor string is connected to the external power supply VDD, and the source of the first transistor N1 is grounded. The output of the voltage divider 201 is connected to the connection point of any two adjacent resistors in the resistor string.

[0057] For example, the output terminal of voltage divider 201 is connected to the junction of first resistor R1 and second resistor R2. First resistor R1 is the resistor connected to the external power supply VDD, and second resistor R2 is the resistor connected to first resistor R1. When the gate of first transistor N1 receives the high-level pulse control signal PLS output by pulse generator 202, first transistor N1 is turned on. When the voltage divider 201 circuit is turned on, the first reference voltage VREF0 output by the voltage divider 201 is (n-1) / n times the external power supply VDD, which is the external power supply VDD divided into n equal parts.

[0058] like Figure 6 As shown, this application discloses a schematic diagram of a second voltage divider. (Compared to...) Figure 5 The difference is that this voltage divider 201 replaces the resistor string with a transistor string; wherein, the transistor string includes n positive channel metal-oxide-semiconductor field-effect transistors (PMOS); that is, Q1-Q n In this configuration, for any PMOS in the transistor string, its gate is connected to its drain; for any two adjacent PMOS in the transistor string, the source of one PMOS is connected to the drain of the other adjacent PMOS. After n PMOS are connected in series, the remaining source terminal that is not connected to any other PMOS serves as the source terminal of the transistor string, and the remaining drain terminal that is not connected to any other PMOS serves as the drain terminal of the transistor string.

[0059] The gate of the first transistor N1 is connected to the output of the pulse generator 202 to receive the pulse control signal PLS. The drain of the first transistor N1 is connected to the drain of the transistor string, and the source of the transistor string is connected to the external power supply VDD. The source of the first transistor N1 is grounded. The output of the voltage divider 201 is connected to the connection point of any two adjacent PMOS transistors in the transistor string.

[0060] For example, the output of voltage divider 201 is connected to the junction of the drain of the first PMOS (i.e., Q1) and the source of the second PMOS (i.e., Q2). The first PMOS (i.e., Q1) is the PMOS connected to the external power supply VDD, and the second PMOS (i.e., Q2) is the PMOS connected adjacent to the first PMOS (i.e., Q1). The gate of the first transistor N1 receives the high-level pulse control signal PLS output by the pulse generator 202, the first transistor N1 is turned on, the voltage divider 201 circuit is turned on, and the first reference voltage VREF0 output by voltage divider 201 is the external input voltage VDD divided into n equal parts, that is, (n-1) / n times the external power supply VDD.

[0061] like Figure 7 As shown, this application discloses a schematic diagram of a third type of voltage divider. (Compared to...) Figure 5 The difference is that the voltage divider 201 replaces the first transistor N1 with the second transistor P1 and adds an inverter; the second transistor P1 is a PMOS transistor.

[0062] The inverter's input is connected to the output of the pulse generator 202, its output is connected to the gate of the second transistor P1, the source of the second transistor P1 is connected to the external power supply VDD, and the drain of the second transistor P1 is connected to the first end of the resistor string, which is grounded. The output of the voltage divider 201 is connected to the connection point of any two adjacent resistors in the resistor string.

[0063] For example, the output terminal of the voltage divider 201 is connected to the connection point of the first resistor R1 and the second resistor R2. The first resistor R1 is the resistor connected to the second transistor P1, and the second resistor R2 is the resistor connected to the first resistor R1.

[0064] The gate of the second transistor P1 receives a high-level pulse control signal PLS output by the pulse generator 202, which is inverted by the inverter. The second transistor P1 is turned on, the voltage divider 201 circuit is turned on, and the first reference voltage VREF0 output by the voltage divider 201 is (n-1) / n times the external power supply VDD, which is divided into n equal parts.

[0065] like Figure 8 As shown in the diagram, this application discloses a structural schematic of a fourth type of voltage divider. (Compared to...) Figure 7 The difference is that this voltage divider 201 replaces the resistor string with a transistor string; wherein the transistor string includes n PMOS transistors; that is, Q1-Q n In this configuration, for any PMOS in the transistor string, its gate is connected to its drain; for any two adjacent PMOS in the transistor string, the source of one PMOS is connected to the drain of the other adjacent PMOS. After n PMOS are connected in series, the remaining source terminal that is not connected to any other PMOS serves as the source terminal of the transistor string, and the remaining drain terminal that is not connected to any other PMOS serves as the drain terminal of the transistor string.

[0066] The input of the inverter is connected to the output of the pulse generator 202, and the output of the inverter is connected to the gate of the second transistor P1. The source of the second transistor P1 is connected to the external power supply VDD, and the drain of the second transistor P1 is connected to the source of the transistor string. The drain of the transistor string is grounded. The output of the voltage divider 201 is connected to the connection point of any two adjacent PMOS transistors in the transistor string.

[0067] For example, the output of voltage divider 201 is connected to the junction of the drain of the first PMOS (i.e., Q1) and the source of the second PMOS (i.e., Q2). The first PMOS (i.e., Q1) is the PMOS connected to the external power supply VDD, and the second PMOS (i.e., Q2) is the PMOS connected adjacent to the first PMOS (i.e., Q1). The gate of the second transistor P1 receives the high-level pulse control signal PLS output by the pulse generator 202, and the second transistor P1 is turned on, the voltage divider 201 circuit is turned on, and the first reference voltage VREF0 output by voltage divider 201 is (n-1) / n times the external power supply VDD, which is obtained by dividing the external input voltage VDD into n equal parts.

[0068] Figure 5 , Figure 6 , Figure 7 , Figure 8 The voltage divider circuits shown are just a few common ones. More types of voltage divider circuits can be obtained by combining PMOS and NMOS enable, resistor voltage divider and MOSFET voltage divider.

[0069] This application also provides a chip, such as... Figure 9As shown. The chip 3 includes a controller 30 and the aforementioned startup voltage output circuit 2, with the controller 30 connected to the startup voltage output circuit 2. Specifically, the controller 30 is connected to the control circuit 20 of the startup voltage output circuit 2, and inputs a sleep enable signal PD to the control circuit 20.

[0070] When the controller 30 receives a command from the electronic device to enter sleep mode, it inputs a high-level sleep enable signal PD to the startup voltage output circuit 2, controlling the startup voltage output circuit 2 to gradually decrease the output voltage signal to enter sleep mode. When the controller 30 receives a command from the electronic device to exit sleep mode and enter standby mode, it inputs a low-level sleep enable signal PD with a falling edge to the startup voltage output circuit 2, controlling the startup voltage output circuit 2 to gradually increase the output voltage signal to the startup voltage VPP to enter standby mode.

[0071] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A startup voltage output circuit, characterized in that, The startup voltage output circuit includes a control circuit and a charge pump circuit. The first output terminal of the control circuit is connected to the input terminal of the charge pump circuit. The control circuit is configured as follows: During the first time period, a first reference voltage is provided to the input terminal of the charge pump circuit to control the charge pump circuit to output an intermediate voltage; During the second time period, a second reference voltage is provided to the input terminal of the charge pump circuit to control the charge pump circuit to output a start-up voltage; The first time period is consecutive to the second time period, and the second time period is after the first time period; the first reference voltage is less than the second reference voltage, and the intermediate voltage is less than the start-up voltage.

2. The start-up voltage output circuit according to claim 1, characterized in that, The control circuit includes a voltage divider, a first voltage selector, a bandgap reference voltage source, and a pulse generator; The output terminal of the voltage divider is connected to the first input terminal of the first voltage selector, and is used to output the first reference voltage. The input terminal of the bandgap reference voltage source is used to receive control signals, and the output terminal of the bandgap reference voltage source is connected to the second input terminal of the first voltage selector. The bandgap reference voltage source generates the second reference voltage according to the control signals. The input terminal of the pulse generator is used to receive the control signal, and the output terminal of the pulse generator is connected to the control terminal of the first voltage selector. The pulse generator generates a pulse control signal according to the control signal. The output terminal of the first voltage selector serves as the first output terminal of the control circuit. The first voltage selector is configured to provide either the first reference voltage or the second reference voltage to the input terminal of the charge pump circuit according to the pulse control signal.

3. The start-up voltage output circuit according to claim 2, characterized in that, The pulse control signal includes a high-level signal and a low-level signal, and the first voltage selector is configured as follows: In response to the pulse control signal being a high-level signal, the first reference voltage is provided to the input terminal of the charge pump circuit; In response to the pulse control signal being a low-level signal, the second reference voltage is provided to the input terminal of the charge pump circuit.

4. The start-up voltage output circuit according to claim 3, characterized in that, The duration of the high-level signal in the pulse control signal is related to the establishment time of the second reference voltage.

5. The start-up voltage output circuit according to claim 4, characterized in that, The voltage divider includes an enable terminal, which is connected to the output terminal of the pulse generator.

6. The start-up voltage output circuit according to claim 5, characterized in that, The charge pump circuit includes an operational amplifier, a charge pump, and a feedback loop; The non-inverting input of the operational amplifier is connected to the output of the feedback loop, the inverting input of the operational amplifier serves as the input of the charge pump circuit, and the output of the operational amplifier is connected to the input of the charge pump. The output terminal of the charge pump is connected to the input terminal of the feedback loop.

7. The start-up voltage output circuit according to claim 6, characterized in that, The charge pump also includes an enable terminal, which is used to receive the control signal.

8. The start-up voltage output circuit according to claim 7, characterized in that, The second output terminal of the control circuit is connected to the bias voltage terminal of the operational amplifier. The control circuit also includes a bias voltage generator and a second voltage selector. The first input terminal of the second voltage selector is connected to the output terminal of the voltage divider; The input terminal of the bias voltage generator is connected to the output terminal of the bandgap reference voltage source, and the output terminal of the bias voltage generator is connected to the second input terminal of the second voltage selector. The bias voltage generator is configured to output a bias voltage according to the second reference voltage. The control terminal of the second voltage selector is connected to the output terminal of the pulse generator, and the output terminal of the second voltage selector serves as the second output terminal of the control circuit.

9. The start-up voltage output circuit according to claim 8, characterized in that, The second voltage selector is configured as follows: In response to the pulse control signal being a high-level signal, the first reference voltage is provided to the bias voltage terminal of the operational amplifier; In response to the pulse control signal being a low-level signal, the bias voltage is provided to the bias voltage terminal of the operational amplifier.

10. A chip, characterized in that, The chip includes a controller and a startup voltage output circuit as described in any one of claims 1-9, the controller being connected to the startup voltage output circuit and configured to output a control signal to the startup voltage output circuit.

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