A power semiconductor device multi-chip parallel electric signal equalization control circuit

Abstract

The application discloses a kind of power semiconductor devices multicore parallel electric signal equalization control circuit.Application is used to multiple MOS parallel circuit, including first control circuit and second control circuit, at least one MOS pipe branch connection has first control circuit, at least one MOS pipe branch connection has second control circuit.First control circuit includes first current sampling circuit, switching switch, first constant current ring and constant voltage ring with current limiting.First current sampling circuit collects the current of the branch where the connected MOS pipe is, and switching switch switches the first current output signal of first current sampling circuit to first constant current ring or constant voltage ring with current limiting, to carry out constant current ring control or constant voltage ring control with current limiting.Second control circuit includes second current sampling circuit and second constant current ring, and second current sampling circuit collects the current of the branch where the connected MOS pipe is, to carry out constant current ring control.The technical scheme of the application has high reliability.

Description

Technical Field

[0001] This invention relates to the field of power electronic control technology, and in particular to a multi-chip parallel electrical signal equalization control circuit for power semiconductor devices. Background Technology

[0002] In the field of power electronics, the use of a single closed-loop control for multiple parallel MOSFETs in switching power supply applications cannot meet the needs of complex application scenarios.

[0003] Currently, in multi-loop control of multiple parallel MOSFETs, two common control methods are used: In single-loop mode, independent voltage and current loops are established, with each loop controlling one MOSFET independently, and each loop's control does not interfere with the others, ensuring excellent constant voltage and constant current accuracy. In dual-loop mode, the voltage and current loops compete for control. Under normal circumstances, only the voltage or current loop controls the power supply. When the sampling signal triggers a certain condition, the normally operating loop exits, and the other loop takes over until the sampling signal returns to its initial state, at which point the control loop returns to its initial operating state. Alternatively, a dual-loop mode combining an outer voltage loop and an inner current loop can be used.

[0004] However, the reliability of the control circuit described above is poor. Summary of the Invention

[0005] This invention provides a parallel electrical signal equalization control circuit for multiple power semiconductor devices to achieve multi-loop control of power semiconductor device chips and improve the reliability of the control circuit.

[0006] According to one aspect of the present invention, a power semiconductor device multi-chip parallel electrical signal equalization control circuit is provided. The power semiconductor device multi-chip parallel electrical signal equalization control circuit of the present invention is applied to a multi-MOS parallel circuit. The multi-MOS parallel circuit includes a plurality of parallel MOS transistors. The power semiconductor device multi-chip parallel electrical signal equalization control circuit includes a first control circuit and a second control circuit. The branch where at least one MOS transistor is located is connected to the first control circuit, and the branch where at least one MOS transistor is located is connected to the second control circuit. The first control circuit includes a first current sampling circuit, a switching switch, a first constant current loop, and a constant voltage loop with current limiting. The first current sampling circuit is used to collect the current of the branch where the connected MOS transistor is located. The switching switch is used to switch the first current output signal of the first current sampling circuit to the first constant current loop or the constant voltage loop with current limiting, so as to perform constant current loop control or constant voltage loop control with current limiting. The second control circuit includes a second current sampling circuit and a second constant current loop. The second current sampling circuit is used to collect the current of the branch where the connected MOS transistor is located in order to perform constant current loop control.

[0007] Optionally, the constant voltage ring with current limiting includes: a voltage sampling circuit, a constant voltage ring, a current limiting ring, and a competition switching circuit; The voltage sampling circuit is used to acquire the output voltage of the branch where the connected MOS transistor is located; The first input terminal of the constant voltage ring is connected to the voltage sampling circuit, and the second input terminal of the constant voltage ring is input to the preset voltage threshold. The constant voltage ring is used to output a first driving voltage to the first input terminal of the contention switching circuit according to the degree of difference between the output voltage and the preset voltage threshold. The input terminal of the current limiting ring is connected to a switching switch, receives a first current output signal, and receives a first preset current threshold. The current limiting ring is used to output a second driving voltage to the second input terminal of the contention switching circuit according to the relationship between the first current output signal and the first preset current threshold. The output of the competition switching circuit serves as the output of a constant voltage ring with current limiting, used to compare the magnitudes of the first driving voltage and the second driving voltage, and outputs the smaller of the first driving voltage and the second driving voltage.

[0008] Optionally, the contention switching circuit includes: a first diode and a second diode; The first end of the first diode serves as the first input terminal of the contention switching circuit, the first end of the second diode serves as the second input terminal of the contention switching circuit, and the node where the second ends of the first diode and the second ends of the second diode are connected serves as the output terminal of the contention switching circuit. The first diode is turned on to connect the first input terminal of the contention switching circuit to the output terminal of the contention switching circuit; or, the second diode is turned on to connect the second input terminal of the contention switching circuit to the output terminal of the contention switching circuit.

[0009] Optionally, the constant voltage ring includes a first operational circuit, a first resistor, a second resistor, a first capacitor, and a second capacitor; The first input terminal of the first operational circuit is connected to the output voltage, and the second input terminal of the first operational circuit is connected to a preset voltage threshold. The first resistor and the first capacitor are connected in series between the second input terminal and the output terminal of the first arithmetic circuit; the second resistor and the second capacitor are connected in series between the second input terminal and the output terminal of the first arithmetic circuit. The impedance parameters of the first resistor and the first capacitor connected in series and the impedance parameters of the second resistor and the second capacitor connected in series are different, and are used to adjust the integral parameters of the first operational circuit.

[0010] Optionally, the current limiting loop includes a second operational circuit and a third capacitor; The input terminal of the second operational circuit is connected to the first current output signal and the first preset current threshold. The third capacitor is connected between the input terminal and the output terminal of the second operational circuit and is used to adjust the integral parameters of the current limiting loop.

[0011] Optionally, the first current sampling circuit includes at least two sampling levels, each with a different sampling precision.

[0012] Optionally, at least two sampling ranges include at least two sampling resistors with different resistance values ​​and at least two analog switches; Each analog switch is connected to a corresponding sampling resistor. When the analog switch is closed, the sampling resistor connected to the analog switch is used to collect the current of the branch where the connected MOS transistor is located.

[0013] Optionally, the first constant current loop includes a third operational circuit; The first input terminal of the third operational circuit is connected to a switching switch, and the second input terminal of the third operational circuit is connected to a second preset current threshold. The third operational circuit is used to output a third driving voltage based on the difference between the first current output signal and the second preset current threshold.

[0014] Optionally, the second constant current loop includes a fourth operational circuit; The first input terminal of the fourth operational circuit is connected to the second current sampling circuit, and the second input terminal of the fourth operational circuit is connected to the reference current. The fourth operational circuit is used to output a fourth driving voltage based on the degree of difference between the second current output signal of the second current sampling circuit and the reference current.

[0015] Optionally, the power semiconductor device multi-chip parallel electrical signal equalization control circuit includes a first switching switch and a second switching switch; The first input terminal of the first switching switch is connected to the output terminal of the first constant current ring, and the second input terminal of the first switching switch is connected to the output terminal of the constant voltage ring with current limiting. The output terminal of the first switching switch serves as the output terminal of the first control circuit. The first switching switch is used to switch the output signal of the first constant current ring or the output signal of the constant voltage ring with current limiting to the output terminal of the first control circuit. The first input terminal of the second switch is connected to the third preset current threshold, and the second input terminal of the second switch is connected to the output terminal of the first current sampling circuit. The second switch is used to switch the third preset current threshold or the first current output signal of the first current sampling circuit to the second constant current loop.

[0016] The technical solution of this invention involves connecting a first control circuit to a branch containing at least one MOSFET, and a second control circuit to the same branch. A first current sampling circuit in the first control circuit collects the current in the branch containing the connected MOSFET. A switch switches the first current output signal of the first current sampling circuit to either a first constant current loop or a constant voltage loop with current limiting, for constant current loop control or constant voltage loop control with current limiting. The constant voltage loop with current limiting can determine whether the current of the MOSFET with a pre-held constant voltage exceeds the maximum current that the downstream load can withstand, based on the first current output signal of the first current sampling circuit. If it does, the output current of the MOSFET is controlled to remain at the maximum current that the downstream load can withstand, providing current limiting protection. This avoids the risk of overcurrent in constant voltage mode and improves the reliability of the parallel signal equalization control circuit for multiple power semiconductor devices. The second current sampling circuit in the second control circuit collects the current in the branch containing the connected MOSFET for constant current loop control. In summary, this invention can achieve multi-loop control of multiple power semiconductor devices, and the constant voltage loop with current limiting can provide timely current limiting protection.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a multi-chip parallel electrical signal equalization control circuit for power semiconductor devices provided by the prior art; Figure 2 This is a schematic diagram of the structure of a multi-chip parallel electrical signal equalization control circuit for power semiconductor devices provided in an embodiment of the present invention; Figure 3 A circuit structure diagram of a constant voltage ring with current limiting provided for an embodiment of the present invention; Figure 4 A circuit structure diagram of a first control circuit provided in an embodiment of the present invention; Figure 5 A circuit structure diagram of a second control circuit provided in an embodiment of the present invention; Figure 6A simulation analysis diagram of a multi-chip parallel electrical signal equalization control circuit for power semiconductor devices provided in an embodiment of the present invention; Figure 7 A simulation analysis diagram of another power semiconductor device multi-chip parallel electrical signal equalization control circuit provided in an embodiment of the present invention; Figure 8 This is a simulation analysis diagram of another power semiconductor device multi-chip parallel electrical signal equalization control circuit provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a schematic diagram of a multi-chip parallel electrical signal equalization control circuit for power semiconductor devices, provided by existing technology. (Example:) Figure 1 As shown, existing related technologies control each MOSFET through a single current loop, which can also be replaced by a single voltage loop. However, the control effect and reliability of existing related technologies are poor.

[0023] In response to the shortcomings of existing related technologies, Figure 2 This is a schematic diagram of a multi-chip parallel electrical signal equalization control circuit for power semiconductor devices, provided in an embodiment of the present invention. This embodiment is applicable to scenarios where parallel electrical signals of multiple power semiconductor devices are controlled to achieve equalization. For example, this can be achieved by controlling the conduction state of a MOSFET.

[0024] like Figure 2As shown, this embodiment of the invention provides a power semiconductor device multi-chip parallel electrical signal equalization control circuit. This circuit is applied to a multi-MOS parallel circuit, which includes multiple parallel-connected MOS transistors. The power semiconductor device multi-chip parallel electrical signal equalization control circuit includes a first control circuit 1 and a second control circuit 2. At least one branch containing a MOS transistor is connected to the first control circuit 1, and at least one branch containing a MOS transistor is connected to the second control circuit 2. The first control circuit 1 includes a first current sampling circuit 11, a switching switch 12, a first constant current loop 13, and a constant voltage loop 14 with current limiting. The first current sampling circuit 11 is used to collect the current of the branch containing the connected MOS transistor. The switching switch 12 is used to switch the first current output signal of the first current sampling circuit 11 to the first constant current loop 13 or the constant voltage loop 14 with current limiting, for constant current loop control or constant voltage loop control with current limiting. The second control circuit 2 includes a second current sampling circuit 21 and a second constant current loop 22. The second current sampling circuit 21 is used to collect the current of the branch where the connected MOS transistor is located in order to perform constant current loop control.

[0025] In this embodiment of the invention, multiple parallel-connected MOS transistors can be generated by... Figure 2 In the MOSFET designation, MOSFET-i represents the transistor, where i is a positive integer greater than or equal to 1. Each MOSFET can be connected to either the first control circuit 1 or the second control circuit 2, and can be controlled by either the first control circuit 1 or the second control circuit 2. For example, MOSFET-1 can be the master MOSFET, and the remaining MOSFETs can be slave MOSFETs. MOSFET-1 is connected to the first control circuit 1, and MOSFET-2 is connected to the second control circuit 2.

[0026] The input terminal of the first current sampling circuit 11 is connected to the source or drain of the MOSFET, used to sample the current in the branch where the corresponding MOSFET is located, and outputs a first current output signal to the input terminal of the switch 12. The input terminal of the second current sampling circuit 21 is connected to the source or drain of the MOSFET, used to sample the current in the branch where the corresponding MOSFET is located, and outputs a second current output signal to the sampling current input terminal of the second constant current loop 22. For example, the current output signal of the first current sampling circuit 11 can be a first current output signal, and the current output signal of the second current sampling circuit 21 can be a second current output signal.

[0027] The first output terminal of the switch 12 is connected to the sampling current input terminal of the first constant current loop 13, and the second output terminal of the switch 12 is connected to the sampling current input terminal of the constant voltage loop 14 with current limiting. The switch 12 can select between the input terminal and the first output terminal, or between the input terminal and the second output terminal, thereby transmitting the first current output signal of the first current sampling circuit 11 to the sampling current input terminal of the first constant current loop 13, or to the sampling current input terminal of the constant voltage loop 14 with current limiting. For example, the selection status of the switch 12 can be controlled by a host computer or controller.

[0028] The output terminal of the first constant current loop 13 is connected to the control terminal of the corresponding MOSFET. The control terminal of the MOSFET can be the gate of the MOSFET. The first constant current loop 13 can control the conduction level of the corresponding MOSFET according to the first current output signal, thereby keeping the output current of the MOSFET constant. The output terminal of the current-limiting constant voltage loop 14 is connected to the control terminal of the corresponding MOSFET. The current-limiting constant voltage loop 14 can control the conduction level of the corresponding MOSFET according to the output voltage of the MOSFET, thereby keeping the output voltage of the MOSFET constant. The current-limiting constant voltage loop 14 can also determine whether the current of the MOSFET with the pre-held constant voltage exceeds the maximum current that the downstream load can withstand, based on the first current output signal. If it exceeds the maximum current, it controls the output current of the MOSFET to be kept at the maximum current that the downstream load can withstand, thus performing current limiting protection. The downstream load can be a load connected to the MOSFET.

[0029] The output terminal of the second constant current loop 22 is connected to the control terminal of the corresponding MOSFET. The control terminal of the MOSFET can be the gate of the MOSFET. The second constant current loop 22 can control the conduction level of the corresponding MOSFET according to the second current output signal, thereby keeping the output current of the MOSFET constant.

[0030] Specifically, the operating mode of the first control circuit 1 can be selected in the host computer or controller. For example, selecting the constant current mode switches the first current output signal to the first constant current loop 13 via the switch 12, and the first constant current loop 13 operates. Selecting the constant voltage mode switches the first current output signal to the constant voltage loop 14 with current limiting via the switch 12, and the constant voltage loop 14 with current limiting operates. The second control circuit 2 can operate simultaneously with the first control circuit 1.

[0031] According to the technical solution of the present invention, a first control circuit is connected to the branch containing at least one MOSFET, and a second control circuit is connected to the branch containing at least one MOSFET. A first current sampling circuit in the first control circuit collects the current of the branch containing the connected MOSFET. A switch switches the first current output signal of the first current sampling circuit to a first constant current loop or a constant voltage loop with current limiting, to perform constant current loop control or constant voltage loop control with current limiting. The constant voltage loop with current limiting can determine whether the current of the MOSFET with a pre-held constant voltage exceeds the maximum current that the downstream load can withstand based on the first current output signal of the first current sampling circuit. If it exceeds, the output current of the MOSFET is controlled to remain at the maximum current that the downstream load can withstand, thus performing current limiting protection. This avoids the risk of overcurrent in constant voltage mode and improves the reliability of the parallel power semiconductor device signal equalization control circuit. The second current sampling circuit in the second control circuit collects the current of the branch containing the connected MOSFET for constant current loop control. In summary, the embodiments of the present invention can realize multi-loop control of multiple power semiconductor devices, and the constant voltage loop with current limiting can provide timely current limiting protection.

[0032] Figure 3 This is a circuit diagram of a constant voltage ring with current limiting provided for an embodiment of the present invention. (Combined with...) Figure 2 and Figure 3 In some embodiments, the constant voltage ring 14 with current limiting includes: a voltage sampling circuit 141, a constant voltage ring 142, a current limiting ring 143, and a contention switching circuit 144. The voltage sampling circuit 141 is used to acquire the output voltage of the branch containing the connected MOSFET. The first input terminal of the constant voltage ring 142 is connected to the voltage sampling circuit 141, and the second input terminal of the constant voltage ring 142 receives a preset voltage threshold Vref. The constant voltage ring 142 outputs a first driving voltage Vgs1 to the first input terminal of the contention switching circuit 144 based on the difference between the output voltage Vout and the preset voltage threshold Vref. The input terminal of the current limiting ring 143 is connected to a switching switch 12, receives a first current output signal Is, and receives a first preset current threshold Ir1. The current limiting ring 143 outputs a second driving voltage Vgs2 to the second input terminal of the contention switching circuit 144 based on the relationship between the first current output signal Is and the first preset current threshold Ir1. The output of the competition switching circuit 144 serves as the output of the constant voltage ring 14 with current limiting. It is used to compare the magnitudes of the first driving voltage Vgs1 and the second driving voltage Vgs2, and outputs the smaller of the first driving voltage Vgs1 and the second driving voltage Vgs2.

[0033] The first and second input terminals of the voltage sampling circuit 141 are respectively connected to the output terminals of the MOSFET connected to the first control circuit 1. The voltage sampling circuit 141 can differentially sample the output voltage of the MOSFET, with the differential input signals being VD and VS, and can process the differential input signals to output the output voltage Vout to the constant voltage ring 142 at the output terminal.

[0034] The preset voltage threshold Vref can be a reference voltage pre-set for the constant voltage control of the MOSFET, serving as a reference for the closed-loop control of the MOSFET by the constant voltage loop 142. The difference between the output voltage Vout and the preset voltage threshold Vref can be the deviation between the actual output voltage of the branch containing the MOSFET and the preset voltage threshold Vref, for example, it can be the absolute value of the difference between the output voltage Vout and the preset voltage threshold Vref. The constant voltage loop 142 can output a first driving voltage Vgs1 according to the degree of difference. The first driving voltage Vgs1 can be varied, thus adjusting the conduction degree of the MOSFET, thereby controlling the actual output voltage of the branch containing the MOSFET to remain constant.

[0035] The first preset current threshold Ir1 can be set with reference to the maximum current value that the downstream load can withstand in the application scenario of the MOSFET. The first preset current threshold Ir1 can be a positive or negative value. The current limiting loop 143 can compare the absolute value of the first current output signal Is with the absolute value of the first preset current threshold Ir1 and output the second driving voltage Vgs2. The second driving voltage Vgs2 can have two forms: one is a high-level signal, the voltage value of which is higher than the upper limit of the first driving voltage Vgs1; the other is a low-level signal, the voltage value of which can be set with reference to the driving voltage of the MOSFET when the current in the branch where the MOSFET is located is the first preset current threshold Ir1. The voltage value of the low-level signal is lower than the upper limit of the first driving voltage Vgs1. For example, when the first current output signal Is is less than or equal to the absolute value of the first preset current threshold Ir1, a high-level signal is output, indicating that there is no need to limit the current of the constant voltage loop 142. When the first current output signal Is is higher than the absolute value of the first preset current threshold Ir1, the output second driving voltage Vgs2 is a low-level signal, indicating that the current limiting ring 143 limits the current of the constant voltage ring 142.

[0036] The competition switching circuit 144 can determine whether the MOSFET is controlled by the constant voltage ring 142 or the current limiting ring 143 based on the relationship between the first driving voltage Vgs1 output by the constant voltage ring 142 and the second driving voltage Vgs2 output by the current limiting ring 143. For example, when the second driving voltage Vgs2 is greater than or equal to the first driving voltage Vgs1, the competition switching circuit 144 connects the output terminal of the constant voltage ring 142 with the output terminal of the current-limited constant voltage ring 143, and the constant voltage ring 142 operates. When the second driving voltage Vgs2 is less than the first driving voltage Vgs1, the competition switching circuit 144 connects the output terminal of the current limiting ring 143 with the output terminal of the current-limited constant voltage ring 143, and the current limiting ring 143 operates.

[0037] Continue to refer to Figure 3 In some embodiments, the contention switching circuit 144 includes a first diode D1 and a second diode D2. The first terminal of the first diode D1 serves as the first input terminal of the contention switching circuit 144, the first terminal of the second diode D2 serves as the second input terminal of the contention switching circuit 144, and the node connecting the second terminals of the first diode D1 and the second terminals of the second diode D2 serves as the output terminal of the contention switching circuit 144. When the first diode D1 is turned on, it connects the first input terminal of the contention switching circuit 144 to its output terminal. Alternatively, when the second diode D2 is turned on, it connects the second input terminal of the contention switching circuit 144 to its output terminal.

[0038] In this diode, the first terminal of the first diode D1 is the cathode, and the second terminal of the first diode D1 is the anode. Similarly, the first terminal of the second diode D2 is the cathode, and the second terminal of the second diode D2 is the anode.

[0039] Specifically, the first terminal of the first diode D1 is connected to the first driving voltage Vgs1, and the first terminal of the second diode D2 is connected to the second driving voltage Vgs2. When the second driving voltage Vgs2 is greater than or equal to the first driving voltage Vgs1, the first diode D1 conducts, and the output terminal of the constant voltage ring 142 is connected to the output terminal of the current-limiting constant voltage ring 14. When the second driving voltage Vgs2 is less than the first driving voltage Vgs1, the second diode D2 conducts, and the output terminal of the current-limiting ring 143 is connected to the output terminal of the current-limiting constant voltage ring 14. Thus, when the constant voltage ring 142 controls the MOSFET, if the current in the branch where the MOSFET is located exceeds the first preset current threshold Ir1, the current-limiting ring 143 is automatically triggered to perform current-limiting protection, preventing excessive current under constant voltage control from damaging the downstream load.

[0040] Continue to refer to Figure 3In some embodiments, the constant voltage ring 142 includes a first operational circuit U1, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The first input terminal of the first operational circuit U1 is connected to the output voltage Vout, and the second input terminal is connected to a preset voltage threshold Vref. The first resistor R1 and the first capacitor C1 are connected in series between the second input terminal and the output terminal of the first operational circuit U1. The second resistor R2 and the second capacitor C2 are connected in series between the second input terminal and the output terminal of the first operational circuit U1. The impedance parameter of the series connection of the first resistor R1 and the first capacitor C1 is different from the impedance parameter of the series connection of the second resistor R2 and the second capacitor C2, and is used to adjust the integral parameter of the first operational circuit U1.

[0041] The impedance parameter can be the product of the resistance of the first resistor R1 and the capacitance of the first capacitor C1, or the product of the resistance of the second resistor R2 and the capacitance of the second capacitor C2. The integral parameter can be the integration time parameter, specifically the reciprocal of the impedance parameter. The resistance of the first resistor R1 can be greater than the resistance of the second resistor R2, and the capacitance of the first capacitor C1 can be greater than the capacitance of the second capacitor C2. Under low current conditions, the second resistor R2 and the second capacitor C2 can be connected in series with the first operational circuit U1, resulting in a larger integral parameter of the first operational circuit U1 and a faster response of the constant voltage ring 142. Under high current conditions, the first resistor R1 and the first capacitor C1 can be connected in series with the first operational circuit U1, resulting in a smaller integral parameter of the first operational circuit U1 and a slower response of the constant voltage ring 142. This avoids the problem of high current overshoot caused by switching.

[0042] In some embodiments, a selector switch can be connected between the first resistor R1 and the output terminal of the first operational circuit U1, and a selector switch can be connected between the second resistor R2 and the output terminal of the first operational circuit U1. By controlling the closed or open state of the selector switch, the first resistor R1 and the first capacitor C1 can be connected to the first operational circuit U1, and / or the second resistor R2 and the second capacitor C2 can be connected to the first operational circuit U1. Furthermore, the integral parameters of the first operational circuit U1 can be adjusted according to actual conditions to adapt to different operating conditions.

[0043] Continue to refer to Figure 3 In some embodiments, the current limiting ring 143 includes a second operational circuit U2 and a third capacitor C3. The input terminal of the second operational circuit U2 is connected to a first current output signal Is and a first preset current threshold Ir1. The third capacitor C3 is connected between the input terminal and the output terminal of the second operational circuit U2 and is used to adjust the integral parameters of the current limiting ring 143.

[0044] Among them, the third capacitor C3 can be selected with a smaller capacitance value, and the second operational circuit U2 has a larger integral parameter, which makes the current limiting ring 143 respond faster, and thus the current limiting protection action of the current limiting ring 143 is faster.

[0045] Figure 4 This is a circuit structure diagram of a first control circuit provided in an embodiment of the present invention. (See diagram below.) Figure 4 As shown, in some embodiments, the first current sampling circuit 11 includes at least two sampling levels, each of which includes a different sampling precision.

[0046] By using different sampling levels, the sampling accuracy under various current conditions can be met, thereby improving the sampling accuracy of the first current sampling circuit 11.

[0047] In some embodiments, at least two sampling ranges include at least two sampling resistors with different resistance values ​​and at least two analog switches. Each analog switch is connected to a corresponding sampling resistor. When the analog switch is closed, the sampling resistor connected to the analog switch is used to acquire the current of the branch where the connected MOSFET is located.

[0048] Specifically, taking the first current sampling circuit 11, which includes four sampling levels, as an example, the first sampling level may include a first sampling resistor RS1 and a first analog switch 111. When the first analog switch 111 is closed, the first current sampling circuit 11 samples through the first sampling resistor RS1. The second sampling level may include a second sampling resistor RS2 and a second analog switch 112. When the second analog switch 112 is closed, the first current sampling circuit 11 samples through the second sampling resistor RS2. The third sampling level may include a third sampling resistor RS3 and a third analog switch 113. The fourth sampling level may include a fourth sampling resistor RS4 and a fourth analog switch 114. The working principle is the same as that of the first or second sampling level, and will not be described again here.

[0049] The operational circuit U4 in the first current sampling circuit 11 can perform differential sampling on the signal across the sampling resistor and output the first current output signal Is.

[0050] By using sampling resistors with different resistance values ​​and analog switches, a small current signal can be converted into a voltage of sufficient amplitude. In this way, at each range, the analog-to-digital converter (ADC) at the input of the operational circuit U4 in the first current sampling circuit 11 can obtain a high-quality input signal close to full scale, thus ensuring accuracy across the entire range.

[0051] Continue to refer to Figure 4In some embodiments, the first constant current loop 13 includes a third operational circuit U3. The first input terminal of the third operational circuit U3 is connected to a switching switch 12, and the second input terminal of the third operational circuit U3 is connected to a second preset current threshold Iref. The third operational circuit U3 is used to output a third driving voltage Vgs3 based on the degree of difference between the first current output signal Is and the second preset current threshold Iref.

[0052] The second preset current threshold Iref can be a current value preset for constant voltage control of the MOSFET, serving as a reference for the closed-loop control of the MOSFET in the first constant current loop 13. The difference between the first current output signal Is and the second preset current threshold Iref can be the deviation between the actual output current of the branch containing the MOSFET and the second preset current threshold Iref, for example, it can be the absolute value of the difference between the first current output signal Is and the second preset current threshold Iref. The third operational circuit U3 can output a third driving voltage Vgs3 according to the degree of difference. The third driving voltage Vgs3 can vary, thus adjusting the conduction degree of the MOSFET, thereby controlling the actual output current of the branch containing the MOSFET to remain constant.

[0053] Based on any of the above embodiments, Figure 5 This is a circuit structure diagram of a second control circuit provided in an embodiment of the present invention. (In conjunction with...) Figure 4 and Figure 5 In some embodiments, the power semiconductor device multi-chip parallel electrical signal equalization control circuit includes a first switching switch 15 and a second switching switch 23. The first input terminal of the first switching switch 15 is connected to the output terminal of the first constant current loop 13, and the second input terminal of the first switching switch 15 is connected to the output terminal of the current-limited constant voltage loop 14. The output terminal of the first switching switch 15 serves as the output terminal of the first control circuit 1. The first switching switch 15 is used to switch the output signal of the first constant current loop 13 or the output signal of the current-limited constant voltage loop 14 to the output terminal of the first control circuit 1. The first input terminal of the second switching switch 23 is connected to a third preset current threshold Ir2, and the second input terminal of the second switching switch 23 is connected to the output terminal of the first current sampling circuit 11. The second switching switch 23 is used to switch the third preset current threshold Ir2 or the first current output signal Is of the first current sampling circuit 11 to the second constant current loop 22.

[0054] The first switching switch 15 can be controlled by a host computer or a controller. For example, when the constant voltage mode is selected on the host computer or controller, the output terminal of the constant voltage ring 14 with current limiting is connected to the output terminal of the first switching switch 15; when the constant current mode is selected on the host computer or controller, the output terminal of the first constant current ring 13 is connected to the output terminal of the first switching switch 15.

[0055] The third preset current threshold Ir2 can be a current value preset for the constant current control of the MOSFET, serving as a reference for the closed-loop control of the MOSFET in the second constant current loop 22.

[0056] The switching state of the second switch 23 is synchronized with the operating mode of the first control circuit 1. For example, when the host computer or controller selects the constant voltage mode, the first control circuit 1 operates in constant voltage mode, the second terminal of the second switch 23 is connected to its output terminal, and the first current output signal Is is input to the second constant current loop 22. When the host computer or controller selects the constant current mode, the first control circuit 1 operates in constant current mode, the first terminal of the second switch 23 is connected to its output terminal, and the third preset current threshold Ir2 is input to the second constant current loop 22. The third preset current threshold Ir2 is a manually set value, and the first current output signal Is is the feedback value of the first current sampling circuit 11.

[0057] By setting the second switching switch 23, the second control circuit 2 can be automatically switched according to the mode change of the first control circuit 1.

[0058] Continue to refer to Figure 5 In some embodiments, the second constant current loop 22 includes a fourth operational circuit U5. The first input terminal of the fourth operational circuit U5 is connected to the second current sampling circuit 21, and the second input terminal of the fourth operational circuit U5 is connected to a reference current. The fourth operational circuit U5 is used to output a fourth driving voltage Vgs4 based on the degree of difference between the second current output signal Is2 of the second current sampling circuit 21 and the reference current.

[0059] The reference current can be either a third preset current threshold Ir2 or the first current output signal Is of the first current sampling circuit 11. By setting the second switching switch 23, the reference current input to the second constant current loop 22 in the second control circuit 2 can be automatically switched according to the mode change of the first control circuit 1.

[0060] The degree of difference between the second current output signal Is2 and the reference current can be the deviation between the actual output current of the branch containing the MOSFET and the reference current. For example, it can be the absolute value of the difference between the second current output signal Is2 and the reference current. The fourth operational circuit U5 can output a fourth driving voltage Vgs4 according to the degree of difference. The fourth driving voltage Vgs4 can be varied, thus adjusting the conduction degree of the MOSFET.

[0061] In some embodiments, the second current sampling circuit 21 may include a fifth sampling resistor RS5, which is connected in series with a MOS transistor connected to the second control circuit 2. The arithmetic circuit U6 in the second current sampling circuit 21 can perform differential sampling on the signal across the fifth sampling resistor RS5 and output a second current output signal Is2.

[0062] Taking the first control circuit controlling MOSFET-1 and the second control circuit controlling MOSFET-2 as an example. Figure 6 This is a simulation analysis diagram of a multi-chip parallel electrical signal equalization control circuit for power semiconductor devices provided in an embodiment of the present invention. Combined with... Figure 4 , Figure 5 and Figure 6 In the power semiconductor device multi-chip parallel electrical signal equalization control circuit, the first control circuit is operated by the first constant current loop 13, and the second control circuit is operated by the second constant current loop 22. Figure 6 The simulation curves, from top to bottom, represent: the total output voltage Vo of the MOSFET, the drive voltage V2 of MOSFET-2, the drive voltage V1 of MOSFET-1, the total output current Io, the output current id2 of the branch containing MOSFET-2, and the output current id1 of the branch containing MOSFET-1. When the first control circuit operates via the first constant current loop 13, the drive voltage V1 of MOSFET-1 can be the third drive voltage Vgs3 output by the first constant current loop 13. The drive voltage V2 of MOSFET-2 can be the fourth drive voltage Vgs4 output by the second constant current loop 22. The output current id2 of the branch containing MOSFET-2 and the output current id1 of the branch containing MOSFET-1 are both output.

[0063] It is understandable that when the first control circuit operates in constant current mode, the reference current connected to the second input terminal of the fourth operation circuit U5 in the second control circuit can be the third preset current threshold Ir2.

[0064] Figure 7 This is a simulation analysis diagram of another power semiconductor device multi-chip parallel electrical signal equalization control circuit provided in an embodiment of the present invention. Combined with... Figure 4 , Figure 5 and Figure 7 In the power semiconductor device multi-chip parallel electrical signal equalization control circuit, the first control circuit operates by a constant voltage ring with current limiting, and the second control circuit operates by a second constant current ring. Figure 7The simulation curves, from top to bottom, are: the total output voltage Vo of the MOSFET, the drive voltage V2 of MOSFET-2, the drive voltage V1 of MOSFET-1, the output voltage Vgs1 of the constant voltage ring, the output voltage Vgs2 of the current limiting ring, the reference current IA of MOSFET-2, the total output current Io, the output current id2 of the branch containing MOSFET-2, and the output current id1 of the branch containing MOSFET-1. When the first control circuit operates with the current-limiting constant voltage ring 14, the drive voltage V1 of MOSFET-1 can be the smaller of the first drive voltage Vgs1 output by the constant voltage ring and the second drive voltage Vgs2 output by the current limiting ring. The drive voltage V2 of MOSFET-2 can be the fourth drive voltage Vgs4 output by the second constant current ring 22. The reference current IA of MOSFET-2 can be the first current output signal Is output by the first current sampling circuit 11. It can be seen that... Figure 7 The current limiting loop in the circuit is not working, and the driving voltage V1 of MOSFET-1 is provided by the output voltage of the constant voltage loop (i.e., the first driving voltage Vgs1).

[0065] Figure 8 This is a simulation analysis diagram of another power semiconductor device multi-chip parallel electrical signal equalization control circuit provided in an embodiment of the present invention. Combined with... Figure 4 , Figure 5 and Figure 8 In the power semiconductor device multi-chip parallel electrical signal equalization control circuit, the first control circuit operates by a constant voltage ring with current limiting, and the second control circuit operates by a second constant current ring. Figure 8 The simulation curves, from top to bottom, are: the total output voltage Vo of the MOSFET, the drive voltage V2 of MOSFET-2, the drive voltage V1 of MOSFET-1, the output voltage Vgs2 of the current-limiting ring, the output voltage Vgs1 of the constant voltage ring, the reference current IA of MOSFET-2, the total output current Io, the output current id2 of the branch containing MOSFET-2, and the output current id1 of the branch containing MOSFET-1. When the first control circuit operates with the current-limiting constant voltage ring 14, the drive voltage V1 of MOSFET-1 can be the smaller of the first drive voltage Vgs1 output by the constant voltage ring and the second drive voltage Vgs2 output by the current-limiting ring. The drive voltage V2 of MOSFET-2 can be the fourth drive voltage Vgs4 output by the second constant current ring 22. The reference current IA of MOSFET-2 can be the first current output signal Is output by the first current sampling circuit 11. It can be seen that... Figure 8 The current-limiting ring in the circuit operates, and the drive voltage V1 of MOSFET-1 is provided by the output voltage of the current-limiting ring (i.e., the second drive voltage Vgs2). After the current-limiting ring operates, the output current is constant, and the output current id2 of the branch containing MOSFET-2 and the output current id1 of the branch containing MOSFET-1 are both output.

[0066] It is understandable that when the first control circuit operates in constant voltage mode, the reference current connected to the second input terminal of the fourth operational circuit U5 in the second control circuit can be the first current output signal Is. At this time, the second control circuit can also be regarded as a constant voltage loop.

[0067] In summary, the power semiconductor device multi-chip parallel electrical signal equalization control circuit of this invention is compatible with both constant current loop and constant voltage loop control, and can trigger current limiting protection when the current is too high. This allows it to be adapted to various complex operating conditions and application scenarios when using MOSFETs.

[0068] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0069] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A multi-chip parallel electrical signal equalization control circuit for power semiconductor devices, characterized in that, The circuit is applied to a multi-MOS parallel circuit, which includes multiple parallel MOS transistors. The power semiconductor device multi-chip parallel electrical signal equalization control circuit includes a first control circuit and a second control circuit. The branch containing at least one MOS transistor is connected to the first control circuit, and the branch containing at least one MOS transistor is connected to the second control circuit. The first control circuit includes a first current sampling circuit, a switching switch, a first constant current loop, and a constant voltage loop with current limiting. The first current sampling circuit is used to collect the current of the branch where the connected MOS transistor is located. The switching switch is used to switch the first current output signal of the first current sampling circuit to the first constant current loop or the constant voltage loop with current limiting, so as to perform constant current loop control or constant voltage loop control with current limiting. The second control circuit includes a second current sampling circuit and a second constant current loop. The second current sampling circuit is used to collect the current of the branch where the connected MOS transistor is located in order to perform constant current loop control.

2. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 1, characterized in that, The constant voltage ring with current limiting includes: a voltage sampling circuit, a constant voltage ring, a current limiting ring, and a competition switching circuit; The voltage sampling circuit is used to collect the output voltage of the branch where the connected MOS transistor is located; The first input terminal of the constant voltage ring is connected to the voltage sampling circuit, and the second input terminal of the constant voltage ring is input to a preset voltage threshold. The constant voltage ring is used to output a first driving voltage to the first input terminal of the contention switching circuit according to the degree of difference between the output voltage and the preset voltage threshold. The input terminal of the current limiting ring is connected to the switching switch, receives the first current output signal, and receives the first preset current threshold. The current limiting ring is used to output a second driving voltage to the second input terminal of the contention switching circuit according to the relationship between the first current output signal and the first preset current threshold. The output terminal of the competition switching circuit serves as the output terminal of the constant voltage ring with current limiting, used to compare the magnitudes of the first driving voltage and the second driving voltage, and output the smaller of the first driving voltage and the second driving voltage.

3. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 2, characterized in that, The competition switching circuit includes: a first diode and a second diode; The first end of the first diode serves as the first input terminal of the contention switching circuit, the first end of the second diode serves as the second input terminal of the contention switching circuit, and the node where the second ends of the first diode and the second ends of the second diode are connected serves as the output terminal of the contention switching circuit. The first diode is turned on to connect the first input terminal of the contention switching circuit to the output terminal of the contention switching circuit; or, the second diode is turned on to connect the second input terminal of the contention switching circuit to the output terminal of the contention switching circuit.

4. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 2, characterized in that, The constant voltage ring includes a first operational circuit, a first resistor, a second resistor, a first capacitor, and a second capacitor; The first input terminal of the first arithmetic circuit is connected to the output voltage, and the second input terminal of the first arithmetic circuit is connected to the preset voltage threshold. The first resistor and the first capacitor are connected in series between the second input terminal and the output terminal of the first arithmetic circuit; the second resistor and the second capacitor are connected in series between the second input terminal and the output terminal of the first arithmetic circuit. The impedance parameter of the first resistor and the first capacitor connected in series is different from the impedance parameter of the second resistor and the second capacitor connected in series, and is used to adjust the integral parameter of the first operational circuit.

5. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 2, characterized in that, The current limiting loop includes a second operational circuit and a third capacitor; The input terminal of the second operational circuit is connected to the first current output signal and the first preset current threshold. The third capacitor is connected between the input terminal and the output terminal of the second operational circuit and is used to adjust the integral parameter of the current limiting loop.

6. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 1, characterized in that, The first current sampling circuit includes at least two sampling levels, each of which includes a different sampling precision.

7. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 6, characterized in that, At least two sampling ranges include at least two sampling resistors with different resistance values ​​and at least two analog switches; Each of the analog switches is connected to a corresponding sampling resistor. When the analog switch is closed, the sampling resistor connected to the analog switch is used to collect the current of the branch where the connected MOS transistor is located.

8. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 1, characterized in that, The first constant current loop includes a third operational circuit; The first input terminal of the third operational circuit is connected to the switching switch, and the second input terminal of the third operational circuit is connected to the second preset current threshold. The third operational circuit is used to output a third driving voltage according to the degree of difference between the first current output signal and the second preset current threshold.

9. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 1, characterized in that, The second constant current loop includes a fourth operational circuit; The first input terminal of the fourth operational circuit is connected to the second current sampling circuit, and the second input terminal of the fourth operational circuit is connected to the reference current. The fourth operational circuit is used to output a fourth driving voltage based on the degree of difference between the second current output signal of the second current sampling circuit and the reference current.

10. The power semiconductor device multi-chip parallel electrical signal equalization control circuit according to claim 9, characterized in that, The power semiconductor device multi-chip parallel electrical signal equalization control circuit includes a first switching switch and a second switching switch; The first input terminal of the first switching switch is connected to the output terminal of the first constant current ring, and the second input terminal of the first switching switch is connected to the output terminal of the constant voltage ring with current limiting. The output terminal of the first switching switch serves as the output terminal of the first control circuit. The first switching switch is used to switch the output signal of the first constant current ring or the output signal of the constant voltage ring with current limiting to the output terminal of the first control circuit. The first input terminal of the second switch is connected to a third preset current threshold, and the second input terminal of the second switch is connected to the output terminal of the first current sampling circuit; the second switch is used to switch the third preset current threshold or the first current output signal of the first current sampling circuit to the second constant current loop.

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