A method for determining the controllable harmonic number when a given inverter drive step size is given

Abstract

The application discloses a method for determining controllable harmonic number when a given inverter driving step is provided, and belongs to the technical field of power electronic control. The application obtains the driving step of the inverter to determine the minimum value of the minimum time interval, and constructs a nonlinear equation set based on the output voltage polarity and the preset harmonic number to be eliminated; under the constraint of the minimum time interval, the equation set is solved to determine the maximum value of the switching angle number corresponding to different output waveform frequencies, and then the controllable harmonic number is obtained; the application quantifies the dynamic relationship among the driving step, the output frequency and the controllable harmonic number, does not need to rely on the calculation capacity of the processor for real-time compromise, and provides a clear theoretical upper limit and engineering guidance for the harmonic control strategy design of the inverter under the fixed switching frequency.

Description

Technical Field

[0001] This invention belongs to the field of power electronic control and relates to a method for determining the number of controllable harmonics when given an inverter drive step size. Background Technology

[0002] As the core device for power conversion, the inverter's output voltage harmonic characteristics directly affect power quality and system operating efficiency. Specific Harmonic Elimination (SHE) technology, by precisely controlling the on and off times (i.e., switching angles) of power switching devices, can theoretically eliminate low-order harmonics of a specific order, making it an important means of improving inverter output performance.

[0003] Currently, the digital control strategy of inverters is typically based on a fixed drive step size (i.e., switching cycle). Under this constraint, the number of controllable harmonics is mainly affected by the coupling influence of several factors: the type of modulation strategy, the ratio of carrier frequency to fundamental frequency, the sampling frequency of the digital control system, and the computing power of the digital signal processor (DSP) or microcontroller unit (MCU).

[0004] According to the Nyquist sampling theorem, the sampling frequency must be at least twice the highest frequency of the analyzed signal, which limits the upper limit of the harmonic order that the system can effectively detect and process. Furthermore, the analysis window length of the Fast Fourier Transform (FFT) must be an integer multiple of the fundamental period to ensure the accuracy of the spectral analysis. In practical engineering applications, although complex harmonic compensation algorithms can accurately compensate for specific harmonic orders, the enormous computational load required to solve the switching angle in real time often becomes a bottleneck. This forces the system to make trade-offs between computational overhead and control accuracy, making it difficult to achieve the global optimum of harmonic mitigation effect and control resource consumption.

[0005] Therefore, how to quantify and determine the maximum number of harmonics that the system can control, and clarify the dynamic relationship between this number and the output waveform frequency and modulation ratio range, under the core hardware constraint of a given inverter drive step size (switching cycle), is a technical problem that urgently needs to be solved in the field of power electronics harmonic control. This invention is proposed against this background. Summary of the Invention

[0006] The technical solution of this invention is used to solve the technical problem of how to accurately calculate the maximum number of switching angles that an inverter can achieve when outputting waveforms of different frequencies based on a fixed switching cycle, thereby clarifying the theoretical limit of its harmonic control capability.

[0007] The present invention solves the above-mentioned technical problems through the following technical solutions: This invention provides a method for determining the number of controllable harmonics when given an inverter drive step size, comprising the following steps: Obtain the switching cycle corresponding to the inverter drive step size, and determine the minimum value of the shortest time interval in which the drive pulse level is maintained. The minimum value of the shortest time interval The minimum time threshold is calculated under the comprehensive constraints of switching characteristics of power switching devices, dead time requirements, and digital control systems to determine the delay. Based on specific harmonic elimination technology, a set of nonlinear equations is established to eliminate preset low-order harmonics when the inverter output voltage has N switching angles in the first quarter cycle; where N is an integer greater than or equal to 2. The minimum value of the shortest time interval Under the constraints, the nonlinear equation system is solved to obtain the solutions for N switching angles under different fundamental modulation ratios, and the minimum angular spacing for the driving pulse level to be maintained is determined based on the solutions for N switching angles. Calculate the maximum output waveform frequency corresponding to N switching angles based on the minimum angular spacing and the switching period. ; Based on the maximum value of the output waveform frequency Determine the frequency of the given output waveform. The maximum number of switching angles that can be used is used to determine the maximum number of harmonics that the inverter can control.

[0008] Furthermore, the relationship between the output waveform frequency and the maximum number of switching angles is as follows: the lower the output waveform frequency, the larger the maximum number of switching angles, and the more harmonics the inverter can control; the higher the output waveform frequency, the smaller the maximum number of switching angles, and the fewer harmonics the inverter can control.

[0009] Furthermore, for a unipolar output voltage waveform with N switching angles within the first quarter cycle, the minimum angular interval at which the level is maintained satisfies:

[0010] in, , , The numerator represents the switching angle of the output voltage during the first quarter cycle. This represents the minimum angular spacing at which the voltage level is maintained.

[0011] Furthermore, when the output voltage is unipolar and the number of switching angles N=3 within the first quarter cycle, the elimination of the 3rd and 5th harmonics is selected, and the specific harmonic elimination nonlinear equations are established as follows:

[0012] Where m is the fundamental frequency modulation ratio.

[0013] Furthermore, the fundamental modulation ratio m=V h1 / E,V h1 E is the fundamental amplitude of the output voltage, and E is the DC bus voltage.

[0014] Furthermore, the minimum value of the shortest time interval The value ranges from 100μs to 800μs, and when the minimum value of the shortest time interval is reached... When decreased, the maximum value of the output waveform frequency The number of harmonics that the inverter can control at a given output waveform frequency increases.

[0015] Furthermore, the specific steps for solving the nonlinear equation system include: The ant colony algorithm is used to perform a global search within the domain of the switching angle to obtain an approximate solution to the nonlinear equation system as the initial value. Using an approximate solution as the initial value, Newton's iteration method is used to perform a locally accurate solution until the preset convergence accuracy requirement is met, thus obtaining a high-precision switching angle value. The fundamental modulation ratio m is scanned within a predetermined range, and the corresponding switching angle solution under each fundamental modulation ratio is recorded. Based on all the switching angle solutions, the maximum value of the minimum angular interval at which the driving pulse level is continuously maintained is determined.

[0016] Furthermore, the inverter employs a unipolar H-bridge circuit.

[0017] The present invention also provides an electronic device, including a memory and a processor, the memory being used to store a program supporting the processor in executing the method for determining the number of controllable harmonics when a given inverter drive step size is given above, and the processor being configured to execute the program stored in the memory.

[0018] The present invention also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the method for determining the number of controllable harmonics when given an inverter drive step size.

[0019] The beneficial effects of this invention are as follows: This invention provides, for the first time, a quantitative correspondence between the number of controllable harmonics and the output waveform frequency of an inverter under a fixed drive step size, offering a clear theoretical boundary for inverter topology selection and control parameter design. The method provided by this invention, based on mathematical derivation and algorithmic solution, determines the number of controllable harmonics by the physical constraint of the drive step size, unaffected by the sampling frequency and computing power of the backend digital signal processor (DSP), effectively avoiding the trade-off between computational overhead and control accuracy in real-time control. Through this invention, engineers can quickly determine the optimal number of switching angles based on the target output frequency, ensuring harmonic cancellation while avoiding excessively high switching frequencies or algorithm convergence failures due to setting too many switching angles, thereby optimizing system efficiency and reliability. Through derivation and simulation, this invention reveals the inherent laws that "the lower the output frequency, the more controllable harmonics" and "the smaller the minimum time interval, the larger the upper limit of the output frequency," providing significant guidance for inverter control strategies across the entire frequency range. Attached Figure Description

[0020] Figure 1 This is the H-bridge circuit topology diagram of a unipolar inverter; Figure 2 This is a waveform diagram of the drive signal of the switching transistor in the H-bridge circuit of a unipolar inverter. Figure 3 This is the switching angle curve when the output voltage is unipolar, N=3, and the 3rd and 5th harmonics are eliminated; Figure 4 It is a graph showing the shortest angular spacing of the drive pulse when the output voltage is unipolar, N=3, and the 3rd and 5th harmonics are eliminated. Figure 5 It is to solve different The flowchart for the maximum value of N; Figure 6 It is the waveform diagram showing the maximum number of controllable harmonics; Figure 7 This is a waveform diagram showing the range of fundamental modulation ratios when the output waveform is 50Hz. Figure 8 This is a unipolar simulation output voltage waveform diagram; Figure 9 This is the FFT analysis plot of the unipolar simulation output voltage; Figure 10 This is a diagram of the experimental platform that was built; Figure 11 This is a waveform diagram of the output voltage in a unipolar experiment; Figure 12 This is the FFT analysis graph of the output voltage in a unipolar experiment. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 The core of this invention lies in: under the condition of a given inverter drive step size (i.e., switching cycle), the switching angle is solved by a specific harmonic elimination technique, thereby determining the maximum number of controllable harmonics at different output waveform frequencies.

[0023] The topology of a unipolar inverter H-bridge circuit is as follows: Figure 1 As shown, the drive signal waveforms of the switching transistors in the H-bridge circuit of a unipolar inverter are as follows: Figure 2 As shown, the drive pulse waveforms of the upper and lower bridge arms are opposite, i.e. and The driving pulses are opposite. and The driving pulses are opposite. Figure 2 The switching angle of the output voltage during the first quarter cycle includes , , The angular intervals between the high and low levels of the drive pulse are as follows: , , .

[0024] In practical engineering applications, the power switching devices of an inverter require a certain amount of time to fully turn on or off after receiving a drive signal. Simultaneously, the algorithm in the digital control system also consumes time to calculate the switching angle. Therefore, the duration of the high and low levels of the drive pulse cannot be infinitely short; it must satisfy the minimum constraint of the shortest time interval.

[0025] set up This represents the minimum value of the shortest time interval (in seconds), and its value is determined comprehensively based on the switching characteristics of the power switching device, dead time requirements, and the calculation delay of the digital control system. The shortest time interval between the high and low levels of the drive pulse is greater than or equal to the minimum value of the shortest time interval. In this specific embodiment, take The analysis was performed at 182 μs, but this value does not constitute a limitation on the present invention.

[0026] For a unipolar output voltage waveform with N switching angles in the first quarter cycle, the minimum angle interval for the level to be maintained must satisfy formula (1): (1) In formula (1), the molecule part This represents the minimum angular spacing at which the voltage level is maintained. Indicates the frequency of the output waveform (in Hz). This represents the minimum value of the shortest time interval, which is the time required for the algorithm to calculate the switching angle.

[0027] The minimum value of the shortest time interval is ≥ At 182μs, the maximum frequency of the output waveform The calculation expression is as follows: (2) Similarly, for any number of switching angles N within the first quarter cycle, when the frequency of the given output waveform... The minimum angular spacing required to maintain the voltage level is calculated using the following expression: (3) From formula (3), we can see that, For the minimum frequency of the output waveform, when given and At that time, the minimum value of the minimum angular spacing is a constant, and it only depends on... It is directly proportional and independent of the number of switching angles N. For example, when =50Hz, When the s t=182μs, in order to ensure that the frequency of the output waveform can be taken as 50Hz, then It must be at least equal to or slightly greater than 50Hz; the minimum angular spacing required to maintain this level is 50 × 360 × 1.82 × 10⁻⁶. -4 =3.276° (constant value).

[0028] When the output voltage is unipolar and the number of switching angles N=3 in the first quarter cycle, the elimination of the 3rd and 5th harmonics is selected, and the specific harmonic elimination nonlinear equation set is established as formula (4): (4) In formula (4), m is the fundamental modulation ratio. Fundamental modulation ratio m = V h1 / E,V h1 E is the fundamental amplitude of the output voltage, and E is the DC bus voltage.

[0029] This specific implementation uses the Newton-Ant Colony Algorithm to solve the aforementioned nonlinear equations. The basic idea of ​​the Newton-Ant Colony Algorithm is as follows: first, the ant colony algorithm is used to search for an approximate solution to the nonlinear equations globally as an initial value; then, starting from this initial value, Newton's iteration method is used for locally accurate solutions to obtain high-precision switching angle values. This method effectively overcomes the problem of the traditional Newton's iteration method's high dependence on initial values.

[0030] The specific solution steps are as follows: Step 1: Transform the nonlinear equation system shown in formula (4) into solving a set of switching angles. , , This makes all three equations in the system of equations true simultaneously.

[0031] Step 2: Perform a global search within the defined domain using the ant colony algorithm. The ant colony algorithm simulates the pheromone accumulation mechanism during ant foraging, gradually converging to the neighborhood of the optimal solution in the solution space.

[0032] Step 3: Use the switching angle obtained by the ant colony algorithm as the initial value of the Newton iteration method, substitute it into the Newton iteration formula for accurate solution, until the preset convergence accuracy requirement is met.

[0033] Step 4: Scan the modulation ratio m in the range of [0, 1.063] and record the corresponding switching angle solution for each modulation ratio.

[0034] The switching angle solution within the modulation ratio m ∈ [0, 1.063] is obtained using the Newton-Ant Colony Algorithm described above. The shortest angular distance between the high and low levels of the driving pulse is then plotted using the solved switching angles, as shown in the figure. Figure 3 and Figure 4 As shown. By Figure 4 Analysis shows that when N=3, the 3rd and 5th harmonics are eliminated. =50Hz, When the fundamental frequency modulation ratio m is 182 μs, the range of m is [0.103, 1.063]. Figure 4 The red dashed line in the middle represents the maximum value of the minimum angular spacing of the level, which is 19.929°. According to formula (2), the following can be calculated: =19.929 / (360×182μs)=304.167Hz. According to... Figure 2 From formula (3), it can be seen that: as The decrease in m indicates that the light green dashed line, representing the minimum angular interval, will shift downwards, and the range of values ​​for m will widen accordingly. Therefore, given the minimum value of the shortest time interval... At that time, with the frequency of the output waveform The smaller the value of m, the wider the range of the fundamental modulation ratio m, and the wider the adjustable output voltage range (V). h1 =m×E).

[0035] Similarly, when the output voltage is unipolar, The maximum output waveform frequency corresponding to different switching angle numbers N at 182μs. The range of the fundamental frequency modulation ratio m is shown in Table 1.

[0036] Table 1 shows that the output voltage is unipolar and At 182μs, different N corresponding to and the value of m

[0037] As shown in Table 1, with the increase of the number of switching angles N, the number of harmonics that can be eliminated increases, but the maximum value of the output waveform frequency decreases. It gradually decreases, and the range of values ​​for the fundamental modulation ratio m gradually narrows when transmitting a 50Hz waveform.

[0038] When given At that time, solve for different output waveform frequencies The flowchart for the maximum value of the corresponding number of switching angles N is as follows: Figure 5 As shown. According to Table 1 and Figure 5 Get: When At 182μs, any given output waveform frequency The maximum value of the corresponding number of switching angles N and the maximum number of controllable harmonics are shown in Table 2.

[0039] Table 2 =182μs, the maximum number of harmonics that can be controlled when outputting different waveform frequencies.

[0040] Table 2 clearly shows that the lower the output waveform frequency, the more switching angles can be used, and the more harmonics can be controlled. For example, when the output frequency is no higher than 51.936Hz, a maximum of 10 switching angles can be used, thus controlling a maximum of 9 harmonics; while when the output frequency is between 304.167Hz and 457.237Hz, a maximum of only 2 switching angles can be used, controlling a maximum of only 1 harmonic. Similarly, according to... Figure 5 The process shown can yield the following results: The maximum output waveform frequency corresponding to different switching angle numbers N at 100μs, 200μs, 400μs, 600μs, and 800μs. The range of the fundamental frequency modulation ratio m. Figure 5The summary shows that the maximum number of controllable harmonics (i.e., N) is achieved when outputting waveforms of different frequencies. 1) such as Figure 6 As shown; when outputting a 50Hz waveform and actually controlling different numbers of harmonics, the corresponding range of the fundamental modulation ratio m is as follows: Figure 7 As shown. By Figure 6 It can be seen that when N is 3 (i.e., controlling N), 1 = 2 harmonics), and When the time was 100μs, 200μs, 400μs, and 800μs respectively (i.e. (Increase by 2 times sequentially), maximum output waveform frequency. The frequencies are 553.6Hz, 276.79Hz, 138.4Hz, and 69.2Hz, respectively. Halve the frequency sequentially. The maximum value of the output waveform frequency is: (5) Therefore, it can be concluded that: with As the frequency decreases, the maximum value of the output waveform frequency increases; when given At that time, with f pwm With a reduction in harmonics, the maximum number of harmonics that can be controlled will increase.

[0041] At the same time, by Figure 7 We can conclude that: 1) When the minimum value of the shortest time interval is given. At that time, with the frequency of the output waveform The lower the value, the wider the range of the fundamental modulation ratio m, and the wider the adjustable output voltage range (V). h1 =m×E), the maximum number of harmonics that can be controlled (i.e., N-1) will increase; 2) when given At that time, as the number of harmonics actually controlled decreases, the range of m will widen; 3) as The reduction in frequency results in the maximum value of the output waveform frequency. The maximum number of harmonics that can be controlled (i.e., N-1) will increase, the range of m will increase, and the adjustable output voltage range will become wider.

[0042] Simulation verification With N=3, eliminating the 3rd and 5th harmonics, m=0.7, and DC bus voltage E=100V, the unipolar simulation output voltage waveform and its FFT analysis are as follows: Figure 8 and Figure 9 As shown, the fundamental amplitude of the output voltage is 69.97V, which is almost equal to the theoretical value V. h1 =m×E=0.7×100=70V, eliminating the 3rd and 5th harmonics.

[0043] Experimental verification like Figure 10As shown, this invention also constructed an experimental platform, using a DSP to send drive control signals to the inverter's switching transistors. With N=3, 3rd and 5th harmonics eliminated, m=0.7, and DC bus voltage E=20V, the unipolar experimental output voltage waveform and its FFT analysis are as follows. Figure 11 and Figure 12 As shown, the fundamental amplitude of the output voltage is 14V, which is equal to the theoretical value, eliminating the 3rd and 5th harmonics.

[0044] Those skilled in the art should understand that the specific embodiments described above employ... =182μs is just a specific example; in practical applications, ... The value of can be flexibly adjusted based on factors such as the actual switching speed of the power switching device, dead time requirements, sampling period of the digital control system, and calculation delay. Different The values ​​correspond to different controllable harmonic quantity distributions; please refer to [reference needed]. Figure 6 The relationship curves shown are used to determine the solution. Furthermore, the above specific implementation method is illustrated using unipolar voltage output as an example, but the method of the present invention is also applicable to inverters with bipolar voltage output; only the construction method of the nonlinear equation system needs to be adjusted accordingly. The Newton-Ant Colony Algorithm in the above specific implementation method is not the only solution method. Those skilled in the art can also use other intelligent optimization algorithms such as genetic algorithms and particle swarm optimization algorithms combined with Newton's iteration method to solve the nonlinear equation system; these are all equivalent alternatives to the present invention.

[0045] Example 2 This embodiment provides an electronic device, including a memory and a processor. The memory is used to store a program that supports the processor in executing a method for determining the number of controllable harmonics when a given inverter drive step size is specified in Embodiment 1. The processor is configured to execute the program stored in the memory.

[0046] Example 3 This embodiment provides a storage medium storing a computer program. When the computer program is run by a processor, it executes the steps of the method for determining the number of controllable harmonics when a given inverter drive step size is given in Embodiment 1.

[0047] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for determining the number of controllable harmonics when a given inverter drive step size is provided, characterized in that, Includes the following steps: Obtain the switching cycle corresponding to the inverter drive step size, and determine the minimum value of the shortest time interval in which the drive pulse level is maintained. The minimum value of the shortest time interval The minimum time threshold is calculated under the comprehensive constraints of switching characteristics of power switching devices, dead time requirements, and digital control systems to determine the delay. Based on specific harmonic elimination technology, a set of nonlinear equations is established to eliminate preset low-order harmonics when the inverter output voltage has N switching angles in the first quarter cycle; where N is an integer greater than or equal to 2. The minimum value of the shortest time interval Under the constraints, the nonlinear equation system is solved to obtain the solutions for N switching angles under different fundamental modulation ratios, and the minimum angular spacing for the driving pulse level to be maintained is determined based on the solutions for N switching angles. Calculate the maximum output waveform frequency corresponding to N switching angles based on the minimum angular spacing and the switching period. ; Based on the maximum value of the output waveform frequency Determine the frequency of the given output waveform. The maximum number of switching angles that can be used is used to determine the maximum number of harmonics that the inverter can control.

2. The method for determining the number of controllable harmonics when a given inverter drive step size is as described in claim 1, characterized in that, The relationship between the output waveform frequency and the maximum number of switching angles is as follows: the lower the output waveform frequency, the larger the maximum number of switching angles, and the more harmonics the inverter can control; the higher the output waveform frequency, the smaller the maximum number of switching angles, and the fewer harmonics the inverter can control.

3. The method for determining the number of controllable harmonics when a given inverter drive step size is as described in claim 1, characterized in that, For a unipolar output voltage waveform with N switching angles in the first quarter cycle, the minimum angle interval at which the level is maintained satisfies: in, , , The numerator represents the switching angle of the output voltage during the first quarter cycle. This represents the minimum angular spacing at which the voltage level is maintained.

4. The method for determining the number of controllable harmonics when a given inverter drive step size is described in claim 3, characterized in that, When the output voltage is unipolar and the number of switching angles N=3 in the first quarter cycle, the elimination of the 3rd and 5th harmonics is selected, and the specific harmonic elimination nonlinear equations are established as follows: Where m is the fundamental frequency modulation ratio.

5. The method for determining the number of controllable harmonics when a given inverter drive step size is described in claim 4, characterized in that, The fundamental modulation ratio m=V h1 / E,V h1 E is the fundamental amplitude of the output voltage, and E is the DC bus voltage.

6. The method for determining the number of controllable harmonics when a given inverter drive step size is as described in claim 1, characterized in that, The minimum value of the shortest time interval The value ranges from 100μs to 800μs, and when the minimum value of the shortest time interval is reached... When decreased, the maximum value of the output waveform frequency The number of harmonics that the inverter can control at a given output waveform frequency increases.

7. The method for determining the number of controllable harmonics when a given inverter drive step size is described in claim 4, characterized in that, The specific steps for solving the nonlinear equation system include: The ant colony algorithm is used to perform a global search within the domain of the switching angle to obtain an approximate solution to the nonlinear equation system as the initial value. Using an approximate solution as the initial value, Newton's iteration method is used to perform a locally accurate solution until the preset convergence accuracy requirement is met, thus obtaining a high-precision switching angle value. The fundamental modulation ratio m is scanned within a predetermined range, and the corresponding switching angle solution under each fundamental modulation ratio is recorded. Based on all the switching angle solutions, the maximum value of the minimum angular interval at which the driving pulse level is continuously maintained is determined.

8. The method for determining the number of controllable harmonics when a given inverter drive step size is as described in claim 1, characterized in that, The inverter uses a unipolar H-bridge circuit.

9. An electronic device, comprising a memory and a processor, characterized in that, The memory is used to store a program that supports the processor in executing the method for determining the number of controllable harmonics for a given inverter drive step size as described in any one of claims 1 to 8, and the processor is configured to execute the program stored in the memory.

10. A storage medium storing a computer program, characterized in that, The steps of the method for determining the number of controllable harmonics for a given inverter drive step size, as described in any one of claims 1 to 8, are executed by a computer program when run by a processor.

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