On-line compensation system for output waveform of switching power supply under strong harmonic interference

Abstract

The application relates to the technical field of electric variable regulation systems, and discloses an online compensation system for an output waveform of a switching power supply under strong harmonic interference, which comprises an output sampling unit, a preprocessing unit, an adaptive scheduling unit, a boundary constraint unit and a final-stage compensation control unit. The output sampling unit collects output electric quantity to generate deviation data. The preprocessing unit calculates power consumption parameters and analyzes harmonic characteristics according to a dynamic power consumption model. The adaptive scheduling unit determines a control starting point and constructs a control window when the deviation and its change rate break through a threshold. The boundary constraint unit sets a voltage amplitude boundary and a frequency modulation step. The optimization calculation unit solves optimal voltage and frequency compensation according to a target function containing waveform error and power factor. The final-stage compensation control unit drives series semiconductor devices to change dynamic impedance and applies driving charge feedforward compensation. The application suppresses alternating thermal resistance hysteresis and phase drift, reduces waveform distortion, and realizes electric variable regulation.

Description

Technical Field

[0001] This invention relates to an online compensation system for the output waveform of a switching power supply under strong harmonic interference, belonging to the technical field of electrical variable regulation systems. Background Technology

[0002] Switching power supplies are commonly used power conversion and supply devices, widely used in industrial automation equipment, communication equipment and power electronic systems. The control of existing switching power supplies is usually based on the premise that the power supply and load are in a linear and stable state. The main switching device is controlled by a feedback loop to keep the output voltage, output current and other electrical quantities near the set reference.

[0003] With a large number of nonlinear loads connected, switching power supplies are susceptible to strong harmonic interference. Harmonic interference causes nonlinear distortion in output voltage and current, increases reactive power components, and exacerbates device heating. Existing waveform correction methods mainly use proportional-integral-derivative (PID) regulation or passive filtering with fixed parameters. Fixed filter circuits are difficult to adapt to constantly changing harmonic conditions. PID regulation is limited by response delay and control bandwidth, making it difficult to track phase changes of high-frequency harmonics in a timely manner. During power regulation, changes in the main switching frequency can also cause internal dynamic power consumption fluctuations and affect the structure of semiconductor regulating devices connected in series with the load. The alternating temperature changes result in alternating thermal resistance and impedance response lag, which can easily cause the compensation action to be out of phase with the actual waveform distortion. This reduces the online adjustment accuracy of the electrical variable regulation system for the output waveform and electrical parameters. To improve the tracking ability of high-frequency harmonics, simply increasing the control loop gain or increasing the frequency modulation step size can easily cause controller saturation and semiconductor drive circuit overload after the harmonic abrupt change and high-frequency deviation are superimposed, leading to self-excited oscillation of the control loop and even damage to power devices. If the filtering effect is improved by increasing the number of passive filter stages, the equipment size will increase and the dynamic response speed of the system will decrease.

[0004] Therefore, in electrical variable regulation systems, how to coordinate dynamic power consumption calculation, time window boundary constraints, and semiconductor device thermal hysteresis feedforward compensation, while ensuring both the online adjustment accuracy of the output waveform and the safety of hardware operation under strong harmonic interference, is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: an online compensation system for the output waveform of a switching power supply under strong harmonic interference, comprising: The output sampling unit is used to collect the output voltage and output current of the switching power supply, compare the output voltage with the waveform reference value, and generate waveform deviation data. The preprocessing unit, connected to the output sampling unit, is used to calculate dynamic power consumption parameters based on the dynamic power consumption model, analyze the harmonic components and phase characteristics of waveform deviation data, and generate preprocessed waveform data. An adaptive scheduling unit, connected to the preprocessing unit, is used to determine the control starting point when the waveform deviation data exceeds the amplitude threshold and its rate of change exceeds the rate of change threshold, and to construct a compensation control window from the preprocessed waveform data. The boundary constraint unit, connected to the adaptive scheduling unit, is used to set the voltage compensation amplitude boundary and the maximum frequency modulation step size according to the compensation control window; The optimization calculation unit, connected to the boundary constraint unit, is used to solve for the extreme values ​​based on the objective function, which includes the square integral of waveform error, power factor and residual reactive power, under the constraints of voltage compensation amplitude boundary and maximum frequency modulation step size, so as to obtain the optimal voltage compensation amount and the optimal frequency compensation amount. The final stage compensation control unit includes a semiconductor regulating device connected in series with the load and is connected to an optimization calculation unit. It is used to drive the semiconductor regulating device to change the inter-terminal dynamic impedance according to the optimal voltage compensation amount and the optimal frequency compensation amount, and to apply gate drive charge feedforward compensation to the semiconductor regulating device according to the optimal frequency compensation amount.

[0006] Preferably, after acquiring waveform deviation data, the adaptive scheduling unit calculates the instantaneous amplitude and time rate of change of the waveform deviation data in real time; when the instantaneous amplitude is greater than the amplitude threshold and the time rate of change is greater than the rate of change threshold during the rising edge phase, the current moment is determined as the control starting point; the adaptive scheduling unit establishes a compensation control window based on the control starting point plus a determined step size; the adaptive scheduling unit extracts the envelope features of high-frequency harmonics within the compensation control window, adjusts the compensation gain based on the steepness of the envelope features, and generates compensation control trajectory data which is transmitted to the boundary constraint unit.

[0007] Preferably, the boundary constraint unit establishes a dynamic time window based on the compensation control trajectory data; the boundary constraint unit sets the voltage compensation amplitude boundary to include a symmetrical upper limit voltage amplitude and a lower limit voltage amplitude, which is used to limit the voltage adjustment limit between the drain and source extremes of the semiconductor regulating device; the boundary constraint unit sets the maximum frequency modulation step size as the upper limit of the frequency modulation, which is used to limit the frequency adjustment amplitude of the optimization calculation unit within a single switching cycle; when the theoretically calculated compensation requirement exceeds the upper limit voltage amplitude or the lower limit voltage amplitude, the boundary constraint unit will lock the output command at the boundary extreme value to prevent the semiconductor regulating device from being damaged by overvoltage or overcurrent.

[0008] Preferably, the optimization calculation unit sets a first weighting coefficient corresponding to the integral term of the square error between the output voltage and the waveform reference value, a second weighting coefficient corresponding to the deviation penalty term of the real-time power factor of the system, and a third weighting coefficient corresponding to the residual reactive power component term in the objective function. Within the feasible region formed by the voltage compensation amplitude boundary and the maximum frequency modulation step size constraint, the optimization calculation unit uses a minimization algorithm to solve the local minimum value of the objective function. When the waveform deviation data shows abrupt changes in higher-order harmonics, the optimization calculation unit guides the search trajectory to tilt towards the power factor correction direction by increasing the weight of the second weighting coefficient, and outputs the optimal voltage compensation amount and the optimal frequency compensation amount that satisfy the minimum total harmonic distortion.

[0009] Preferably, the semiconductor regulating device in the final stage compensation control unit adopts a power MOSFET or an insulated gate bipolar transistor connected in series with the load; the semiconductor regulating device operates in a hybrid regulation mode combining linear amplification and pulse width modulation; the final stage compensation control unit adjusts the bias voltage of the control terminal of the semiconductor regulating device according to the optimal voltage compensation amount, changes the equivalent on-resistance of the drain and source of the semiconductor regulating device and the dynamic impedance between terminals, absorbs or fills the distortion energy on the output bus of the switching power supply, and keeps the waveform residual deviation at the output terminal of the switching power supply within the preset error range.

[0010] Preferably, the final stage compensation control unit includes a drive feedforward module; the drive feedforward module obtains the optimal frequency compensation amount and calculates the transient alternating thermal hysteresis after the main switch frequency change causes the junction temperature change of the semiconductor regulating device; the drive feedforward module adjusts the peak value of the gate drive current and the drive charge injection rate of the semiconductor regulating device according to the transient alternating thermal hysteresis after the change, and synchronously applies gate drive charge feedforward compensation at the impedance adjustment time to offset the junction capacitance charging and discharging delay and thermal hysteresis effect during the dynamic impedance transition process between the semiconductor regulating device terminals, and maintains phase synchronization between frequency conversion regulation and impedance regulation.

[0011] Preferably, the output sampling unit includes a current transformer and an analog-to-digital converter; the output sampling unit synchronously samples the output voltage and output current at a specific phase point in each switching cycle; the output sampling unit subtracts the sampled real-time voltage value from the internally stored AC sinusoidal reference voltage value to generate waveform deviation data; the preprocessing unit, adaptive scheduling unit, boundary constraint unit, and optimization calculation unit complete signal transmission and extreme value solving within a single switching cycle, enabling the final-stage compensation control unit to apply dynamic impedance adjustment in the latter half of the current cycle.

[0012] Preferably, when external strong harmonic interference causes the voltage sampling signal acquired by the output sampling unit to exceed the upper limit voltage amplitude limit, the boundary constraint unit outputs a limiting trigger signal; the final stage compensation control unit responds to the limiting trigger signal by clamping the inter-terminal dynamic impedance of the semiconductor regulating device to the safe impedance boundary corresponding to the highest voltage compensation amplitude, preventing the semiconductor regulating device from overvoltage and overcurrent, while maintaining the output bus voltage of the switching power supply within the safe operating voltage range.

[0013] Preferably, after the final-stage compensation control unit adjusts the inter-terminal dynamic impedance of the semiconductor regulating device, the output sampling unit continuously detects the adjusted output voltage and output current and updates the waveform deviation data to form a real-time closed-loop compensation circuit. The final-stage compensation control unit reduces the total harmonic distortion of the switching power supply output waveform, improves the power factor of the system, and reduces the residual reactive power component by dynamically adjusting the impedance and the main switching frequency, thereby realizing steady-state and dynamic adaptive adjustment of electrical variables under strong harmonic interference conditions.

[0014] Compared with the prior art, the beneficial effects of the present invention are: 1. In the online compensation of the output waveform of a switching power supply under strong harmonic interference, the timing of compensation is determined by combining the output waveform deviation, dynamic power consumption parameters, and harmonic changes. The compensation amount is then calculated within the set voltage and frequency range, so that voltage compensation and frequency adjustment can change synchronously with strong harmonic disturbances. This can improve the tracking speed of high-frequency harmonics, reduce the phase lag between compensation action and waveform distortion, and avoid controller saturation caused by sudden changes in compensation amount, which is beneficial to maintaining the stability of the output waveform of the switching power supply.

[0015] 2. While the semiconductor regulating device changes the dynamic impedance between terminals, gate drive charge feedforward compensation is applied according to the change of the main switching frequency. This can correct the impedance response lag caused by junction temperature fluctuations and junction capacitance charging and discharging delays in advance, so that impedance regulation and frequency regulation are kept in phase synchronization, reducing phase drift that occurs during frequent frequency modulation, and improving the tracking accuracy of the final stage compensation control unit for output waveform changes.

[0016] 3. By setting boundaries for the voltage compensation amplitude and the single frequency modulation amplitude, and comprehensively considering waveform error, power factor and residual reactive power within these boundaries to obtain the compensation amount, excessive control output can be limited during strong harmonic abrupt changes, reducing the risk of overvoltage, overcurrent and thermal damage to series semiconductor regulating devices. At the same time, voltage correction and reactive power regulation can be coordinated within a safe range, taking into account both output waveform compensation accuracy and system operation stability. Attached Figure Description

[0017] Figure 1 This is a block diagram of the control signal flow of the online compensation system for switching power supplies of the present invention; Figure 2This is a diagram showing the functional units and their distribution in the online compensation system for switching power supplies of the present invention.

[0018] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0020] An online compensation system for the output waveform of a switching power supply under strong harmonic interference includes: The output sampling unit is used to collect the output voltage and output current of the switching power supply, compare the output voltage with the waveform reference value, and generate waveform deviation data. The preprocessing unit, connected to the output sampling unit, is used to calculate dynamic power consumption parameters based on the dynamic power consumption model, analyze the harmonic components and phase characteristics of waveform deviation data, and generate preprocessed waveform data. An adaptive scheduling unit, connected to the preprocessing unit, is used to determine the control starting point when the waveform deviation data exceeds the amplitude threshold and its rate of change exceeds the rate of change threshold, and to construct a compensation control window from the preprocessed waveform data. The boundary constraint unit, connected to the adaptive scheduling unit, is used to set the voltage compensation amplitude boundary and the maximum frequency modulation step size according to the compensation control window; The optimization calculation unit, connected to the boundary constraint unit, is used to solve for the extreme values ​​based on the objective function, which includes the square integral of waveform error, power factor and residual reactive power, under the constraints of voltage compensation amplitude boundary and maximum frequency modulation step size, so as to obtain the optimal voltage compensation amount and the optimal frequency compensation amount. The final stage compensation control unit includes a semiconductor regulating device connected in series with the load and is connected to an optimization calculation unit. It is used to drive the semiconductor regulating device to change the inter-terminal dynamic impedance according to the optimal voltage compensation amount and the optimal frequency compensation amount, and to apply gate drive charge feedforward compensation to the semiconductor regulating device according to the optimal frequency compensation amount.

[0021] Preferably, after acquiring waveform deviation data, the adaptive scheduling unit calculates the instantaneous amplitude and time rate of change of the waveform deviation data in real time; when the instantaneous amplitude is greater than the amplitude threshold and the time rate of change is greater than the rate of change threshold during the rising edge phase, the current moment is determined as the control starting point; the adaptive scheduling unit establishes a compensation control window based on the control starting point plus a determined step size; the adaptive scheduling unit extracts the envelope features of high-frequency harmonics within the compensation control window, adjusts the compensation gain based on the steepness of the envelope features, and generates compensation control trajectory data which is transmitted to the boundary constraint unit.

[0022] Preferably, the boundary constraint unit establishes a dynamic time window based on the compensation control trajectory data; the boundary constraint unit sets the voltage compensation amplitude boundary to include a symmetrical upper limit voltage amplitude and a lower limit voltage amplitude, which is used to limit the voltage adjustment limit between the drain and source extremes of the semiconductor regulating device; the boundary constraint unit sets the maximum frequency modulation step size as the upper limit of the frequency modulation, which is used to limit the frequency adjustment amplitude of the optimization calculation unit within a single switching cycle; when the theoretically calculated compensation requirement exceeds the upper limit voltage amplitude or the lower limit voltage amplitude, the boundary constraint unit will lock the output command at the boundary extreme value to prevent the semiconductor regulating device from being damaged by overvoltage or overcurrent.

[0023] Preferably, the optimization calculation unit sets a first weighting coefficient corresponding to the integral term of the square error between the output voltage and the waveform reference value, a second weighting coefficient corresponding to the deviation penalty term of the real-time power factor of the system, and a third weighting coefficient corresponding to the residual reactive power component term in the objective function. Within the feasible region formed by the voltage compensation amplitude boundary and the maximum frequency modulation step size constraint, the optimization calculation unit uses a minimization algorithm to solve the local minimum value of the objective function. When the waveform deviation data shows abrupt changes in higher-order harmonics, the optimization calculation unit guides the search trajectory to tilt towards the power factor correction direction by increasing the weight of the second weighting coefficient, and outputs the optimal voltage compensation amount and the optimal frequency compensation amount that satisfy the minimum total harmonic distortion.

[0024] Preferably, the semiconductor regulating device in the final stage compensation control unit adopts a power MOSFET or an insulated gate bipolar transistor connected in series with the load; the semiconductor regulating device operates in a hybrid regulation mode combining linear amplification and pulse width modulation; the final stage compensation control unit adjusts the bias voltage of the control terminal of the semiconductor regulating device according to the optimal voltage compensation amount, changes the equivalent on-resistance of the drain and source of the semiconductor regulating device and the dynamic impedance between terminals, absorbs or fills the distortion energy on the output bus of the switching power supply, and keeps the waveform residual deviation at the output terminal of the switching power supply within the preset error range.

[0025] Preferably, the final stage compensation control unit includes a drive feedforward module; the drive feedforward module obtains the optimal frequency compensation amount and calculates the transient alternating thermal hysteresis after the main switch frequency change causes the junction temperature change of the semiconductor regulating device; the drive feedforward module adjusts the peak value of the gate drive current and the drive charge injection rate of the semiconductor regulating device according to the transient alternating thermal hysteresis after the change, and synchronously applies gate drive charge feedforward compensation at the impedance adjustment time to offset the junction capacitance charging and discharging delay and thermal hysteresis effect during the dynamic impedance transition process between the semiconductor regulating device terminals, and maintains phase synchronization between frequency conversion regulation and impedance regulation.

[0026] Preferably, the output sampling unit includes a current transformer and an analog-to-digital converter; the output sampling unit synchronously samples the output voltage and output current at a specific phase point in each switching cycle; the output sampling unit subtracts the sampled real-time voltage value from the internally stored AC sinusoidal reference voltage value to generate waveform deviation data; the preprocessing unit, adaptive scheduling unit, boundary constraint unit, and optimization calculation unit complete signal transmission and extreme value solving within a single switching cycle, enabling the final-stage compensation control unit to apply dynamic impedance adjustment in the latter half of the current cycle.

[0027] Preferably, when external strong harmonic interference causes the voltage sampling signal acquired by the output sampling unit to exceed the upper limit voltage amplitude limit, the boundary constraint unit outputs a limiting trigger signal; the final stage compensation control unit responds to the limiting trigger signal by clamping the inter-terminal dynamic impedance of the semiconductor regulating device to the safe impedance boundary corresponding to the highest voltage compensation amplitude, preventing the semiconductor regulating device from overvoltage and overcurrent, while maintaining the output bus voltage of the switching power supply within the safe operating voltage range.

[0028] Preferably, after the final-stage compensation control unit adjusts the inter-terminal dynamic impedance of the semiconductor regulating device, the output sampling unit continuously detects the adjusted output voltage and output current and updates the waveform deviation data to form a real-time closed-loop compensation circuit. The final-stage compensation control unit reduces the total harmonic distortion of the switching power supply output waveform, improves the power factor of the system, and reduces the residual reactive power component by dynamically adjusting the impedance and the main switching frequency, thereby realizing steady-state and dynamic adaptive adjustment of electrical variables under strong harmonic interference conditions.

[0029] Example 1: The current output sampling unit is connected to a switching power supply variable regulation system that uses a nonlinear industrial load and injects high-order harmonics. It detects the output power at the output terminal of the switching power supply in real time, and the unit collects the waveform reference value. The reference voltage is a sinusoidal waveform with a peak voltage of 220.0V and a frequency of 50.0Hz; simultaneously, at the main switching frequency... At 100.0kHz, the output voltage sampling signal is acquired. With the output current sampling signal, at the sampling time At 1.25ms, the system is injected with 3rd and 5th high-frequency harmonics, and the actual output voltage... The voltage drops to 208.50V, and the output sampling unit compares this voltage with a waveform reference value of 220.00V. Compare and generate waveform deviation data Its instantaneous value is 11.50V.

[0030] The preprocessing unit receives data transmitted from the output sampling unit and processes it based on the equivalent load capacitance of 470.0 μF. and the loss current component induced by high-frequency harmonics. During the switching cycle The integral value within the range is 12.35W. A dynamic power consumption model is constructed based on this value. ,in, For dynamic power consumption, This is the equivalent load capacitance. This is the real-time value of the output voltage. Main switching frequency, This refers to the loss current component induced by high-frequency harmonics. For integration time variable, Based on the switching cycle, the preprocessing unit obtains the dynamic power consumption parameters under the current operating condition. The power consumption is 2055.47W, and harmonic component extraction and phase feature analysis are completed to generate dynamic power consumption parameters. The preprocessed waveform data and waveform deviation data are used. This dynamic power consumption parameter characterizes the total transmission power of the system. The main power of the system is undertaken by the main power circuit of the switching power supply. The power MOSFET connected in series with the load is used to handle the dynamic deviation power corresponding to the bus voltage distortion. When the waveform deviation data is 11.50V and the load current is 10A, the instantaneous voltage withstand of the power MOSFET in the linear amplification state is 11.50V and the maximum power consumption is 115W. The device is mounted on an aluminum substrate with a heat sink, and the thermal resistance is less than 0.5℃ / W. In the hybrid regulation mode combining linear amplification state and pulse width modulation state, its average power consumption is less than 45W and the junction temperature is maintained within the safe threshold of 75℃.

[0031] The adaptive scheduling unit receives preprocessed waveform data and calculates waveform deviation data in real time. The instantaneous value of 11.50V and its rise time rate of change of 1.45V / μs are compared with the amplitude threshold. 3.50V and rate of change threshold The comparison is performed using 1.20V / μs, and the corresponding judgment condition is: ,in, For waveform deviation data, This is the real-time value of the output voltage. As the waveform reference value, For amplitude threshold, As the rate of change threshold, once both conditions are met, the adaptive scheduling unit determines the current time of 1.25ms as the control start point. An adaptive control window length of 2.00 ms is superimposed on this control starting point. A compensation control window with a time range of 1.25ms to 3.25ms was established. .

[0032] Within the compensation control window, the adaptive scheduling unit takes the absolute value of the high-frequency harmonic components in the preprocessed waveform data and performs low-pass smoothing to obtain the envelope characteristics of the high-frequency harmonics. Then, it determines the steepness of the envelope characteristics based on the difference in envelope amplitude between adjacent sampling points and the sampling interval, and selects the compensation gain according to the pre-calibrated correspondence between the steepness and the compensation gain. The steeper the envelope change, the higher the compensation gain is used. The adaptive scheduling unit combines the compensation gain, time-domain trajectory, and harmonic phase characteristics into compensation control trajectory data and transmits it to the boundary constraint unit.

[0033] The boundary constraint unit reads the time information from the compensation control trajectory data to control the starting point. The corresponding timestamp serves as the starting point of the dynamic time window, and the timestamp of the last sampling point of the trajectory serves as the ending point of the dynamic time window. When the compensation control trajectory data is updated, the starting and ending points of the dynamic time window are updated accordingly, and the boundary constraint unit sets the upper limit of the voltage compensation amplitude. Set it to 15.0V to set the lower limit of the voltage compensation amplitude. Set to -15.0V to limit the adjustment limit of the drain-source voltage of the power MOSFET; simultaneously, set the maximum frequency modulation step size. Set to 5.0kHz to limit the frequency adjustment amplitude within a single switching cycle, the corresponding boundary relationship is as follows: ,in, For voltage compensation amplitude, The compensated main switching frequency, The difference between the two frequencies is the frequency compensation amount, where the frequency is the main switching frequency before compensation.

[0034] The optimization calculation unit solves for the objective function within the closed feasible region defined by the voltage compensation amplitude boundary and the maximum frequency modulation step size. : ,in, Let be the objective function. The first weighting coefficient, This is the second weighting coefficient. The third weighting coefficient, For output voltage sampling signal, For voltage compensation amplitude, As the waveform reference value, The real-time power factor of the system. This refers to the residual reactive power component. To control the starting point, To adaptively control the window length, this embodiment uses the first weighting coefficient Set to 0.60, the second weighting coefficient Set to 0.25, the third weighting coefficient Setting the value to 0.15, the optimal voltage compensation amount is obtained by minimizing the integral term of the square of the output voltage error, the power factor deviation penalty term, and the residual reactive power component term. 11.20V, optimal frequency compensation The frequency was set to 1.80kHz, adjusting the main switching frequency to 101.80kHz, which did not exceed the maximum frequency modulation step size. When a high-order harmonic abrupt change occurred in the waveform deviation data, the optimization calculation unit increased the second weighting coefficient. The objective function is then re-solved to adjust the search trajectory toward power factor correction.

[0035] Before weighted summation, the optimization calculation unit performs per-unit normalization on each physical quantity in the objective function. The output voltage error square integral term is divided by the product of the square of the waveform reference value and the length of the adaptive control window, and converted into a dimensionless voltage deviation per-unit value. The power factor deviation term itself is a dimensionless value. The residual reactive power component is divided by the system rated reactive power reference value and converted into a dimensionless reactive power per-unit value. After all three terms are converted into dimensionless values ​​in the range of 0 to 1, they are multiplied by the corresponding weighting coefficients and then superimposed.

[0036] The final stage compensation control unit receives the optimal voltage compensation amount. With optimal frequency compensation amount The optimal frequency compensation is output to the main switch driver of the switching power supply, adjusting the main switch frequency from 100.0kHz to 101.80kHz. Simultaneously, the power MOSFET connected in series with the load is driven to operate in a hybrid regulation mode combining linear amplification and pulse width modulation, and the inter-terminal dynamic impedance is changed. When the output voltage is higher than the waveform reference value, the final compensation control unit increases the inter-terminal dynamic impedance to absorb the distortion energy corresponding to the portion exceeding the waveform reference value. When the output voltage is lower than the waveform reference value, the inter-terminal dynamic impedance is reduced, allowing the energy output after the main switch frequency adjustment to be transferred to the load through the power MOSFET, filling the distortion energy corresponding to the portion below the waveform reference value. In this undervoltage condition, the power MOSFET, in conjunction with the main switch frequency adjustment, forms an 11.20V voltage compensation on the output bus of the switching power supply.

[0037] The drive feedforward module in the final stage compensation control unit reads the main switch frequency variation of 1.80kHz and, based on this variation and dynamic power consumption parameters, obtains the current impedance transition delay from the frequency variation and inter-terminal dynamic impedance response curves pre-calibrated according to different junction temperatures. The drive feedforward module subtracts the current impedance transition delay from the reference impedance transition delay when the main switch frequency is unchanged to obtain the transient alternating thermal hysteresis. Based on this hysteresis, the injection time of the gate drive charge is advanced accordingly, and the peak value of the gate drive current and the drive charge injection rate are adjusted. At the impedance adjustment time, gate drive charge feedforward compensation is applied to compensate for the junction capacitance charging and discharging delay and the inter-terminal dynamic impedance response hysteresis caused by junction temperature alternation, so that the frequency conversion regulation and impedance regulation remain in phase synchronization.

[0038] The hybrid regulation mode is implemented by a dual-path drive synthesis circuit within the final-stage compensation control unit. The first path is a linear bias control circuit, where a digital-to-analog converter converts the optimal voltage compensation amount into a continuously varying control terminal bias voltage, which is then applied to the control terminal of the power MOSFET. This changes the drain-source equivalent on-resistance and inter-terminal dynamic impedance by adjusting the static operating point. The second path is a pulse width modulation drive circuit, which converts the optimal frequency compensation amount into a high-frequency switching pulse signal synchronized with the adjusted main switching frequency. This signal is then superimposed onto the same control terminal via a pulse transformer. In the first half of each switching cycle, the control terminal receives the high-frequency pulse signal, putting the power MOSFET in pulse width modulation mode and transmitting energy. In the second half of the cycle, the control terminal receives a continuous control terminal bias voltage, putting the power MOSFET in linear amplification mode. The output waveform is corrected by adjusting the inter-terminal dynamic impedance. The two control signals are voltage superimposed and time-division multiplexed at the drive front end, allowing the same power MOSFET to switch between linear amplification and pulse width modulation modes.

[0039] After adjustment by the final stage compensation control unit, the actual output voltage reached 219.70V, and the residual waveform deviation from the 220.00V waveform reference value decreased to 0.30V; the total harmonic distortion of the output voltage decreased from 9.20% before compensation to 1.05%, and the system's real-time power factor improved. The residual reactive power component increased from 0.82 to 0.98. The power consumption was reduced from 145.0VAR to 12.5VAR. Dynamic power consumption parameters were used to solve the objective function. Dynamic time windows defined the compensation boundary. The transient alternating thermal hysteresis was used to adjust the gate drive charge feedforward compensation. Each unit formed a closed-loop compensation circuit according to the same control timing.

[0040] Example 2: The test platform uses an AC programmable power supply to generate a sinusoidal waveform reference value with a peak value of 220.0V and a frequency of 50.0Hz. The equivalent load capacitance of the main circuit The main switching frequency is 470.0 μF. Set to 100.0kHz, a multi-harmonic generator composed of thyristors and nonlinear impedances is connected to the output terminal to inject alternating disturbance current containing 3rd, 5th, 7th, and 11th high-frequency harmonic components into the main circuit. The current transformer in the output sampling unit obtains the output voltage and output current signals. The analog-to-digital converter operates at a sampling frequency of 10.0MHz and synchronously samples the output voltage sampling signal at a specific phase point in each switching cycle. The sampling frequency of the output current sampling signal is determined according to the requirements for acquiring high-order harmonic details, while also taking into account the computational load of data processing.

[0041] Under steady-state, interference-free operating conditions, the output sampling unit measured a maximum amplitude of 2.10V and a maximum rate of change of 0.85V / μs for the background voltage noise ripple. Based on this, the amplitude threshold was set. Set the rate of change threshold to 3.50V. Set to 1.20V / μs to avoid conventional high-frequency ripple triggering compensation control and to identify strong harmonic abrupt signals.

[0042] The experiment was conducted with four parallel sample groups. Each sample group consisted of an output sampling unit, a preprocessing unit, an adaptive scheduling unit, a boundary constraint unit, an optimization calculation unit, and a final-stage compensation control unit with a drive feedforward module. Control group 1 used a fixed PID feedback regulation loop; control group 2 removed the drive feedforward module, retaining only the inter-terminal dynamic impedance regulation; control group 3 removed the limiting function of the boundary constraint unit, thus limiting the voltage compensation amplitude. With the compensated main switching frequency Unconstrained by voltage compensation amplitude boundaries and maximum frequency modulation step size, the four sample groups were subjected to comparative tests under the same temperature and electric field interference environment, and five operating conditions were carried out in sequence: steady-state condition, moderate harmonic injection, severe harmonic mutation, dynamic load step, and ultimate voltage drop.

[0043] Under steady-state conditions, the total harmonic distortion (THD) of the output voltage before compensation was 3.20% for both the sample group of this invention and the control group 1. After closed-loop compensation, the THD of the sample group of this invention decreased to 0.85%, and the power factor was [not specified]. The residual reactive power component is 0.99. The reactive power component of the control group was 8.2 VAR, the phase tracking lag was 0.32 μs, and the junction temperature of the semiconductor device was 45.2 °C. After fixed PID feedback regulation, the THD of the control group was 1.85%, the power factor was 0.93, the residual reactive power component was 32.5 VAR, the phase tracking lag was 6.50 μs, and the junction temperature of the semiconductor device was 48.0 °C.

[0044] Under moderate harmonic injection conditions, the pre-compensation THD of all three sample groups was 9.20%, and the actual output voltage measured by the output sampling unit was... The voltage is 208.50V, and the waveform deviation relative to the waveform reference value is 11.50V; the adaptive scheduling unit determines 1.25ms as the control start point. And according to an adaptive control window length of 2.00ms. Construct a compensation control window The preprocessing unit is based on the loss current component. The dynamic power consumption parameter is calculated from the integral value of 12.35W. The voltage is 2055.47W. The optimization calculation unit finds the optimal voltage compensation amount within the voltage compensation amplitude boundary and the maximum frequency modulation step size. 11.20V, optimal frequency compensation The optimal frequency compensation control unit outputs the optimal frequency compensation to the main switch drive terminal at 1.80kHz, adjusting the main switch frequency to 101.80kHz. Simultaneously, it drives the power MOSFET to change the inter-terminal dynamic impedance. The drive feedforward module calculates the transient alternating thermal hysteresis based on the optimal frequency compensation, adjusts the peak value of the gate drive current and the drive charge injection rate accordingly, and applies gate drive charge feedforward compensation. The power factor of the sample group of this invention is improved from 0.82 to 0.98, the THD after compensation is 1.05%, the residual reactive power component is 12.5VAR, the phase tracking hysteresis is 0.45μs, and the junction temperature of the semiconductor device is 52.1℃.

[0045] Control group 1 uses fixed PID feedback regulation. Due to the limited bandwidth of the control loop, the phase tracking lag is 18.20 μs. After compensation, its THD is 4.25%, power factor is 0.86, residual reactive power component is 88.0 VAR, and semiconductor device junction temperature is 58.6℃. Control group 2 only adjusts the inter-terminal dynamic impedance. During the same main switch frequency adjustment process, no gate drive charge feedforward compensation is applied. The junction capacitance charging and discharging delay and alternating thermal resistance effect cause the phase tracking lag to reach 8.10 μs. Some harmonic energy is not smoothly absorbed by the inter-terminal dynamic impedance. After compensation, its THD is 2.65%, power factor is 0.91, residual reactive power component is 45.0 VAR, and semiconductor device junction temperature is 68.4℃.

[0046] Under severe harmonic abrupt change conditions, the pre-compensation THD of both the sample group of this invention and control group 2 was 14.80%. After the waveform deviation data showed a high-order harmonic abrupt change, the optimization calculation unit increased the weight of the second weighting coefficient and resolved the optimal voltage compensation amount and the optimal frequency compensation amount. The post-compensation THD of the sample group of this invention was 1.62%, the power factor was 0.96, the residual reactive power component was 18.2 VAR, the phase tracking lag was 0.58 μs, and the semiconductor device junction temperature was 61.5℃. Control group 2 did not apply gate drive charge feedforward compensation, and its post-compensation THD was 5.80%, the power factor was 0.83, the residual reactive power component was 112.0 VAR, the phase tracking lag was 12.40 μs, and the semiconductor device junction temperature was 89.2℃.

[0047] Under extreme voltage drop conditions, the THD before compensation for both the sample group and control group 3 was 22.50%. External strong harmonics caused the output voltage to drop to 190.00V, and the waveform deviation reached 30.00V. The theoretical voltage compensation requirement obtained by the optimization calculation unit was 29.80V. Control group 3 did not set the voltage compensation amplitude boundary and the maximum frequency modulation step size. The final stage compensation control unit drove the power MOSFET according to the theoretical requirement, resulting in overvoltage, overcurrent and self-excited oscillation of the control loop. After compensation, the THD was 18.90%, the power factor was 0.65, the residual reactive power component was 240.0VAR, the phase tracking lag was 22.50μs, the semiconductor device junction temperature was 138.5℃, and the system lost its electrical variable regulation capability.

[0048] The present invention detected that the waveform deviation data corresponding to the voltage sampling signal exceeded the upper limit voltage amplitude of 15.0V in the sample group. Subsequently, the boundary constraint unit outputs a limiting trigger signal; the final-stage compensation control unit responds to this signal by clamping the inter-terminal dynamic impedance of the power MOSFET at the safe impedance boundary corresponding to the highest voltage compensation amplitude, and sets the maximum frequency modulation step size. Limited to within 5.0kHz, after adjusting the output voltage to 205.00V, the compensated THD is 3.15%, the power factor is 0.92, the residual reactive power component is 35.0VAR, the phase tracking lag is 0.82μs, and the semiconductor device junction temperature is 74.8℃.

[0049] In the above operating conditions, the preprocessing unit calculates dynamic power consumption parameters, the adaptive scheduling unit determines the control starting point and constructs a compensation control window based on the amplitude threshold and the rate of change threshold, the boundary constraint unit limits the voltage compensation amplitude and the main switch frequency adjustment range, and the final-stage compensation control unit completes closed-loop regulation through inter-terminal dynamic impedance adjustment and gate drive charge feedforward compensation. Gate drive charge feedforward compensation reduces alternating thermal hysteresis and phase tracking hysteresis in the impedance adjustment process. The voltage compensation amplitude boundary and the maximum frequency modulation step size limit the electrical and thermal stress of the device when the ultimate voltage drops, preventing device thermal failure and control saturation. The changes in the total harmonic distortion, power factor and residual reactive power components of the output waveform correspond to the above control process. The system realizes online compensation and hardware safety regulation under strong harmonic interference.

[0050] Example 3: The current optimization calculation unit receives real-time dynamic power consumption parameters from the preprocessed waveform data. Within the feasible region defined by the voltage compensation amplitude boundary of -15.0V to 15.0V and the maximum frequency modulation step size of 5.0kHz, and the instantaneous value of the waveform deviation data, the continuous-time objective function will be... The evaluation sequence is expanded based on the discrete sampling points in the compensation control window, with the sampling period applied to the compensation control window. After meshing, a candidate state matrix consisting of discrete voltage compensation and discrete frequency compensation is constructed, and candidate nodes that cause the inter-terminal voltage of the semiconductor regulating device to exceed the voltage compensation amplitude boundary are eliminated; then, each effective node is substituted into the output voltage sampling signal. With waveform reference value The sum of squared instantaneous errors is calculated and weighted and superimposed with the power factor deviation term and the residual reactive power component term to obtain the evaluation scalar of each candidate node.

[0051] In this embodiment, the first weighting coefficient Set to 0.60, the second weighting coefficient Set to 0.25, the third weighting coefficient. The value is set to 0.15. The optimization calculation unit compares the evaluation scalars of each candidate node, selects the node that minimizes the evaluation scalar, and obtains the optimal voltage compensation amount. 11.20V, optimal frequency compensation The frequency is 1.80 kHz. The compensation control window is used to limit the range of sampling sequences participating in the evaluation. Within each switching cycle, the optimization calculation unit calculates the evaluation scalar in parallel for the candidate nodes corresponding to the sampling sequence and completes the minimum value screening. The time length of the compensation control window is not considered as the processing delay of a single extreme value solution.

[0052] The preprocessing unit, adaptive scheduling unit, boundary constraint unit, and optimization calculation unit are integrated into the same field-programmable gate array chip and adopt a hardware pipelined parallel processing architecture. The output sampling unit synchronously collects the output voltage and output current at a specific phase point in each switching cycle. After completing the analog-to-digital conversion, each unit transmits data sequentially under the drive of a unified clock pulse. The optimization calculation unit calls the pre-fixed parallel lookup table and fast hardware comparator tree inside the chip to complete the scalar parallel calculation of the evaluation of a finite number of candidate grid nodes and the selection of the minimum value within 1.5μs. The total processing time from output sampling, preprocessing, boundary constraint to extreme value solution is less than 5μs, enabling the final-stage compensation control unit to apply inter-terminal dynamic impedance adjustment in the second half of the current switching cycle.

[0053] Amplitude threshold With the rate of change threshold During the system self-test phase, calibration is performed based on the sampling results of background electromagnetic noise. The output sampling unit continuously acquires 100 cycles of output voltage signal under the reference operating state without strong harmonic injection. The preprocessing unit calculates the amplitude variance of the background voltage ripple and sets three times the peak value of the variance as the amplitude threshold. Simultaneously, calculate the difference slope between adjacent sampling points, and set 1.5 times the maximum absolute value of the slope as the rate of change threshold. According to the calibration results, the amplitude threshold is 3.50V and the rate of change threshold is 1.20V / μs.

[0054] When a strong harmonic injection causes the instantaneous value of the waveform deviation data to exceed 3.50V and the rise time change rate to exceed 1.20V / μs, the adaptive scheduling unit determines the current moment as the control start point. An adaptive control window length of 2.00 ms is superimposed on this control starting point. The construction time range is The compensation control window is then used. Subsequently, the adaptive scheduling unit synchronously transmits the compensation control trajectory data with the time domain boundary to the boundary constraint unit, the optimization calculation unit, and the final compensation control unit to reduce false triggering caused by high-frequency switching ripple.

[0055] The final stage compensation control unit receives the optimal voltage compensation amount. With optimal frequency compensation amount The power MOSFET connected in series with the load is driven to adjust its drain-source equivalent on-resistance and inter-terminal dynamic impedance, and the main switching frequency is adjusted from 100.0kHz to 101.80kHz. The drive feedforward module calculates the transient alternating thermal hysteresis caused by the main switching frequency change in the power MOSFET junction temperature based on the optimal frequency compensation of 1.80kHz; this is then combined with the input junction capacitance of the power MOSFET. Determine the required gate drive charge increment and adjust the peak gate drive current and drive charge injection rate accordingly.

[0056] Before the rising edge of the pulse width modulation drive signal arrives, the drive feedforward module pre-injects the corresponding gate drive charge into the gate equivalent capacitance, so that the adjustment time of the inter-terminal dynamic impedance is advanced relative to the uncompensated state, in order to offset the impedance response lag caused by the junction capacitance charging and discharging delay and alternating thermal resistance. After inter-terminal dynamic impedance adjustment and gate drive charge feedforward compensation, the phase tracking lag is compressed to within 0.45μs, and the total harmonic distortion of the output voltage is stabilized at 1.05%, completing the online compensation of the switching power supply output waveform under strong harmonic interference.

[0057] Example 4: This example combines Figures 1 to 2 This paper describes an online compensation system for the output waveform of a switching power supply under strong harmonic interference, such as... Figure 1 As shown, the output power of the switching power supply is transmitted to the output sampling unit to generate waveform deviation data. The output sampling unit inputs the generated waveform deviation data to the preprocessing unit to generate preprocessed data. The preprocessing unit transmits the generated preprocessed data to the adaptive scheduling unit to construct a compensation control window. The adaptive scheduling unit sends the constructed compensation control window signal to the boundary constraint unit to set the boundary and step size. The boundary constraint unit provides the set boundary and step size parameters to the optimization calculation unit to calculate the optimal compensation amount. The optimization calculation unit outputs the calculated optimal compensation amount to the drive feedforward module and the semiconductor regulating device inside the final stage compensation control unit. The drive feedforward module applies feedforward compensation and acts on the semiconductor regulating device. The semiconductor regulating device changes the inter-terminal impedance and outputs the online compensated power to the load nonlinear device.

[0058] like Figure 2 As shown, the online compensation system for a switching power supply includes an output sampling unit, a preprocessing unit, an adaptive scheduling unit, a boundary constraint unit, an optimization calculation unit, and a final-stage compensation control unit. The output sampling unit is used to collect output power and generate waveform deviation data. The preprocessing unit is used to calculate dynamic power consumption parameters and analyze harmonic characteristics. The adaptive scheduling unit is used to adjust the compensation gain and construct the compensation control window. The boundary constraint unit is used to set the voltage compensation boundary and set the maximum frequency modulation step size. The optimization calculation unit is used to solve for the optimal compensation amount and guide power factor correction. The final-stage compensation control unit is used to change the inter-terminal dynamic impedance and apply charge feedforward compensation.

[0059] Example 5: After the switching power supply system is powered on, the main control chip first applies a micro-excitation pulse with a frequency of 100.0kHz and a duty cycle of 0.10 to the drive circuit. After the micro-excitation pulse ends, the output sampling unit collects the attenuation process of the output voltage under no-load conditions, recording the output voltage attenuating from the peak value of 220.0V to its value. The time constant required to achieve 80.9V is times that of the previous value. The preprocessing unit uses sampling resistors Given the resistance, the real-time equivalent load capacitance is calculated using the following formula: Calculated real-time equivalent load capacitance The capacitor reference parameter in the dynamic power consumption model is used to update the system. Subsequently, the system acquires the no-load alternating leakage current in the closed-loop state and calculates the initial loss current component without harmonic injection. During the switching cycle The baseline integral value is calculated and written to a cache register. The preprocessing unit uses this as a subtraction offset in subsequent calculations to deduct the baseline component corresponding to the no-load leakage current from the acquired results. This corrects the static power consumption calculation deviation caused by component aging, ensuring the generated dynamic power consumption parameters are accurate. Matches the current hardware status.

[0060] Before deploying the system to the new operating environment, the drive feedforward module undergoes temperature adaptability calibration. The calibration temperature range is 0℃ to 70.0℃. Within this temperature range, the drive feedforward module gradually adjusts the drive signal pulse width and switching frequency. Measuring the input junction capacitance of a power MOSFET The charge and discharge response curves at different junction temperatures were recorded, and the response delay of the inter-terminal dynamic impedance relative to the drive signal was recorded. For each set of main switch frequency variations, the increase in response delay of the inter-terminal dynamic impedance relative to the reference frequency state was taken as the transient alternating thermal hysteresis. The peak gate drive current and drive charge injection rate were then adjusted until the response delay was compensated, thus forming the optimal frequency compensation amount. Gate drive charge injection amount A discrete correspondence table is generated and the correspondence table is stored in non-volatile memory.

[0061] The optimization calculation unit outputs the optimal frequency compensation amount. Subsequently, the drive feedforward module looks up the transient alternating thermal hysteresis and gate drive charge injection amount by referring to a table based on the corresponding junction temperature and main switch frequency variation. The drive current adjustment circuit determines the application time of the gate drive charge based on this hysteresis, and according to... Adjust the peak value of the gate drive current and the drive charge injection rate; inject or extract dynamic feedforward charge into the gate of the power MOSFET within 30.0 ns before the rising edge of the drive pulse, so that the gate drive charge feedforward compensation and the inter-terminal dynamic impedance adjustment are performed synchronously, and the inter-terminal dynamic impedance conversion delay is maintained within the lower limit window of 0.45 μs.

[0062] The junction temperature of the semiconductor regulating device still changes according to the millisecond-level heat conduction process. After the junction temperature drift causes the drain-source equivalent on-resistance and input junction capacitance to change continuously, the drive feedforward module uses the gate drive charge injection amount obtained from calibration to adjust the gate charging and discharging slope before each switching pulse arrives. This makes the actual response time of the inter-terminal dynamic impedance advance relative to the uncompensated state. This advance amount offsets the impedance response lag caused by junction temperature change, so that the inter-terminal dynamic impedance adjustment and the main switch frequency change remain in phase synchronization.

[0063] Example 6: Under strong harmonic interference conditions, the final stage compensation control unit drives the series power MOSFET to adjust the dynamic impedance between its terminals, and the output sampling unit collects the sampling time in real time. Output voltage sampling signal Based on the output current sampling signal, the preprocessing unit calculates three consecutive switching cycles. The waveform deviation data change rate within the range, when the dominant component of the harmonic spectrum changes from the 3rd and 5th harmonics to the 7th and 11th harmonics, the adaptive scheduling unit extracts the envelope features of high-frequency harmonics from the preprocessed waveform data, adjusts the compensation gain according to the change of envelope amplitude of adjacent sampling points, and retrieves the baseline control window length of 2.00ms.

[0064] The adaptive scheduling unit simultaneously calculates the discrete waveform distortion kurtosis factor according to the following formula. : when When the value exceeds 0.15V / μs, the adaptive scheduling unit will adaptively control the window length. The timeframe is shortened from 2.00ms to 1.00ms, and compensation control trajectory data is generated according to the updated compensation control window. The optimization calculation unit improves the objective function as the control window shortens. The discrete solution frequency makes the optimal voltage compensation amount With optimal frequency compensation amount The update time has been reduced from 2.00ms to 1.00ms to keep up with the rapid changes in the higher-order harmonic envelope.

[0065] Extracting the loss current component During this process, the preprocessing unit uses a hardware quadrature phase-locked loop to track the fundamental frequency and phase of the composite output current signal and synthesizes a sinusoidal fundamental current signal accordingly. A hardware differential amplifier subtracts the sinusoidal fundamental current signal from the composite output current signal to obtain the harmonic current components. A high-pass filter then filters out the low-frequency fluctuations, outputting the loss current components caused by the high-frequency harmonics. This is used for integral calculations in the dynamic power consumption model.

[0066] The final stage compensation control unit receives the updated optimal voltage compensation amount. With optimal frequency compensation amount The optimal frequency compensation is output to the main switch driver, which simultaneously drives the power MOSFET connected in series with the load to change the drain-source equivalent on-resistance and inter-terminal dynamic impedance, addressing the gate threshold voltage issue that occurs after the power MOSFET has been subjected to alternating thermal stress for a long time. Drift and On Resistance Increase, drive the feedforward module in the current switching cycle The voltage and drive current between the drain and source terminals of the semiconductor regulating device are synchronously acquired to obtain the actual response of the inter-terminal dynamic impedance. This response is then compared with the calibration response at the corresponding main switching frequency to determine the transient alternating thermal hysteresis.

[0067] The drive feedforward module adjusts the peak gate drive current and drive charge injection rate based on the hysteresis, applies gate drive charge feedforward compensation synchronously at the impedance adjustment moment, and injects compensation charge before the rising edge of the drive pulse. This corrects the adjustment trajectory of the dynamic impedance between terminals, ensuring that the frequency conversion regulation and impedance regulation remain in phase synchronization.

[0068] When the intensity of external harmonic interference increases, the waveform deviation data corresponding to the voltage sampling signal exceeds the upper limit voltage amplitude. When the corresponding 15.0V limit is met, and the theoretical voltage compensation obtained by the optimization calculation unit reaches 32.00V, the boundary constraint unit outputs a limiting trigger signal. The final-stage compensation control unit responds to this signal by clamping the inter-terminal dynamic impedance of the power MOSFET at the safe impedance boundary corresponding to the maximum voltage compensation amplitude of 15.0V, thus maintaining the inter-terminal voltage adjustment at 15.0V and setting the maximum frequency modulation step size. Limiting the frequency to within 5.0kHz, after boundary limiting, the total harmonic distortion of the output voltage waveform is maintained at 3.15%, and the system continuously performs closed-loop regulation of the power output of the switching power supply under strong harmonic interference.

[0069] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An online compensation system for the output waveform of a switching power supply under strong harmonic interference, characterized in that, include: The output sampling unit is used to collect the output voltage and output current of the switching power supply, compare the output voltage with the waveform reference value, and generate waveform deviation data. The preprocessing unit, connected to the output sampling unit, is used to calculate dynamic power consumption parameters based on the dynamic power consumption model, analyze the harmonic components and phase characteristics of waveform deviation data, and generate preprocessed waveform data. An adaptive scheduling unit, connected to the preprocessing unit, is used to determine the control starting point when the waveform deviation data exceeds the amplitude threshold and its rate of change exceeds the rate of change threshold, and to construct a compensation control window from the preprocessed waveform data. The boundary constraint unit, connected to the adaptive scheduling unit, is used to set the voltage compensation amplitude boundary and the maximum frequency modulation step size according to the compensation control window; The optimization calculation unit, connected to the boundary constraint unit, is used to solve for the extreme values ​​based on the objective function, which includes the square integral of waveform error, power factor and residual reactive power, under the constraints of voltage compensation amplitude boundary and maximum frequency modulation step size, so as to obtain the optimal voltage compensation amount and the optimal frequency compensation amount. The final stage compensation control unit includes a semiconductor regulating device connected in series with the load and is connected to an optimization calculation unit. It is used to drive the semiconductor regulating device to change the inter-terminal dynamic impedance according to the optimal voltage compensation amount and the optimal frequency compensation amount, and to apply gate drive charge feedforward compensation to the semiconductor regulating device according to the optimal frequency compensation amount.

2. The online compensation system for the output waveform of a switching power supply under strong harmonic interference as described in claim 1, characterized in that, After acquiring waveform deviation data, the adaptive scheduling unit calculates the instantaneous amplitude and time rate of change of the waveform deviation data in real time. When the instantaneous amplitude is greater than the amplitude threshold and the time rate of change is greater than the rate of change threshold during the rising edge phase, the current moment is determined as the control start point. The adaptive scheduling unit establishes a compensation control window based on the control starting point plus a determined step size. The adaptive scheduling unit extracts the envelope features of high-frequency harmonics within the compensation control window, adjusts the compensation gain based on the steepness of the envelope features, and generates compensation control trajectory data which is then transmitted to the boundary constraint unit.

3. The online compensation system for the output waveform of a switching power supply under strong harmonic interference according to claim 2, characterized in that, The boundary constraint unit establishes a dynamic time window based on the compensation control trajectory data; the boundary constraint unit sets the voltage compensation amplitude boundary to include symmetrical upper and lower voltage amplitudes, which are used to limit the voltage adjustment limit between the drain and source extremes of the semiconductor regulating device; the boundary constraint unit sets the maximum frequency modulation step size as the upper frequency modulation value, which is used to limit the frequency adjustment amplitude of the optimization calculation unit within a single switching cycle; when the theoretically calculated compensation requirement exceeds the upper or lower voltage amplitude, the boundary constraint unit will lock the output command at the boundary extreme value to prevent the semiconductor regulating device from being damaged by overvoltage or overcurrent.

4. The online compensation system for the output waveform of a switching power supply under strong harmonic interference according to claim 1, characterized in that, The optimization calculation unit sets the first weighting coefficient to correspond to the integral term of the square error between the output voltage and the waveform reference value, the second weighting coefficient to correspond to the deviation penalty term of the real-time power factor of the system, and the third weighting coefficient to correspond to the residual reactive power component term in the objective function. Within the feasible region formed by the voltage compensation amplitude boundary and the maximum frequency modulation step size constraint, the optimization calculation unit uses a minimization algorithm to solve the local minimum value of the objective function. When the waveform deviation data shows abrupt changes in higher-order harmonics, the optimization calculation unit guides the search trajectory to tilt towards the power factor correction direction by increasing the weight of the second weighting coefficient, and outputs the optimal voltage compensation amount and the optimal frequency compensation amount that satisfy the minimum total harmonic distortion.

5. The online compensation system for the output waveform of a switching power supply under strong harmonic interference according to claim 1, characterized in that, The semiconductor regulating device in the final stage compensation control unit adopts a power MOSFET or an insulated gate bipolar transistor connected in series with the load; the semiconductor regulating device operates in a hybrid regulation mode combining linear amplification and pulse width modulation; the final stage compensation control unit adjusts the bias voltage of the control terminal of the semiconductor regulating device according to the optimal voltage compensation amount, changes the equivalent on-resistance of the drain and source of the semiconductor regulating device and the dynamic impedance between terminals, absorbs or fills the distortion energy on the output bus of the switching power supply, and keeps the waveform residual deviation at the output terminal of the switching power supply within the preset error range.

6. The online compensation system for the output waveform of a switching power supply under strong harmonic interference according to claim 1, characterized in that, The final stage compensation control unit includes a drive feedforward module; the drive feedforward module obtains the optimal frequency compensation amount and calculates the transient alternating thermal hysteresis after the main switch frequency variation causes the junction temperature change of the semiconductor regulating device. The drive feedforward module adjusts the peak value of the gate drive current and the drive charge injection rate of the semiconductor regulating device according to the transient alternating thermal hysteresis. At the impedance adjustment time, gate drive charge feedforward compensation is applied synchronously to offset the junction capacitance charging and discharging delay and thermal hysteresis effect during the dynamic impedance transition process between the semiconductor regulating device terminals, and to maintain phase synchronization between frequency conversion regulation and impedance regulation.

7. The online compensation system for the output waveform of a switching power supply under strong harmonic interference according to claim 1, characterized in that, The output sampling unit includes a current transformer and an analog-to-digital converter; The output sampling unit synchronously samples the output voltage and output current at a specific phase point in each switching cycle; the output sampling unit subtracts the sampled real-time voltage value from the internally stored AC sinusoidal reference voltage value to generate waveform deviation data; the preprocessing unit, adaptive scheduling unit, boundary constraint unit, and optimization calculation unit complete signal transmission and extreme value solving within a single switching cycle, enabling the final-stage compensation control unit to apply dynamic impedance adjustment in the latter half of the current cycle.

8. The online compensation system for the output waveform of a switching power supply under strong harmonic interference according to claim 3, characterized in that, When external strong harmonic interference causes the voltage sampling signal acquired by the output sampling unit to exceed the upper limit voltage amplitude limit, the boundary constraint unit outputs a limiting trigger signal; the final stage compensation control unit responds to the limiting trigger signal, clamps the inter-terminal dynamic impedance of the semiconductor regulating device to the safe impedance boundary corresponding to the highest voltage compensation amplitude, prevents the semiconductor regulating device from overvoltage and overcurrent, and maintains the output bus voltage of the switching power supply within the safe operating voltage range.

9. The online compensation system for the output waveform of a switching power supply under strong harmonic interference according to claim 1, characterized in that, After the final-stage compensation control unit adjusts the inter-terminal dynamic impedance of the semiconductor regulating device, the output sampling unit continuously detects the adjusted output voltage and output current and updates the waveform deviation data to form a real-time closed-loop compensation circuit. The final-stage compensation control unit reduces the total harmonic distortion of the switching power supply output waveform, improves the power factor of the system, and reduces the residual reactive power component by dynamically adjusting the impedance and the main switching frequency, thereby achieving steady-state and dynamic adaptive adjustment of electrical variables under strong harmonic interference conditions.

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