Transient response control circuit and method for a dc-dc converter

Abstract

The application relates to the field of electronic circuits, and discloses a transient response control circuit and method of a direct-current-direct-current converter, which comprises a power conversion circuit and a transient response adjusting circuit; the power conversion circuit comprises at least one phase power unit, each phase power unit comprises an energy storage inductor and a power switch tube; the transient response adjusting circuit comprises an error amplification circuit, a slope generation circuit, a transient enhancement circuit, a hysteresis comparison circuit and a driving circuit; the error amplification circuit receives a reference voltage and an output voltage of the power conversion circuit and outputs an error signal, the slope generation circuit is connected with the energy storage inductor to obtain current ripple information and outputs a slope signal, the transient enhancement circuit receives the error signal and adjusts a charging and discharging slope of the slope signal when a transient occurs, the hysteresis comparison circuit receives the error signal and the slope signal and outputs a PWM signal, and the driving circuit receives the PWM signal and drives the power switch tube. The application can improve the transient response speed when the transient occurs.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, and in particular to a transient response control circuit and method for a DC-DC converter. Background Technology

[0002] DC-DC converters are widely used in electronic devices to provide stable voltage. In high-voltage, high-conversion-ratio applications, multiphase DC-DC converters are typically used to meet high current requirements. Currently, the control methods for DC-DC converters are mostly based on fixed-frequency control or hysteresis control.

[0003] For fixed-frequency control, due to the fixed switching frequency and lack of a fast adjustment mechanism, the system cannot respond quickly to changes in load or input voltage, resulting in poor transient response capability.

[0004] Compared to fixed-frequency control, hysteresis control exhibits better transient response capabilities and can flexibly adjust the switching frequency within a certain range. However, when a transient occurs, due to the fixed inductor magnetization slope, its pulse width extension remains limited. Simply increasing the switching frequency cannot achieve optimal transient response, and the output voltage will still experience a significant drop.

[0005] Furthermore, in multiphase parallel DC-DC converters, to avoid overlapping conduction times of the power transistors in each phase, the control signals for each phase are typically required to maintain a fixed phase difference (e.g., 360° / N). This fixed phase difference limitation prevents the power transistor control signals from achieving a wider range of conduction time extensions. When a transient load change occurs, the multiphase inductor currents are limited by the fixed phase difference and cannot synchronously charge the load, thus limiting the transient response speed improvement of the multiphase system.

[0006] Regarding the aforementioned technologies, existing DC-DC converter control methods suffer from problems such as limited pulse width expansion, inability to charge multiple phases synchronously due to fixed phase differences, and slow overall transient response speed. Summary of the Invention

[0007] To address the aforementioned technical problems, this application provides a transient response control circuit and method for a DC-DC converter.

[0008] Firstly, the transient response control circuit for a DC-DC converter provided in this application adopts the following technical solution: A transient response control circuit for a DC-DC converter includes a power conversion circuit and a transient response adjustment circuit. The power conversion circuit includes at least one phase power unit, each phase power unit including an energy storage inductor and a power switch. The transient response adjustment circuit includes an error amplifier circuit, a ramp generation circuit, a transient enhancement circuit, a hysteresis comparator circuit, and a drive circuit. The error amplifier circuit receives a reference voltage and the output voltage of the power conversion circuit and outputs an error signal. The ramp generation circuit is connected to the energy storage inductor to obtain current ripple information and outputs a ramp signal. The transient enhancement circuit receives the error signal and adjusts the charging and discharging slope of the ramp signal when a transient occurs. The hysteresis comparator circuit receives the error signal and the ramp signal and outputs a PWM signal. The drive circuit receives the PWM signal and drives the power switch.

[0009] By adopting the above technical solution, when a transient occurs, the hysteresis comparator circuit is forced to quickly flip the PWM signal to achieve a fast response by accelerating the descent of the ramp signal. Furthermore, by slowing down the rise of the ramp signal, the limitation of the traditional fixed magnetization slope is overcome, thereby achieving adaptive expansion of the pulse width, improving the transient response speed, and reducing the output voltage drop.

[0010] Optionally, the ramp generation circuit is connected in parallel across the energy storage inductor and includes a capacitor and a sampling branch connected in series. The connection point between the capacitor and the sampling branch is the ramp signal output terminal, and the sampling branch is a resistor voltage divider sampling branch or a current source sampling branch.

[0011] By adopting the above technical solution, current ripple information can be directly obtained from both ends of the energy storage inductor. The circuit structure is simple and can accurately and quickly reflect the inductor current state, providing a reliable ramp signal for hysteresis control.

[0012] Optionally, each phase of the power unit includes a high-side power switch and a low-side power switch connected in series. One end of the energy storage inductor is connected to the connection node of the high-side power switch and the low-side power switch, and the other end is used to connect to the load.

[0013] By adopting the above technical solution, the basic topology of the power conversion circuit is clarified, ensuring the normal operation of power conversion and inductor energy storage, and providing a control basis for the control circuit.

[0014] Optionally, the transient enhancement circuit includes a first input terminal, a second input terminal, and a first output terminal; the first input terminal receives the error signal; the second input terminal receives a fast dynamic sampling signal; the transient enhancement circuit is configured to: compare the error signal with the fast dynamic sampling signal to obtain a difference value; when the difference value reaches a preset threshold, determine that a load transient has occurred; and output a pull-down current signal to the ramp generation circuit through the first output terminal to adjust the charging and discharging slope of the ramp signal.

[0015] By adopting the above technical solution, the moment of transient occurrence can be accurately determined with low delay by comparing the slowly changing error signal with the rapidly changing sampling signal, and the difference can be converted into pull-down current to adjust the ramp signal, thus realizing rapid transient response and adaptive adjustment of duty cycle information.

[0016] Optionally, the transient enhancement circuit further includes a unidirectional isolation diode D1, disposed between the first output terminal and the ramp generation circuit, for limiting the unidirectional output pull-down current of the transient enhancement circuit.

[0017] By adopting the above technical solution, the transient enhancement circuit is limited to outputting pull-down current in only one direction, preventing interference signals under normal operating conditions from affecting the ramp generation circuit in reverse, thus ensuring the stability and unidirectionality of the control.

[0018] Optionally, the power conversion circuit includes N parallel power units, where N is a positive integer greater than or equal to 2; the transient enhancement circuit further includes a second output terminal, which outputs an N-phase common charging signal; the transient response adjustment circuit further includes a phase-interleaving circuit, which receives the PWM signal output by the hysteresis comparator circuit and the N-phase common charging signal, and is configured to: when the N-phase common charging signal is in a second level state, perform phase-division processing on the PWM signal and output N interleaved PWM signals with a preset phase difference; when the N-phase common charging signal is in a first level state, release the phase difference constraint between the N phases and output N synchronous PWM signals; the drive circuit responds to the N interleaved PWM signals or the N synchronous PWM signals and controls the power switching transistors of each phase power unit to be turned on or off.

[0019] By adopting the above technical solution, in multiphase parallel applications, when a load transient occurs, the phase difference constraint is released by outputting an N-phase common charging signal, and the N-phase power switching transistors are controlled to conduct synchronously, so that the multiphase inductor current charges the load at the same time, increasing the equivalent inductor charging slope by N times, breaking through the limitation of the fixed phase difference on the conduction time, and greatly improving the transient response speed of the multiphase system.

[0020] Secondly, the transient response control method for a DC-DC converter provided in this application adopts the following technical solution: A transient response control method for a DC-DC converter, applied to the transient response control circuit in the first aspect described above, includes the following steps: S1. The error amplifier circuit receives the reference voltage and the output voltage of the power conversion circuit, generates and outputs the error signal; the ramp generation circuit obtains the current ripple information of the energy storage inductor, generates and outputs the ramp signal; the hysteresis comparator circuit receives the error signal and the ramp signal, and continuously generates the PWM signal. S2. The transient enhancement circuit adjusts the charging and discharging slope of the ramp signal when it determines that a load transient has occurred. S3. The drive circuit receives the PWM signal and drives the power switching transistor in the power conversion circuit.

[0021] By adopting the above technical solution, the PWM duty cycle can be quickly adjusted by adjusting the charging and discharging slope of the ramp signal when a transient event is detected, thereby achieving a fast response.

[0022] Optionally, step S2 specifically includes: the transient enhancement circuit receives the fast dynamic sampling signal and continuously monitors the difference between the error signal and the fast dynamic sampling signal; when the difference reaches a preset threshold, it is determined that a load transient has occurred, and the transient enhancement circuit outputs a pull-down current signal to the ramp generation circuit to change the charging and discharging slope of the ramp signal, thereby adjusting the duty cycle of the PWM signal; when the difference is lower than the preset threshold, it is determined that the load transient has disappeared, and the transient enhancement circuit stops outputting the pull-down current signal.

[0023] By adopting the above technical solution, the occurrence and disappearance of transients can be accurately determined by comparing the error signal and the fast dynamic sampling signal and outputting the pull-down current, and the PWM duty cycle can be adaptively adjusted.

[0024] Optionally, when the power conversion circuit includes N-phase parallel power units and the transient response adjustment circuit includes a phase-interleaving circuit, where N is a positive integer greater than or equal to 2, the method further includes the following steps: When a load transient is determined to occur, in step S2, the transient enhancement circuit simultaneously outputs an N-phase common-charge signal at a first-level state; the phase-interleaving circuit receives the PWM signal output by the hysteresis comparator circuit and the N-phase common-charge signal, and outputs N synchronous PWM signals; in step S3, the drive circuit receives the N synchronous PWM signals... In step S2, the transient enhancement circuit switches the N-phase common charging signal to a second level state when the load transient disappears. The phase-splitting circuit performs phase-splitting processing on the PWM signal output by the hysteresis comparator circuit, outputting N interleaved PWM signals with a preset phase difference. In step S3, the drive circuit receives the N interleaved PWM signals and controls the power switches of each phase power unit to resume interleaved conduction.

[0025] By adopting the above technical solution, in a multiphase system, phase difference constraints are released by issuing a specific common charging signal, thereby realizing synchronous conduction and charging of multiple phases, improving the transient response speed of the multiphase system; and after the transient disappears, interleaved conduction is restored to ensure steady-state performance.

[0026] Optionally, the following steps are also included: S4, jump to step S2 for continuous cyclic monitoring to respond to load transients in real time.

[0027] By adopting the above technical solutions, a closed-loop control is formed, continuously monitoring load transients to ensure that the system resumes normal interleaved operation after the transients disappear, and is ready to respond to new transients at any time to maintain the continuous stability of the output voltage.

[0028] In summary, this application includes at least one of the following beneficial technical effects: 1. By setting a transient enhancement circuit to adjust the charging and discharging slope of the ramp signal when a transient occurs, the limitation of a fixed magnetization slope is overcome, and adaptive pulse width expansion is achieved, thereby improving the transient response speed of single-phase and multi-phase systems and reducing output voltage drop; 2. By comparing slowly changing error signals and rapidly changing sampled signals, the system can accurately determine the moment of transient occurrence with low latency and respond quickly, and the control logic is simple and effective; 3. In multiphase parallel applications, when a load transient occurs, the phase difference constraint is released by outputting an N-phase common charging signal, controlling the synchronous conduction of the N-phase power switches. This allows the multiphase inductors to charge the load simultaneously, reducing the equivalent inductance value and thus increasing the charging slope, thereby improving the load transient response speed of the multiphase DC-DC converter. Attached Figure Description

[0029] Figure 1 This is a block diagram of the principle of traditional current-type hysteresis control provided in related technologies; Figure 2 These are waveform diagrams of the transient processes of single-phase and two-phase parallel operation of traditional hysteresis control provided in related technologies. Figure (a) is a single-phase waveform diagram, and Figure (b) is a two-phase waveform diagram. Figure 3 This is a block diagram of the principle of multiphase parallel non-master-slave current-type hysteresis control provided in related technologies; Figure 4 This is a schematic block diagram of the transient response control circuit of the DC-DC converter provided in the embodiments of this application; Figure 5 This is a schematic diagram of the circuit structure of the ramp generation circuit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the circuit structure of another ramp generation circuit provided in the embodiments of this application; Figure 7 This is a waveform diagram of the transient regulation process under single-phase application provided in the embodiments of this application; Figure 8 This is a waveform diagram comparing the transient response of this application with that of traditional hysteresis control, provided in an embodiment of this application. Figure 9 This is a schematic block diagram of the transient response control circuit for a two-phase parallel application provided in the embodiments of this application; Figure 10 This is the internal logic circuit diagram of the phase-interleaved circuit in the two-phase parallel application provided in the embodiments of this application; Figure 11 This is a schematic block diagram of the transient response control circuit for N-phase parallel applications provided in the embodiments of this application; Figure 12 This is a waveform diagram of the transient adjustment process under two-phase parallel application provided in the embodiments of this application; Figure 13 This is a flowchart of the transient response control method for a DC-DC converter provided in the embodiments of this application.

[0030] Explanation of reference numerals in the attached figures: 11. Power unit; 111. Energy storage inductor; 112. Power switching transistor; 21. Error amplifier circuit; 22. Ramp generation circuit; 23. Transient enhancement circuit; 24. Hysteresis comparator circuit; 25. Drive circuit; 26. Phase-interleaved circuit. Detailed Implementation

[0031] The following combination Figures 1 to 13 This application will be described in further detail.

[0032] It should be noted that in the description of this application, PWM is the abbreviation for Pulse Width Modulation; the reference voltage is denoted as VREF, the output voltage as VOUT, and the output current as IOUT; the error signal output by the error amplifier circuit is denoted as VEA; the ramp signal output by the ramp generation circuit is denoted as VSF; the fast dynamic sampling signal received at the second input terminal of the transient enhancement circuit is denoted as VC; and the inductor current of each phase energy storage inductor is denoted as IL (in multi-phase circuits, they are denoted as IL1, IL2, etc.). "Transient" refers to the process in which the load current of the DC-DC converter changes abruptly (such as from a light load to a heavy load), during which the output voltage is prone to drop.

[0033] Before providing a detailed description of this application, let's first combine... Figures 1 to 3 A brief description of the relevant technologies is provided to facilitate a clearer understanding of the technical problem to be solved in this application.

[0034] Reference Figure 1 , Figure 1 A block diagram illustrating the principle of conventional current-type hysteresis control in related technologies is shown. This control scheme includes a power stage section 101, a negative feedback loop 102, and an inductor current ripple sampling network 103. The negative feedback loop 102 includes an amplifier EA, which converts the difference between the output voltage VOUT and the reference voltage VREF into an error signal VEA. Subsequently, a hysteresis comparator circuit compares the inductor current ripple signal with the error signal VEA to generate a PWM pulse with duty cycle information. The PWM signal is then sent back to the power stage section 101 after passing through the power transistor drive circuit to adjust its operating state. The current ripple information sampling network 103 uses an RC network connected across the inductor to sample the inductor current ripple and transmits it to the hysteresis comparator.

[0035] Reference Figure 2 , Figure 2 The transient waveform of a conventional hysteresis control is shown. Figure 2 (a) shows the transient waveform of single-phase traditional hysteresis control, from bottom to top: PWM signal, output voltage VOUT, output current IOUT, inductor current IL, ramp signal VSF and error signal interval VEA+ΔV; Figure 2(b) shows the transient waveforms of a two-phase parallel conventional hysteresis control, displayed from bottom to top as follows: the second-phase PWM signal PWM2, the first-phase PWM signal PWM1, the output voltage VOUT, half the output current IOUT, the first-phase inductor current IL1, the second-phase inductor current IL2, the output current IOUT, and the equivalent inductor current IL'. The horizontal axis of each waveform represents time t, and the vertical axis represents the voltage or current amplitude for the corresponding parameter. Compared to fixed-frequency control, hysteresis control is not limited by a specific switching frequency and can turn the power transistor on or off at any time, resulting in superior transient response. However, it is understandable that conventional hysteresis control has the following drawbacks: (Refer to...) Figure 2 (a) Near time t0, a transient change occurs in the load, causing the output voltage VOUT to drop and the error signal VEA to rise. The hysteresis comparator flips, slightly widening the PWM pulse width. Since the inductor magnetization slope is fixed, the inductor current IL rises slowly until time t1, when the inductor current IL catches up with the output current IOUT, and the transient process essentially ends. The time from t0 to t1 is the transient recovery time of traditional single-phase hysteresis control. During the transient, although the ramp signal VSF decreases rapidly due to the drop in output voltage VOUT and the error signal VEA rises, causing the hysteresis comparator to flip and achieving a certain degree of fast response, the fixed magnetization slope of the inductor means the rising slope of the ramp signal VSF remains unchanged. The pulse width only slightly widens due to the rise in VEA. Simply increasing the switching frequency cannot achieve the optimal transient solution, and the output voltage VOUT will still experience a significant drop. (Refer to...) Figure 2 (b) When the load transient occurs at time t0, the two-phase inductor currents IL1 and IL2 are limited by a fixed phase difference of 180° and cannot be charged synchronously. The rise of the equivalent inductor current IL' is limited, and the transient recovery is completed at time t1'. The recovery time is longer and the transient response is further limited.

[0036] Reference Figure 3 , Figure 3This diagram illustrates the principle block diagram of a traditional multiphase parallel current-type hysteresis control system without master or slave control. The scheme includes a two-phase power stage 104, an RC ripple sampling branch 105, and a hysteresis control loop 106. The hysteresis control loop 106 outputs PWMA and PWMB with a fixed phase difference through a phase-interleaving circuit. The scheme samples the current ripple of each phase through the RC ripple sampling branch 105 connected across the inductor, and transmits the sampled ripple information to the hysteresis comparator in the hysteresis control loop 106. The output of the hysteresis comparator is processed by the phase-interleaving circuit to generate a first-phase PWM signal PWMA and a second-phase PWM signal PWMB with equal phase differences, which are then fed into the power transistor drive circuit. This control method uses only one set of control logic to generate multiphase PWM signals (PWMA and PWMB) with equal phase differences, has a simple control loop, and features a master-slave characteristic. However, when multiple phases are connected in parallel, the power transistor control signal is constrained by a fixed phase difference of 360° / N, which prevents the conduction time extension of the power transistor control signal from being greater than T / N, thus limiting the improvement of the load transient response speed.

[0037] To address the aforementioned shortcomings, this application proposes a transient response control circuit and method. By adding a transient enhancement circuit, it is possible to achieve rapid transient response, adaptive adjustment of duty cycle information, and generate multi-phase common charging signals with almost no delay, thereby improving the equivalent inductor charging slope and enhancing the transient response speed of the load.

[0038] Reference Figure 4 This application discloses a transient response control circuit for a DC-DC converter, including a power conversion circuit and a transient response adjustment circuit.

[0039] The power conversion circuit is used to convert an input DC voltage into a stable DC voltage for the load. The power conversion circuit includes at least one phase power unit 11, each phase power unit 11 including an energy storage inductor 111 and a power switch 112.

[0040] In one embodiment, reference is made to Figure 4 Each phase power unit 11 includes a high-side power switch SAH (SAH) and a low-side power switch SAL (SAL) connected in series. One end of the energy storage inductor 111 (L1) is connected to the connection node of the high-side power switch SAH and the low-side power switch SAL, and the other end is used to connect to the load.

[0041] Understandably, this topology clarifies the basic operation of the power conversion circuit: when the high-side power switch SAH is on and the low-side power switch SAL is off, the input voltage charges the energy storage inductor 111, and the inductor current IL rises; when the high-side power switch SAH is off and the low-side power switch SAL is on, the energy storage inductor 111 freewheels and discharges. By controlling the on-state ratio (i.e., duty cycle) of the high-side and low-side power switches, stable regulation of the output voltage can be achieved, providing a control basis for the control circuit.

[0042] It should be noted that the power conversion circuit can be any power stage topology, such as Buck, Boost, etc. This embodiment is only an example and is not limited in this application.

[0043] In one embodiment, the transient response adjustment circuit includes an error amplifier circuit 21, a ramp generation circuit 22, a transient enhancement circuit 23, a hysteresis comparator circuit 24, and a drive circuit 25. Preferably, the error amplifier circuit 21 is implemented using an error amplifier, and the hysteresis comparator circuit 24 is preferably implemented using a hysteresis comparator.

[0044] Error amplifier circuit 21 receives the reference voltage VREF and the output voltage VOUT of the power conversion circuit, and outputs an error signal VEA. The error signal VEA reflects the deviation of the output voltage from the target value, and is a slowly changing signal after integration processing by error amplifier circuit 21.

[0045] The ramp generation circuit 22 is connected to the energy storage inductor 111 to obtain current ripple information and outputs a ramp signal VSF.

[0046] Reference Figure 4 In one embodiment, the ramp generation circuit 22 is connected in parallel across the energy storage inductor 111, including a capacitor C and a sampling branch connected in series. The connection point between the capacitor C and the sampling branch is the ramp signal output terminal. Since the ramp generation circuit 22 is directly connected across the energy storage inductor 111, it can accurately and quickly reflect the ripple state of the inductor current, providing a reliable ramp signal VSF for hysteresis control, and the circuit structure is simple.

[0047] It should be noted that the sampling branch can be a resistor divider sampling branch, that is, an RC network is used for sampling, as shown in the reference. Figure 5 In this case, the sampling branch is composed of voltage divider resistors; the sampling branch can also be a current source sampling branch, that is, a current source controlled by the switching node is used in conjunction with a capacitor for sampling, as shown in the reference. Figure 6 In this case, the sampling branch is composed of a current source controlled by the switching node. Both of the above sampling branches can obtain inductor current ripple information, which are equivalent substitutions and are both within the protection scope of this application.

[0048] Hysteresis comparator circuit 24 receives error signal VEA and ramp signal VSF and outputs PWM signal. Hysteresis comparator circuit 24 generates duty cycle information PWM by comparing inductor current ripple information (ramp signal VSF) with error signal VEA. Hysteresis comparator circuit 24 is not limited by fixed switching frequency and can flip at any time, providing a basis for fast response. Transient enhancement circuit 23 receives error signal VEA and adjusts the charging and discharging slope of ramp signal VSF when a transient occurs. Drive circuit 25 receives PWM signal and drives power switch 112.

[0049] Reference Figure 4 In one embodiment, the transient enhancement circuit 23 includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal receives an error signal VEA; the second input terminal receives a fast dynamic sampling signal VC; the transient enhancement circuit 23 is configured to: compare the error signal VEA with the fast dynamic sampling signal VC to obtain a difference; when the difference reaches a preset threshold, it determines that a load transient has occurred, and outputs a pull-down current signal to the ramp generation circuit 22 through the first output terminal to adjust the charging and discharging slope of the ramp signal VSF.

[0050] It is understandable that the error signal VEA is a slowly changing signal after being processed by the error amplifier circuit 21, while the fast dynamic sampling signal VC contains rapidly changing output voltage information, and the difference in their rates of change is significant. When a transient change occurs in the load, VC will change rapidly due to the drop in output voltage, thus quickly widening the gap with the slow VEA. The transient enhancement circuit 23 utilizes this rate difference, and by comparing VEA and VC, it can accurately determine the moment of transient occurrence with low delay, and convert the difference between the two into a pull-down current to adjust the charging and discharging slope of the ramp signal VSF, thereby achieving a fast transient response and adaptive adjustment of duty cycle information. The transient enhancement circuit 23 can be a circuit structure with comparison and current output functions, such as an operational amplifier, a dedicated comparator, a transconductance amplifier circuit, or other analog integrated circuit unit, which reduces the output voltage drop during the transient process. Preferably, the transient enhancement circuit 23 is implemented using an operational amplifier. Compared with traditional solutions, this application only needs to add one operational amplifier to achieve the above functions, without complex circuitry, and without increasing design complexity.

[0051] It should be noted that the fast dynamic sampling signal VC in this application is not limited to the output voltage VOUT resistor direct voltage divider sampling signal. As long as the sampling path does not pass through the error amplifier circuit integration stage and can instantaneously follow the fluctuation of the operating condition to form a significant difference in the rate of change with the slowly changing error signal VEA, it is acceptable. In other embodiments, VC can also be selected as the output capacitor differential sampling signal, the output total load current sampling signal, the energy storage inductor instantaneous current sampling signal, the switching node high-speed sampling signal, or the multi-channel sampling gating multiplexing signal.

[0052] Reference Figure 4 In one embodiment, the transient enhancement circuit 23 further includes a unidirectional isolation diode D1, disposed between the first output terminal and the ramp generation circuit 22, for limiting the unidirectional output pull-down current of the transient enhancement circuit 23. The unidirectional isolation diode D1 limits the transient enhancement circuit 23 to only output pull-down current in one direction, thereby controlling the single-phase output current and preventing interference signals under normal operating conditions from affecting the ramp generation circuit 22 in the reverse direction, ensuring the stability and unidirectionality of the control.

[0053] The implementation principle of a transient response control circuit for a DC-DC converter in this application embodiment is as follows: (Refer to...) Figure 7 , Figure 7 The transient regulation waveform in a single-phase application is shown. During a transient, the ramp signal VSF decreases due to the drop in output voltage VOUT, and its decrease is accelerated by the pull-down current of the transient enhancement circuit 23, until the hysteresis comparator circuit 24 rapidly flips the PWM signal, achieving a fast response. After the power switch 112 is turned on, since the inductor current IL has not yet charged to the output current IOUT, the output capacitor COUT continues to discharge, the output voltage VOUT continues to decrease, and the error signal VEA continues to rise. Therefore, the transient enhancement circuit 23 provides more pull-down current to slow down the charging (i.e., rising) of the ramp signal VSF, allowing the pulse width expansion to overcome the fixed charging slope limitation of the ramp signal VSF, thus charging the inductor current to the output current IOUT in one go. After several cycles of adjustment, the transient process is complete. (Refer to...) Figure 7 At time t2, a load transient is detected. The transient enhancement circuit 23 forces the ramp signal VSF to drop rapidly through a pull-down current. The hysteresis comparator circuit 24 quickly flips the PWM signal at time t3 to achieve a fast response. Subsequently, the transient enhancement circuit 23 provides more pull-down current to slow down the rise of the ramp signal VSF, causing the conduction pulse width of the power switch 112 to adaptively expand. This expanded pulse width corresponds to the time interval between t4 and t3 (i.e., t4-t3). The overall recovery time (t2-t4) from transient detection at t2 to recovery completion at t4 in this application is compared to... Figure 2 (a) shows a significantly shortened recovery time from t0 to t1.

[0054] Understandably, referring to Figure 8 , Figure 8The diagram shows a waveform comparison between the transient response of this application and that of conventional hysteresis control. The gray curve represents the transient response waveform of conventional hysteresis control, and the black curve represents the transient response waveform of this application. The output current curve is used to characterize the load transient transition process. Compared with conventional hysteresis control, this application achieves a fast response by accelerating the descent of the ramp signal VSF during the transient, forcing the hysteresis comparator circuit 24 to flip rapidly. It also overcomes the limitation of the conventional fixed magnetization slope by slowing down the rise of the ramp signal VSF, thereby achieving adaptive pulse width expansion and reducing the output voltage drop during the transient process.

[0055] It should be noted that the output of the transient enhancement circuit 23 can be used to adjust the charging and discharging slope of the ramp signal VSF as described above, or it can be used to adjust the adaptive hysteresis window of the hysteresis comparator circuit 24. The final adjustment effect of both is the same and both fall within the protection scope of this application.

[0056] Reference Figure 9 and Figure 11 The transient response control circuit described above in this application can be extended to multi-phase parallel applications. In one embodiment, the power conversion circuit includes N-phase parallel power units 11, where N is a positive integer greater than or equal to 2.

[0057] At this time, the transient enhancement circuit 23 also includes a second output terminal for outputting an N-phase common-charge signal. The transient response adjustment circuit also includes a phase-interleaving circuit 26. The phase-interleaving circuit 26 receives the PWM signal output from the hysteresis comparator circuit 24 and the N-phase common-charge signal, and is configured as follows: When the N-phase common charge signal is in the second level state, the PWM signal is processed by phase splitting, and N interleaved PWM signals with a preset phase difference (e.g., 360° / N) are output. When the N-phase common charging signal is in the first level state, the phase difference constraint between the N phases is released, and N synchronous PWM signals are output.

[0058] The drive circuit 25 responds to N interleaved PWM signals or N synchronous PWM signals to control the power switching transistors 112 of each phase power unit 11 to turn on or off.

[0059] Reference Figure 10In one embodiment, the internal logic circuit diagram of a two-phase parallel interleaved circuit 26 is shown. The interleaved circuit 26 internally includes a divide-by-two D flip-flop, an inverter, two OR gates, and two AND gates; the hysteresis comparator circuit 24 outputs the original PWM signal denoted as CMP_OUT, which is connected to the clock terminal CP of the D flip-flop, and the Q terminal output signal of the D flip-flop is denoted as A1. A1 is inverterized to generate signal A2; A1 and A2 are respectively used as one input of the two OR gates, and the other input of the two OR gates receives the common charge signal output by the transient enhancement circuit 23; the outputs of the two OR gates are respectively connected to the original signal CMP_OUT and then connected to the two AND gates, and the two AND gates finally output two-phase drive signals PWMA and PWMB. Under steady-state conditions, the common-charge signal is at the second level (low level). The two OR gates output only A1 and A2 respectively. After logical operation with CMP_OUT by AND gate, PWMA and PWMB interleaved pulses with a phase difference of 180° are generated. The two-phase power units 11 are turned on in a time-sharing manner to suppress steady-state output current ripple. When a load transient occurs, the transient enhancement circuit 23 outputs the first level (high level) common-charge signal and sends it to the two OR gates. The outputs of the two OR gates are forced high, bypassing the phase difference constraint generated by the divide-by-two D flip-flop. The two AND gates are turned on synchronously to output PWMA and PWMB. The two-phase power units 11 are turned on synchronously, and the energy storage inductors 111 of each phase charge the output load at the same time, improving the equivalent inductance charging slope and accelerating the transient recovery speed.

[0060] It should be noted that the phase-interleaving circuit 26 can also be composed of a counter, phase allocation logic, and a selector. Specifically, after receiving the PWM signal output by the hysteresis comparator circuit 24, the phase-interleaving circuit 26 uses its internal phase allocation logic to distribute the PWM signal to each phase output terminal according to a phase difference of 360° / N based on a preset number of phases N, thereby generating N interleaved PWM signals. When the N-phase common charge signal is in the first level state, the selector inside the phase-interleaving circuit 26 bypasses the above phase allocation logic, directly and simultaneously outputting the same PWM signal to all N phase output terminals, thereby generating N synchronous PWM signals. Thus, the phase-interleaving circuit 26 realizes the switching between interleaved output and synchronous output modes according to the level state of the N-phase common charge signal.

[0061] Understandably, in multi-phase parallel applications, the transient enhancement circuit 23 also compares the slowly changing error signal VEA with the rapidly changing fast dynamic sampling signal VC to quickly determine the moment of transient occurrence. Based on this, the transient enhancement circuit 23 not only outputs a pull-down current through its first output terminal to adaptively adjust the duty cycle, but also outputs a digital N-phase common-charge signal through its second output terminal to control the synchronous conduction of the N-phase power units 11. Preferably, the comparator stage output of the transient enhancement circuit 23, after passing through a buffer / shaping circuit, generates a digital N-phase common-charge signal at its second output terminal.

[0062] Reference Figure 12 , Figure 12 The transient regulation process waveform under two-phase parallel application is shown (the two-phase case is used as an example, and the same applies to multi-phase cases). Figure 12 The following parameters are displayed from bottom to top: the second-phase PWM signal PWMB, the first-phase PWM signal PWMA, the output voltage VOUT, half of the output current IOUT / 2, the first-phase inductor current IL1, the second-phase inductor current IL2, the equivalent inductor current (IL1+IL2), and the output current IOUT. During a transient, the ramp signal VSF is rapidly pulled down, enabling a fast response from the control loop. After the power switch 112 is turned on, the transient enhancement circuit 23 provides more pull-down current to slow down the charging of the ramp signal VSF, and the pulse width expansion overcomes the limitation of the fixed charging slope. Simultaneously, the transient enhancement circuit 23 outputs an N-phase common-charge signal at the first level. Based on this, the phase-interleaving circuit 26 outputs N synchronous PWM signals, meaning that the first-phase PWM signal PWMA and the second-phase PWM signal PWMB switch from interleaved phases before the transient to near-synchronous alignment (as shown in the t5-t6 interval). This synchronously turns on all N-phase power switches 112 during the transient, allowing each phase energy storage inductor 111 to charge the load simultaneously. Therefore, the equivalent inductor current (IL1+IL2) Figure 12 The charging slope of the inductor current (IL1+IL2) is increased to N times the charging slope of the single-phase inductor current IL1 or IL2 (twice for two phases), accelerating the charging process of the inductor current. After several cycles of adjustment, the transient process is completed. When the transient disappears, the N-phase common charging signal switches back to the second level state, and the first-phase PWM signal PWMA and the second-phase PWM signal PWMB return to an interleaved state with a 180° phase difference.

[0063] Understandably, this application overcomes the limitation of the 360° / N fixed phase difference on the power transistor conduction time in traditional multiphase schemes. When a transient load change occurs, by releasing the phase difference constraint, the N-phase inductor currents simultaneously charge the load, achieving a power transistor conduction time extension greater than T / N. The time for the equivalent inductor current to continuously charge the output load within a single cycle is significantly extended, thereby improving the load transient response speed of the multiphase DC-DC converter.

[0064] Reference Figure 13 This application also provides a transient response control method for a DC-DC converter, applied to the transient response control circuit in any of the above embodiments, comprising the following steps: Step S1: Error amplifier circuit 21 receives reference voltage VREF and output voltage VOUT of power conversion circuit, generates and outputs error signal VEA; ramp generation circuit 22 obtains current ripple information of energy storage inductor 111, generates and outputs ramp signal VSF; hysteresis comparator circuit 24 receives error signal VEA and ramp signal VSF, and continuously generates PWM signal.

[0065] Step S2: When the transient enhancement circuit 23 determines that a load transient has occurred, it adjusts the charging and discharging slope of the ramp signal VSF.

[0066] In one embodiment, step S2 specifically includes: the transient enhancement circuit 23 receives the fast dynamic sampling signal VC and continuously monitors the difference between the error signal VEA and the fast dynamic sampling signal VC; when the difference reaches a preset threshold, it is determined that a load transient has occurred, and the transient enhancement circuit 23 outputs a pull-down current signal to the ramp generation circuit 22 to change the charging and discharging slope of the ramp signal VSF, thereby adjusting the duty cycle of the PWM signal; when the difference is lower than the preset threshold, it is determined that the load transient has disappeared, and the transient enhancement circuit 23 stops outputting the pull-down current signal.

[0067] Understandably, by comparing the slowly changing error signal VEA with the rapidly changing fast dynamic sampling signal VC and outputting the pull-down current accordingly, the occurrence and disappearance of transients can be accurately determined, and the PWM duty cycle can be adaptively adjusted. The control logic is simple and effective.

[0068] Step S3: The drive circuit 25 receives the PWM signal and drives the power switch 112 in the power conversion circuit.

[0069] Furthermore, when the power conversion circuit includes N-phase parallel power units 11, and the transient response adjustment circuit includes a phase-interleaving circuit 26 (N is a positive integer greater than or equal to 2), the method also includes control of multi-phase common charging, specifically: When a load transient occurs, in step S2, the transient enhancement circuit 23 outputs a pull-down current signal to the ramp generation circuit 22, and also outputs an N-phase common charging signal at the first level through the second output terminal. The phase-interleaving circuit 26 receives the PWM signal output by the hysteresis comparator circuit 24 and the N-phase common charging signal, and outputs N synchronous PWM signals. In step S3, the drive circuit 25 receives the N synchronous PWM signals and drives the power switching transistors 112 of all N-phase power units 11 to conduct synchronously, so that each energy storage inductor 111 charges the load simultaneously.

[0070] When the load transient disappears, in step S2, the transient enhancement circuit 23 switches the N-phase common charging signal to the second level state, and the phase-splitting circuit 26 performs phase-splitting processing on the PWM signal output by the hysteresis comparator circuit 24, and outputs N interleaved PWM signals with a preset phase difference; in step S3, the drive circuit 25 receives the N interleaved PWM signals and controls the power switch transistors 112 of each phase power unit 11 to resume interleaved conduction.

[0071] It should be noted that the aforementioned first level state and second level state are two opposite logic level states. For example, the first level state may correspond to the digital signal "1" (high level), and the second level state may correspond to the digital signal "0" (low level); or, the first level state may correspond to the digital signal "0", and the second level state may correspond to the digital signal "1"; alternatively, the first level state may be characterized by the output of an effective level signal by the transient enhancement circuit 23, and the second level state may be characterized by the transient enhancement circuit 23 not outputting a signal. The specific values ​​of the above level states are only illustrative examples, and are sufficient to distinguish between the common-charge mode and the interleaved mode. This application does not impose any limitations on this.

[0072] Understandably, in a multiphase system, by issuing an N-phase common-charge signal in the first level state to release the phase difference constraint, multiphase synchronous conduction and charging are achieved, which improves the transient response speed of the multiphase system. After the transient disappears, by switching the N-phase common-charge signal back to the second level state, the phases resume staggered conduction, thereby ensuring the ripple suppression and other performance characteristics in steady state.

[0073] In one embodiment, reference is made to Figure 13 The method also includes: Step S4: Jump to step S2 for continuous loop monitoring to respond to load transients in real time.

[0074] Understandably, by jumping to step S4 to form closed-loop control, the corresponding transient response adjustment circuit continuously monitors the load transients, ensuring that the system can return to normal interleaved operation after each transient disappears, and is ready to respond to new transients at any time, thereby maintaining the continuous stability of the output voltage.

[0075] It should be noted that the control method proposed in this application can be applied not only to single-phase DC-DC converters, but also to two-phase or even multi-phase parallel converters, demonstrating good scalability. The level states, phase difference values, and preset thresholds listed in the above embodiments are merely illustrative examples, and those skilled in the art can make equivalent adjustments according to actual application requirements.

[0076] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A transient response control circuit for a DC-DC converter, characterized in that, include: A power conversion circuit for converting an input DC voltage into a stable DC voltage for a load, wherein the power conversion circuit includes at least one phase power unit (11), each phase power unit (11) including an energy storage inductor (111) and a power switch (112). The transient response adjustment circuit includes an error amplifier circuit (21), a ramp generation circuit (22), a transient enhancement circuit (23), a hysteresis comparator circuit (24), and a drive circuit (25). The error amplifier circuit (21) receives the reference voltage and the output voltage of the power conversion circuit and outputs an error signal. The ramp generation circuit (22) is connected to the energy storage inductor (111) to obtain current ripple information and output a ramp signal. The transient enhancement circuit (23) receives the error signal and adjusts the charging and discharging slope of the ramp signal when a transient occurs. The hysteresis comparator circuit (24) receives the error signal and the ramp signal and outputs a PWM signal. The drive circuit (25) receives the PWM signal and drives the power switch (112).

2. The transient response control circuit for a DC-DC converter according to claim 1, characterized in that, The ramp generation circuit (22) is connected in parallel across the energy storage inductor (111) and includes a capacitor and a sampling branch connected in series. The connection point of the capacitor and the sampling branch is the ramp signal output terminal. The sampling branch is a resistor voltage divider sampling branch or a current source sampling branch.

3. The transient response control circuit for the DC-DC converter according to claim 1, characterized in that, Each phase of the power unit (11) includes a high-side power switch and a low-side power switch connected in series. One end of the energy storage inductor (111) is connected to the connection node of the high-side power switch and the low-side power switch, and the other end is used to connect to the load.

4. The transient response control circuit for the DC-DC converter according to claim 1, characterized in that, The transient enhancement circuit (23) includes a first input terminal, a second input terminal, and a first output terminal; the first input terminal receives the error signal; the second input terminal receives the fast dynamic sampling signal; the transient enhancement circuit (23) is configured to: compare the error signal with the fast dynamic sampling signal to obtain a difference value; when the difference value reaches a preset threshold, determine that a load transient has occurred; and output a pull-down current signal to the ramp generation circuit (22) through the first output terminal to adjust the charging and discharging slope of the ramp signal.

5. The transient response control circuit for a DC-DC converter according to claim 4, characterized in that, The transient enhancement circuit (23) also includes a unidirectional isolation diode D1, which is disposed between the first output terminal and the ramp generation circuit (22) to limit the unidirectional output pull-down current of the transient enhancement circuit (23).

6. The transient response control circuit for a DC-DC converter according to claim 4, characterized in that, The power conversion circuit includes N parallel power units (11), where N is a positive integer greater than or equal to 2; The transient enhancement circuit (23) also includes a second output terminal, which outputs an N-phase common charging signal; the transient response adjustment circuit also includes a phase-interleaving circuit (26), which receives the PWM signal output by the hysteresis comparator circuit (24) and the N-phase common charging signal. The phase-interleaving circuit (26) is configured to: when the N-phase common charging signal is in the second level state, perform phase-interleaving processing on the PWM signal and output N interleaved PWM signals with a preset phase difference; when the N-phase common charging signal is in the first level state, release the phase difference constraint between the N phases and output N synchronous PWM signals. The drive circuit (25) responds to the N-channel interleaved PWM signal or the N-channel synchronous PWM signal to control the power switching transistors (112) of each phase power unit (11) to be turned on or off.

7. A transient response control method for a DC-DC converter, applied to the transient response control circuit as described in claim 1, characterized in that, Including the following steps: S1, Error amplifier circuit (21) receives the reference voltage and the output voltage of the power conversion circuit, generates and outputs the error signal; ramp generation circuit (22) obtains the current ripple information of the energy storage inductor (111), generates and outputs the ramp signal; hysteresis comparator circuit (24) receives the error signal and the ramp signal, and continuously generates the PWM signal; S2, Transient enhancement circuit (23) adjusts the charging and discharging slope of the ramp signal when it is determined that a load transient has occurred; S3, the drive circuit (25) receives the PWM signal and drives the power switch (112) in the power conversion circuit.

8. The transient response control method for a DC-DC converter according to claim 7, characterized in that, Step S2 specifically includes: The transient enhancement circuit (23) receives the fast dynamic sampling signal and continuously monitors the difference between the error signal and the fast dynamic sampling signal. When the difference reaches the preset threshold, it is determined that the load transient has occurred. The transient enhancement circuit (23) outputs a pull-down current signal to the ramp generation circuit (22) to change the ramp signal charging and discharging slope, thereby adjusting the duty cycle of the PWM signal. When the difference is lower than the preset threshold, it is determined that the load transient has disappeared, and the transient enhancement circuit (23) stops outputting the pull-down current signal.

9. The transient response control method for a DC-DC converter according to claim 8, characterized in that, When the power conversion circuit includes N-phase parallel power units (11) and the transient response adjustment circuit includes a phase-interleaved circuit (26), where N is a positive integer greater than or equal to 2, the following steps are also included: When a load transient occurs, in step S2, the transient enhancement circuit (23) simultaneously outputs an N-phase common charging signal at the first level. It receives the PWM signal and the N-phase common charging signal output by the hysteresis comparator circuit (24) through the phase-splitting interleaving circuit (26) and outputs N synchronous PWM signals. In step S3, the drive circuit (25) receives the N synchronous PWM signals and drives the power switching transistors (112) of all N-phase power units (11) to conduct synchronously, so that each energy storage inductor (111) charges the load simultaneously. When a load transient disappears, in step S2, the transient enhancement circuit (23) switches the N-phase common charging signal to the second level. It performs phase-splitting processing on the PWM signal output by the hysteresis comparator circuit (24) through the phase-splitting interleaving circuit (26) and outputs N interleaved PWM signals with a preset phase difference. In step S3, the drive circuit (25) receives the N interleaved PWM signals and restores the interleaved conduction of each phase power unit (11).

10. The transient response control method for a DC-DC converter according to claim 9, characterized in that, It also includes the following steps: S4. Jump to step S2 for continuous loop monitoring to respond to load transients in real time.

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