Voltage reduction circuit with short-circuit delay and voltage reduction device

Abstract

The embodiment of the present application provides a step-down circuit with short-circuit delay and a step-down device. The circuit comprises an input interface for connecting a power supply; an output interface for connecting a load; a first overcurrent detection module connected with the input interface, for collecting a first electric signal of the input interface, and generating a hiccup control signal according to the first electric signal, to control the step-down circuit to work in a hiccup mode; a second overcurrent detection module connected with the output interface and the first overcurrent detection module, for collecting a second electric signal of the output interface, and triggering a hiccup delay time according to the second electric signal and the hiccup control signal, and generating a control signal within the hiccup delay time; and the control signal is used to drive a power module. The technical scheme provided by the embodiment solves the problem that the output power of the step-down circuit is low in the hiccup mode, so that the step-down circuit is locked in the hiccup mode and cannot exit, and needs to be restarted manually.

Description

Technical Field

[0001] The present invention relates to the field of control technology, and in particular to a step-down circuit and a step-down device with short-circuit delay. Background Technology

[0002] When existing portable / handheld devices experience a persistent short circuit or severe overload, the system in hiccup mode shuts down and periodically restarts (e.g., every few hundred milliseconds). If the fault persists, it shuts down again and repeats the process. Compared to traditional systems that completely shut down and lock, requiring manual intervention to restart, hiccup mode provides an opportunity for the system to automatically recover from temporary faults. However, in applications driving capacitive loads such as flashlights, the system remains under heavy load after a high-power discharge. In this case, the system's output power in hiccup mode is extremely low, preventing it from properly charging the capacitive load and locking it in hiccup mode, requiring a manual restart. Summary of the Invention

[0003] This invention provides a step-down circuit and a step-down device with short-circuit delay to solve the problem that existing step-down circuits with hiccup mode have extremely low output power in hiccup mode, the system is locked in hiccup mode and cannot exit, requiring manual restart.

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: This invention provides a step-down circuit with short-circuit delay, comprising: Input interface, used to connect the power supply; Output interface for connecting a load, including a capacitive load; A power module is connected between the input interface and the output interface; The first overcurrent detection module is connected to the input interface and is used to collect the first electrical signal of the input interface and generate a hiccup control signal based on the first electrical signal to control the step-down circuit to work in hiccup mode. The second overcurrent detection module is connected to the output interface and the first overcurrent detection module. It is used to collect the second electrical signal of the output interface, and trigger a hiccup delay time according to the second electrical signal and the hiccup control signal, and generate a control signal during the hiccup delay time. The control signal is used to drive the power module.

[0005] Optionally, the first overcurrent detection module includes: A first sampling unit is connected to the input interface. The first sampling unit is used to acquire a first current signal from the input interface and convert it into a first voltage signal. A first comparison unit is connected to the first sampling unit. The first comparison unit is used to compare the first voltage signal with the first reference signal to generate a first comparison signal. The first delay unit is connected to the first comparison unit and the second overcurrent detection module. The first delay unit is used to implement the hiccup mode according to the first comparison signal and the output signal of the second overcurrent detection module, or to output a square wave signal during the hiccup delay time.

[0006] Optionally, the first sampling unit includes: A constant current source, the first end of which is connected to the input interface; A first switching transistor, the first end of which is connected to the second end of the constant current source; the control end of the first switching transistor is connected to the control end of the power module. A first resistor, the first end of which is connected to the second end of the first switching transistor and the input end of the first comparison unit, and the second end of which is connected to the ground terminal.

[0007] Optionally, the first delay unit includes: A first timer, the input of which is connected to the output of the second overcurrent detection module; A second timer, wherein the first input terminal of the second timer is connected to the output terminal of the first timer; The NOR gate has its first input connected to the output of the first comparison unit, and its second input connected to the output of the second timer and the input of the logic unit of the second overcurrent detection module.

[0008] Optionally, the second overcurrent detection module includes: The second sampling unit is connected to the output interface and is used to acquire the second voltage signal of the output interface; The second comparison unit is connected to the second sampling unit. The second comparison unit is used to compare the second voltage signal with the second reference signal to generate a second comparison signal. A delay unit is connected to the output of the second comparison unit. The delay unit is used to control the delay-triggered hiccup mode and generate a delay signal. The logic unit is connected to the output terminal of the delay unit and the output terminal of the second timer of the first overcurrent detection module. The output terminal of the logic unit is connected to the input terminal of the power module and the first timer of the first overcurrent detection module. The output terminal of the logic unit is also connected to the control terminal of the first switching transistor of the first overcurrent detection module.

[0009] Optionally, the second sampling unit includes: The second resistor and the third resistor are connected, with the first end of the second resistor connected to the output interface, the second end of the second resistor connected to the first end of the third resistor and the input terminal of the second comparison unit, and the second end of the third resistor grounded.

[0010] Optionally, the delay unit includes: A third timer, the input of which is connected to the output of the second comparison unit; An adder, wherein the clock input terminal of the adder is connected to the output terminal of the third timer, the first input terminal of the adder is connected to the output terminal of the second comparison unit, and the second input terminal of the adder is used to input the battery voltage; The logic unit includes an AND gate, the first input of which is connected to the output of the adder, the second input of which is connected to the output of the second timer of the first overcurrent detection module, and the output of which is connected to the power module.

[0011] Optionally, the power module includes: A first power transistor and a second power transistor, wherein the first terminal of the first power transistor is connected to the input interface, the second terminal of the first power transistor is connected to the first terminal of the second power transistor, the second terminal of the second power transistor is connected to the ground terminal, and the control terminals of the first power transistor and the second power transistor are both connected to the second overcurrent detection module. The first power transistor and the second power transistor are used to turn on or off according to the control signal output by the second overcurrent detection module.

[0012] Optionally, the power module further includes: First inductor, first capacitor, and load; The first inductor is connected between the second terminal of the first power transistor and the output interface; The first capacitor is connected between the output interface and the ground terminal, and the load is connected between the output interface and the ground terminal.

[0013] Secondly, this embodiment provides a step-down device, including: a step-down circuit with short-circuit delay provided in any of the first aspects.

[0014] The buck circuit with short-circuit delay provided in this embodiment of the invention, when the hiccup mode is triggered, the first overcurrent detection module detects the first electrical signal of the input interface. When the first electrical signal indicates that the load is short-circuited or severely overloaded, a hiccup control signal is generated according to the first electrical signal to control the buck circuit not to discharge to the load within a set first time. Together with the second overcurrent detection module, the buck circuit is controlled to discharge to the load within a set second time, and this process is repeated to trigger the buck circuit to work in hiccup mode. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a step-down circuit with short-circuit delay provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another step-down circuit with short-circuit delay provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another step-down circuit with short-circuit delay provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another step-down circuit with short-circuit delay provided in an embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] Based on the above-mentioned technical problems, this embodiment proposes the following solutions: Figure 1 This is a schematic diagram of a step-down circuit with short-circuit delay provided in an embodiment of the present invention. See also... Figure 1 This invention provides a step-down circuit with short-circuit delay, comprising: an input interface BAT for connecting to a power supply; an output interface VOUT for connecting to a load, the load including a capacitive load; a power module 10 connected between the input interface BAT and the output interface VOUT; a first overcurrent detection module 1 connected to the input interface BAT for acquiring a first electrical signal from the input interface BAT and generating a hiccup control signal based on the first electrical signal to control the step-down circuit to operate in hiccup mode; a second overcurrent detection module 2 connected to the output interface VOUT and the first overcurrent detection module 1 for acquiring a second electrical signal from the output interface VOUT and triggering a hiccup delay time based on the second electrical signal and the hiccup control signal, and generating a control signal during the hiccup delay time; the control signal is used to drive the power module.

[0020] Specifically, the input interface BAT is used to connect a power source. The power source can be a battery that provides DC voltage. The power module 10 is connected between the input interface BAT and the output interface VOUT. The power module 10 is used to convert DC to DC based on control signals.

[0021] The first overcurrent detection module 1 is used to detect the first electrical signal of the input interface BAT. When the first electrical signal indicates that the load is short-circuited or severely overloaded, a hiccup control signal is generated according to the first electrical signal to control the buck circuit not to discharge the load within a set first time period, and to discharge the load within a set second time period, and repeat this process to trigger the buck circuit to work in hiccup mode.

[0022] The second overcurrent detection module 2 is used to detect the second electrical signal of the output interface VOUT. When the second electrical signal indicates a short circuit or severe overload of the capacitive load in the step-down circuit, a hiccup is initiated after a third time delay based on the second electrical signal. During the hiccup delay time, the second overcurrent detection module 2 outputs a control signal. For example, the control signal can be a square wave signal. The control signal is used to drive the power module.

[0023] This configuration ensures that the system will not be under heavy load after a high-power discharge of a capacitive load, thus effectively preventing the step-down circuit from being locked in hiccup mode and unable to exit when connected to an external capacitive load.

[0024] The buck circuit with short-circuit delay provided in this embodiment allows the second overcurrent detection module 2 to control the power module 10 to work normally when the hiccup delay is triggered. The buck circuit outputs the maximum current, enabling the system to charge the capacitive load under severe overload and discharge to ground when the capacitive load is short-circuited. After the hiccup delay ends, it enters the hiccup mode.

[0025] When the buck circuit with short-circuit delay provided in this embodiment is triggered in hiccup mode, the first overcurrent detection module 1 can detect the first electrical signal of the input interface BAT. When the first electrical signal indicates that the load is short-circuited or severely overloaded, a hiccup control signal is generated according to the first electrical signal to control the buck circuit not to discharge the load within a set first time. Together with the second overcurrent detection module 2, the buck circuit is controlled to discharge to the load within a set second time, and this process is repeated to trigger the buck circuit to work in hiccup mode.

[0026] Optional, Figure 2 This is a schematic diagram of another step-down circuit with short-circuit delay provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 2 The first overcurrent detection module 1 may include: a first sampling unit 11 connected to the input interface BAT, the first sampling unit 11 being used to acquire a first current signal from the input interface BAT and convert it into a first voltage signal; a first comparison unit 12 connected to the first sampling unit 11, the first comparison unit 12 being used to compare the first voltage signal with a first reference signal to generate a first comparison signal; and a first delay unit 13 connected to the first comparison unit 12 and the second overcurrent detection module 2, the first delay unit 13 being used to implement a hiccup mode based on the first comparison signal and the output signal of the second overcurrent detection module 2, or to output a square wave signal during the hiccup delay time.

[0027] Specifically, under load short-circuit or severe overload conditions, the first sampling unit 11 can acquire the first electrical signal of the input interface BAT. The first comparison unit 12 is used to compare the first electrical signal with the first reference signal, and generate a first comparison signal based on the comparison result. For example, the first comparison signal is generated when the first electrical signal is greater than the first reference signal. The first delay unit 13 is connected to the AND gate of the logic units of the first comparison unit 12 and the second overcurrent detection module 2. The first delay unit 13 is used to trigger a hiccup mode based on the first comparison signal and the output signal of the second overcurrent detection module 2; or to output a square wave signal during the hiccup delay time to control the power module 10 to charge the capacitive load with the maximum current output.

[0028] Optionally, based on the above embodiments, see also... Figure 2 The first sampling unit 11 includes: a constant current source, the first end of which is connected to the input interface BAT; a first switch P1, the first end of which is connected to the second end of the constant current source; a control terminal of the first switch P1 connected to the control terminal of the power module 10; and a first resistor R1, the first end of which is connected to the second end of the first switch P1 and the input terminal of the first comparison unit 12, and the second end of the first resistor R1 connected to the ground terminal.

[0029] Specifically, when the first switch P1 is turned on, the voltage generated by the inductor sampling current I0 through resistor R1 serves as the first electrical signal. The constant current source can be the inductor sampling current I0.

[0030] Optionally, based on the above embodiments, see also... Figure 2 The first delay unit 13 includes: a first timer 131, a second timer 133, and a NOR gate 134. The input terminal of the first timer 131 is connected to the output terminal of the second overcurrent detection module 2; the first input terminal of the second timer 133 is connected to the output terminal of the first timer 131; the NOR gate 134 has its first input terminal connected to the output terminal of the first comparison unit 12, and its second input terminal connected to the output terminal of the second timer 133 and the input terminal of the logic unit 24 of the second overcurrent detection module 2.

[0031] Specifically, the first comparison unit 12 includes an overcurrent comparator OCP. The overcurrent comparator OCP compares the acquired first electrical signal with the first reference voltage VREF1 to generate a fundamental frequency oscillation signal, which is then fed into the second timer 133. The second timer 133 outputs high after a set second time period, during which the power module 10 discharges to the load. After the output of the second timer 133 flips high, the signal output from the AND gate of the second overcurrent detection module 2 controls the first timer 131 to start. The first timer 131 outputs low after a set first time period, controlling the output of the second timer 133 to flip low. The signal output from the AND gate of the second overcurrent detection module 2 controls the first timer 131 to turn off. When the first timer 131 outputs high, the second timer 133 operates. The second timer 133 restarts its timing, and this process repeats to achieve the hiccup mode of the buck converter circuit.

[0032] Optional, Figure 3 This is a schematic diagram of another buck circuit with short-circuit delay provided by an embodiment of the present invention. Based on the above embodiments, see... Figure 3 The second overcurrent detection module 2 may include: a second sampling unit 21 connected to the output interface VOUT, used to acquire the second voltage signal of the output interface VOUT; a second comparison unit 22 connected to the second sampling unit 21, used to compare the second voltage signal with a second reference signal to generate a second comparison signal; a delay unit 23 connected to the output terminal of the second comparison unit 22, used to control the delay triggering hiccup mode and generate a delay signal; and a logic unit 24 connected to the output terminal of the delay unit 23 and the output terminal of the second timer 133 of the first overcurrent detection module 1, the output terminal of the logic unit 24 being connected to the input terminal of the power module 10 and the first timer 131 of the first overcurrent detection module 1, and the output terminal of the logic unit 24 also being connected to the control terminal of the first switching transistor P1 of the first overcurrent detection module 1.

[0033] Specifically, the second sampling unit 21 is used to acquire the second voltage signal of the output interface VOUT. The second comparison unit 22 is connected to the second sampling unit 21. The second comparison unit 22 is used to compare the second voltage signal with the second reference signal to generate a second comparison signal. For example, the second comparison signal can be generated when the second voltage signal is greater than or equal to the second reference signal.

[0034] The delay unit 23 is connected to the output of the second comparison unit 22. The delay unit 23 provides a preset delay time, controls the delay to trigger the hiccup mode, and generates a delay signal. The logic unit 24 generates a control signal based on the level signal output from the output of the delay unit 23 and the level signal output from the output of the second timer 133 of the first overcurrent detection module 1. The control signal controls the power module 10 and is transmitted to the input of the first timer 131 of the first overcurrent detection module 1. It controls the first overcurrent detection module 1 to output a square wave signal during the hiccup delay time and transmits it to the control terminal of the first switching transistor P1. It controls the inductor sampling current I0 of the first overcurrent detection module 1 during the hiccup delay time. This configuration facilitates the second overcurrent detection module 2 and the first overcurrent detection module 1 to jointly control the power module 10 to charge the capacitive load with the maximum current output during the hiccup delay time. This configuration ensures that the system will not be in a heavy load state after the capacitive load discharges at high power, thereby effectively preventing the buck circuit from locking into the hiccup mode and being unable to exit.

[0035] Optionally, based on the above embodiments, see also... Figure 3 The second sampling unit 21 may include a second resistor R2 and a third resistor R3. The first end of the second resistor R2 is connected to the output interface VOUT, the second end of the second resistor R2 is connected to the first end of the third resistor R3 and the input end of the second comparison unit 22, and the second end of the third resistor R3 is grounded.

[0036] Specifically, the second resistor R2 and the third resistor R3 act as a voltage divider. The second comparison unit 22 may include a short-circuit detection comparator SP.

[0037] Optionally, based on the above embodiments, see also... Figure 3 The delay unit 23 includes: a third timer 231, the input of which is connected to the output of the second comparison unit 22; an adder 232, the clock input of which is connected to the output of the third timer 231, the first input of which is connected to the output of the second comparison unit 22, and the second input of which is used to input the battery voltage; the logic unit 24 includes an AND gate 241, the first input of which is connected to the output of the adder 232, the second input of which is connected to the output of the second timer 133 of the first overcurrent detection module 1, the output of which is connected to the power module 10, and the output of which is also connected to the input of the first timer 131 of the first overcurrent detection module 1 and the first switching transistor P1.

[0038] Specifically, during the hiccup delay trigger: Under capacitive load short-circuit or severe overload conditions, the output interface VOUT of the step-down circuit is low. The output of the short-circuit detection comparator SP is high, and the third timer 231 and adder 232 are started. The third timer 231 outputs high after a set third time, and the adder 232 outputs high. This set third time is the hiccup delay time. During the hiccup delay time, the output of the third timer 231 is low, the output of the adder 232 is low, the output of the AND gate 241 is low, the first timer 131 is turned off, and the output of the first timer 131 is low. The second timer 133 operates and outputs a square wave signal during the hiccup time. At the same time, the AND gate 241 controls the power module 10 to operate normally, and the power module 10 charges the capacitive load with maximum current output.

[0039] When the hiccup mode is triggered: Adder 232 outputs high, and the inductor sampling current I0 generates a voltage through the first resistor R1. This voltage is compared with the first reference voltage VREF1 by the overcurrent comparator OCP to generate a fundamental frequency oscillation signal. The fundamental frequency oscillation signal enters the second timer 133. The second timer 133 outputs high after a second time setting. AND gate 241 outputs high, and the first timer 131 starts. The first timer 131 outputs high after a first time setting. The second timer 133 resets and outputs low. Then, AND gate 241 outputs low, the first timer 131 is turned off, and the second timer 133 starts. NOR gate 134 outputs the inverted signal of the overcurrent comparator OCP. The second timer 133 outputs high after a second time setting. The first timer 131 is started, and the second timer 133 is turned off. This process is repeated to realize the hiccup mode of the system.

[0040] Optional, Figure 4 This is a schematic diagram of another buck circuit with short-circuit delay provided by an embodiment of the present invention. Based on the above embodiments, see... Figure 4 The power module 10 includes a first power transistor P2 and a second power transistor N1. The first terminal of the first power transistor P2 is connected to the input interface BAT, the second terminal of the first power transistor P2 is connected to the first terminal of the second power transistor N1, the second terminal of the second power transistor N1 is connected to the ground terminal, and the control terminals of the first power transistor P2 and the second power transistor N1 are both connected to the second overcurrent detection module 2. The first power transistor P2 and the second power transistor N1 are used to turn on or off according to the control signal output by the second overcurrent detection module 2.

[0041] Specifically, the first power transistor P2 is responsible for connecting the power supply to store energy in the inductor. After the first power transistor P2 is turned off, the second power transistor N1 turns on to provide a freewheeling circuit for the inductor. The first power transistor P2 and the second power transistor N1 switch alternately to achieve synchronous Buck converter.

[0042] Optionally, based on the above embodiments, see also... Figure 4 The power module 10 further includes: a first inductor L, a first capacitor C, and a load R. LOAD The first inductor L is connected between the second terminal of the first power transistor P2 and the output interface VOUT; the first capacitor C is connected between the output interface VOUT and the ground terminal; and the load is connected between the output interface VOUT and the ground terminal.

[0043] Specifically, the first inductor L is responsible for smoothing the current, and the first capacitor C is responsible for smoothing the voltage. The first inductor L and the first capacitor C work together to convert high-frequency square wave energy into stable DC power to supply the load R. LOAD .

[0044] Based on the same inventive concept, this embodiment provides a step-down device. The step-down device provided in this embodiment includes the step-down circuit with short-circuit delay provided in any of the above embodiments, and has the beneficial effects of the step-down circuit with short-circuit delay provided in any of the above embodiments, which will not be described again here.

[0045] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A step-down circuit with short-circuit delay, characterized in that, include: Input interface, used to connect to the power supply; Output interface for connecting a load, including a capacitive load; A power module is connected between the input interface and the output interface; The first overcurrent detection module is connected to the input interface and is used to collect the first electrical signal of the input interface and generate a hiccup control signal based on the first electrical signal to control the step-down circuit to work in hiccup mode. The second overcurrent detection module is connected to the output interface and the first overcurrent detection module. It is used to collect the second electrical signal of the output interface, and trigger a hiccup delay time according to the second electrical signal and the hiccup control signal, and generate a control signal during the hiccup delay time. The control signal is used to drive the power module.

2. The step-down circuit according to claim 1, characterized in that, The first overcurrent detection module includes: A first sampling unit is connected to the input interface. The first sampling unit is used to acquire a first current signal from the input interface and convert it into a first voltage signal. A first comparison unit is connected to the first sampling unit. The first comparison unit is used to compare the first voltage signal with the first reference signal to generate a first comparison signal. The first delay unit is connected to the first comparison unit and the second overcurrent detection module. The first delay unit is used to implement the hiccup mode according to the first comparison signal and the output signal of the second overcurrent detection module, or to output a square wave signal during the hiccup delay time.

3. The step-down circuit according to claim 2, characterized in that, The first sampling unit includes: A constant current source, the first end of which is connected to the input interface; A first switching transistor, the first end of which is connected to the second end of the constant current source; the control end of the first switching transistor is connected to the control end of the power module. A first resistor, the first end of which is connected to the second end of the first switching transistor and the input end of the first comparison unit, and the second end of which is connected to the ground terminal.

4. The step-down circuit according to claim 3, characterized in that, The first delay unit includes: A first timer, the input of which is connected to the output of the second overcurrent detection module; A second timer, wherein the first input terminal of the second timer is connected to the output terminal of the first timer; The NOR gate has its first input connected to the output of the first comparison unit, and its second input connected to the output of the second timer and the input of the logic unit of the second overcurrent detection module.

5. The step-down circuit according to any one of claims 1 to 4, characterized in that, The second overcurrent detection module includes: The second sampling unit is connected to the output interface and is used to acquire the second voltage signal of the output interface; The second comparison unit is connected to the second sampling unit. The second comparison unit is used to compare the second voltage signal with the second reference signal to generate a second comparison signal. A delay unit is connected to the output of the second comparison unit. The delay unit is used to control the delay-triggered hiccup mode and generate a delay signal. The logic unit is connected to the output terminal of the delay unit and the output terminal of the second timer of the first overcurrent detection module. The output terminal of the logic unit is connected to the input terminal of the power module and the first timer of the first overcurrent detection module. The output terminal of the logic unit is also connected to the control terminal of the first switching transistor of the first overcurrent detection module.

6. The step-down circuit according to claim 5, characterized in that, The second sampling unit includes: The second resistor and the third resistor are connected, with the first end of the second resistor connected to the output interface, the second end of the second resistor connected to the first end of the third resistor and the input terminal of the second comparison unit, and the second end of the third resistor grounded.

7. The step-down circuit according to claim 5, characterized in that, The delay unit includes: A third timer, the input of which is connected to the output of the second comparison unit; An adder, wherein the clock input terminal of the adder is connected to the output terminal of the third timer, the first input terminal of the adder is connected to the output terminal of the second comparison unit, and the second input terminal of the adder is used to input the battery voltage; The logic unit includes an AND gate, the first input of which is connected to the output of the adder, the second input of which is connected to the output of the second timer of the first overcurrent detection module, and the output of which is connected to the power module.

8. The step-down circuit according to claim 1, characterized in that, The power module includes: A first power transistor and a second power transistor, wherein the first terminal of the first power transistor is connected to the input interface, the second terminal of the first power transistor is connected to the first terminal of the second power transistor, the second terminal of the second power transistor is connected to the ground terminal, and the control terminals of the first power transistor and the second power transistor are both connected to the second overcurrent detection module. The first power transistor and the second power transistor are used to turn on or off according to the control signal output by the second overcurrent detection module.

9. The step-down circuit according to claim 8, characterized in that, The power module also includes: First inductor, first capacitor, and load; The first inductor is connected between the second terminal of the first power transistor and the output interface; The first capacitor is connected between the output interface and the ground terminal, and the load is connected between the output interface and the ground terminal.

10. A voltage reduction device, characterized in that, include: The step-down circuit with short-circuit delay according to any one of claims 1 to 9.

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