Totem column power factor correction converter control method, control system and converter

Abstract

The application relates to a control method and system of a Totem-Pole power factor correction converter and the Totem-Pole power factor correction converter. The method comprises obtaining a grid input voltage, a DC bus voltage and a boost inductor current; based on the grid input voltage and a phase-locked operation parameter, performing first operation and phase-locked processing through an operation module to obtain grid phase information and grid frequency information; updating a ripple operation parameter according to the grid frequency information, and in the same control cycle as the first operation, performing second operation through the operation module based on the DC bus voltage and the updated ripple operation parameter to obtain a ripple component, the first operation and the second operation calling the same set of program instructions for performing second-order generalized integrator operation; obtaining a voltage feedback signal based on the ripple component, and generating a current reference signal and a switching control signal accordingly. The application can reduce program storage resource occupation and realize same-cycle frequency adaptive updating of the ripple operation parameter.

Description

Technical Field

[0001] This application relates to the field of power electronic converter control technology, and more specifically, to a control method, a control system, and a totem pole power factor correction converter including the control system. Background Technology

[0002] Totem-pole bridgeless power factor correction (PFC) converters are characterized by low conduction losses and high power density, and are widely used in single-phase AC-DC power conversion. Under a digital control architecture, totem-pole PFC converters typically employ dual closed-loop control consisting of an outer voltage loop and an inner current loop. Phase-locked loop (PLL) processing is used to obtain the phase and frequency information of the grid input voltage, enabling the input current to follow the grid voltage.

[0003] For a single-phase PFC converter, the instantaneous power on the input side contains a pulsating component at twice the grid frequency, thus the DC bus voltage typically contains ripple at twice the grid frequency. When this ripple enters the voltage outer loop and is further coupled to the current reference signal, it may cause distortion of the input current waveform. To reduce the impact of this ripple, existing digital control schemes can employ filtering or frequency-selective structures such as second-order generalized integrators (SOGI) to suppress or extract ripple.

[0004] In some digital control schemes, the phase-locked loop and the DC bus second harmonic ripple extraction each use independent SOGI operation modules and are configured with corresponding operation programs. This results in the program resources used to implement the two SOGI operations occupying the program storage space of the digital controller, increasing the program storage resource overhead.

[0005] Furthermore, SOGI's frequency selectivity is related to its resonant parameters. When the actual grid frequency changes relative to the rated frequency, phase-locked looping or ripple extraction based on preset resonant parameters may introduce a certain frequency deviation, thus affecting the processing accuracy of the corresponding signals. Therefore, in application environments where the grid frequency fluctuates, there is still room for improvement in the frequency adaptability of existing control schemes.

[0006] On the other hand, during the digital control process, digital sampling and holding, digital computation, and PWM updates introduce a certain digital delay, which may cause amplitude attenuation or phase shift in the extracted second harmonic ripple signal. These errors will further affect the compensation accuracy when using the extracted ripple for bus voltage compensation, thereby affecting the ripple suppression effect.

[0007] Therefore, how to reduce the program storage resource consumption in the totem pole PFC digital control process, and improve the signal processing adaptability and bus ripple compensation accuracy under power grid frequency change conditions, are still issues that need further research. Summary of the Invention

[0008] The technical problem to be solved by this application is to provide a control method, a control system, and a totem pole power factor correction converter that includes the above-mentioned defects of the prior art.

[0009] According to one aspect of this application, a control method for a totem-pole power factor correction converter is provided, comprising the following steps: S1. Obtain the grid input voltage, DC bus voltage, and boost inductor current of the totem pole power factor correction converter; S2. Based on the grid input voltage and the phase-locked operation parameters corresponding to the phase-locked processing, the first calculation is performed by the calculation module, and the phase-locked processing is performed based on the result of the first calculation to obtain grid phase information and grid frequency information. S3. Based on the power grid frequency information, update the ripple operation parameters corresponding to the ripple processing. Within the same control cycle of the first operation and after updating the ripple operation parameters, perform a second operation through the operation module based on the DC bus voltage and the updated ripple operation parameters, and obtain the ripple component in the DC bus voltage based on the result of the second operation. Both the first and second operations are executed by calling the same set of program instructions in the operation module for performing second-order generalized integrator operations. S4. Compensate the DC bus voltage based on the ripple component to obtain a voltage feedback signal; S5. Adjust the voltage based on the voltage feedback signal and the DC bus voltage reference value, and generate a current reference signal by combining the grid phase information; and S6. Adjust the current according to the current reference signal and the boost inductor current to generate a switching control signal for controlling the totem pole power factor correction converter.

[0010] Preferably, the phase-locked loop operating parameters include a first resonant angular frequency and a first discrete operation coefficient, and step S2 includes: S21. Based on the grid input voltage, the phase-locked operation parameters and the first state variable group corresponding to the phase-locked processing, the same set of program instructions in the calculation module is called to perform the first calculation to obtain the first in-phase signal and the first quadrature signal, and the first in-phase signal and the first quadrature signal are stored in the first output buffer corresponding to the phase-locked processing. S22. Perform coordinate transformation on the first in-phase signal and the first quadrature signal to obtain the phase error signal; S23. Perform closed-loop adjustment based on the phase error signal to obtain the grid angular frequency estimate, obtain the grid frequency information based on the grid angular frequency estimate, and integrate the grid angular frequency estimate to obtain the grid phase information; S24. Update the first resonant angular frequency according to the estimated value of the power grid angular frequency, and update the first discrete operation coefficient according to the updated first resonant angular frequency.

[0011] Preferably, the ripple operating parameters include the second resonant angular frequency and the second discrete operation coefficients, and step S3 includes: S31. Update the second resonant angular frequency to twice the estimated value of the power grid angular frequency, and update the second discrete operation coefficients according to the updated second resonant angular frequency; S32. Based on the DC bus voltage, the updated ripple operating parameters and the second state variable group corresponding to the ripple processing, the same set of program instructions in the operation module is called to perform the second operation to obtain the second in-phase signal and the second quadrature signal, and the second in-phase signal and the second quadrature signal are stored in the second output buffer corresponding to the ripple processing. S33. The second in-phase signal is used as the ripple component in the DC bus voltage.

[0012] Preferably, the first state variable group and the second state variable group are independent of each other, and the first output buffer and the second output buffer are independent of each other; The first state variable group and the second state variable group respectively include the historical values ​​of the corresponding input signal, the historical values ​​of the in-phase output, and the historical values ​​of the quadrature output.

[0013] Preferably, when the first resonant angular frequency or the second resonant angular frequency is updated, the corresponding discrete operation coefficients are updated according to the updated resonant angular frequency, and the historical quantities stored in the corresponding state variable group are maintained; when the same set of program instructions is called again to perform the corresponding first operation or second operation, the second-order generalized integrator operation is performed based on the updated discrete operation coefficients and the maintained historical quantities.

[0014] Preferably, step S4 includes: S41. Based on the sampling period of the digital control system and the frequency of the ripple component, determine the ripple amplitude compensation coefficient based on the frequency domain amplitude characteristics of the zero-order hold element. S42. Perform amplitude compensation on the ripple component according to the ripple amplitude compensation coefficient; S43. Subtract the amplitude-compensated ripple component from the DC bus voltage to obtain the voltage feedback signal; Wherein, the ripple amplitude compensation coefficient K f satisfy: In the formula, ω g Let T be the estimated angular frequency of the power grid. s The sampling period of the digital control system is denoted as .

[0015] Preferably, step S5 includes: S51. Based on the difference between the DC bus voltage reference value and the voltage feedback signal, the current amplitude reference value is obtained through voltage outer loop proportional-integral control; S52. Obtain a sinusoidal phase signal based on the power grid phase information; S53. Multiply the current amplitude reference value with the sinusoidal phase signal to generate the current reference signal.

[0016] Preferably, step S6 includes: S61. Obtain a current error signal based on the current reference signal and the boost inductor current; S62. The current error signal is adjusted by a proportional resonant controller to obtain a pulse width modulation control quantity; S63. Generate the switching control signal according to the pulse width modulation control amount.

[0017] According to a second aspect of this application, a control system for a totem pole power factor correction converter is also provided, including a sampling module, an arithmetic module, a phase-locked loop module, a parameter update module, a ripple compensation module, a voltage regulation module, and a current regulation module. The sampling module is used to acquire the grid input voltage, DC bus voltage, and boost inductor current of the totem pole power factor correction converter. The computation module includes a set of program instructions for performing second-order generalized integrator operations, and is used to call the set of program instructions to perform a first operation based on the grid input voltage and the phase-locked operation parameters corresponding to the phase-locked processing. The phase-locked module is used to perform phase-locked processing based on the result of the first calculation to obtain power grid phase information and power grid frequency information; The parameter update module is used to update the ripple operation parameters corresponding to the ripple processing according to the power grid frequency information. The calculation module is also used to, within the same control cycle of the first calculation and after the ripple operating parameters are updated, call the set of program instructions to perform a second calculation based on the DC bus voltage and the updated ripple operating parameters, and obtain the ripple component in the DC bus voltage based on the result of the second calculation. The ripple compensation module is used to compensate the DC bus voltage based on the ripple component to obtain a voltage feedback signal; The voltage regulation module is used to regulate the voltage according to the voltage feedback signal and the DC bus voltage reference value, and to generate a current reference signal in combination with the grid phase information; The current regulation module is used to regulate the current according to the current reference signal and the boost inductor current, and generate a switching control signal for controlling the totem pole power factor correction converter.

[0018] According to a third aspect of this application, a totem pole power factor correction converter is also provided, including a main power circuit and a control system as described above. The main power circuit includes a boost inductor and switching devices; The control system is used to acquire the grid input voltage, DC bus voltage and boost inductor current of the main power circuit, and generate the switch control signal to control the switching state of the switching device according to the switch control signal.

[0019] Implementing the technical solution constructed in this application has at least the following beneficial effects: This application utilizes the same set of program instructions in the arithmetic module for executing second-order generalized integrator operations to perform the first and second operations respectively. This allows the grid phase-locked loop (PLL) processing and DC bus ripple processing to reuse the same set of arithmetic programs. The ripple operating parameters are updated based on the grid frequency information obtained from the first operation and PLL processing, enabling the updated ripple operating parameters to be used in the second operation within the same control cycle as the first operation. This reduces redundant program code and program storage resource consumption while improving the adaptability of ripple processing to grid frequency changes. Furthermore, by compensating the DC bus voltage based on the obtained ripple components and generating current reference signals and switching control signals based on the compensated voltage feedback signal, the impact of DC bus ripple on subsequent closed-loop control is reduced, improving the control performance of the totem-pole power factor correction converter. Attached Figure Description

[0020] The present application will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is an overall block diagram of the composite control of the totem pole power factor correction converter provided in the embodiments of the present invention; Figure 2This is a flowchart illustrating the control method for the totem pole power factor correction converter provided in an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating the principle of time-division multiplexing of the same set of program instructions in the computing module provided in this embodiment of the invention; Figure 4 This is a timing diagram of time-sharing calls within a single control cycle provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the control system of the totem pole power factor correction converter provided in an embodiment of the present invention; Figure 6 This is a waveform diagram of the output voltage and inductor current under rated operating conditions according to an embodiment of the present invention; Figure 7 This is an FFT harmonic analysis diagram of the input current under rated operating conditions according to an embodiment of the present invention; Figure 8 This is a waveform diagram of the output voltage and current under a sudden increase in load of 50% to 100% according to an embodiment of the present invention; Figure 9 This is a waveform diagram of the output voltage and current under the load drop condition of 100%~50% according to an embodiment of the present invention; Figure 10 This is a waveform diagram of inductor current and output voltage in an embodiment of the present invention with an input voltage of 176V; Figure 11 This is an FFT harmonic analysis diagram of the input current in an embodiment of the present invention with an input voltage of 176V; Figure 12 This is a waveform diagram of inductor current and output voltage in an embodiment of the present invention with an input voltage of 275V; Figure 13 This is an FFT harmonic analysis diagram of the input current in an embodiment of the present invention with an input voltage of 275V; Figure 14 This is a waveform diagram of inductor current and output voltage at a grid frequency of 49.5Hz according to an embodiment of the present invention; Figure 15 This is an FFT harmonic analysis diagram of the input current at a grid frequency of 49.5Hz, according to an embodiment of the present invention. Figure 16 This is a waveform diagram of inductor current and output voltage at a grid frequency of 50.5Hz according to an embodiment of the present invention; Figure 17 This is an FFT harmonic analysis diagram of the input current at a grid frequency of 50.5Hz, according to an embodiment of the present invention. Detailed Implementation

[0021] To provide a clearer understanding of the technical features, objectives, and effects of this application, the specific embodiments of this application are now described in detail with reference to the accompanying drawings. Many specific details are set forth in the following description to facilitate a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below. This embodiment uses a totem-pole power factor correction converter in continuous conduction mode as an example, but the present invention is not limited to the specific power level, main circuit parameters, and digital controller type described herein.

[0022] like Figure 1 As shown, this embodiment provides a composite control architecture for a totem-pole power factor correction converter. This control architecture performs second-order generalized integrator operations on the grid input voltage and DC bus voltage using the same computation module. Specifically, a first operation is performed based on the grid input voltage, and phase-locked loop (PLL) processing is performed based on the result to obtain grid phase and frequency information. The operating parameters corresponding to ripple processing are updated based on the obtained grid frequency information. Within the same control cycle as the first operation, a second operation is performed based on the DC bus voltage and the updated operating parameters to obtain the ripple component in the DC bus voltage. Both the first and second operations call the same set of program instructions for performing the second-order generalized integrator operation. After obtaining the ripple component, the DC bus voltage is compensated, and voltage and current are adjusted sequentially to generate switching control signals for controlling the totem-pole power factor correction converter.

[0023] The following is combined Figure 1 and Figure 2 The control method of this embodiment will be described in detail. Before executing the control method, the digital control system can be initialized. For example, the set of program instructions for performing the second-order generalized integrator operation can be configured, the damping coefficient can be set, and the first resonant frequency corresponding to the phase-locked loop processing and the second resonant frequency corresponding to the ripple processing can be initialized according to the rated grid frequency, and independent first state variable groups, second state variable groups, and corresponding output buffers can be configured respectively. In the embodiment where the rated grid frequency is 50Hz, the initial value of the first resonant frequency can be set to 50Hz, and the initial value of the second resonant frequency can be set to 100Hz. Figure 2 As shown, the control method provided in this embodiment includes the following steps: S1. Obtain the grid input voltage, DC bus voltage, and boost inductor current of the totem pole power factor correction converter.

[0024] In this embodiment, the grid input voltage, DC bus voltage, and boost inductor current are sampled in each control cycle, and the sampled analog signals are subjected to AD conversion and data filtering to obtain the grid input voltage, DC bus voltage, and boost inductor current corresponding to the current control cycle, which are then used for subsequent phase-locked loop processing, ripple processing, voltage regulation, and current regulation.

[0025] S2. Based on the grid input voltage and the phase-locked operation parameters corresponding to the phase-locked processing, the first calculation is performed by the calculation module, and the phase-locked processing is performed based on the result of the first calculation to obtain grid phase information and grid frequency information.

[0026] In this embodiment, the arithmetic module can be implemented by a digital controller executing a corresponding program, and includes a set of program instructions for performing second-order generalized integrator operations. These program instructions can be stored in the controller's program memory, such as Flash. To enable phase-locked loop processing and subsequent ripple processing to reuse the same operational logic, the differential iteration operation, state update, and output calculation of the second-order generalized integrator are encapsulated into the set of reusable program instructions. When the program instructions are invoked, corresponding input signals, operating parameters, state variable groups, and output buffers are provided according to different processing functions, thereby using the same set of program instructions to complete second-order generalized integrator operations under different operating parameters.

[0027] Specifically, let the current input sampling signal be v(n), the resonant angular frequency be ω0, the damping coefficient be k, and the sampling period be T. s To achieve digital control, this embodiment uses the bilinear transform method to discretize the second-order generalized integrator, wherein: The corresponding discrete operation coefficients can then be expressed as: In one specific implementation, the program instructions calculate the in-phase output v′(n) and quadrature output qv′(n) based on the current input signal, discrete operation coefficients, and historical quantities stored in the corresponding state variable group, and update the historical quantities and the corresponding output buffer after the calculation is completed.

[0028] like Figure 3 As shown, phase-locked loop (PLL) processing and ripple processing are configured with corresponding parameter areas, state areas, and output buffers, respectively. Both processing channels call the same set of second-order generalized integrator program instructions, but the input signals, operating parameters, and storage addresses of the state area and output buffer provided during the call are different. For example... Figure 3As shown in the middle, in the first and second operations, the same set of program instructions executes the same operation flow, including reading the input parameter, differential iteration, state update, and output buffer update. The difference between the two lies in the input signal, running parameters, and corresponding state area and output buffer provided during the call. Specifically, the phase-locked loop (PLL) processing corresponds to the first state variable group (h1[0]~h1[5]) and the first output buffer (out1[0], out1[1]), while the ripple processing corresponds to the second state variable group (h2[0]~h2[5]) and the second output buffer (out2[0], out2[1]). The first and second state variable groups are independent of each other, as are the first and second output buffers. The two processing paths achieve independent second-order generalized integrator operations by passing different running parameters and the corresponding state variable groups and output buffer storage addresses to the same set of program instructions.

[0029] Based on this, step S2 further includes steps S21 to S24.

[0030] S21. Based on the grid input voltage, the phase-locked operation parameters, and the first state variable group corresponding to the phase-locked processing, the same set of program instructions in the calculation module is called to perform the first calculation, obtain the first in-phase signal and the first quadrature signal, and store the first in-phase signal and the first quadrature signal in the first output buffer corresponding to the phase-locked processing.

[0031] Specifically, the grid input voltage obtained in the current control cycle is used as the input signal for the first operation, and the first resonant angular frequency and the first discrete operation coefficients corresponding to the phase-locked loop processing are loaded, while the first state variable group is accessed. After the first operation is completed, the first in-phase signal v1′ and the first quadrature signal qv1′ are obtained and written to the first output buffer. This call corresponds to... Figure 3 The first input process of the phase-locked branch in the process.

[0032] S22. Perform coordinate transformation on the first in-phase signal and the first quadrature signal to obtain the phase error signal.

[0033] Specifically, the first in-phase signal and the first quadrature signal constitute two mutually orthogonal phase signals. Performing a Park transform on these two phase signals yields the d-axis and q-axis components in a synchronously rotating coordinate system. For example, it can be expressed as: Where θ is the current grid phase estimate. When the phase-locked loop tends to stabilize, the q-axis component v q Since the q-axis component approaches zero, it can be used as a phase error signal to characterize the phase deviation.

[0034] S23. Perform closed-loop adjustment based on the phase error signal to obtain the grid angular frequency estimate, obtain the grid frequency information based on the grid angular frequency estimate, and integrate the grid angular frequency estimate to obtain the grid phase information.

[0035] Specifically, the phase error signal is input into a proportional-integral (PI) regulator for closed-loop regulation, and the output of the PI regulator is compared with the rated grid angular frequency ω. n By superimposing the values, the estimated grid angular frequency ω for the current control cycle is obtained. g (n), for example: Therefore, the power grid frequency f g (n) can be represented as: Simultaneously, the grid angular frequency estimate is integrated to obtain grid phase information. In discrete control systems, the current grid phase can be determined based on the grid phase of the previous control cycle and the grid angular frequency estimate of the current control cycle. For example: In one implementation, to reduce frequency fluctuations caused by grid harmonics and sampling noise, the estimated grid angular frequency can be low-pass filtered and limited. For example, the cutoff frequency of the low-pass filter can be set to approximately 10 Hz, and the limiting range can correspond to the grid frequency range of 49.5 Hz to 50.5 Hz. Both the low-pass filtering and limiting are performed after the first calculation and before the subsequent second calculation, enabling the grid frequency information obtained and processed in the current control cycle to be used for updating the ripple operating parameters of the current control cycle.

[0036] S24. Update the first resonant angular frequency according to the estimated value of the power grid angular frequency, and update the first discrete operation coefficient according to the updated first resonant angular frequency.

[0037] Specifically, a new first resonant angular frequency is determined based on the currently obtained grid angular frequency estimate, and the corresponding first discrete operation coefficients are re-determined based on the updated first resonant angular frequency. The updated first resonant angular frequency and the first discrete operation coefficients are stored in the parameter area corresponding to the phase-locked loop (PLL) processing and can be called during subsequent first operations, thereby enabling the resonant parameters of the second-order generalized integrator corresponding to the PLL processing to be updated as the grid frequency changes.

[0038] It should be noted that, in this embodiment, although the phase-locked loop (PLL) processing and ripple processing call the same set of program instructions for performing second-order generalized integrator operations, their operating parameters, state variable groups, and output buffers are configured separately. The two calls only reuse the program instructions themselves and do not share the historical states or output data that need to be maintained during the operation.

[0039] S3. Based on the power grid frequency information, update the ripple operation parameters corresponding to the ripple processing. Within the same control cycle of the first operation and after updating the ripple operation parameters, perform a second operation through the operation module based on the DC bus voltage and the updated ripple operation parameters, and obtain the ripple component in the DC bus voltage based on the result of the second operation.

[0040] In this step, the ripple operation parameters include a second resonant angular frequency and second discrete operation coefficients. The second resonant angular frequency is used to determine the resonant frequency of the second-order generalized integrator corresponding to the ripple processing, and the second discrete operation coefficients are determined based on the second resonant angular frequency.

[0041] In this embodiment, during system initialization, the second resonant angular frequency is set to an initial value corresponding to twice the rated mains frequency. For example, when the rated mains frequency is 50Hz, the initial value of the second resonant angular frequency can be set as follows: During the control process, the second resonant angular frequency is dynamically updated based on the grid frequency information obtained from the phase-locked loop (PLL) processing, and the second discrete operation coefficients are updated accordingly based on the updated second resonant angular frequency, so that the resonant parameters corresponding to the ripple processing are adjusted as the grid frequency changes.

[0042] In one implementation, step S3 specifically includes steps S31 to S33.

[0043] S31. Update the second resonant angular frequency to twice the estimated value of the power grid angular frequency, and update the second discrete operation coefficients according to the updated second resonant angular frequency.

[0044] Specifically, based on the grid angular frequency estimate ω obtained in the current control cycle g (n), update the second resonant angular frequency to: The corresponding second discrete operation coefficients are re-determined based on the updated second resonant angular frequency. For example, let: Then, the second discrete operation coefficients A2, B2, and C2 can be calculated according to the aforementioned discrete operation relationship, and the updated second resonant angular frequency and the second discrete operation coefficients can be written into the parameter area corresponding to the ripple processing.

[0045] In this embodiment, the fluctuation range of the power grid frequency is 49.5Hz to 50.5Hz. Correspondingly, the resonant frequency of the ripple processing branch can vary with the power grid frequency in the range of 99Hz to 101Hz. This allows the resonant parameters used in the ripple processing to be adjusted according to twice the actual power grid frequency, which helps to reduce the impact of the power grid frequency offset on the ripple extraction accuracy.

[0046] It should be noted that, as Figure 4 As shown, within one control cycle, signal sampling, the first operation, phase-locked loop (PLL) processing and grid frequency calculation, ripple operating parameter update, and the second operation are executed sequentially. Specifically, after the first operation is completed, the grid frequency for the current control cycle is calculated based on the first operation result. Before the second operation begins, the second resonant angular frequency and the second discrete operation coefficients are updated according to the grid frequency information of the current control cycle. The subsequent second operation directly uses the updated ripple operating parameters. Thus, the grid frequency information obtained in the current control cycle can take effect in the ripple processing of the current control cycle without waiting for the next control cycle.

[0047] When the estimated grid angular frequency needs to be low-pass filtered or limited, the low-pass filtering or limiting process is also completed after the first operation and before the second operation, so that the processed grid frequency information of the current control cycle can be used to update the second resonant angular frequency and the second discrete operation coefficient of the current control cycle.

[0048] S32. Based on the DC bus voltage, the updated ripple operating parameters, and the second state variable group corresponding to the ripple processing, the same set of program instructions in the calculation module is called to perform the second calculation, to obtain the second in-phase signal and the second quadrature signal, and the second in-phase signal and the second quadrature signal are stored in the second output buffer corresponding to the ripple processing.

[0049] Specifically, the DC bus voltage V obtained in the current control cycle o As the input signal for the second operation, and loading the updated second resonant angular frequency, second discrete operation coefficients, and the storage addresses corresponding to the second state variable group and the second output buffer, the same set of program instructions used to perform the second-order generalized integrator operation is called again. This call corresponds to... Figure 3 The second input process of the ripple branch in the middle.

[0050] After the second operation is completed, the second in-phase signal v2' and the second quadrature signal qv2' are obtained and written to the second output buffer respectively. Compared with the first operation, the second operation has different input signals, operating parameters, state variable groups and output buffers, but the program instructions for differential iteration, state update and output calculation are the same.

[0051] S33. The second in-phase signal is used as the ripple component in the DC bus voltage.

[0052] Specifically, the in-phase output v′ of the second-order generalized integrator is a bandpass output, and its frequency selectivity is determined by the corresponding resonant angular frequency. In the second operation, the second resonant angular frequency is set to twice the estimated grid angular frequency; therefore, the second in-phase signal mainly characterizes the AC component in the DC bus voltage corresponding to twice the grid frequency. In this embodiment, the second in-phase signal v2′ is taken as the ripple component in the DC bus voltage, and this ripple component can be denoted as ΔV. o .

[0053] Furthermore, such as Figure 3 As shown, although the first and second operations call the same set of program instructions, they use independent sets of state variables and output buffers. Specifically, the first and second state variable sets are independent of each other, as are the first and second output buffers. Each operation saves its own historical state and stores its own results, thus achieving instruction reuse while avoiding the mixing of states between the two recursive operations.

[0054] Each state variable group can include six historical values: two historical values ​​corresponding to the input signal, two historical values ​​for the in-phase output, and two historical values ​​for the quadrature output. Taking the aforementioned reentrant function as an example, before the nth operation begins: Furthermore, when the first or second resonant angular frequency is updated, the corresponding discrete operation coefficients are updated according to the updated resonant angular frequency, while the historical values ​​already stored in the corresponding state variable group are maintained. In the next call to the same set of program instructions to perform the corresponding first or second operation, the updated discrete operation coefficients and the maintained historical values ​​are directly used to continue the differential iteration without re-initializing the state variable group.

[0055] In other words, the parameter update changes the operating parameters used in subsequent second-order generalized integrator operations, while the existing input history, in-phase output history, and quadrature output history are retained. This maintains the continuity of the recursive operation state before and after the parameter update, reduces output abrupt changes and transient disturbances caused by state reinitialization, and achieves a smooth transition during the dynamic update of resonant parameters.

[0056] In one implementation, the first and second operations can use the same damping coefficient k, so that the same set of program instructions for performing the second-order generalized integrator operation can be used for phase-locked loop processing and ripple processing at different resonant angular frequencies, respectively. Specifically, it can be set according to dynamic response speed, frequency selectivity, and anti-interference performance. For example, k can be selected in the range of about 0.5 to 2, preferably in the range of about 1 to 1.5. As k increases, the bandwidth of the second-order generalized integrator increases accordingly, and the dynamic convergence speed improves, but the frequency selectivity decreases relatively; as k decreases, the frequency selectivity improves, but the dynamic convergence speed decreases relatively. In this embodiment, the damping coefficient... By employing this damping coefficient, both the dynamic response speed and frequency selectivity of the second-order generalized integrator can be considered, making it suitable for both phase-locked loop (PLL) and ripple processing operating conditions. Specifically, in PLL, the damping coefficient setting facilitates faster dynamic convergence; in ripple processing, the second-order generalized integrator exhibits corresponding frequency selectivity near its resonant frequency, thus facilitating the extraction of the twice-grid-frequency ripple component from the DC bus voltage.

[0057] Through steps S2 and S3 above, this embodiment utilizes the same set of program instructions for executing the second-order generalized integrator operation to complete the first operation corresponding to phase-locked loop processing and the second operation corresponding to ripple processing. The grid frequency information obtained from the first operation is used to update the second resonant angular frequency and the second discrete operation coefficients corresponding to the ripple processing, and is used in the subsequent second operation within the same control cycle, ensuring that the resonant parameters used in the ripple processing can keep pace with changes in the grid frequency. Simultaneously, the two operations employ independent sets of state variables and output buffers, reusing only the program instructions of the second-order generalized integrator. This reduces redundant operation code and program storage resource consumption while maintaining the independence of the two recursive operation states. Furthermore, when updating the resonant angular frequency and discrete operation coefficients, by maintaining the existing historical state and continuing subsequent iterations based on the updated discrete operation coefficients, the continuity of the recursive state of the second-order generalized integrator before and after parameter updates can be maintained, reducing output abrupt changes caused by state re-initialization and achieving a smooth transition during the dynamic adjustment of resonant parameters.

[0058] In one specific implementation, the above-mentioned program instruction reuse method can reduce the program storage resource consumption. Compared with the implementation of configuring two independent SOGI operation programs, where a single SOGI core operation code occupies approximately 120 bytes of Flash and the two core operation codes together occupy approximately 240 bytes of Flash; after adopting the program instruction reuse method described in this embodiment, only one SOGI core operation code is retained, and corresponding parameter configuration and calling instructions are added. The program storage resource consumption is approximately 156 bytes, which is about 35% lower than the aforementioned dual independent SOGI implementation. This significantly reduces the storage capacity requirements of the main control chip and can be adapted to low-cost, entry-level digital control chips.

[0059] Step S4: Compensate the DC bus voltage based on the ripple component to obtain a voltage feedback signal.

[0060] like Figure 1 As shown, after obtaining the ripple component in the DC bus voltage, the DC bus voltage is compensated using the ripple component to obtain a voltage feedback signal V for voltage outer loop regulation. o ′.

[0061] In digital control processes, digital delays occur during AD sampling and holding, algorithm computation, and PWM updates. This causes a certain amplitude attenuation in the extracted ripple component at twice the grid frequency relative to the actual ripple in the DC bus voltage. Directly using the extracted ripple component to compensate the DC bus voltage may result in residual ripple after compensation. To improve the accuracy of ripple compensation, in this embodiment, based on the sampling period of the digital control system and the frequency of the ripple component, a ripple amplitude compensation coefficient is determined using the frequency domain amplitude characteristics of the zero-order hold stage. This coefficient is then used to compensate the amplitude of the extracted ripple component.

[0062] In one embodiment, step S4 includes steps S41 to S43.

[0063] S41. Based on the sampling period of the digital control system and the frequency of the ripple component, determine the ripple amplitude compensation coefficient based on the frequency domain amplitude characteristics of the zero-order hold element.

[0064] The frequency domain amplitude characteristic of the zero-order hold circuit can be expressed as: In the formula, Ts is the sampling period of the digital control system, and ω is the angular frequency of the signal to be compensated.

[0065] In this embodiment, the ripple component corresponds to twice the grid frequency, therefore its angular frequency is 2ω. g , where ω gThis is the estimated grid angular frequency obtained from the aforementioned phase-locked loop (PLL) processing. The second resonant angular frequency of the second-order generalized integrator used in the second operation is set to 2ω. g Furthermore, its in-phase output channel has an amplitude-frequency gain of 1 at the resonant frequency, therefore, based on the zero-order hold circuit at 2ω... g The amplitude attenuation at a certain point determines the ripple amplitude compensation coefficient K. f ,Right now: Therefore, the ripple amplitude compensation coefficient can be determined based on the estimated grid angular frequency and the sampling period, thereby compensating for the ripple amplitude attenuation caused by the digital control process.

[0066] S42. Perform amplitude compensation on the ripple component according to the ripple amplitude compensation coefficient.

[0067] Specifically, let the ripple component obtained in step S33 be ΔVo, then the compensated ripple component can be expressed as: S43. Subtract the amplitude-compensated ripple component from the DC bus voltage to obtain the voltage feedback signal.

[0068] This reduces the impact of the DC bus voltage ripple at twice the grid frequency on the subsequent voltage regulation process and decreases the extent to which the ripple is coupled to the current reference signal through the voltage outer loop.

[0069] In this embodiment, the sampling frequency is 68kHz. When the power grid frequency is 50Hz, the corresponding ripple amplitude compensation coefficient can be determined according to the above relationship. Since the sampling frequency is much higher than twice the power grid frequency, the ripple amplitude compensation coefficient is close to 1.

[0070] By processing the above methods, the amplitude of the extracted ripple component can be corrected according to the sampling characteristics of the digital control system before it is used for DC bus voltage compensation. This can improve the accuracy of ripple compensation and reduce the degree to which ripple at twice the grid frequency enters the subsequent voltage and current regulation processes, thus providing conditions for balancing DC bus ripple suppression and closed-loop dynamic response.

[0071] Step S5: Adjust the voltage according to the voltage feedback signal and the DC bus voltage reference value, and generate a current reference signal in combination with the grid phase information.

[0072] like Figure 1 As shown, the voltage feedback signal V o ′ and DC bus voltage reference value V ref The values ​​are compared, and the current amplitude reference value i is obtained through proportional-integral PI regulation in the outer voltage loop. L_refFurthermore, the current reference signal is generated by combining the grid phase information obtained from phase-locked loop processing.

[0073] In this embodiment, a voltage error signal Ve is formed by the voltage feedback signal and the DC bus voltage reference value, and a control loop that adjusts the voltage error signal by a proportional-integral controller constitutes the voltage outer loop.

[0074] In one embodiment, step S5 includes steps S51 to S53.

[0075] S51. Based on the difference between the DC bus voltage reference value and the voltage feedback signal, the current amplitude reference value is obtained through voltage outer loop proportional-integral control.

[0076] Specifically, the DC bus voltage reference value V ref The voltage feedback signal V obtained in step S4 o The voltage error signal is obtained by subtracting the voltage from the current, and then the voltage error signal is input into the voltage outer loop proportional-integral controller to obtain the current amplitude reference value.

[0077] S52. Obtain a sinusoidal phase signal based on the power grid phase information.

[0078] Specifically, based on the grid phase information obtained in step S2, a sinusoidal phase signal synchronized with the grid input voltage is determined.

[0079] S53. Multiply the current amplitude reference value with the sinusoidal phase signal to generate the current reference signal.

[0080] Since step S4 has already compensated the DC bus voltage based on the extracted ripple component, it can reduce the extent to which the ripple of twice the grid frequency enters the voltage outer loop and is further coupled to the current amplitude reference value, thereby improving the sinusoidality of the generated current reference signal and reducing the impact of bus ripple on the input current waveform.

[0081] Step S6: Adjust the current according to the current reference signal and the boost inductor current to generate a switching control signal for controlling the totem pole power factor correction converter.

[0082] like Figure 1 As shown, the current reference signal i L_ref With boost inductor current i L A current error signal is generated, and after being adjusted by the proportional resonant controller PR, a corresponding switching control signal is generated.

[0083] In this embodiment, a current error signal is formed by the current reference signal and the boost inductor current, and a control loop that adjusts the current error signal through a proportional resonant controller constitutes the inner current loop.

[0084] In one embodiment, step S6 includes steps S61 to S63.

[0085] S61. Obtain a current error signal based on the current reference signal and the boost inductor current.

[0086] Specifically, the current error signal is obtained by subtracting the current reference signal from the boost inductor current acquired in the current control cycle.

[0087] S62. The current error signal is adjusted by a proportional resonant controller to obtain a pulse width modulation control quantity.

[0088] In one specific implementation, the proportional resonant controller can be a non-ideal damped PR controller. In this embodiment, the resonant angular frequency can be set to the angular frequency corresponding to the rated mains frequency of 50Hz, and the cutoff bandwidth can be set to 10rad / s. By providing a higher control gain near the mains frequency, the tracking capability of the sinusoidal current reference signal can be improved, and the steady-state waveform of the input current can be improved.

[0089] S63. Generate the switching control signal according to the pulse width modulation control amount.

[0090] Specifically, a corresponding PWM control signal is generated based on the pulse width modulation control quantity output by the proportional resonant controller, and the switching devices in the totem pole power factor correction converter are controlled by the PWM control signal to adjust the boost inductor current to follow the current reference signal, thereby realizing closed-loop current control.

[0091] Combination Figure 4 The single-control-cycle execution timing shown allows for the continuation of ripple compensation, voltage regulation, and current regulation within the current control cycle after the second operation is completed and the ripple component is obtained. Based on the corresponding regulation results, switching control signals are generated and the PWM output is updated. It should be noted that... Figure 4 In the timing sequence shown, the timing relationship related to the aforementioned program instruction multiplexing and frequency adaptation is as follows: the update of the ripple operation parameters is located after the first operation and the grid frequency calculation and before the second operation, so that the grid frequency information obtained in the current control cycle can be used for the second operation of the current control cycle.

[0092] Through the above steps S4 to S6, the DC bus voltage feedback is first compensated using the ripple component, and then a current reference signal is generated based on the compensated voltage feedback signal. The closed-loop tracking of the boost inductor current is achieved through a proportional resonant controller, thereby reducing the impact of the DC bus ripple at twice the grid frequency on the current reference and input current control, and realizing the closed-loop control of the totem pole power factor correction converter.

[0093] Furthermore, in one embodiment, the frequency domain parameters of the outer voltage loop and the inner current loop can be set, wherein the crossover frequency refers to the frequency at which the amplitude of the open-loop amplitude-frequency characteristic of the corresponding control loop crosses 0 dB. The crossover frequency of the outer voltage loop and the crossover frequency of the inner current loop can be determined based on the main circuit parameters, switching frequency, sampling frequency, and closed-loop stability margin, etc.

[0094] In one optional embodiment, the crossover frequency of the outer voltage loop can be lower than the frequency of the ripple component in the DC bus voltage, so that the outer voltage loop has a certain attenuation capability at the frequency corresponding to the ripple component; the crossover frequency of the inner current loop can be higher than the crossover frequency of the outer voltage loop and can be higher than the frequency of the ripple component, so that the inner current loop has a faster response speed relative to the outer voltage loop and improves the tracking capability of the current reference signal.

[0095] Furthermore, in one optional embodiment, the crossover frequency of the outer voltage loop can be 20Hz to 60Hz, the crossover frequency of the inner current loop can be 2kHz to 8kHz, and the ratio of the crossover frequency of the inner current loop to the crossover frequency of the outer voltage loop can be no less than 50:1. Through the above frequency domain parameter settings, coordination can be achieved between the dynamic response of the outer voltage loop, the attenuation of ripple at twice the grid frequency, and the tracking performance of the inner current loop.

[0096] In a preferred embodiment, the crossover frequency of the outer voltage loop can be 30Hz to 50Hz, and the crossover frequency of the inner current loop can be 3kHz to 6kHz. In a specific embodiment, the crossover frequency of the outer voltage loop can be set to approximately 40Hz, and the crossover frequency of the inner current loop can be set to approximately 4kHz, with the ratio of the crossover frequency of the inner current loop to the crossover frequency of the outer voltage loop being approximately 100:1.

[0097] It should be noted that the aforementioned crossover frequencies and their ratios are merely specific implementation methods and do not constitute a limitation of the present invention. Increasing the crossover frequency of the outer voltage loop can improve the dynamic response speed of the DC bus voltage, but its attenuation capability for ripple at twice the grid frequency decreases accordingly; decreasing the crossover frequency of the outer voltage loop improves the attenuation capability for ripple at twice the grid frequency, but relatively reduces the dynamic response speed. Increasing the crossover frequency of the inner current loop can improve the tracking capability of the current reference signal, but its upper limit is limited by factors such as switching frequency, sampling frequency, and closed-loop stability margin; decreasing the crossover frequency of the inner current loop reduces its current tracking capability and disturbance rejection capability. Therefore, the crossover frequencies of the outer voltage loop and the inner current loop can be set according to the ripple suppression requirements, dynamic response requirements, and closed-loop stability requirements in specific applications.

[0098] By coordinating the aforementioned ripple compensation branch with the frequency domain parameter settings of the voltage outer loop and current inner loop, the degree to which the DC bus ripple at twice the grid frequency is coupled to the current reference signal through the voltage outer loop can be reduced. Furthermore, the proportional resonant controller can be used to improve the tracking capability of the current inner loop to the sinusoidal current reference signal, thereby balancing the dynamic response performance and steady-state input current quality of the totem-pole power factor correction converter.

[0099] Furthermore, in one specific implementation, the control system parameters can be tuned in the order of the relevant parameters of the second-order generalized integrator, the current inner loop control parameters, the voltage outer loop control parameters, and the system joint debugging.

[0100] First, the relevant parameters of the second-order generalized integrator can be set. Specifically, the damping coefficients used in the first and second operations can be set according to the aforementioned implementation method, and the first and second resonant angular frequencies can be initialized according to the rated grid frequency, while simultaneously enabling the resonant parameter update mechanism based on grid frequency information. The ripple amplitude compensation coefficient can be determined according to the frequency domain amplitude characteristics of the zero-order hold element described in step S41, based on the sampling period of the digital control system and the frequency of the ripple component.

[0101] Subsequently, the proportional resonant controller of the current inner loop can be parameter-tuned. Specifically, the aforementioned non-ideal damped PR controller can be used, with the set current inner loop crossover frequency as the design reference. By adjusting the proportional gain and resonant gain, the current inner loop can obtain the required control gain near the power frequency, while simultaneously meeting the corresponding stability margin requirements. In this embodiment, the power frequency open-loop gain of the current inner loop can be made not less than approximately 60 dB, and the phase margin not less than approximately 45°.

[0102] Furthermore, the proportional-integral controller of the voltage outer loop can be parameter-tuned. Specifically, the proportional and integral parameters can be determined based on the set voltage outer loop crossover frequency and the small-signal model of the totem-pole power factor correction converter. If necessary, compensation can also be performed based on the frequency response characteristics of the main power circuit. In this embodiment, the phase margin of the voltage outer loop can reach approximately 60°.

[0103] After completing the above parameter tuning, the control system can be jointly debugged. For example, the tracking performance of the current inner loop on the current reference signal can be verified first, and then the aforementioned ripple compensation branch can be connected to verify the compensation effect of DC bus ripple at twice the grid frequency. Subsequently, the voltage outer loop can be closed, and the relevant parameters can be adjusted under operating conditions such as load change, input voltage change, and grid frequency change to verify the closed-loop stability and dynamic and steady-state control performance of the control system.

[0104] Figure 5 The diagram shown is a schematic of the control system of the totem-pole power factor correction converter provided in an embodiment of the present invention. Figure 5 As shown, the control system includes: a sampling module 110, a calculation module 120, a phase-locked loop module 130, a parameter update module 140, a ripple compensation module 150, a voltage regulation module 160, and a current regulation module 170.

[0105] The sampling module 110 is used to acquire the grid input voltage, DC bus voltage, and boost inductor current of the totem-pole power factor correction converter. The calculation module 120 includes a set of program instructions for performing second-order generalized integrator operations, and is used to call the set of program instructions to perform a first calculation based on the grid input voltage and the phase-locked loop (PLL) operating parameters corresponding to the PLL processing. The PLL module 130 is used to perform PLL processing based on the result of the first calculation to obtain grid phase information and grid frequency information. The parameter update module 140 is used to update the ripple operating parameters corresponding to the ripple processing according to the grid frequency information. The calculation module 120 is also used, within the same control cycle of the first calculation and after the ripple operating parameters are updated, to call the set of program instructions again to perform a second calculation based on the DC bus voltage and the updated ripple operating parameters, and to obtain the ripple component in the DC bus voltage based on the result of the second calculation. The ripple compensation module 150 is used to compensate the DC bus voltage based on the ripple component to obtain a voltage feedback signal. The voltage regulation module 160 is used to regulate the voltage based on the voltage feedback signal and the DC bus voltage reference value, and to generate a current reference signal in conjunction with the grid phase information. The current regulation module 170 is used to regulate the current based on the current reference signal and the boost inductor current, and to generate a switching control signal for controlling the totem-pole power factor correction converter.

[0106] In one optional embodiment, the control system may further include a storage unit. The storage unit may be configured with a first parameter area, a first state area, and a first output buffer area corresponding to phase-locked loop (PLL) processing, and a second parameter area, a second state area, and a second output buffer area corresponding to ripple processing. Specifically, the first parameter area stores the PLL operating parameters, the first state area stores a first set of state variables, and the first output buffer area stores a first in-phase signal and a first quadrature signal obtained from the first operation; the second parameter area stores the ripple operating parameters, the second state area stores a second set of state variables, and the second output buffer area stores a second in-phase signal and a second quadrature signal obtained from the second operation.

[0107] The first state region and the second state region are independent of each other, as are the first output buffer and the second output buffer. During the first and second operations, corresponding running parameters and storage addresses for the state region and output buffer are provided to the same set of program instructions in the operation module 120, enabling the first and second operations to read and update their respective state variables and store their respective operation results, while reusing the same set of program instructions for executing the second-order generalized integrator operation.

[0108] Furthermore, the first set of state variables and the second set of state variables can respectively include historical values ​​of the corresponding input signal, historical values ​​of the in-phase output, and historical values ​​of the quadrature output. When the corresponding resonant angular frequency and discrete operation coefficients are updated, the historical values ​​stored in the corresponding state region can be retained. When the set of program instructions is called subsequently, the second-order generalized integrator operation is continued based on the updated discrete operation coefficients and the retained historical values, thereby maintaining the continuity of the recursive operation state before and after the parameter update.

[0109] It should be noted that the above modules are functionally divided according to the functions they perform, and it is not required that each module correspond to an independent hardware device. In one embodiment, one or more of the above modules can be implemented by the same digital processor by executing corresponding program instructions; wherein, the program instructions in the arithmetic module 120 for performing second-order generalized integrator operations can be stored only once and reused by phase-locked loop processing and ripple processing in different calling processes.

[0110] Furthermore, this embodiment of the invention also provides a totem-pole power factor correction converter. The totem-pole power factor correction converter includes a main power circuit and the aforementioned control system. The main power circuit includes a boost inductor and switching devices. The control system is connected to the main power circuit and is used to acquire the grid input voltage, DC bus voltage, and boost inductor current of the main power circuit, and to perform phase-locked loop processing, ripple processing, ripple compensation, voltage regulation, and current regulation according to the aforementioned control method to generate a switching control signal for controlling the switching devices.

[0111] In one specific implementation, the main power circuit may employ a totem-pole bridgeless PFC topology, and the switching devices may include high-frequency switching devices for high-frequency switching and power-frequency switching devices for power-frequency commutation. The control system outputs corresponding switching control signals to drive the switching devices to operate, thereby achieving closed-loop control of the totem-pole power factor correction converter.

[0112] To verify the control effect of the above control method and control system, the following explanation is based on a specific totem pole power factor correction converter.

[0113] In this embodiment, the totem-pole power factor correction converter operates in continuous conduction mode, with a rated power of 1kW, a rated input voltage of 220V, a rated grid frequency of 50Hz, an input voltage range of 176V to 275V, a grid frequency range of 49.5Hz to 50.5Hz, a rated DC output voltage of 400V, a boost inductor of 2mH, an output filter capacitor of 940μF, a switching frequency and a sampling frequency of 68kHz, and employs a 32-bit digital signal processor to execute the aforementioned digital control algorithm. The above parameters are merely specific hardware and control parameters for this embodiment and do not constitute a limitation of the present invention.

[0114] Under the aforementioned hardware parameters, the initial value of the first resonant frequency corresponding to the phase-locked loop (PLL) processing can be set to 50Hz, and the initial value of the second resonant frequency corresponding to the ripple processing can be set to 100Hz, using the aforementioned damping coefficient. The ripple amplitude compensation coefficient can be determined based on the 68kHz sampling frequency and the frequency domain amplitude characteristics of the aforementioned zero-order hold circuit. The inner current loop uses a non-ideal damped PR controller, whose resonant frequency can be set to 50Hz, cutoff bandwidth can be set to 10rad / s, and approximately 4kHz is used as the design reference for the crossover frequency; the outer voltage loop uses a PI controller, with approximately 40Hz as the design reference for the crossover frequency. The relevant control parameters can be further determined according to the aforementioned parameter tuning method.

[0115] After completing the above parameter settings, simulation verification was performed on this embodiment under different input voltages, grid frequencies, and load variation conditions.

[0116] like Figure 6 and Figure 7 As shown, the steady-state control performance of the totem-pole power factor correction converter was verified under rated operating conditions of 220V input voltage, 50Hz grid frequency, and 1kW full load. Figure 6 The output voltage and boost inductor current waveforms under rated operating conditions are shown. Figure 7 The results of the input current FFT harmonic analysis under rated operating conditions are shown. Figure 6 It can be seen that under rated operating conditions, the totem-pole power factor correction converter can maintain stable operation, the boost inductor current exhibits periodic changes, and the DC output voltage remains stable; Figure 7 The FFT analysis results shown can further characterize the harmonic components in the input current. Under this operating condition, the total harmonic distortion (THD) of the input current is 3.86%, and the power factor is 0.999, indicating that this embodiment can achieve good input current control and power factor correction performance.

[0117] like Figure 8 and Figure 9As shown, the dynamic response performance of the control method is further verified through load step simulation. Among them, Figure 8 The output voltage and current waveforms are shown when the load suddenly increases from 50% to 100% of the rated load. Figure 9 The output voltage and current waveforms are shown when the load suddenly drops from 100% of the rated load to 50% of the rated load. Figure 8 and Figure 9 It can be seen that when the load undergoes a step change, the output voltage recovers to a stable state after a brief change, and the corresponding current can adjust with the load change. Under the condition of a sudden increase in load of 50% to 100%, the maximum output voltage fluctuation is about 7V, and the recovery time is about 20ms; under the condition of a sudden decrease in load of 100% to 50%, the maximum output voltage fluctuation is about 7V, and the recovery time is about 30ms. This shows that, under the parameter settings of this embodiment, the control method has good load dynamic response capability.

[0118] like Figure 10 and Figure 11 As shown, with the rated power remaining constant, the input voltage was adjusted to 176V to verify the operating performance of the control method under low input voltage conditions. Figure 10 The waveforms of the boost inductor current and output voltage are shown when the input voltage is 176V. Figure 11 The FFT harmonic analysis results for the corresponding input current are shown. Figure 10 It can be seen that under low input voltage conditions, the boost inductor current and output voltage can still maintain a stable periodic operating state; combined with Figure 11 The FFT analysis results show that the input current THD is 3.21% and the power factor is 0.998 under this operating condition. This indicates that, even with a low input voltage of 176V, this embodiment can still maintain good input current control and power factor correction performance.

[0119] like Figure 12 and Figure 13 As shown, with the rated power remaining constant, the input voltage was adjusted to 275V to verify the operating performance of the control method under high input voltage conditions. Figure 12 The waveforms of the boost inductor current and output voltage are shown when the input voltage is 275V. Figure 13 The FFT harmonic analysis results for the corresponding input current are shown. Under this operating condition, the input current THD is 4.16%, and the power factor is 0.999. Combined with... Figure 12 and Figure 13 It can be seen that under a high input voltage of 275V, the totem-pole power factor correction converter can still maintain stable operation and maintain good input current quality.

[0120] The simulation results of the above 176V and 275V input voltage conditions show that, within the 176V to 275V input voltage range used in this embodiment, the control method can maintain the stable closed-loop operation of the totem pole power factor correction converter and obtain a high power factor and a low input current harmonic level.

[0121] like Figure 14 and Figure 15 As shown, with an input voltage of 220V and a rated power of 1kW, the grid frequency was adjusted to 49.5Hz to verify the aforementioned frequency adaptive control mechanism. Figure 14 The waveforms of the boost inductor current and output voltage at a mains frequency of 49.5 Hz are shown. Figure 15 The FFT harmonic analysis results for the corresponding input current are shown. Under this operating condition, the input current THD is 3.85%, and the power factor is 0.999. Since the grid frequency information obtained from the phase-locked loop (PLL) processing is used to update the resonant parameters corresponding to the PLL and ripple processing, the resonant frequency corresponding to the ripple processing can be adjusted accordingly with changes in the grid frequency. Therefore, even when the grid frequency deviates from the rated 50Hz, the system can still maintain stable closed-loop control performance.

[0122] like Figure 16 and Figure 17 As shown, the power grid frequency was further adjusted to 50.5Hz. Figure 16 The waveforms of the boost inductor current and output voltage at a 50.5Hz mains frequency are shown. Figure 17 The FFT harmonic analysis results for the corresponding input current are shown. Under this operating condition, the input current THD is 3.88%, and the power factor is 0.999. Combining the two frequency offset conditions of 49.5Hz and 50.5Hz, it can be seen that within the grid frequency variation range of 49.5Hz to 50.5Hz given in this embodiment, dynamically updating the ripple operating parameters based on the grid frequency information obtained through phase-locked loop processing is beneficial for adapting the ripple processing to changes in grid frequency and maintaining the corresponding closed-loop control performance.

[0123] comprehensive Figures 6-17The simulation results show that, under the hardware and control parameters used in this embodiment, the totem-pole power factor correction converter can maintain stable operation under rated operating conditions, wide input voltage operating conditions, grid frequency deviation operating conditions, and load step operating conditions. Specifically, by multiplexing the same set of second-order generalized integrator operation program instructions for phase-locked loop (PLL) processing and ripple processing, and dynamically updating the ripple operating parameters based on the grid frequency information obtained from PLL processing, the ripple processing can adapt to changes in grid frequency. Furthermore, by combining ripple compensation, voltage outer loop proportional-integral regulation, and current inner loop proportional-resonant regulation, closed-loop control of the DC bus voltage and boost inductor current can be achieved, resulting in good steady-state input current quality and load dynamic response performance.

[0124] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They do not limit the scope of protection of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the claims of the present invention.

Claims

1. A control method for a totem-pole power factor correction converter, characterized in that, Includes the following steps: S1. Obtain the grid input voltage, DC bus voltage, and boost inductor current of the totem pole power factor correction converter; S2. Based on the grid input voltage and the phase-locked operation parameters corresponding to the phase-locked processing, the first calculation is performed by the calculation module, and the phase-locked processing is performed based on the result of the first calculation to obtain grid phase information and grid frequency information. S3. Based on the power grid frequency information, update the ripple operation parameters corresponding to the ripple processing. Within the same control cycle of the first operation and after updating the ripple operation parameters, perform a second operation through the operation module based on the DC bus voltage and the updated ripple operation parameters, and obtain the ripple component in the DC bus voltage based on the result of the second operation. Both the first and second operations are executed by calling the same set of program instructions in the operation module for performing second-order generalized integrator operations. S4. Compensate the DC bus voltage based on the ripple component to obtain a voltage feedback signal; S5. Adjust the voltage based on the voltage feedback signal and the DC bus voltage reference value, and generate a current reference signal by combining the grid phase information; and S6. Adjust the current according to the current reference signal and the boost inductor current to generate a switching control signal for controlling the totem pole power factor correction converter.

2. The control method for the totem-pole power factor correction converter according to claim 1, characterized in that, The phase-locked loop operating parameters include a first resonant angular frequency and a first discrete operation coefficient. Step S2 includes: S21. Based on the grid input voltage, the phase-locked operation parameters and the first state variable group corresponding to the phase-locked processing, the same set of program instructions in the calculation module is called to perform the first calculation to obtain the first in-phase signal and the first quadrature signal, and the first in-phase signal and the first quadrature signal are stored in the first output buffer corresponding to the phase-locked processing. S22. Perform coordinate transformation on the first in-phase signal and the first quadrature signal to obtain the phase error signal; S23. Perform closed-loop adjustment based on the phase error signal to obtain the grid angular frequency estimate, obtain the grid frequency information based on the grid angular frequency estimate, and integrate the grid angular frequency estimate to obtain the grid phase information; S24. Update the first resonant angular frequency according to the estimated value of the power grid angular frequency, and update the first discrete operation coefficient according to the updated first resonant angular frequency.

3. The control method for the totem-pole power factor correction converter according to claim 2, characterized in that, The ripple operating parameters include the second resonant angular frequency and the second discrete operation coefficients. Step S3 includes: S31. Update the second resonant angular frequency to twice the estimated value of the power grid angular frequency, and update the second discrete operation coefficients according to the updated second resonant angular frequency; S32. Based on the DC bus voltage, the updated ripple operating parameters and the second state variable group corresponding to the ripple processing, the same set of program instructions in the operation module is called to perform the second operation to obtain the second in-phase signal and the second quadrature signal, and the second in-phase signal and the second quadrature signal are stored in the second output buffer corresponding to the ripple processing. S33. The second in-phase signal is used as the ripple component in the DC bus voltage.

4. The control method for the totem pole power factor correction converter according to claim 3, characterized in that: The first state variable group and the second state variable group are independent of each other, and the first output buffer and the second output buffer are independent of each other; The first state variable group and the second state variable group respectively include the historical values ​​of the corresponding input signal, the historical values ​​of the in-phase output, and the historical values ​​of the quadrature output.

5. The control method for the totem-pole power factor correction converter according to claim 4, characterized in that: When the first resonant angular frequency or the second resonant angular frequency is updated, the corresponding discrete operation coefficients are updated according to the updated resonant angular frequency, and the historical quantities stored in the corresponding state variable group are maintained; when the same set of program instructions is called again to perform the corresponding first operation or second operation, the second-order generalized integrator operation is performed based on the updated discrete operation coefficients and the maintained historical quantities.

6. The control method for the totem-pole power factor correction converter according to claim 3, characterized in that, Step S4 includes: S41. Based on the sampling period of the digital control system and the frequency of the ripple component, determine the ripple amplitude compensation coefficient based on the frequency domain amplitude characteristics of the zero-order hold element. S42. Perform amplitude compensation on the ripple component according to the ripple amplitude compensation coefficient; S43. Subtract the amplitude-compensated ripple component from the DC bus voltage to obtain the voltage feedback signal; Wherein, the ripple amplitude compensation coefficient K f satisfy: In the formula, ω g Let T be the estimated angular frequency of the power grid. s The sampling period of the digital control system is denoted as .

7. The control method for the totem-pole power factor correction converter according to claim 1, characterized in that, Step S5 includes: S51. Based on the difference between the DC bus voltage reference value and the voltage feedback signal, the current amplitude reference value is obtained through voltage outer loop proportional-integral control; S52. Obtain a sinusoidal phase signal based on the power grid phase information; S53. Multiply the current amplitude reference value with the sinusoidal phase signal to generate the current reference signal.

8. The control method for the totem-pole power factor correction converter according to claim 7, characterized in that, Step S6 includes: S61. Obtain a current error signal based on the current reference signal and the boost inductor current; S62. The current error signal is adjusted by a proportional resonant controller to obtain a pulse width modulation control quantity; S63. Generate the switching control signal according to the pulse width modulation control amount.

9. A control system for a totem-pole power factor correction converter, characterized in that, It includes a sampling module, a calculation module, a phase-locked loop module, a parameter update module, a ripple compensation module, a voltage regulation module, and a current regulation module; The sampling module is used to acquire the grid input voltage, DC bus voltage, and boost inductor current of the totem pole power factor correction converter. The computation module includes a set of program instructions for performing second-order generalized integrator operations, and is used to call the set of program instructions to perform a first operation based on the grid input voltage and the phase-locked operation parameters corresponding to the phase-locked processing. The phase-locked module is used to perform phase-locked processing based on the result of the first calculation to obtain power grid phase information and power grid frequency information; The parameter update module is used to update the ripple operation parameters corresponding to the ripple processing according to the power grid frequency information. The calculation module is also used to, within the same control cycle of the first calculation and after the ripple operating parameters are updated, call the set of program instructions to perform a second calculation based on the DC bus voltage and the updated ripple operating parameters, and obtain the ripple component in the DC bus voltage based on the result of the second calculation. The ripple compensation module is used to compensate the DC bus voltage based on the ripple component to obtain a voltage feedback signal; The voltage regulation module is used to regulate the voltage according to the voltage feedback signal and the DC bus voltage reference value, and to generate a current reference signal in combination with the grid phase information; The current regulation module is used to regulate the current according to the current reference signal and the boost inductor current, and generate a switching control signal for controlling the totem pole power factor correction converter.

10. A totem-pole power factor correction converter, characterized in that, Includes the main power circuit and the control system as described in claim 9; The main power circuit includes a boost inductor and switching devices; The control system is used to acquire the grid input voltage, DC bus voltage and boost inductor current of the main power circuit, and generate the switch control signal to control the switching state of the switching device according to the switch control signal.

Images