A digital power closed-loop adaptive regulation method and system based on lightweight neural network on-chip hardware deployment

Abstract

The application discloses a digital power supply closed-loop adaptive regulation method and system based on lightweight neural network on-chip hardware deployment. The system comprises an ADC sampling quantization module, a state observation module, a full connection neural network inference module, a DPWM module based on DDS and a DC-DC power stage. The network parameters obtained through offline training are written into the on-chip storage unit after fixed-point quantization. During runtime, the output voltage data is digitally processed, and a state observation vector containing the current state and its historical information is constructed. The full connection neural network inference module adopts a multi-MAC parallel multiplexing and inter-layer serial scheduling structure to complete low-delay inference and output control actions. The control actions are subjected to limiting amplitude processing to form a duty cycle control code, which is sent to the DPWM module to generate a PWM signal through a phase accumulation and carry output mode to drive the power stage. The application realizes real-time hardware closed-loop control of the neural network control strategy in the digital power supply.

Description

Technical Field

[0001] This invention relates to the field of digital power control and intelligent hardware acceleration technology, and in particular to a digital power closed-loop adaptive regulation method and system based on lightweight neural network on-chip hardware deployment. Background Technology

[0002] DC-DC converters are widely used in on-chip power management, embedded systems, communication equipment, server power supply, and DC microgrids. With the increasing speed of load dynamic changes and the rise in system power density, digital power control systems face higher demands for control accuracy, transient response speed, and robustness. Neural network-based control strategies have been used in DC-DC converter control and can be trained offline to adapt to different operating conditions. However, existing solutions largely focus on algorithm training, simulation verification, or control performance comparison, with insufficient attention paid to the real-time deployment and closed-loop operation of the trained control strategy in digital hardware.

[0003] In practical digital power systems, the ADC sampling and quantization module continuously digitizes the output voltage sampling data and generates a state update trigger signal according to the switching cycle. After the state update trigger signal is valid, the controller needs to complete the state observation update, fully connected neural network forward inference, duty cycle control code formation, and DPWM duty cycle update within one switching cycle. For DC-DC converters with MHz-level switching frequencies, this closed-loop calculation time is usually strictly limited. If a completely serial neural network computing structure is used, the inference delay is difficult to meet the real-time control requirements; if a fully expanded parallel structure is used, it will significantly increase the number of multipliers, area, and power consumption, which is not conducive to FPGA or ASIC implementation.

[0004] Furthermore, the DPWM module is a crucial interface for converting digital control actions into power switch drive signals, and its resolution, linearity, and monotonicity directly affect the output voltage regulation effect. Insufficient DPWM resolution can easily introduce quantization errors and may lead to steady-state limiting cycle oscillations. Traditional counter-type DPWM structures are simple, but their resolution is limited by both the system clock frequency and the switching frequency; at MHz-level switching frequencies, improving resolution usually requires a significant increase in the system clock frequency. While delayed linear or multiphase clock-type DPWM can improve the equivalent resolution, they suffer from issues such as timing calibration, PVT sensitivity, and clock design complexity. Therefore, a digital power supply closed-loop control scheme is needed for deployment in neural network controller hardware, enabling low-latency neural network inference with limited hardware resources, and combining it with a DPWM structure that has good linearity and monotonicity to complete real-time closed-loop control. Summary of the Invention

[0005] To address the issue that existing neural network-based control strategies often remain at the algorithm training and simulation verification stage, making it difficult to directly meet the real-time hardware closed-loop control requirements of digital power supplies, this invention proposes a digital power supply closed-loop adaptive control method and system based on lightweight neural network on-chip hardware deployment. This method converts the offline-trained control strategy into a deployable digital hardware structure. Through ADC sampling quantization, state observation updates, fully connected neural network hardware inference, action limiting processing, and DDS-based DPWM duty cycle updates, the real-time hardware closed-loop operation of the offline-trained neural network control strategy in the DC-DC converter is achieved.

[0006] The technical solution of the present invention is as follows:

[0007] A closed-loop adaptive control method for digital power supply based on lightweight neural network on-chip hardware deployment includes the following steps:

[0008] S1. The output voltage of the DC-DC converter is sampled and digitally quantized by ADC to obtain the digital state quantity corresponding to the output voltage;

[0009] S2. Generate a state update trigger signal according to a preset switching cycle, and latch and update the digital state quantity sampled and quantized by the ADC based on the state update trigger signal;

[0010] S3. Construct a state observation vector based on the current output voltage, reference voltage, and historical state information. The state observation vector includes at least the current output voltage, current error, output voltage at the previous moment, and error at the previous moment.

[0011] S4. Input the state observation vector into the fully connected neural network inference module. The fully connected neural network inference module loads the network parameters obtained through offline training and fixed-point quantization, and generates control actions through hardware forward inference.

[0012] S5. Perform action limiting processing on the control action to form a duty cycle control code that meets the DPWM input range and bit width constraints;

[0013] S6. Input the duty cycle control code into the DDS-based DPWM module, and the DPWM module generates a PWM signal through phase accumulation and carry output.

[0014] S7. Use the PWM signal to drive the power stage of the DC-DC converter, so that the output voltage of the DC-DC converter participates in the sampling quantization and closed-loop control of the next switching cycle.

[0015] Furthermore, the state update trigger signal is generated by ADC clock division counting;

[0016] The frequency of the state update trigger signal is matched with the switching frequency of the DC-DC converter, so that state observation, fully connected neural network inference and DPWM duty cycle update are executed sequentially within the same control cycle.

[0017] The digital state quantity output by the ADC sampling and quantization is latched by the state observation module when the state update trigger signal is valid;

[0018] State observation update, forward inference of fully connected neural network, duty cycle control code formation and DPWM duty cycle update are completed within one switching cycle to meet the real-time hardware closed-loop control constraints at a switching frequency of 1 MHz.

[0019] Furthermore, when the state update trigger signal is valid, the current output voltage and current error saved in the previous sampling period are respectively used as the output voltage and error of the previous moment.

[0020] The current sampling period's ADC sampled and quantized output voltage and its error with the reference voltage are updated to the current output voltage and the current error, respectively, thereby constructing the state observation vector;

[0021] The error is obtained by subtracting the digital value corresponding to the reference voltage from the digital value of the output voltage after sampling and quantization by the ADC, and is input into the fully connected neural network inference module in the form of a signed fixed-point number.

[0022] Furthermore, the weights and biases in the fully connected neural network inference module are obtained through offline training and stored in on-chip storage units after fixed-point quantization;

[0023] The fully connected neural network inference module adopts a lightweight computing structure with multi-MAC parallel multiplexing and inter-layer serial scheduling;

[0024] Within each layer, parallel multiplication and accumulation calculations are performed based on the number of neurons and the input dimension, and forward inference is performed sequentially between adjacent network layers according to the calculation order of the network layers.

[0025] Furthermore, the fully connected neural network inference module employs several MAC units to perform network computation;

[0026] In the first layer, several MAC units correspond to several neurons, and the input dimension is time-division multiplexed;

[0027] In the second layer, a grouped parallel approach is used to improve the utilization of the MAC unit;

[0028] In the output layer, multi-path parallel multiplication and multi-level addition trees are used to perform weighted summation of the output neurons.

[0029] Furthermore, the action limiting processing is used to limit the control action output by the fully connected neural network inference module to a preset duty cycle range, and to form a duty cycle control code that matches the input range and bit width of the DPWM module.

[0030] The duty cycle control code is an L-bit digital value used to determine the duration of the high level of the PWM signal within one switching cycle.

[0031] Furthermore, the DDS-based DPWM module includes a phase accumulator, a phase interception unit, and a carry output unit;

[0032] The switching frequency of the DPWM output signal is set according to the frequency control word, and the phase accumulator accumulates according to the frequency control word under the action of the clock.

[0033] The phase truncation unit extracts the highest L bit from the phase accumulation result as the digital sawtooth carrier.

[0034] The carry-out unit adds the digital sawtooth carrier to the duty cycle control code and generates a PWM signal based on the carry bit of the addition result.

[0035] The present invention also provides a digital power closed-loop adaptive control system based on lightweight neural network on-chip hardware deployment, including an ADC sampling and quantization module, a state observation module, a fully connected neural network inference module, a DDS-based DPWM module, and a DC-DC power stage;

[0036] The ADC sampling and quantization module, state observation module, fully connected neural network inference module, DDS-based DPWM module and DC-DC power stage are connected in sequence, and the output of the DC-DC power stage is fed back to the ADC sampling and quantization module to form a real-time hardware closed loop.

[0037] The real-time hardware closed loop is used to deploy the neural network control strategy obtained from offline training and to realize the output voltage regulation of the DC-DC converter under the real-time switching cycle constraint.

[0038] The ADC sampling and quantization module is used to digitize the output voltage sampling data of the DC-DC power stage to obtain digital state quantities;

[0039] The state observation module is used to construct a state observation vector based on the digital state quantity, the reference voltage digital quantity, and the historical state.

[0040] The fully connected neural network inference module is used to load the network parameters obtained from offline training and fixed-point quantization, and generate control actions based on the state observation vector. The control actions are then processed by action limiting to form a duty cycle control code.

[0041] The DDS-based DPWM module is used to generate a PWM signal according to the duty cycle control code;

[0042] The DC-DC power stage is used to adjust the output voltage under the drive of the PWM signal and feed the output voltage back to the ADC sampling and quantization module to form a hardware closed loop.

[0043] Furthermore, the fully connected neural network inference module includes an input interface, a parameter storage unit, a first hidden layer, a second hidden layer, an output layer, and an output interface;

[0044] The input interface is used to receive the state observation vector output by the state observation module; the parameter storage unit is used to store the network weights and biases after fixed-point quantization.

[0045] Both the first and second hidden layers include a multiply-accumulate array and an activation function unit. The multiply-accumulate array adopts a multi-MAC parallel multiplexing structure, which calculates the multiply-accumulate results of multiple neurons in parallel within a single network layer and is time-division multiplexed on the input dimension. The activation function unit is used to perform nonlinear mapping on the multiply-accumulate results of the hidden layer.

[0046] The output layer includes a multiplication calculation unit and an addition tree;

[0047] The multiplication calculation unit is used to perform parallel multiplication calculations on the output of the second hidden layer and the corresponding weights of the output layer, and the resulting multiplication results are input into the addition tree.

[0048] The addition tree is used to perform parallel reduction and summation on the multiplication results of the output layer to obtain the inference results of the fully connected neural network.

[0049] The output interface is used to output the inference result of the fully connected neural network and the inference completion flag.

[0050] Furthermore, the DDS-based DPWM module includes an N-bit phase accumulator and an L-bit duty cycle control code input terminal, wherein N is greater than or equal to L;

[0051] The high L bits of the N-bit phase accumulator are used as a digital sawtooth carrier and added to the L-bit duty cycle control code. The carry bit of the addition result is used to generate a PWM output signal.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] First, this invention transforms the neural network control strategy obtained through offline training into a deployable and real-time operational digital hardware structure, enabling the neural network control method to go beyond simulation verification and be used for hardware closed-loop control of DC-DC converters. Because the fully connected neural network inference module generates control actions in real time based on the current output voltage, error, and historical state variables, it can adjust the duty cycle according to changes in the DC-DC converter's operating state, thereby achieving closed-loop adaptive control.

[0054] Second, this invention employs a fully connected neural network inference structure with multi-MAC parallel multiplexing and inter-layer serial scheduling, achieving a trade-off between fully serial computation and fully parallel deployment. This structure can reduce the number of multipliers and hardware resource overhead while meeting the low-latency inference requirements within switching cycles.

[0055] Third, the present invention adopts a DDS-based DPWM structure, which generates PWM signals through phase accumulation and carry output. Compared with traditional counter-type DPWM, it is beneficial to improve the linearity and monotonicity of digital pulse width modulation output and reduce the dependence on ultra-high system clock at high switching frequencies.

[0056] Fourth, this invention forms a complete digital hardware closed-loop control link from ADC sampling and quantization, state observation, fully connected neural network hardware inference to PWM drive output. It has good real-time performance, configurability and engineering implementation value, and can be used for FPGA verification of digital power controllers or subsequent ASIC integration implementation. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the overall structure of the digital power supply hardware closed-loop control system of the present invention;

[0058] Figure 2 This is a schematic diagram of the fully connected neural network hardware inference architecture of the present invention;

[0059] Figure 3 This is a schematic diagram of the DPWM module structure based on DDS of the present invention;

[0060] Figure 4 This is a schematic diagram illustrating the timing of hardware closed-loop state update, inference, and duty cycle update in this invention. Detailed Implementation

[0061] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be understood that the following embodiments are only for illustrating the present invention and are not intended to limit the scope of protection of the present invention. Without departing from the technical concept of the present invention, those skilled in the art can make equivalent adjustments to the network size, fixed-point bit width, sampling frequency, switching frequency, and DPWM bit width.

[0062] The present invention discloses a digital power supply closed-loop adaptive control method based on lightweight neural network on-chip hardware deployment, comprising the following steps:

[0063] First, the output voltage of the DC-DC converter is sampled and digitally quantized using an ADC to obtain a digital state quantity corresponding to the output voltage. A state update trigger signal is generated according to a preset switching cycle, and the state observation data is updated when the state update trigger signal is valid to construct a state observation vector.

[0064] Secondly, a state observation vector is constructed based on the current output voltage, reference voltage, and historical state information. This state observation vector includes at least the current output voltage, current error, previous output voltage, and previous error. By introducing historical state variables, the fully connected neural network inference module can obtain temporal changes in the output voltage and error.

[0065] Then, the state observation vector is input into the fully connected neural network inference module. The fully connected neural network inference module loads the network parameters obtained from offline training and after fixed-point quantization, and generates control actions through hardware forward inference. The fully connected neural network inference module adopts a multi-MAC parallel multiplexing and inter-layer serial scheduling structure to complete low-latency inference with limited hardware resources. Specifically, the multiply-accumulate array calculates the multiply-accumulate results of multiple neurons in parallel within a single network layer and reuses them in a time-division multiplexing manner along the input dimension; the output layer uses multi-path parallel multiplication and an addition tree to achieve reduction and summation.

[0066] The control action is subjected to action limiting processing to form a duty cycle control code that meets the DPWM input range and bit width constraints. After the duty cycle control code is input to the DDS-based DPWM module, it is accumulated by a phase accumulator according to the frequency control word, and the high-order bits are truncated from the phase accumulation result as a digital sawtooth carrier. The digital sawtooth carrier is added to the duty cycle control code, and a PWM signal is generated based on the carry bit of the addition result. The PWM signal is used to drive the power stage of the DC-DC converter, thereby enabling the output voltage to enter the sampling, quantization, and closed-loop control process of the next switching cycle.

[0067] This invention also proposes a digital power supply closed-loop adaptive control system based on lightweight neural network on-chip hardware deployment, including an ADC sampling and quantization module, a state observation module, a fully connected neural network inference module, a DDS-based DPWM module, and a DC-DC power stage.

[0068] The ADC sampling and quantization module digitizes the output voltage sampling data of the DC-DC power stage to obtain digital state variables. The state observation module constructs a state observation vector based on the digital state variables, the reference voltage digital value, and historical states. The fully connected neural network inference module loads the offline-trained and fixed-point quantized network parameters and generates control actions based on the state observation vector; the control actions are then processed by action limiting to form a duty cycle control code. The DDS-based DPWM module generates a PWM signal based on the duty cycle control code. The DC-DC power stage adjusts its output voltage under the drive of the PWM signal and feeds the output voltage back to the ADC sampling and quantization module, forming a real-time hardware closed loop.

[0069] like Figure 1 As shown, this embodiment provides a digital power supply closed-loop adaptive control system based on lightweight neural network on-chip hardware deployment. The system includes an ADC sampling and quantization module, a state observation module, a fully connected neural network inference module, a DDS-based DPWM module, and a DC-DC power stage. The ADC sampling and quantization module digitizes the output voltage sampling data of the DC-DC power stage to obtain digital state quantities. The state observation module constructs a state observation vector based on the digital output voltage, the digital reference voltage, and historical state information. The fully connected neural network inference module loads the network parameters obtained through offline training and fixed-point quantization, and generates control actions based on the state observation vector. The control actions are processed by action limiting to form a duty cycle control code, which is then input to the DDS-based DPWM module. The DDS-based DPWM module outputs a PWM signal to drive the DC-DC power stage, and the power stage output voltage is then fed back to the ADC sampling and quantization module, thereby forming real-time hardware closed-loop control.

[0070] I. Construction of ADC Sampling Quantization and State Observation

[0071] In this embodiment, the ADC sampling and quantization module operates in the ADC sampling clock domain to receive raw ADC sampling data and perform digitization processing on it. This digitization processing includes, but is not limited to, sampling data latching, gain correction, bias correction, and fixed-point processing, and outputs a digital state quantity corresponding to the output voltage. As one implementation, when the ADC clock frequency is 50 MHz, a 1 MHz state update trigger signal can be generated every 50 ADC clock cycles through frequency division.

[0072] The state observation module, the fully connected neural network inference module, and the DDS-based DPWM module operate in the 200 MHz control clock domain. The state update trigger signal is used to trigger the state observation module to latch the current ADC sampling and quantization result and update the current and historical states. If the control clock frequency is 200 MHz and the switching frequency is 1 MHz, then from the effective start of the state update trigger signal, the state observation update, the fully connected neural network forward inference, the duty cycle control code formation, and the DPWM duty cycle update need to be completed within 200 control clock cycles to meet the timing constraints of real-time closed-loop control within one switching cycle.

[0073] Let the digital output voltage of the ADC after sampling and quantization in the k-th sampling period be... The digital quantity corresponding to the reference voltage is Then the error can be expressed as:

[0074]

[0075] in, This represents the current error. To enable the fully connected neural network inference module to obtain the timing changes of the output voltage and error signal, the state observation module latches the current ADC sampling and quantization result when the state update trigger signal is valid, and uses it as the current digital output voltage. According to the digital value of the reference voltage With the current output voltage digital quantity Calculate the current error Simultaneously, the digital output voltage and error from the previous sampling period are updated to the output voltage from the previous moment. Error compared to the previous time step As one implementation method, the state observation vector can be represented as:

[0076]

[0077] in, Indicates the current output voltage. Indicates the current error. This indicates the output voltage at the previous moment. This represents the error at the previous time step. The above state variables can be represented using signed fixed-point numbers and input into the fully connected neural network inference module.

[0078] The state observation vector can also be extended to more dimensions, such as including input voltage, inductor current, output current, reference voltage, output voltage error, and its historical state quantities. As long as the state observation vector can reflect the current operating state of the DC-DC converter and its dynamic change trend, it falls within the protection scope of this invention.

[0079] II. Fully Connected Neural Network Inference Module

[0080] In this embodiment, the neural network for digital power regulation is trained offline. The network's weights and bias parameters are written to on-chip memory after fixed-point quantization.

[0081] The neural network employs a three-layer fully connected structure with a network size of 4→20→10→1. The input includes four state inputs, the first hidden layer contains 20 neurons, the second hidden layer contains 10 neurons, and the output layer contains one output neuron. The hidden layer activation function is the ReLU function. The output layer network inference result is mapped using the Sigmoid function to represent the control action, and further processed by action limiting to form a duty cycle control code. The inputs, weights, and biases in the network can be represented in fixed-point format. For example, the input state and network parameters can be represented using 16-bit fixed-point numbers, and the multiplication and accumulation results are stored with a higher bit width to reduce the risk of overflow during accumulation. When the state observation vector is expanded to more dimensions, the size of the neural network input layer can also be expanded accordingly. Adjusting the network size under different input dimensions does not affect the hardware implementation concept of multi-MAC parallel multiplexing and inter-layer serial scheduling described in this invention.

[0082] like Figure 2 As shown, the fully connected neural network inference module includes an input interface, a parameter storage unit, a first hidden layer, a second hidden layer, an output layer, and an output interface. The input interface receives the state observation vector output by the state observation module. The parameter storage unit stores the network weights and biases after fixed-point quantization. Both the first and second hidden layers include a multiply-accumulate array and an activation function unit. The multiply-accumulate array adopts a multi-MAC parallel multiplexing structure, which calculates the multiply-accumulate results of multiple neurons in parallel within a single network layer and is time-division multiplexed on the input dimension. The activation function unit performs nonlinear mapping on the multiply-accumulate results of the hidden layers. The output layer includes a multiplication calculation unit and an addition tree. The addition tree performs parallel reduction and summation on the multiplication results of the output layer to obtain the fully connected neural network inference result. The output interface outputs the fully connected neural network inference result and an inference completion flag.

[0083] If the fully connected network of 4→20→10→1 is fully expanded, the first layer requires 4×20 multipliers, the second layer requires 20×10 multipliers, and the output layer requires 10×1 multipliers, for a total of 290 multipliers. Although this method has low latency, it has a large area and power consumption, which is not conducive to the integration of digital power controllers into FPGAs or ASICs. If only a single MAC unit is used for full serial multiplexing, the hardware resources are limited, but the computational latency is long, making it difficult to meet the real-time control constraints at MHz-level switching frequencies. Therefore, this embodiment uses 20 MAC units to form a multiply-accumulate array and adopts a lightweight structure with inter-layer serial and intra-layer parallel multiplexing.

[0084] The first layer has a 4→20 structure. In this layer, 20 MAC units correspond to 20 neurons in the first hidden layer. The state input dimension uses time-division multiplexing to input to the multiply-accumulate array. In each computation cycle, an input state variable is broadcast to the 20 MAC units, and each MAC unit reads the weights of its corresponding neuron and simultaneously performs the multiply-accumulate operation. After time-division computation across the four input dimensions, the multiply-accumulate result of the 20 neurons in the first hidden layer is obtained. Then, ReLU activation is applied to obtain the output of the first hidden layer.

[0085] The second layer has a 20→10 structure. To improve the utilization of MAC units, this embodiment adopts a grouped parallel computing method, that is, for each neuron in the second hidden layer, two MAC units are allocated to process two input dimensions in parallel. Since the second layer includes 10 neurons, 20 MAC units can simultaneously correspond to 10 neurons. Each computation cycle processes two input dimensions, and the multiplication and accumulation calculation of 20 input dimensions can be completed after 10 computation cycles. Then, ReLU activation is used to obtain the output of the second hidden layer.

[0086] The output layer has a 10→1 structure. Since the output layer has only one output neuron, this embodiment uses parallel multiplication and a multi-level addition tree structure to reduce the output layer latency. Specifically, 10 MAC units in the multiply-accumulate array are used to perform multiplication operations on the 10 outputs of the second hidden layer with their corresponding weights in parallel, and the resulting multiplications are input into the addition tree for reduction and summation. The addition tree can be implemented using a multi-level structure. The reduction and summation result is then passed through a sigmoid function to obtain the final network inference result.

[0087] Through the above structure, the fully connected neural network inference module achieves a trade-off between hardware resources and inference latency. This structure avoids the problem of excessive multiplier resources caused by full expansion, and also avoids the problem of excessive inference time caused by single MAC serial multiplexing, thus meeting the real-time hardware inference requirements of digital power controllers at MHz-level switching frequencies.

[0088] III. DDS-based DPWM module

[0089] The control action output by the fully connected neural network inference module is used to characterize the duty cycle of the next switching cycle. To avoid the control action exceeding the safe operating range of the power stage, this embodiment limits the control action to a preset safe duty cycle range. As one implementation method, the safe duty cycle range is... The limited control action generates a duty cycle control code based on the DPWM input bit width. As one implementation method, when the DPWM input bit width is... At that time, duty cycle control code It can be represented as:

[0090]

[0091] in, For the control actions after amplitude limiting, For input to the DDS-based DPWM module The duty cycle control code is used to determine the duration of the high level of the PWM signal within one switching cycle.

[0092] like Figure 3 As shown, the DDS-based DPWM module includes a phase accumulator, a phase extraction unit, and a carry output unit. The phase accumulator is used to accumulate phase according to the frequency control word under the action of the system clock. The phase extraction unit is used to extract the high-order bits from the phase accumulation result to form a digital sawtooth carrier. The carry output unit is used to add the digital sawtooth carrier to the duty cycle control code and generate a PWM signal according to the carry bit of the addition result.

[0093] As one implementation method, let the system clock frequency be... The target switching frequency is The phase accumulator bit width is The frequency control word is Then the switching frequency satisfies:

[0094]

[0095] in, This is the bit width of the phase accumulator. The phase accumulator is updated in each clock cycle according to the following formula:

[0096]

[0097] in, For the first The phase accumulation value over one clock cycle. As one specific implementation, when... At that time, the frequency control word can be:

[0098]

[0099] To match the phase accumulation result with the DPWM input bit width, the phase truncation unit from High-frequency extraction from phase accumulation value Position, obtained Bit-digit sawtooth carrier:

[0100]

[0101] in, To control the code bit width for duty cycle, For digital sawtooth carrier. As one implementation method, when... hour, It is a 10-bit digital carrier, with a value range of 0 to 1023.

[0102] The carry-out unit will output the digital sawtooth carrier. With duty cycle control code Add:

[0103]

[0104] The carry bit of the addition result is then used as the PWM output.

[0105]

[0106] in, The duty cycle control code is obtained by applying action limiting to the inference result of a fully connected neural network. This indicates the carry bit in the addition operation. In other words, when a carry is generated by adding the digital sawtooth carrier and the duty cycle control code, the PWM output is high; when no carry is generated, the PWM output is low.

[0107] Compared to traditional counter-comparison type DPWM, this structure utilizes phase accumulation to form a digital sawtooth carrier and employs an addition-carry method to generate the PWM signal, eliminating the need to store a complete PWM waveform lookup table. The PWM output frequency can be adjusted by changing the frequency control word, and the PWM high-level duration can be adjusted by changing the duty cycle control code. This method is advantageous for achieving linear, monotonic digital pulse width modulation output and is suitable for real-time hardware closed-loop control of the duty cycle control code output by a neural network controller.

[0108] IV. Overall Closed-Loop Working Sequence

[0109] like Figure 4As shown, in this embodiment, the control clock frequency is 200MHz. The ADC sampling and quantization module digitizes the ADC sampling data corresponding to the DC-DC converter output voltage and maps the original ADC data to a fixed-point voltage digital quantity. Under the ADC clock, the ADC sampling and quantization module generates a 1 MHz state update trigger signal by decimation counting. The interval between two consecutive valid pulses of this signal is one switching cycle.

[0110] The state observation module receives the fixed-point voltage digital value output by the ADC sampling and quantization module. When the 1MHz state update trigger signal is valid, the state observation module latches the current ADC sampling and quantization result, calculates the error between the output voltage and the reference voltage, and updates the current state and historical states to construct a state observation vector for inference of the fully connected neural network. After the state update is completed, the state observation module outputs a valid signal, indicating that the state observation vector for this cycle is valid.

[0111] After the state observation module outputs a valid signal, the fully connected neural network inference module starts forward inference. Upon completion of inference, it outputs a valid signal indicating the neural network calculation result. Subsequently, the network output result undergoes action limiting processing to form a duty cycle control code, and a valid duty cycle control code signal is output.

[0112] When the output duty cycle control code is valid, the DDS-based DPWM module adopts the duty cycle control code obtained from the neural network inference and generates a valid DPWM duty cycle update signal. After the new duty cycle control code is adopted, the DDS-based DPWM module updates the subsequent PWM drive waveform according to this duty cycle control code. In other words, the PWM duty cycle update is triggered by the valid signal output by the neural network, thereby ensuring that the PWM drive signal corresponds to the neural network inference result of the current cycle.

[0113] The time from the 1 MHz state update trigger signal to the valid DPWM duty cycle update signal is less than 1 µs, which is one switching cycle. Therefore, the system can complete state observation, fully connected neural network inference, duty cycle control code formation, and DPWM duty cycle update before the next 1 MHz state update trigger signal arrives, realizing real-time hardware closed-loop control of the neural network control strategy obtained through offline training.

[0114] Through the above implementation methods, this invention transforms the control strategy obtained through offline training into a deployable hardware inference structure, and combines it with a DDS-based DPWM module to form a complete digital power supply closed-loop control link. This system maintains the adaptive control capability of the offline-trained neural network control strategy while meeting the requirements of digital power supply systems for real-time performance, timing determinism, and engineering feasibility.

Claims

1. A digital power supply closed-loop adaptive control method based on lightweight neural network on-chip hardware deployment, characterized in that, Includes the following steps: S1. The output voltage of the DC-DC converter is sampled and digitally quantized by ADC to obtain the digital state quantity corresponding to the output voltage; S2. Generate a state update trigger signal according to a preset switching cycle, and latch and update the digital state quantity sampled and quantized by the ADC based on the state update trigger signal; S3. Construct a state observation vector based on the current output voltage, reference voltage, and historical state information. The state observation vector includes at least the current output voltage, current error, output voltage at the previous moment, and error at the previous moment. S4. Input the state observation vector into the fully connected neural network inference module. The fully connected neural network inference module loads the network parameters obtained through offline training and fixed-point quantization, and generates control actions through hardware forward inference. S5. Perform action limiting processing on the control action to form a duty cycle control code that meets the DPWM input range and bit width constraints; S6. Input the duty cycle control code into the DDS-based DPWM module, and the DPWM module generates a PWM signal through phase accumulation and carry output. S7. Use the PWM signal to drive the power stage of the DC-DC converter, so that the output voltage of the DC-DC converter participates in the sampling quantization and closed-loop control of the next switching cycle.

2. The digital power supply closed-loop adaptive control method based on lightweight neural network on-chip hardware deployment according to claim 1, characterized in that, The state update trigger signal is generated by ADC clock frequency division and counting; The frequency of the state update trigger signal is matched with the switching frequency of the DC-DC converter, so that state observation, fully connected neural network inference and DPWM duty cycle update are executed sequentially within the same control cycle. The digital state quantity output by the ADC sampling and quantization is latched by the state observation module when the state update trigger signal is valid; State observation update, forward inference of fully connected neural network, duty cycle control code formation and DPWM duty cycle update are completed within one switching cycle to meet the real-time hardware closed-loop control constraints at a switching frequency of 1 MHz.

3. The digital power supply closed-loop adaptive control method based on lightweight neural network on-chip hardware deployment according to claim 1 or 2, characterized in that, When the state update trigger signal is valid, the current output voltage and current error saved in the previous sampling period are used as the output voltage and error of the previous moment, respectively. The current sampling period's ADC sampled and quantized output voltage and its error with the reference voltage are updated to the current output voltage and the current error, respectively, thereby constructing the state observation vector; The error is obtained by subtracting the digital value corresponding to the reference voltage from the digital value of the output voltage after sampling and quantization by the ADC, and is input into the fully connected neural network inference module in the form of a signed fixed-point number.

4. The digital power supply closed-loop adaptive control method based on lightweight neural network on-chip hardware deployment according to claim 1, characterized in that, The weights and biases in the fully connected neural network inference module are obtained through offline training and stored in on-chip storage units after fixed-point quantization. The fully connected neural network inference module adopts a lightweight computing structure with multi-MAC parallel multiplexing and inter-layer serial scheduling; Within each layer, parallel multiplication and accumulation calculations are performed based on the number of neurons and the input dimension, and forward inference is performed sequentially between adjacent network layers according to the calculation order of the network layers.

5. The digital power supply closed-loop adaptive control method based on lightweight neural network on-chip hardware deployment according to claim 4, characterized in that, The fully connected neural network inference module uses several MAC units to perform network computation; In the first layer, several MAC units correspond to several neurons, and the input dimension is time-division multiplexed; In the second layer, a grouped parallel approach is used to improve the utilization of MAC units; In the output layer, multi-path parallel multiplication and multi-level addition trees are used to perform weighted summation of the output neurons.

6. The digital power supply closed-loop adaptive control method based on lightweight neural network on-chip hardware deployment according to claim 1, characterized in that, The action limiting processing is used to limit the control action output by the fully connected neural network inference module to a preset duty cycle range, and to form a duty cycle control code that matches the input range and bit width of the DPWM module. The duty cycle control code is an L-bit digital value used to determine the duration of the high level of the PWM signal within one switching cycle.

7. The digital power supply closed-loop adaptive control method based on lightweight neural network on-chip hardware deployment according to claim 1 or 6, characterized in that, The DDS-based DPWM module includes a phase accumulator, a phase interception unit, and a carry output unit. The switching frequency of the DPWM output signal is set according to the frequency control word, and the phase accumulator accumulates according to the frequency control word under the action of the clock. The phase truncation unit extracts the highest L bit from the phase accumulation result as the digital sawtooth carrier. The carry-out unit adds the digital sawtooth carrier to the duty cycle control code and generates a PWM signal based on the carry bit of the addition result.

8. A digital power supply closed-loop adaptive control system based on lightweight neural network on-chip hardware deployment, characterized in that, It includes an ADC sampling and quantization module, a state observation module, a fully connected neural network inference module, a DDS-based DPWM module, and a DC-DC power stage; The ADC sampling and quantization module, state observation module, fully connected neural network inference module, DDS-based DPWM module and DC-DC power stage are connected in sequence, and the output of the DC-DC power stage is fed back to the ADC sampling and quantization module to form a real-time hardware closed loop. The real-time hardware closed loop is used to deploy the neural network control strategy obtained from offline training and to realize the output voltage regulation of the DC-DC converter under the real-time switching cycle constraint. The ADC sampling and quantization module is used to digitize the output voltage sampling data of the DC-DC power stage to obtain digital state quantities; The state observation module is used to construct a state observation vector based on the digital state quantity, the reference voltage digital quantity, and the historical state. The fully connected neural network inference module is used to load the network parameters obtained from offline training and fixed-point quantization, and generate control actions based on the state observation vector. The control actions are then processed by action limiting to form a duty cycle control code. The DDS-based DPWM module is used to generate a PWM signal according to the duty cycle control code; The DC-DC power stage is used to adjust the output voltage under the drive of the PWM signal and feed the output voltage back to the ADC sampling and quantization module to form a hardware closed loop.

9. The digital power closed-loop adaptive control system based on lightweight neural network on-chip hardware deployment according to claim 8, characterized in that, The fully connected neural network inference module includes an input interface, a parameter storage unit, a first hidden layer, a second hidden layer, an output layer, and an output interface; The input interface is used to receive the state observation vector output by the state observation module; The parameter storage unit is used to store the network weights and biases after fixed-point quantization; Both the first and second hidden layers include a multiply-accumulate array and an activation function unit. The multiply-accumulate array adopts a multi-MAC parallel multiplexing structure, which calculates the multiply-accumulate results of multiple neurons in parallel within a single network layer and is time-division multiplexed on the input dimension. The activation function unit is used to perform nonlinear mapping on the multiply-accumulate results of the hidden layer. The output layer includes a multiplication calculation unit and an addition tree; The multiplication calculation unit is used to perform parallel multiplication calculations on the output of the second hidden layer and the corresponding weights of the output layer, and the resulting multiplication results are input into the addition tree. The addition tree is used to perform parallel reduction and summation on the multiplication results of the output layer to obtain the inference results of the fully connected neural network. The output interface is used to output the inference result of the fully connected neural network and the inference completion flag.

10. The digital power supply closed-loop adaptive control system based on lightweight neural network on-chip hardware deployment according to claim 8 or 9, characterized in that, The DDS-based DPWM module includes an N-bit phase accumulator and an L-bit duty cycle control code input, where N is greater than or equal to L. The high L bits of the N-bit phase accumulator are used as a digital sawtooth carrier and added to the L-bit duty cycle control code. The carry bit of the addition result is used to generate a PWM output signal.

Images