Charge pump circuit and electronic device

Abstract

The present disclosure provides a charge pump circuit and an electronic device, and relates to the technical field of integrated circuits. The charge pump circuit comprises: a charge pump module receiving a first clock signal output by a clock driving module, an input end being electrically connected with a voltage regulating module to input a control voltage, and an output end being electrically connected with a voltage dividing module; the voltage dividing module is electrically connected with a first input end of a voltage comparison module; a second input end of the voltage comparison module receives a reference voltage, and an output end is electrically connected with the voltage regulating module; a first end of the voltage regulating module is electrically connected with a power supply, a second end is electrically connected with an oscillator and the clock driving module, so as to provide the control voltage to the oscillator and the clock driving module; the oscillator is electrically connected with the clock driving module, so as to output a second clock signal to the clock driving module; and the clock driving module is electrically connected with the charge pump module, so as to provide the first clock signal to the charge pump module, which can effectively reduce the output ripple of the charge pump circuit and reduce the power consumption of the circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a charge pump circuit and electronic device. Background Technology

[0002] In integrated circuits, voltage is generated by charge pump circuits to power the chip. Charge pump circuits typically include a charge pump, an oscillator, and a clock drive module.

[0003] In related technologies, a power supply is typically used to power the oscillator and clock drive module. However, in a wide voltage range, when the power supply voltage is high, if the power supply voltage is directly supplied to the oscillator and clock drive module, the clock amplitude delivered to the charge pump will be high, which can easily lead to large ripples in the output voltage after the charge pump stabilizes, resulting in high power consumption of the charge pump. Summary of the Invention

[0004] This disclosure provides a charge pump circuit and electronic device, which at least to some extent overcomes the problems in the related art where using a power supply to power the charge pump circuit easily leads to large output voltage ripple and high power consumption of the charge pump after it has stabilized.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a charge pump circuit is provided, comprising a charge pump module, a voltage divider module, a voltage comparator module, a voltage regulation module, an oscillator, and a clock drive module, wherein:

[0007] The charge pump module receives the first clock signal output by the clock drive module. The input terminal of the charge pump module is electrically connected to the voltage regulation module for inputting the control voltage output by the voltage regulation module. The output terminal of the charge pump module is electrically connected to the voltage divider module.

[0008] The voltage divider module is electrically connected to the first input terminal of the voltage comparison module, and is used to divide the first voltage value output by the charge pump module, and input the second voltage value obtained after voltage division to the first input terminal of the voltage comparison module.

[0009] The second input terminal of the voltage comparison module receives a reference voltage, and the output terminal of the voltage comparison module is electrically connected to the voltage regulation module.

[0010] The first terminal of the voltage regulation module is electrically connected to the power supply, and the second terminal of the voltage regulation module is electrically connected to the oscillator and the clock drive module, for providing the control voltage to the oscillator and the clock drive module;

[0011] The oscillator is electrically connected to the clock drive module. The oscillator is turned on or off under the action of the control voltage, and outputs a second clock signal to the clock drive module.

[0012] The clock driving module is electrically connected to the charge pump module and is used to process the second clock signal and the control voltage to obtain the first clock signal, and to provide the first clock signal to the charge pump module.

[0013] In one embodiment of this disclosure, during the voltage build-up phase before the voltage value output by the charge pump module reaches the target voltage value, the control voltage output by the voltage regulation module is less than and close to the power supply voltage value of the power supply.

[0014] During the voltage stabilization phase after the voltage output by the charge pump module reaches the target voltage, the control voltage output by the voltage regulation module is less than the power supply voltage.

[0015] Specifically, the control voltage in the voltage stabilization phase is smaller than the control voltage in the voltage establishment phase; and the amplitude and frequency of the first clock signal in the voltage stabilization phase are smaller than those in the first clock signal in the voltage establishment phase.

[0016] In one embodiment of this disclosure, the voltage regulation module includes a first PMOS transistor, the gate of which is electrically connected to the output terminal of the voltage comparison module, the source of which is electrically connected to the power supply, and the drain of which is electrically connected to the input terminal of the charge pump module, the oscillator, and the clock drive module.

[0017] In one embodiment of this disclosure, the charge pump module includes m-stage charge pump sub-modules, where m is a positive integer. The input terminal of the first-stage charge pump sub-module is electrically connected to the second terminal of the voltage regulation module to input the control voltage.

[0018] In one embodiment of this disclosure, the charge pump submodules at each stage include any one of a Dickson charge pump circuit, a voltage doubler charge pump circuit, and a bootstrap voltage boosting circuit.

[0019] In one embodiment of this disclosure, the oscillator includes an n-stage oscillation module, where n is a positive integer. The i-th stage oscillation module includes a second PMOS transistor, a first NMOS transistor, a first capacitor, and a first inverter group. The first inverter group includes a plurality of first inverters connected in series. Each first inverter is electrically connected to the second terminal of the voltage regulation module and a reference potential, where i ≤ n.

[0020] The gate of the second PMOS transistor and the gate of the first NMOS transistor are input with the (i-1)th level second clock signal. The source of the second PMOS transistor is electrically connected to the second terminal of the voltage regulation module to input the control voltage. The drain of the second PMOS transistor is electrically connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is electrically connected to the reference potential.

[0021] One end of the first capacitor is electrically connected to the drain of the second PMOS transistor, and the other end of the first capacitor is electrically connected to the reference potential.

[0022] The input terminal of the first inverter group is electrically connected to the drain of the second PMOS transistor. The output terminal of the first inverter group outputs the i-th stage second clock signal. If i is less than n, the i-th stage second clock signal is output to the (i+1)-th stage oscillation module. If i = n, the i-th stage second clock signal is output to the clock drive module.

[0023] In one embodiment of this disclosure, the clock driving module includes a NAND gate and a second inverter group, the second inverter group including a plurality of second inverters connected in series, each of the second inverters being electrically connected to a second terminal of the voltage regulation module and a reference potential.

[0024] The first input terminal of the NAND gate receives an enable signal, the second input terminal of the NAND gate receives the second clock signal, the output terminal of the NAND gate is electrically connected to the input terminal of the second inverter group, and the output terminal of the second inverter group outputs the first clock signal to the charge pump module.

[0025] In one embodiment of this disclosure, the voltage divider module includes a first voltage divider element and a second voltage divider element, one end of the first voltage divider element is electrically connected to the output terminal of the charge pump module, and the other end of the first voltage divider element is electrically connected to the voltage divider node;

[0026] The first end of the second voltage divider element is electrically connected to the voltage divider node, and the second end of the second voltage divider element is electrically connected to the reference potential.

[0027] The first input terminal of the voltage comparison module is electrically connected to the voltage divider node.

[0028] In one embodiment of this disclosure, the voltage comparison module includes a first-stage comparison module and a second-stage comparison module, wherein:

[0029] The first-stage comparison module is used to input the first voltage value and the reference voltage, and output the second-stage input voltage and bias voltage to the second-stage comparison module;

[0030] The second-stage comparator module includes a third PMOS transistor and a second NMOS transistor. The gate of the third PMOS transistor receives the second-stage input voltage, the source of the third PMOS transistor is electrically connected to the power supply, the drain of the third PMOS transistor is electrically connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor receives the bias voltage, and the source of the second NMOS transistor is electrically connected to the reference potential.

[0031] The width-to-length ratio of the third PMOS transistor is greater than that of the second NMOS transistor.

[0032] According to another aspect of this disclosure, an electronic device is provided, including a power module and a charge pump circuit provided in the above embodiments, the charge pump circuit being used to supply power to the power module.

[0033] In the embodiments of this disclosure, by setting a voltage regulation module in the charge pump circuit, the voltage regulation module can generate a voltage with a low amplitude range as a power supply after the output voltage of the charge pump module stabilizes, and supply it to the charge pump module, oscillator, and clock drive module, thereby generating a clock signal with a low amplitude range and a short high-level time, thereby effectively reducing the ripple of the output voltage of the charge pump circuit and reducing the power consumption of the charge pump circuit.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0036] Figure 1 A schematic diagram of a charge pump circuit provided in an embodiment of this disclosure is shown.

[0037] Figure 2 A schematic diagram of another charge pump circuit provided in an embodiment of this disclosure is shown.

[0038] Figure 3 A circuit diagram of an oscillator provided in an embodiment of this disclosure is shown.

[0039] Figure 4 The diagram shows a circuit diagram of a clock driving module provided in an embodiment of this disclosure.

[0040] Figure 5 A circuit diagram of a charge pump module provided in an embodiment of this disclosure is shown.

[0041] Figure 6 This diagram illustrates a circuit diagram of a second-level comparison module provided in an embodiment of the present disclosure.

[0042] Figure 7 The diagram shows a circuit diagram of a voltage divider module provided in an embodiment of this disclosure.

[0043] Figure 8 This diagram illustrates the change of the output voltage of the charge pump circuit provided in the embodiments of this disclosure over time at different stages.

[0044] Figure 9 This diagram illustrates the structure of an electronic device provided in an embodiment of the present disclosure.

[0045] The reference numerals in the attached figures are explained as follows:

[0046] 100. Charge pump circuit; 110. Charge pump module; 120. Voltage divider module; 121. First voltage divider element; 122. Second voltage divider element; 130. Voltage comparator module; 140. Voltage regulation module; 150. Oscillator; 160. Clock drive module;

[0047] 900. Electronic equipment; 910. Power modules. Detailed Implementation

[0048] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0049] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly stated.

[0050] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0051] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0052] In related technologies, when using integrated circuits, a charge pump circuit is needed to generate voltage to power the chip. A charge pump circuit typically includes a charge pump, an oscillator, and a clock drive module. The charge pump primarily achieves voltage rise and fall / conversion through the charging and discharging process of a capacitor, usually used to provide the required high-voltage power supply. A charge pump is a DC-to-DC converter that uses a fast or pumping capacitor to store energy. It can control the charging and discharging of the capacitor through an internal field-effect transistor (FET) switching array, thereby doubling or decreasing the input voltage, or even generating a negative voltage. The oscillator converts DC power into AC power with a certain frequency and amplitude, and can spontaneously generate and maintain a stable oscillation state without external periodic signals. The clock signal generated by the oscillator can be used to synchronize various electronic devices. The clock drive module generates and distributes a stable clock signal to drive the normal operation of the charge pump.

[0053] When the power supply voltage is in a wide voltage range, such as between 1.5V and 6.5V, if the power supply voltage is directly supplied to the oscillator and clock drive module when the power supply voltage is high, the amplitude of the clock signal generated by the clock drive module will be high, that is, the amplitude of the clock signal sent to the charge pump will be high. This situation will cause the output voltage of the charge pump to have large ripples after stabilization, and the charge pump circuit will generate high power consumption.

[0054] Figure 1 A schematic diagram of a charge pump circuit 100 provided in an embodiment of this disclosure is shown. Figure 1 As shown, in one embodiment, the charge pump circuit 100 of this disclosure includes a charge pump module 110, a voltage divider module 120, a voltage comparator module 130, a voltage regulator module 140, an oscillator 150, and a clock drive module 160, wherein:

[0055] The charge pump module 110 receives the first clock signal CLK output by the clock drive module 160. The input terminal of the charge pump module 110 is electrically connected to the voltage regulation module 140 and is used to input the control voltage VDDREG output by the voltage regulation module 140. The output terminal VOUT of the charge pump module 110 is electrically connected to the voltage divider module 120.

[0056] The voltage divider module 120 is electrically connected to the first input terminal of the voltage comparator module 130, and is used to divide the first voltage value output by the charge pump module 110, and input the second voltage value VBACK obtained after voltage division to the first input terminal of the voltage comparator module 130.

[0057] The second input terminal of the voltage comparison module 130 receives the reference voltage VREF, and the output terminal of the voltage comparison module 130 is electrically connected to the voltage regulation module 140.

[0058] The first terminal of the voltage regulation module 140 is electrically connected to the power supply VDD, and the second terminal of the voltage regulation module 140 is electrically connected to the oscillator 150 and the clock drive module 160, for providing control voltage VDDREG to the oscillator 150 and the clock drive module 160.

[0059] Oscillator 150 is electrically connected to clock drive module 160. Oscillator 150 is turned on or off under the action of control voltage VDDREG, and outputs second clock signal CLK2 to clock drive module 160.

[0060] The clock drive module 160 is electrically connected to the charge pump module 110 and is used to process the second clock signal CLK2 and the control voltage VDDREG to obtain the first clock signal CLK1, and provide the first clock signal CLK1 to the charge pump module 110.

[0061] In one embodiment, the charge pump module 110 includes m-stage charge pump sub-modules, where m is a positive integer. The input terminal of the first-stage charge pump sub-module is electrically connected to the second terminal of the voltage regulation module 140 to input a control voltage.

[0062] The charge pump module 110 may include m-level charge pump sub-modules, where m is a positive integer. When m ≥ 2, i.e., when the charge pump module 110 includes multiple levels of charge pump sub-modules, the m-level charge pump sub-modules are connected in series. The input terminal of the first-level charge pump sub-module is electrically connected to the output terminal of the voltage regulation module 140 to input the control voltage VDDREG. The output terminal of the m-th level charge pump sub-module serves as the output terminal VOUT of the charge pump module 110. For example, the output terminal of the first-level charge pump sub-module is electrically connected to the input terminal of the second-level charge pump sub-module, and so on, until the input terminal of the (m-1)-th level charge pump sub-module is electrically connected to the output terminal of the (m-2)-th level charge pump sub-module. The output terminal of the (m-1)-th level charge pump sub-module is electrically connected to the input terminal of the m-th level charge pump module. The output terminal of the m-th level charge pump module serves as the output terminal VOUT of the charge pump module 110, used to output the voltage value of the charge pump circuit 100.

[0063] In one embodiment, each charge pump submodule includes any one of a Dickson charge pump circuit, a voltage multiplier charge pump circuit, and a bootstrap voltage boosting circuit.

[0064] The number and type of charge pump submodules can be determined according to actual needs, and this disclosure does not impose specific limitations on them.

[0065] The voltage divider module 120 is used to divide the first voltage value output by the charge pump module 110 and input the second voltage value VBACK obtained after voltage division to the voltage comparison module 130, thereby realizing precise control of the output voltage of the charge pump circuit 100.

[0066] The voltage divider module 120 can be a voltage divider unit determined based on the series or parallel connection of resistor units, a voltage divider unit determined based on the series or parallel connection of self-biased transistors, or a voltage divider unit determined by the combination of resistor units and self-biased transistors. The number of resistor units or self-biased transistors can be determined according to the magnitude of the second voltage value VBACK generated as needed, and this disclosure does not impose specific limitations.

[0067] The voltage comparison module 130 can detect and compare the output voltage of the charge pump module 110, and control the working state of the charge pump circuit 100 by the difference between the output voltage value and the target voltage value Vtarget, so that the output voltage of the charge pump module 110 fluctuates within a certain range around the target voltage Vtarget.

[0068] The voltage comparison module 130 can be a single-limit comparator, a hysteresis comparator, a window comparator, or a three-state voltage comparator, etc.

[0069] The reference voltage VREF received at the second terminal of the voltage comparison module 130 is a fixed voltage that is compared with the input second voltage value VBACK. The reference voltage VREF is a constant voltage value that does not change with factors such as load, power supply, temperature drift and time. An integrated circuit can be used as the reference voltage source. The integrated circuit can integrate functions such as voltage regulator, temperature compensation and noise filtering. Alternatively, a resistor voltage divider circuit can be used to generate the required reference voltage VREF.

[0070] It should be noted that this disclosure does not specify the method of generating the reference voltage VREF or the value of the reference voltage VREF.

[0071] The voltage regulation module 140 can generate a control voltage based on the comparison result output by the voltage comparison module 130, so that the oscillator 150 and the clock drive module 160 generate corresponding clock signals according to the control voltage, thereby realizing effective control of the charge pump module 110.

[0072] In one embodiment, during the voltage build-up phase before the voltage value output by the charge pump module 110 reaches the target voltage value Vtarget, the control voltage VDDREG output by the voltage regulation module 140 is less than and close to the power supply voltage value VDD.

[0073] During the voltage stabilization phase after the voltage output of the charge pump module 110 reaches the target voltage value Vtarget, the control voltage VDDREG output by the voltage regulation module 110 is less than the power supply voltage value VDD.

[0074] Among them, the control voltage VDDREG in the voltage stabilization stage is smaller than that in the voltage setup stage; and the amplitude and frequency of the first clock signal CLK1 in the voltage stabilization stage are smaller than those in the voltage setup stage.

[0075] When the output voltage of the charge pump module 110 at the output terminal VOUT does not reach the target voltage value Vtarget, the charge pump module 110 is in the voltage build-up stage. The second voltage value VBACK is output by the voltage divider module 120. At this time, the second voltage value VBACK is less than the reference voltage VBEF. The voltage comparison module 130 outputs a low level, and the control voltage VDDREG output by the voltage regulation module 140 is close to the high level of the power supply VDD.

[0076] When the output voltage of the charge pump module 110 reaches the target voltage value Vtarget, the charge pump module 110 is in a voltage stabilization phase. After the output voltage of the charge pump module 110 reaches the target voltage value Vtarget, the output voltage has a certain jitter, causing the second voltage value VBACK to be higher than the target voltage value Vtarget for a period of time, and lower than the target voltage value Vtarget for another period of time. Correspondingly, the voltage output by the voltage comparison module 130 will also jitter with the output voltage of the charge pump module 110. That is, the voltage input to the voltage regulation module 140 will fluctuate within a certain range close to the power supply voltage VDD. The voltage regulation module 140 can process the input voltage signal and output a control voltage VDDREG. The control voltage VDDREG can carry the jitter characteristics of the input voltage signal, and then generate a clock signal based on the control voltage VDDREG to realize the control of the charge pump module 110. During this stage, the control voltage VDDREG is a low-frequency, low-amplitude voltage value, so that the second clock signal CLK2 output by the oscillator 150 and the first clock signal CLK1 connected to the charge pump module 110 are also low-frequency, low-amplitude clock signals.

[0077] The power supply VDD can be provided by a constant voltage source or a constant voltage circuit. The voltage value of the power supply VDD can be determined according to actual needs, and this disclosure does not make specific limitations in this regard.

[0078] Oscillator 150 can convert the DC control signal VDDREG into AC power with a certain frequency and amplitude, that is, generate a second clock signal CLK2. The second clock signal CLK2 is a rectangular wave signal generated by oscillator 150. For example, the high level of the rectangular wave signal is the control voltage VDDREG, the low level is 0V, and the duration of the high and low levels is the same, that is, the duty cycle is 50%.

[0079] The clock drive module 160 is able to generate and distribute a stable first clock signal CLK1, thereby driving the charge pump module 110 to operate normally.

[0080] When the output voltage of the charge pump module 110 output terminal VOUT is in the voltage establishment stage, the control voltage VDDREG is a high level close to the voltage value of the power supply VDD, so that the voltage amplitude of the first clock signal CLK1 and the second clock signal CLK2 are also close to the voltage value of the power supply VDD, which helps to quickly establish the output voltage of the charge pump module 110 output terminal VOUT.

[0081] When the output voltage of the charge pump module 110 output terminal VOUT is in the stable stage, the generated first clock signal CLK1 and second clock signal CLK2 can maintain the output voltage of the charge pump module 110 stable near the target voltage value Vtarget, and greatly reduce the ripple of the charge pump module 110 in the stable stage. The voltage amplitude of the first clock signal CLK1 and the second clock signal CLK2 is reduced, which can also reduce the power consumption of the charge pump circuit 100.

[0082] In this embodiment of the present disclosure, by providing a voltage regulation module 140 in the charge pump circuit 100, the voltage regulation module 140 can generate a voltage with a low amplitude range as a power supply after the output voltage of the charge pump module 110 stabilizes, and supply it to the charge pump module 110, the oscillator 150 and the clock drive module 160, thereby generating a clock signal with a low amplitude range and a short high-level time, thereby effectively reducing the ripple of the output voltage of the charge pump circuit 100 and reducing the power consumption of the charge pump circuit 100.

[0083] Figure 2 A schematic diagram of another charge pump circuit 100 provided in an embodiment of this disclosure is shown. Figure 2 As shown, in one embodiment, the voltage regulation module 140 includes a first PMOS transistor MP1. The gate of the first PMOS transistor MP1 is electrically connected to the output terminal of the voltage comparison module 130, the source of the first PMOS transistor MP1 is electrically connected to the power supply VDD, and the drain of the first PMOS transistor MP1 is electrically connected to the input terminal of the charge pump module 110, the oscillator 150, and the clock drive module 160.

[0084] In one embodiment, when the output voltage of the charge pump module 110 output terminal VOUT is in the voltage establishment phase, the voltage comparison module 130 outputs a low level, that is, the gate of the first PMOS transistor MP1 is applied with a low level, the first PMOS transistor MP1 is fully turned on, and the drain of the first PMOS transistor MP1 is pulled up, so that the control voltage VDDREG is close to the voltage value of the power supply VDD. As a result, the voltage amplitude of the clock signal generated by the oscillator 150 and the clock drive module 160 is close to the voltage value of the power supply VDD, which helps the output voltage of the charge pump module 110 to be established quickly.

[0085] When the output voltage of the charge pump module 110 is in the stable voltage stage, the voltage output of the voltage comparison module 130 fluctuates within a certain range close to the voltage value of the power supply VDD. The gate-source voltage of the first PMOS transistor MP1 is Vgs = Vg - Vs = Vg - VDD. At this time, the gate-source voltage of the first PMOS transistor MP1 fluctuates within [-V1, V2]. It should be noted that the values ​​of V1 and V2 are smaller than the voltage value of the power supply VDD.

[0086] Because the first PMOS transistor MP1 has a threshold voltage, it is only slightly turned on at a few times. The first PMOS transistor MP1 is in the deep transistor region and has a large resistance, which results in a small control voltage VDDREG. That is, the control voltage VDDREG supplied to the oscillator 150, the clock drive module 160 and the charge pump module 110 is a voltage with a low frequency and a small amplitude, thereby causing the oscillator 150 and the clock drive module 160 to generate a clock signal with a low frequency and a small amplitude.

[0087] It should be noted that the selection of the first PMOS transistor MP1 can be determined according to actual needs, and this disclosure does not impose specific limitations on it.

[0088] In some feasible implementations, the voltage regulation module 140 may also employ an insulated gate bipolar transistor (IGBT) or a PNP transistor, etc., which is not limited in this disclosure.

[0089] In this embodiment, a first PMOS transistor MP1 is used as the voltage regulation module 140. The feedback structure is composed of a voltage divider module 120, a voltage comparator module 130, and the first PMOS transistor MP1. The control voltage VDDREG output by the feedback structure serves as the power supply voltage for the charge pump module 110 on one hand, and as the power supply voltage for the oscillator 150 and the clock drive module 160 on the other hand. The control voltage VDDREG is high before the voltage is stable in the voltage build-up phase of the charge pump module 110. After the voltage is stable in the voltage build-up phase, the amplitude is small, which enables the charge pump module 110 to quickly boost the voltage during the voltage build-up phase. During the voltage stabilization phase, the frequency and amplitude of the clock signals generated by the oscillator 150 and the clock drive module 160 are low, thereby reducing the ripple of the output voltage of the charge pump module 110 after it stabilizes and the power consumption of the charge pump circuit 100.

[0090] Figure 3 A circuit diagram of an oscillator 150 provided in an embodiment of this disclosure is shown. For example... Figure 3As shown, in one embodiment, the oscillator 150 includes n-stage oscillation modules, where n is a positive integer. The i-th stage oscillation module includes a second PMOS transistor MP2, a first NMOS transistor MN1, a first capacitor C1, and a first inverter group. The first inverter group includes multiple first inverters NOT1 connected in series. Each first inverter NOT1 is electrically connected to the second terminal of the voltage regulation module 140 and the reference potential GND, where i≤n.

[0091] The gate of the second PMOS transistor MP2 and the gate of the first NMOS transistor MN1 are input to the (i-1)th stage second clock signal CLK. <i-1>The source of the second PMOS transistor MP2 is electrically connected to the second terminal of the voltage regulation module 140 to input the control voltage VDDREG. The drain of the second PMOS transistor MP2 is electrically connected to the drain of the first NMOS transistor MN1. The source of the first NMOS transistor MN1 is electrically connected to the reference potential GND.

[0092] One end of the first capacitor C1 is electrically connected to the drain of the second PMOS transistor MP2, and the other end of the first capacitor C1 is electrically connected to the reference potential GND.

[0093] The input terminal of the first inverter group is electrically connected to the drain of the second PMOS transistor MP2, and the output terminal of the first inverter group outputs the second clock signal CLK of the i-th stage. If i is less than n, then the second clock signal CLK of the i-th stage will be... The output is sent to the (i+1)th stage oscillation module. If i = n, then the second clock signal CLK of the i-th stage is... Output to clock driver module 160.

[0094] In one embodiment, n-stage oscillation modules are connected in series, meaning the output of the current-stage oscillation module is electrically connected to the input of the next-stage oscillation module. For example, when n = 3, the input of the first-stage oscillation module is used to input the 0th-stage second clock signal CLK generated according to the switching frequency of the first PMOS transistor MP1 or the first NMOS transistor MN1. <0> Generate the first-stage second clock signal CLK <1> and the first-stage second clock signal CLK <1> The input is sent to the second-stage oscillation module, which then processes the first-stage second clock signal CLK. <1> The process generates the second-level second clock signal CLK. <2> And the second clock signal CLK of the second stage <2> The input is sent to the third-stage oscillation module, and the second-stage clock signal CLK is then processed. <2> After processing, the third-level second clock signal CLK is generated. <3> This serves as the output signal of the oscillator 150.

[0095] Specifically, the first inverter group includes an odd number of first inverters, when the (i-1)th stage second clock signal CLK <i-1>When the voltage is high, the first NMOS transistor MN1 is turned on, and the second PMOS transistor MP2 is turned off, causing the first node N1 to be pulled down to the reference potential GND. After passing through the first inverter group, the i-th stage second clock signal CLK is output. It is a low level.

[0096] When the second clock signal CLK of the (i-1)th stage <i-1>When the voltage is low, the first NMOS transistor MN1 is off, and the second PMOS transistor MP2 is on, pulling the first node N1 up to the control voltage VDDREG. After passing through the first inverter group, the output i-th stage second clock signal CLK is generated. It is a high level.

[0097] The voltage of the reference potential GND is lower than the voltage of the power supply VDD, and the reference potential GND can be ground.

[0098] The number of first inverters NOT1 in the first inverter group can be determined according to actual needs, and this disclosure does not limit it.

[0099] In this embodiment, the input clock signal is processed by the second PMOS transistor MP2 and the first NMOS transistor MN1 to generate a corresponding second clock signal. This enables the generation of a voltage value with an amplitude close to the power supply VDD during the voltage build-up phase of the charge pump module 110, achieving rapid voltage boost. During the voltage stabilization phase of the charge pump module 110, a clock signal with a smaller amplitude and lower frequency is generated to reduce the ripple of the output voltage after the charge pump module 110 stabilizes, thereby reducing the power consumption of the charge pump module 110.

[0100] Figure 4 This diagram illustrates a circuit diagram of a clock driving module 160 provided in an embodiment of this disclosure. Figure 4 As shown, in one embodiment, the clock drive module 160 includes a NAND gate NAND1 and a second inverter group, the second inverter group including a plurality of second inverters NOT2 connected in series, each of the second inverters NOT2 being electrically connected to the second terminal of the voltage regulation module 140 and the reference potential GND.

[0101] The first input terminal of the NAND gate NAND1 receives the enable signal EN, the second input terminal of the NAND gate NAND1 receives the second clock signal CLK2, the output terminal of the NAND gate NAND1 is electrically connected to the input terminal of the second inverter group, and the output terminal of the second inverter group outputs the first clock signal CLK1 to the charge pump module 110.

[0102] In one embodiment, to control the charge pump module 110, the clock drive module 160 can generate a first clock signal CLK1 or an inverted signal CLKB1 of the first clock signal. The inverted signal CLKB1 of the first clock signal can be obtained by appropriately setting the number of second inverters NOT2 in the second inverter group. It should be noted that implementing the charge pump circuit 100 under the control of the inverted signal CLKB1 of the first clock signal can also be seen as implementing the charge pump circuit 100 under the control of the first clock signal CLK1, only the high and low levels of the control are reversed.

[0103] The enable signal EN is a control signal used to enable or disable the NAND gate NAND1. It should be noted that the NAND gate NAND1 is effective when the enable signal EN is high, or when the enable signal EN is low. The comparison is not limited.

[0104] When both the first and second inputs of the NAND gate are 1, the NAND gate outputs 0; when at least one of the first and second inputs of the NAND gate is 0, the NAND gate outputs 1.

[0105] In this embodiment, the input second clock signal CLK2 is processed by NAND gate NAND1 and the second inverter group to generate a corresponding first clock signal CLK1. This enables the generation of a voltage value with an amplitude close to the power supply VDD during the voltage build-up phase of the charge pump module 110, achieving rapid voltage boost. During the voltage stabilization phase of the charge pump module 110, a clock signal with a smaller amplitude and lower frequency is generated to reduce the ripple of the output voltage after the charge pump module 110 stabilizes and reduce the power consumption of the charge pump module 110.

[0106] Figure 5 This diagram illustrates a circuit diagram of a second-level comparison module provided in an embodiment of this disclosure. Figure 5 As shown, in one embodiment, the voltage comparison module 130 includes a first-stage comparison module and a second-stage comparison module, wherein:

[0107] The first-stage comparison module is used to input the first voltage value VBACK and the reference voltage VREF, and outputs the second-stage input voltage Vin and the bias voltage Vbias to the second-stage comparison module.

[0108] The second-stage comparator module includes a third PMOS transistor MP3 and a second NMOS transistor MN2. The gate of the third PMOS transistor MP3 receives the second-stage input voltage Vin. The source of the third PMOS transistor MP3 is electrically connected to the power supply VDD. The drain of the third PMOS transistor MP3 is electrically connected to the drain of the second NMOS transistor MN2. The gate of the second NMOS transistor MN2 receives the bias voltage Vbias. The source of the second NMOS transistor MN2 is electrically connected to the reference potential GND.

[0109] Among them, the width-to-length ratio of the third PMOS transistor MP3 is greater than that of the second NMOS transistor MN2.

[0110] When the second-stage input voltage Vin of the third PMOS transistor MP3 is lower than its threshold voltage, the third PMOS transistor MP3 is turned on, pulling the output Vout1 up to the voltage value of the power supply VDD; when the second-stage input voltage Vin of the third PMOS transistor MP3 is higher than its threshold voltage, the third PMOS transistor MP3 is turned off, and the output Vout1 is controlled by the second NMOS transistor MN2.

[0111] When the bias voltage Vbias is higher than the threshold voltage of the second NMOS transistor MN2, the second NMOS transistor MN2 is turned on, pulling the output terminal Vout1 down to the reference potential GND; when the bias voltage Vbias is lower than the threshold voltage of the second NMOS transistor MN2, the output terminal Vout1 is controlled by the third PMOS transistor MP3.

[0112] In one embodiment, in the second-stage comparison module, the third PMOS transistor MP3 acts as a pull-up transistor, and the second NMOS transistor MN2 acts as a pull-down transistor. The aspect ratio of the third PMOS transistor MP3 is much larger than that of the second NMOS transistor MN2, which makes the third PMOS transistor MP3 have stronger driving capability and lower on-resistance. It can respond to changes in the second-stage input voltage Vin in real time, improve the reliability of the charge pump circuit 100, and improve the accuracy of the voltage comparison module 130. The sensitivity of the voltage comparison module 130 can be flexibly controlled by adjusting the bias voltage Vbias.

[0113] In one embodiment, the charge pump module 110 of this disclosure includes m-stage charge pump sub-modules, where each stage of the charge pump sub-module is connected in series when m > 2. For example... Figure 6 As shown, only the case where the charge pump module 110 includes a single-stage charge pump submodule is illustrated. The case of multiple-stage charge pump submodules is similar and will not be described in detail here.

[0114] like Figure 6 As shown, in one embodiment, the charge pump module 110 includes a fourth PMOS transistor MP4, a third NMOS transistor MN3, a fifth PMOS transistor MP5, a fourth NMOS transistor MN4, a second capacitor C2, and a third capacitor C3. The sources of the fourth PMOS transistor and the fifth PMOS transistor MP5 are used to input the control voltage VDDREG. The gate of the fourth PMOS transistor MP4 is electrically connected to the third node N3, and its drain is electrically connected to the second node N2. The gate of the fifth PMOS transistor is electrically connected to the second node N2, and its drain is electrically connected to the third node N3. The gate of the third NMOS transistor MN3 is electrically connected to the third node N3, its drain is electrically connected to the second node N2, and its source is electrically connected to the output terminal VOUT. The gate of the fourth NMOS transistor MN4 is electrically connected to the second node N2, its drain is electrically connected to the third node N3, and its source is electrically connected to the output terminal VOUT.

[0115] Figure 7 A circuit diagram of a voltage divider module 120 provided in an embodiment of this disclosure is shown. Figure 7 As shown, in one embodiment, the voltage divider module 120 includes a first voltage divider element 121 and a second voltage divider element 122. One end of the first voltage divider element 121 is electrically connected to the output terminal VOUT of the charge pump module 110, and the other end of the first voltage divider element 121 is electrically connected to the voltage divider node N4.

[0116] The first end of the second voltage divider element 122 is electrically connected to the voltage divider node N4, and the second end of the second voltage divider element 122 is electrically connected to the reference potential GND.

[0117] The first input terminal of the voltage comparator module 130 is electrically connected to the voltage divider node N4.

[0118] In one embodiment, the first voltage divider element 121 and the second voltage divider element 122 can be resistor units. The resistor units can be implemented by multiple resistors connected in series or in parallel, or by multiple self-biased transistors connected in series or in parallel, or by a combination of resistors and self-biased transistors. The number of resistors or self-biased transistors can be determined according to the magnitude of the first voltage to be generated, and this disclosure does not make specific limitations in this regard.

[0119] exist Figure 7 In this configuration, the first voltage divider element 121 is a self-biased sixth PMOS transistor MP6, and the second voltage divider element 122 is a self-biased seventh PMOS transistor MP7. The source of the self-biased sixth PMOS transistor MP6 is electrically connected to the output terminal VOUT of the charge pump module 110, and its gate and drain are both electrically connected to the voltage divider node N4. The source of the self-biased seventh PMOS transistor MP7 is electrically connected to the voltage divider node N4, and its gate and drain are both electrically connected to the reference potential GND. The voltage divider node N4 serves as the output terminal of the voltage divider module 120 and is electrically connected to the first input terminal of the voltage comparator module 130.

[0120] It should be noted that the circuit structures of the charge pump module 110, voltage divider module 120, voltage comparator module 130, voltage regulator module 140, oscillator 150, and clock drive module 160 described above are merely illustrative. The circuit structures of the charge pump module 110, voltage divider module 120, voltage comparator module 130, voltage regulator module 140, oscillator 150, and clock drive module 160 in this embodiment are not limited to the above-described manner. The aforementioned circuit structures of the charge pump module 110, voltage divider module 120, voltage comparator module 130, voltage regulator module 140, oscillator 150, and clock drive module 160 can be implemented individually or in combination, and this embodiment does not impose any limitations on this.

[0121] Figure 8 The curve showing the change of output voltage VOUT of the charge pump circuit 100 provided in this disclosure over time is shown. During the time period from 0 to t1, the charge pump module 110 is in the voltage build-up stage, during which the output voltage rises rapidly. During the time period greater than t1, the charge pump module 110 is in the voltage stabilization stage, and the output voltage fluctuates within a certain range of the target voltage value Vtarget.

[0122] Figure 9 This diagram illustrates the structure of an electronic device 900 according to an embodiment of the present disclosure. Figure 9 As shown, in one embodiment, the electronic device 900 of this disclosure includes a power module 910 and a charge pump circuit 100 as described in the above embodiment, wherein the charge pump circuit 100 supplies power to the power module 910.

[0123] It should be noted that the voltage provided by the charge pump circuit 100 to the power module 910 can be generated in accordance with the generation method in the aforementioned embodiment of the charge pump circuit 100, and will not be repeated here.

[0124] In conjunction with the charge pump circuit 100 described above, by setting a voltage regulation module 140 in the charge pump circuit 100, the voltage regulation module 140 can generate a voltage with a low amplitude range as a power supply after the output voltage of the charge pump module 110 stabilizes. This power supply is then supplied to the charge pump module 110, the oscillator 150, and the clock drive module 160, thereby generating a clock signal with a low amplitude range and a short high-level time. This effectively reduces the ripple of the output voltage of the charge pump circuit 100 and lowers the power consumption of the charge pump circuit 100.

[0125] In the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0126] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the application.

[0127] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the claims. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0128] The above are merely preferred embodiments of the application examples and are not intended to limit the application examples. For those skilled in the art, the application examples can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the application examples should be included within the protection scope of the application examples.

Claims

1. A charge pump circuit, characterized in that, It includes a charge pump module, a voltage divider module, a voltage comparator module, a voltage regulator module, an oscillator, and a clock drive module, wherein: The charge pump module receives the first clock signal output by the clock drive module. The input terminal of the charge pump module is electrically connected to the voltage regulation module for inputting the control voltage output by the voltage regulation module. The output terminal of the charge pump module is electrically connected to the voltage divider module. The voltage divider module is electrically connected to the first input terminal of the voltage comparison module, and is used to divide the first voltage value output by the charge pump module, and input the second voltage value obtained after voltage division to the first input terminal of the voltage comparison module. The second input terminal of the voltage comparison module receives a reference voltage, and the output terminal of the voltage comparison module is electrically connected to the voltage regulation module. The first terminal of the voltage regulation module is electrically connected to the power supply, and the second terminal of the voltage regulation module is electrically connected to the oscillator and the clock drive module, for providing the control voltage to the oscillator and the clock drive module; The oscillator is electrically connected to the clock drive module. The oscillator is turned on or off under the action of the control voltage, and outputs a second clock signal to the clock drive module. The clock driving module is electrically connected to the charge pump module and is used to process the second clock signal and the control voltage to obtain the first clock signal, and to provide the first clock signal to the charge pump module.

2. The charge pump circuit according to claim 1, characterized in that, During the voltage build-up phase before the voltage output by the charge pump module reaches the target voltage, the control voltage output by the voltage regulation module is less than and close to the power supply voltage. During the voltage stabilization phase after the voltage output by the charge pump module reaches the target voltage, the control voltage output by the voltage regulation module is less than the power supply voltage. Among them, the control voltage in the voltage stabilization phase is smaller than the control voltage in the voltage establishment phase; Compared to the first clock signal during the voltage setup phase, the first clock signal during the voltage stabilization phase has a smaller amplitude and frequency.

3. The charge pump circuit according to claim 2, characterized in that, The voltage regulation module includes a first PMOS transistor, the gate of which is electrically connected to the output terminal of the voltage comparison module, the source of which is electrically connected to the power supply, and the drain of which is electrically connected to the input terminal of the charge pump module, the oscillator, and the clock drive module.

4. The charge pump circuit according to any one of claims 1-3, characterized in that, The charge pump module includes m-stage charge pump sub-modules, where m is a positive integer. The input terminal of the first-stage charge pump sub-module is electrically connected to the second terminal of the voltage regulation module to input the control voltage.

5. The charge pump circuit according to claim 4, characterized in that, The charge pump submodules described at each level include any one of the following: Dickson charge pump circuit, voltage multiplier charge pump circuit, and bootstrap voltage boost circuit.

6. The charge pump circuit according to any one of claims 1-3, characterized in that, The oscillator includes n-stage oscillation modules, where n is a positive integer. The i-th stage oscillation module includes a second PMOS transistor, a first NMOS transistor, a first capacitor, and a first inverter group. The first inverter group includes multiple first inverters connected in series. Each first inverter is electrically connected to the second terminal of the voltage regulation module and the reference potential, where i ≤ n. The gate of the second PMOS transistor and the gate of the first NMOS transistor are input with the (i-1)th level second clock signal. The source of the second PMOS transistor is electrically connected to the second terminal of the voltage regulation module to input the control voltage. The drain of the second PMOS transistor is electrically connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is electrically connected to the reference potential. One end of the first capacitor is electrically connected to the drain of the second PMOS transistor, and the other end of the first capacitor is electrically connected to the reference potential. The input terminal of the first inverter group is electrically connected to the drain of the second PMOS transistor. The output terminal of the first inverter group outputs the i-th stage second clock signal. If i is less than n, the i-th stage second clock signal is output to the (i+1)-th stage oscillation module. If i = n, the i-th stage second clock signal is output to the clock drive module.

7. The charge pump circuit according to any one of claims 1-3, characterized in that, The clock driving module includes a NAND gate and a second inverter group. The second inverter group includes multiple second inverters connected in series. Each second inverter is electrically connected to the second terminal of the voltage regulation module and the reference potential. The first input terminal of the NAND gate receives an enable signal, the second input terminal of the NAND gate receives the second clock signal, the output terminal of the NAND gate is electrically connected to the input terminal of the second inverter group, and the output terminal of the second inverter group outputs the first clock signal to the charge pump module.

8. The charge pump circuit according to any one of claims 1-3, characterized in that, The voltage divider module includes a first voltage divider element and a second voltage divider element. One end of the first voltage divider element is electrically connected to the output end of the charge pump module, and the other end of the first voltage divider element is electrically connected to the voltage divider node. The first end of the second voltage divider element is electrically connected to the voltage divider node, and the second end of the second voltage divider element is electrically connected to the reference potential. The first input terminal of the voltage comparison module is electrically connected to the voltage divider node.

9. The charge pump circuit according to any one of claims 1-3, characterized in that, The voltage comparison module includes a first-stage comparison module and a second-stage comparison module, wherein: The first-stage comparison module is used to input the first voltage value and the reference voltage, and output the second-stage input voltage and bias voltage to the second-stage comparison module; The second-stage comparator module includes a third PMOS transistor and a second NMOS transistor. The gate of the third PMOS transistor receives the second-stage input voltage, the source of the third PMOS transistor is electrically connected to the power supply, the drain of the third PMOS transistor is electrically connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor receives the bias voltage, and the source of the second NMOS transistor is electrically connected to the reference potential. The width-to-length ratio of the third PMOS transistor is greater than that of the second NMOS transistor.

10. An electronic device, characterized in that, It includes a power module and a charge pump circuit as described in any one of claims 1-9, wherein the charge pump circuit is used to supply power to the power module.

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