Charge pump control circuit

Abstract

The application relates to the technical field of charge pump control, and particularly discloses a charge pump control circuit, which comprises: a charge pump output module for storing energy through charging of a flying capacitor and discharging to output an output voltage higher than a power supply voltage; an output voltage detection module for detecting the output voltage of the charge pump output module and generating an output protection signal according to the output voltage; a step-by-step charging control module for detecting the voltage of the flying capacitor in the charge pump output module and step-by-step adjusting the charging rate of the flying capacitor according to the voltage of the flying capacitor; a dead zone mutual exclusion control module for controlling a logic control and driving module according to the output protection signal to adjust the on time of the charge pump output module; and a logic control and driving module for outputting a driving signal to control the on-off of the charge pump output module. The charge pump control circuit provided by the application can improve the reliability of the charge pump control circuit under extreme application conditions.

Description

Technical Field

[0001] This invention relates to the field of charge pump control technology, and in particular to a charge pump control circuit. Background Technology

[0002] With the trend towards portability and miniaturization, the output stage of power drive chips (such as motor drivers, half-bridge drivers, and DC / DC converters) commonly adopts a dual N-type field-effect transistor (FET) design. Since driving the high-side N-type FET to conduct normally requires a power supply voltage higher than the supply voltage, charge pumps are widely used in power drive chips to generate a power supply voltage higher than the supply voltage.

[0003] However, existing charge pump control circuits mainly focus on the basic boost function of the charge pump and generally lack detailed detection and protection of the flying capacitor voltage and the output voltage. This makes the charge pump prone to failure under extreme application conditions such as output short circuit, output voltage undervoltage, and output voltage overvoltage, and may even damage the chip. Specifically, existing charge pump control circuits have the following defects: (1) Lack of detailed detection and protection of the output voltage. Existing charge pump control circuits do not have output voltage short circuit detection, undervoltage detection, and overvoltage detection. When a short circuit occurs at the output terminal or abnormal conditions such as overvoltage or undervoltage occur in the output voltage, the conduction time of the high-side switch and the low-side switch cannot be adaptively adjusted, resulting in excessive short-circuit power consumption, reduced conversion efficiency, and even damage to the device; (2) Lack of control over the charging process of the flying capacitor. The existing charge pump control circuit does not detect the voltage state of the leap capacitor and adjust the charging rate accordingly when charging the leap capacitor. The voltage of the leap capacitor rises rapidly during the charging process, which can easily generate overshoot spikes, affecting the charging stability and device lifespan; (3) It lacks complete and configurable protection logic. The existing charge pump control circuit has a single protection method, which makes it difficult to adjust parameters such as charging rate according to different application scenarios, and cannot meet the requirement of maintaining high reliability under various extreme application conditions.

[0004] Therefore, improving the reliability of charge pump control circuits under extreme application conditions has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This invention provides a charge pump control circuit that solves the problem of insufficient reliability of charge pump control circuits under extreme application conditions in related technologies.

[0006] As one aspect of the present invention, a charge pump control circuit is provided, comprising: a charge pump output module, an output voltage detection module, a step-charging control module, a dead-zone mutual exclusion control module, and a logic control and drive module; the output voltage detection module is connected to the charge pump output module, the dead-zone mutual exclusion control module is connected to the output voltage detection module, the logic control and drive module and the step-charging control module are both connected to the dead-zone mutual exclusion control module, and the step-charging control module and the logic control and drive module are both connected to the charge pump output module.

[0007] The charge pump output module is used to charge and discharge the leap capacitor to output a voltage higher than the power supply voltage.

[0008] The output voltage detection module is used to detect the output voltage of the charge pump output module and generate an output protection signal based on the output voltage. The output protection signal includes at least an undervoltage protection signal, a short-circuit protection signal, and an overvoltage protection signal.

[0009] The step-by-step charging control module is used to detect the voltage of the leap capacitor in the charge pump output module, and adjust the charging rate of the leap capacitor step by step according to the voltage of the leap capacitor.

[0010] The dead-zone mutual exclusion control module is used to control the logic control and drive module according to the output protection signal, so as to adjust the conduction time of the charge pump output module.

[0011] The logic control and drive module is used to output drive signals to control the on / off state of the charge pump output module.

[0012] Furthermore, the output voltage detection module includes a first comparator, a second comparator, a third comparator, a first resistor, a second resistor, and a first capacitor.

[0013] One end of the first resistor is connected to the positive output terminal of the charge pump output module, the other end of the first resistor is connected to one end of the second resistor, the other end of the second resistor is connected to the negative output terminal of the charge pump output module, one end of the first capacitor is connected to one end of the second resistor, and the other end of the first capacitor is connected to the other end of the second resistor.

[0014] The inverting input of the first comparator is connected to one end of the second resistor, the non-inverting input of the first comparator is connected to the undervoltage protection reference signal, and the output of the first comparator outputs the undervoltage protection signal.

[0015] The inverting input of the second comparator is connected to one end of the second resistor, the non-inverting input of the second comparator is connected to the short-circuit protection reference signal, and the output of the second comparator outputs the short-circuit protection signal.

[0016] The non-inverting input of the third comparator is connected to one end of the second resistor, the inverting input of the third comparator is connected to the overvoltage protection reference signal, and the output of the third comparator outputs the overvoltage protection signal.

[0017] Furthermore, the step-by-step charging control module includes a leap capacitor detection unit and a step-by-step charging unit. The step-by-step charging unit is connected to the leap capacitor detection unit, the leap capacitor detection unit is connected to the leap capacitor, and the step-by-step charging unit is connected to the dead-zone mutual exclusion control module.

[0018] The leap capacitor detection unit is used to detect the voltage of the leap capacitor and generate a charging rate control signal based on the voltage of the leap capacitor. A first rate charging control signal is generated when the voltage of the leap capacitor is lower than a first preset percentage of a preset voltage; a second rate charging control signal is generated when the voltage of the leap capacitor is higher than a second preset percentage of a preset voltage; and a third rate charging control signal is generated when the voltage of the leap capacitor is between the first preset percentage and the second preset percentage of the preset voltage. The first preset percentage is less than the second preset percentage and both are less than 1. The charging rate of the first rate charging control signal is greater than the charging rate of the third rate charging control signal, and the charging rate of the third rate charging control signal is greater than the charging rate of the second rate charging control signal.

[0019] The step-by-step charging unit is used to adjust the charging rate of the leap capacitor step by step according to the charging rate control signal.

[0020] Furthermore, the leap capacitor detection unit includes a fourth comparator, a fifth comparator, a third resistor, a fourth resistor, a second capacitor, and a first NOR gate.

[0021] One end of the third resistor is connected to the positive terminal of the leap capacitor, the other end of the third resistor is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the negative terminal of the leap capacitor, one end of the second capacitor is connected to one end of the fourth resistor, and the other end of the second capacitor is connected to the other end of the fourth resistor.

[0022] The inverting input of the fourth comparator is connected to one end of the fourth resistor, the non-inverting input of the fourth comparator is connected to the first speed charging reference signal, the output of the fourth comparator is connected to the first input of the first NOR gate, and the fourth comparator is used to output the first rate charging control signal.

[0023] The non-inverting input of the fifth comparator is connected to one end of the fourth resistor, the inverting input of the fifth comparator is connected to the second speed charging reference signal, the output of the fifth comparator is connected to the second input of the first NOR gate, and the fifth comparator is used to output the second rate charging control signal.

[0024] The output of the first NOR gate is used to output the third rate charging control signal.

[0025] Furthermore, the step-by-step charging unit includes a fuse adjustment unit, a charging rate adjustment unit, and a leap capacitor charging switch control unit, wherein the charging rate adjustment unit and the leap capacitor charging switch control unit are both connected to the fuse adjustment unit.

[0026] The fuse adjustment unit includes a first fuse adjustment current source, a second fuse adjustment current source, and a third fuse adjustment current source. The first fuse adjustment current source is used to adjust the charging rate of the charging rate adjustment unit. The second fuse adjustment current source is used to determine the delay of the switch control signal for the charging stage of the leap capacitor. The third fuse adjustment current source is used to determine the delay of the switch control signal for the discharging stage of the leap capacitor.

[0027] The charging rate adjustment unit is used to adjust the charging rate of the leap capacitor in steps according to the charging rate control signal and the output signal of the first fuse adjustment current source when the external enable signal is valid, and output the adjusted leap capacitor charging signal.

[0028] The leap capacitor charging switch control unit is used to generate a leap capacitor charging switch control signal based on the external clock signal, the output signal of the second fuse trimming current source, and the output signal of the dead zone mutual exclusion control module when the external enable signal is valid.

[0029] Furthermore, the charging rate adjustment unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first inverter, a second inverter, a third inverter, a high-side charging switch for the leap capacitor, and a low-side charging switch for the leap capacitor.

[0030] The first terminal of the first switching transistor is connected to the power supply voltage, and the second terminal of the first switching transistor is connected to the driving terminal of the first switching transistor.

[0031] The driving terminal of the second switch is connected to the driving terminal of the first switch, the first terminal of the second switch is connected to the first terminal of the first switch, and the second terminal of the second switch is connected to the first terminal of the fifth switch.

[0032] The driving terminal of the third switch is connected to the driving terminal of the first switch, the first terminal of the third switch is connected to the first terminal of the first switch, and the second terminal of the third switch is connected to the first terminal of the sixth switch.

[0033] The driving terminal of the fourth switch is connected to the driving terminal of the first switch, the first terminal of the fourth switch is connected to the first terminal of the first switch, and the second terminal of the fourth switch is connected to the first terminal of the seventh switch.

[0034] The driving terminal of the fifth switch is connected to the output terminal of the first inverter, the input terminal of the first inverter is connected to the first rate charging control signal, and the second terminal of the fifth switch is connected to the first terminal of the high-side charging switch of the leap capacitor.

[0035] The driving terminal of the sixth switch is connected to the output terminal of the second inverter, the input terminal of the second inverter is connected to the third rate charging control signal, and the second terminal of the sixth switch is connected to the first terminal of the high-side charging switch of the leap capacitor.

[0036] The driving terminal of the seventh switch is connected to the output terminal of the third inverter, the input terminal of the third inverter is connected to the second rate charging control signal, and the second terminal of the seventh switch is connected to the first terminal of the high-side charging switch of the leap capacitor.

[0037] The driving terminal of the eighth switch is connected to the external enable signal, the first terminal of the eighth switch is connected to the second terminal of the first switch, the second terminal of the eighth switch is connected to the first terminal of the first fuse adjustment current source, and the other terminal of the first fuse adjustment current source is connected to signal ground.

[0038] The second terminal of the high-side charging switch of the leap capacitor is connected to the positive terminal of the leap capacitor, the second terminal of the low-side charging switch of the leap capacitor is connected to the negative terminal of the leap capacitor, the first terminal of the low-side charging switch of the leap capacitor is connected to signal ground, and the control terminals of the high-side charging switch and the low-side charging switch of the leap capacitor are both connected to the output terminal of the control unit of the leap capacitor charging switch.

[0039] Furthermore, the leap capacitor charging switch control unit includes a ninth switch, a tenth switch, a first NAND gate, a first buffer, a first level shifter, and a third capacitor.

[0040] The first input terminal of the first NAND gate is connected to the external enable signal, the second input terminal of the first NAND gate is connected to the external clock signal, and the output terminal of the first NAND gate is connected to the driving terminals of the ninth switch and the tenth switch, respectively.

[0041] The first terminal of the ninth switch is connected to one end of the second fuse adjustment current source, the other end of the second fuse adjustment current source is connected to the power supply voltage, the second terminal of the ninth switch is connected to the first terminal of the tenth switch, and the second terminal of the tenth switch is connected to the signal ground.

[0042] One end of the third capacitor is connected to the first end of the tenth switch transistor, and the other end of the third capacitor is connected to the second end of the tenth switch transistor.

[0043] The input terminal of the first buffer is connected to the first terminal of the tenth switch transistor, the output terminal of the first buffer is connected to the input terminal of the first level shifter, the output terminal of the first level shifter is connected to the control terminal of the high-side charging switch of the leap capacitor and is used to output the control signal of the high-side charging switch of the leap capacitor, and the output terminal of the first buffer is also connected to the control terminal of the low-side charging switch of the leap capacitor and is used to output the control signal of the low-side charging switch of the leap capacitor.

[0044] Furthermore, the dead-time mutual exclusion control module includes: a dead-time generation unit and an adaptive pulse width frequency control unit. The dead-time generation unit is connected to the third fuse adjustment current source of the fuse adjustment unit, and the adaptive pulse width frequency control unit is connected to the dead-time generation unit.

[0045] The dead time generation unit is used to generate a dead time clock signal based on an external enable signal and an external clock signal, and to adjust the delay of the dead time clock signal based on the output signal of the third fuse adjustment current source.

[0046] The adaptive pulse width frequency control unit is used to adaptively adjust the control signal generated by the logic control and drive module according to the dead-time clock signal and the output protection signal, and adaptively adjust the pulse width and frequency of the control signal of the logic control and drive module, wherein the control signal of the logic control and drive module includes a high-side control signal and a low-side control signal.

[0047] Furthermore, the dead-time generation unit includes a fourth inverter, a second NAND gate, an eleventh switch, a twelfth switch, a fourth capacitor, and a second buffer.

[0048] The input terminal of the fourth inverter is used to input an external clock signal, and the output terminal of the fourth inverter is connected to the first input terminal of the second NAND gate.

[0049] The second input terminal of the second NAND gate is used to input an external enable signal, and the output terminal of the second NAND gate is connected to the driving terminal of the eleventh switch and the driving terminal of the twelfth switch, respectively.

[0050] The first terminal of the eleventh switch is connected to one terminal of the third fuse adjustment current source, the other terminal of the third fuse adjustment current source is connected to the power supply voltage, the second terminal of the eleventh switch is connected to the first terminal of the twelfth switch, and the second terminal of the twelfth switch is connected to the signal ground.

[0051] One end of the fourth capacitor is connected to the first end of the twelfth switch, and the other end of the fourth capacitor is connected to the second end of the twelfth switch.

[0052] The input terminal of the second buffer is connected to one end of the fourth capacitor, and the output terminal of the second buffer is connected to the adaptive pulse width frequency control unit.

[0053] Furthermore, the charge pump output module includes a flyback capacitor, an output capacitor, a high-side switch, and a low-side switch; the positive terminal of the flyback capacitor is connected to the first terminal of the high-side switch, the negative terminal of the flyback capacitor is connected to the first terminal of the low-side switch, the second terminal of the high-side switch is connected to the positive terminal of the output capacitor, the second terminal of the low-side switch is connected to the negative terminal of the output capacitor, and the control terminals of the high-side switch and the low-side switch are both connected to the logic control and drive module.

[0054] The logic control and drive module includes a high-side logic control and drive unit and a low-side logic control and drive unit. The high-side logic control and drive unit is connected to the high-side switch, and the low-side logic control and drive unit is connected to the low-side switch.

[0055] The high-side logic control and drive unit is used to output a high-side drive signal according to the high-side control signal to control the on / off state of the high-side switch.

[0056] The low-side logic control and drive unit is used to output a low-side drive signal according to the low-side control signal to control the on / off state of the low-side switch.

[0057] The charge pump control circuit provided by this invention detects the output voltage and generates an output protection signal through an output voltage detection module. The dead-zone mutual exclusion control module adaptively adjusts the conduction time of the charge pump output module according to the output protection signal, realizing adaptive protection under abnormal operating conditions such as output short circuit, undervoltage, and overvoltage. The step-by-step charging control module adjusts the charging rate step by step according to the voltage of the leap capacitor, realizing critical damped charging of the leap capacitor and reducing overshoot spikes. Thus, the reliability of the charge pump control circuit under extreme application conditions is improved. Attached Figure Description

[0058] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.

[0059] Figure 1 The structural block diagram of the charge pump control circuit provided by the present invention.

[0060] Figure 2 The circuit diagram of the output voltage detection module provided by the present invention.

[0061] Figure 3 The structural block diagram of the step-by-step charging control module provided by the present invention is shown.

[0062] Figure 4 The circuit diagram of the leap capacitor detection unit provided by the present invention.

[0063] Figure 5 The circuit diagram of the step charging unit provided by the present invention.

[0064] Figure 6 The circuit schematic diagram of the dead-time mutual exclusion control module and the logic control and drive module provided by the present invention.

[0065] Figure 7 This is a structural block diagram of the adaptive pulse width frequency control unit provided by the present invention.

[0066] Figure 8 A structural block diagram illustrating a specific embodiment of the charge pump control circuit provided by the present invention.

[0067] Figure 9 The circuit diagram shows a specific implementation of the first level shifter provided by the present invention.

[0068] Figure 10 The timing diagram for the three-stage charging of the leap capacitor provided by the present invention.

[0069] Figure 11 The timing diagram for the charging and discharging control of the flyover capacitor and the output capacitor under typical operating conditions provided by this invention.

[0070] Figure 12 Timing diagram of typical operating conditions of the charge pump output stage provided by the present invention.

[0071] Figure 13 Timing diagram for triggering undervoltage protection of the charge pump output stage provided by the present invention.

[0072] Figure 14 The timing diagram for triggering overvoltage protection of the charge pump output stage provided by the present invention.

[0073] Figure 15 Timing diagram for triggering short-circuit protection of the charge pump output stage provided by the present invention. Detailed Implementation

[0074] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0075] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0076] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0077] This embodiment provides a charge pump control circuit. Figure 1 This is a structural block diagram of the charge pump control circuit 10 provided according to an embodiment of the present invention, such as... Figure 1 As shown, it includes: a charge pump output module 100, an output voltage detection module 200, a step-charge control module 300, a dead-zone mutual exclusion control module 400, and a logic control and drive module 500; the output voltage detection module 200 is connected to the charge pump output module 100, the dead-zone mutual exclusion control module 400 is connected to the output voltage detection module 200, the logic control and drive module 500 and the step-charge control module 300 are both connected to the dead-zone mutual exclusion control module 400, and the step-charge control module 300 and the logic control and drive module 500 are both connected to the charge pump output module 100.

[0078] In this embodiment of the invention, the charge pump output module 100 is used to store energy through charging the leap capacitor and output an output voltage higher than the power supply voltage. Specifically, the charge pump output module 100 is provided with a leap capacitor and an output capacitor. During the charging phase, the leap capacitor is charged and stores energy; during the discharging phase, the leap capacitor discharges to the output capacitor, thereby establishing an output voltage higher than the power supply voltage across the output capacitor, which is used to drive the high-side N-type field-effect transistor of the power driver chip.

[0079] In this embodiment of the invention, the output voltage detection module 200 is used to detect the output voltage of the charge pump output module and generate an output protection signal based on the output voltage. The output protection signal includes at least an undervoltage protection signal, a short-circuit protection signal, and an overvoltage protection signal. Specifically, the output voltage detection module 200 detects the output voltage across the output capacitor in real time and compares it with a corresponding reference signal. When the output voltage is lower than the undervoltage threshold, the undervoltage protection signal is effective; when the output voltage is lower than the short-circuit threshold, the short-circuit protection signal is effective; and when the output voltage is higher than the overvoltage threshold, the overvoltage protection signal is effective.

[0080] In this embodiment of the invention, the step-by-step charging control module 300 is used to detect the voltage of the leap capacitor in the charge pump output module and adjust the charging rate of the leap capacitor in steps according to the voltage of the leap capacitor. Specifically, the step-by-step charging control module 300 detects the voltage across the leap capacitor in real time. When the voltage of the leap capacitor is low, a faster charging rate is used to charge the leap capacitor; as the voltage of the leap capacitor increases, the charging rate is gradually reduced, thereby avoiding overshoot spikes during the charging process of the leap capacitor.

[0081] In this embodiment of the invention, the dead-time mutual exclusion control module 400 is used to control the logic control and drive module according to the output protection signal to adjust the conduction time of the charge pump output module. Specifically, the dead-time mutual exclusion control module 400 receives the output protection signal generated by the output voltage detection module, and adaptively shortens or shuts off the conduction time of the charge pump output module under abnormal operating conditions such as output short circuit, output voltage undervoltage, and output voltage overvoltage, thereby reducing short-circuit power consumption and protecting the circuit.

[0082] In this embodiment of the invention, the logic control and drive module 500 is used to output a drive signal to control the on / off state of the charge pump output module. Specifically, the logic control and drive module 500 receives a control signal output by the dead-zone mutual exclusion control module, generates a drive signal, and controls the on / off state of the switching devices within the charge pump output module 100 to achieve alternating switching between charging and discharging of the leap capacitor.

[0083] In this embodiment of the invention, the charge pump control circuit is controlled by an external enable signal Φenable and an external clock signal Φclk. When the external enable signal Φenable is invalid, the charge pump control circuit stops working, the voltage across the flyaway capacitor and the voltage across the output capacitor both drop to a low level, and the high-side switch and low-side switch in the charge pump output module 100 are both turned off. When the external enable signal Φenable is valid, the charge pump control circuit starts working, and the output voltage detection module 200 and the step-by-step charging control module 300 are not affected by the external clock signal Φclk and continue to perform detection. The external clock signal Φclk serves as a time axis control line, controlling the timing of the step-by-step charging control module 300 and the dead-time mutual exclusion control module 400.

[0084] Therefore, the charge pump control circuit provided by this invention detects the output voltage and generates an output protection signal through an output voltage detection module, and the dead-zone mutual exclusion control module adaptively adjusts the conduction time of the charge pump output module according to the output protection signal, thereby realizing adaptive protection under abnormal operating conditions such as output short circuit, undervoltage, and overvoltage; and by using a step-by-step charging control module to adjust the charging rate step by step according to the voltage of the leap capacitor, the critical damping charging of the leap capacitor is realized, reducing overshoot spikes; thus improving the reliability of the charge pump control circuit under extreme application conditions.

[0085] In embodiments of the present invention, such as Figure 2 As shown, the output voltage detection module 200 includes a first comparator AMP1, a second comparator AMP2, a third comparator AMP3, a first resistor R1, a second resistor R2, and a first capacitor C1. One end of the first resistor R1 is connected to the positive output terminal of the charge pump output module 100, and the other end of the first resistor R1 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the negative output terminal of the charge pump output module 100. One end of the first capacitor C1 is connected to one end of the second resistor R2, and the other end of the first capacitor C1 is connected to the other end of the second resistor R2. The first resistor R1 and the second resistor R2 form a voltage divider network to divide the output voltage across the output capacitor Co. The first capacitor C1 performs voltage regulation and filtering on the divided voltage. The divided voltage vcomp1 = [R2 / (R1+R2)]*(VBST-SW), where VBST-SW is the voltage difference across the output capacitor Co.

[0086] The inverting input of the first comparator AMP1 is connected to one end of the second resistor R2, and the non-inverting input is connected to the undervoltage protection reference signal vref_uvlo. The output of the first comparator AMP1 is the undervoltage protection signal Φuvlo. When the voltage after voltage division is lower than the undervoltage protection reference signal vref_uvlo, the first comparator AMP1 outputs the valid undervoltage protection signal Φuvlo.

[0087] The inverting input of the second comparator AMP2 is connected to one end of the second resistor R2, and the non-inverting input is connected to the short-circuit protection reference signal vref_scp. The output of the second comparator AMP2 is the short-circuit protection signal Φscp. When the voltage after voltage division is lower than the short-circuit protection reference signal vref_scp, the second comparator AMP2 outputs a valid short-circuit protection signal Φscp.

[0088] The non-inverting input of the third comparator AMP3 is connected to one end of the second resistor R2, and the inverting input is connected to the overvoltage protection reference signal vref_ovp. The output of the third comparator AMP3 is the overvoltage protection signal Φovp. When the voltage after voltage division is higher than the overvoltage protection reference signal vref_ovp, the third comparator AMP3 outputs the valid overvoltage protection signal Φovp.

[0089] In embodiments of the present invention, such as Figure 3 As shown, the step-by-step charging control module 300 includes a leap capacitor detection unit 310 and a step-by-step charging unit 320. The step-by-step charging unit 320 is connected to the leap capacitor detection unit 310, the leap capacitor detection unit 310 is connected to the leap capacitor Cfly, and the step-by-step charging unit 320 is connected to the dead zone mutual exclusion control module 400.

[0090] Specifically, the leap capacitor detection unit 310 is used to detect the voltage of the leap capacitor Cfly and generate a charging rate control signal based on the voltage of the leap capacitor Cfly. A first rate charging control signal Φfast is generated when the voltage of the leap capacitor Cfly is lower than a first preset ratio of a preset voltage; a second rate charging control signal Φslow is generated when the voltage of the leap capacitor is higher than a second preset ratio of a preset voltage; and a third rate charging control signal Φmiddle is generated when the voltage of the leap capacitor is between the first preset ratio and the second preset ratio of the preset voltage. The first preset ratio is less than the second preset ratio and both are less than 1. The charging rate of the first rate charging control signal Φfast is greater than the charging rate of the third rate charging control signal Φmiddle, and the charging rate of the third rate charging control signal Φmiddle is greater than the charging rate of the second rate charging control signal Φslow.

[0091] It should be understood that the first rate charging control signal Φfast can be specifically understood as a fast charging signal, the third rate charging control signal Φmiddle can be specifically understood as a medium-speed charging signal, and the second rate charging control signal Φslow can be specifically understood as a slow charging signal. For example, when the voltage of the leap capacitor is lower than 40% of the preset voltage, the first rate charging control signal Φfast is high, that is, the charging process of the leap capacitor is controlled according to the charging rate of the first rate charging control signal; when the voltage of the leap capacitor is between 40% and 70% of the preset voltage, the third rate charging control signal Φmiddle is high, that is, the charging process of the leap capacitor is controlled according to the charging rate of the third rate charging control signal; when the voltage of the leap capacitor is higher than 70% of the preset voltage, the second rate charging control signal Φslow is high, that is, the charging process of the leap capacitor is controlled according to the charging rate of the second rate charging control signal.

[0092] In this embodiment of the invention, the step-by-step charging unit 320 is used to adjust the charging rate of the leap capacitor step by step according to the charging rate control signal.

[0093] It should be understood that the step-by-step charging unit 320 gradually adjusts the charging rate of the leap capacitor based on Φfast, Φmiddle, and Φslow. As the voltage of the leap capacitor increases, the charging rate decreases, ultimately achieving a three-segment broken-line charging curve, achieving the effect of critical damped charging, and reducing charging overshoot peaks.

[0094] In embodiments of the present invention, such as Figure 4 As shown, the leap capacitor detection unit 310 includes a fourth comparator AMP4, a fifth comparator AMP5, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a first NOR gate NOR1.

[0095] One end of the third resistor R3 is connected to the positive terminal of the leap capacitor Cfly, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the negative terminal of the leap capacitor Cfly. One end of the second capacitor C2 is connected to one end of the fourth resistor R4, and the other end of the second capacitor C2 is connected to the other end of the fourth resistor R4. The third resistor R3 and the fourth resistor R4 form a voltage divider network, which divides the voltage across the leap capacitor Cfly. The second capacitor C2 performs voltage regulation and filtering on the divided voltage. The voltage after voltage division is vcomp2 = [R4 / (R3+R4)]*(VB-VS), where VB-VS is the voltage difference across the leap capacitor Cfly.

[0096] The inverting input of the fourth comparator AMP4 is connected to one end of the fourth resistor R4, the non-inverting input is connected to the first speed charging reference signal, and the output is connected to the first input of the first NOR gate NOR1. The fourth comparator AMP4 is used to output the first rate charging control signal vref_fast. When the voltage of the jump capacitor Cfly after voltage division is lower than the first speed charging reference signal vref_fast, the fourth comparator AMP4 outputs a valid first rate charging control signal Φfast.

[0097] The non-inverting input of the fifth comparator AMP5 is connected to one end of the fourth resistor R4, and the inverting input is connected to the second speed charging reference signal vref_slow. The output of the fifth comparator AMP5 is connected to the second input of the first NOR gate NOR1. The fifth comparator AMP5 is used to output the second speed charging control signal Φslow. When the voltage of the jump capacitor Cfly after voltage division is higher than the second speed charging reference signal vref_slow, the fifth comparator AMP5 outputs a valid second speed charging control signal Φslow.

[0098] The output of the first NOR gate NOR1 is used to output the third rate charging control signal Φmiddle. When both the first rate charging control signal Φfast and the second rate charging control signal Φslow are invalid, the first NOR gate NOR1 outputs the valid third rate charging control signal Φmiddle.

[0099] In embodiments of the present invention, such as Figure 5 As shown, the step charging unit 320 includes a fuse adjustment unit 321, a charging rate adjustment unit 322, and a leap capacitor charging switch control unit 323. The charging rate adjustment unit 322 and the leap capacitor charging switch control unit 323 are both connected to the fuse adjustment unit 321.

[0100] The fuse adjustment unit 321 includes a first fuse adjustment current source Ifuse1, a second fuse adjustment current source Ifuse2, and a third fuse adjustment current source Ifuse3. The first fuse adjustment current source Ifuse1 is used to adjust the charging rate of the charging rate adjustment unit 322; the second fuse adjustment current source Ifuse2 is used to determine the delay of the switch control signal during the charging phase of the leap capacitor Cfly; and the third fuse adjustment current source Ifuse3 is used to determine the delay of the switch control signal during the discharging phase of the leap capacitor Cfly. By adjusting the charging rate and the delay of the switch control signal through the fuse adjustment current sources, the consistency of the time parameters between the step-by-step charging structure and the dead-time logic control can be ensured, and process deviations can be calibrated.

[0101] The charging rate adjustment unit 322 is used to adjust the charging rate of the leap capacitor in steps according to the charging rate control signal and the output signal of the first fuse adjustment current source Ifuse1 when the external enable signal Φenable is valid, and output the adjusted leap capacitor charging signal.

[0102] The leap capacitor charging switch control unit 323 is used to generate a leap capacitor charging switch control signal based on the external clock signal Φclk, the output signal of the second fuse adjustment current source Ifuse2, and the output signal of the dead zone mutual exclusion control module 400 when the external enable signal Φenable is valid, so as to control the on and off of the leap capacitor charging switch.

[0103] Specifically, such as Figure 5 As shown, the charging rate adjustment unit includes a first switch M1, a second switch M2, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7, an eighth switch M8, a first inverter INV1, a second inverter INV2, a third inverter INV3, a high-side charging switch KB for the leap capacitor, and a low-side charging switch KS for the leap capacitor.

[0104] The first terminal of the first switch M1 is connected to the supply voltage VDD, and the second terminal of the first switch M1 is connected to the drive terminal of the first switch M1. The drive terminal of the second switch M2 is connected to the drive terminal of the first switch M1, and the first terminal of the second switch M2 is connected to the first terminal of the first switch M1. The second terminal of the second switch M2 is connected to the first terminal of the fifth switch M5. The drive terminal of the third switch M3 is connected to the drive terminal of the first switch M1, and the first terminal of the third switch M3 is connected to the first terminal of the first switch M1. The second terminal of the third switch M3 is connected to the first terminal of the sixth switch M6. The drive terminal of the fourth switch M4 is connected to the drive terminal of the first switch M1, and the first terminal of the fourth switch M4 is connected to the first terminal of the first switch M1. The second terminal of the fourth switch M4 is connected to the first terminal of the seventh switch M7. The first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 constitute a current mirror, where the first switch M1 is the main current mirror circuit, and the second switch M2, the third switch M3, and the fourth switch M4 are the branches of the current mirror. Among the three current mirror paths, the second switch M2 has the largest width-to-length ratio and its branch current is the largest, corresponding to the charging rate of the first rate charging control signal Φfast (fast charging); the third switch M3 has the second largest width-to-length ratio and its branch current is the second largest, corresponding to the charging rate of the third rate charging control signal Φmiddle (medium-speed charging); the fourth switch M4 has the smallest width-to-length ratio and its branch current is the smallest, corresponding to the charging rate of the second rate charging control signal Φslow (slow charging).

[0105] The driving terminal of the fifth switch M5 is connected to the output terminal of the first inverter INV1, and the input terminal of the first inverter INV1 is connected to the first rate charging control signal Φfast. The second terminal of the fifth switch M5 is connected to the first terminal of the high-side charging switch KB of the leap capacitor. The driving terminal of the sixth switch M6 is connected to the output terminal of the second inverter INV2, and the input terminal of the second inverter INV2 is connected to the third rate charging control signal Φmiddle. The second terminal of the sixth switch M6 is connected to the first terminal of the high-side charging switch KB of the leap capacitor. The driving terminal of the seventh switch M7 is connected to the output terminal of the third inverter INV3, and the input terminal of the third inverter INV3 is connected to the second rate charging control signal Φslow. The second terminal of the seventh switch M7 is connected to the first terminal of the high-side charging switch KB of the leap capacitor. Thus, the first rate charging control signal Φfast, the third rate charging control signal Φmiddle, and the second rate charging control signal Φslow control the on / off states of the fifth switch M5, the sixth switch M6, and the seventh switch M7, respectively, thereby controlling whether the corresponding branch current in the current mirror charges the leap capacitor Cfly.

[0106] The drive terminal of the eighth switch M8 is connected to an external enable signal Φenable. The first terminal of the eighth switch M8 is connected to the second terminal of the first switch M1. The second terminal of the eighth switch M8 is connected to the first terminal of the first fuse adjustment current source Ifuse1. The other terminal of the first fuse adjustment current source Ifuse1 is connected to signal ground. When the external enable signal Φenable is valid, the eighth switch M8 is turned on, the main circuit of the current mirror is turned on, and each branch of the current mirror is controlled by the corresponding charging rate control signal. When the external enable signal Φenable is invalid, the eighth switch M8 is turned off, the main circuit of the current mirror is cut off, and charging stops.

[0107] In this embodiment of the invention, the first switch M1 to the seventh switch M7 can be P-type MOS transistors, and the eighth switch M8 can be N-type MOS transistors. Based on this, the first terminal of the first switch M1 to the seventh switch M7 is the source, and the second terminal is the drain; the first terminal of the eighth switch M8 is the drain, and the second terminal is the source.

[0108] The second terminal of the high-side charging switch KB is connected to the positive terminal of the high-side charging capacitor Cfly, and the second terminal of the low-side charging switch KS is connected to the negative terminal of the high-side charging capacitor Cfly. The first terminal of the low-side charging switch KS is connected to signal ground. The control terminals of both the high-side charging switch KB and the low-side charging switch KS are connected to the output terminal of the high-side charging switch control unit 323. Preferably, both the high-side charging switch KB and the low-side charging switch KS can be designed using NMOS to control the charging phase of the high-side charging capacitor Cfly.

[0109] In embodiments of the present invention, such as Figure 5 As shown, the leap capacitor charging switch control unit 323 includes a ninth switch M9, a tenth switch M10, a first NAND gate NAND1, a first buffer BUFF1, a first level shifter LS1, and a third capacitor C3.

[0110] The first input of the first NAND gate NAND1 is connected to the external enable signal Φenable, and the second input is connected to the external clock signal Φclk. The output of the first NAND gate NAND1 is connected to the driving terminals of the ninth switch M9 and the tenth switch M10, respectively. The first terminal of the ninth switch M9 is connected to one terminal of the second fuse adjustment current source Ifuse2, and the other terminal of the second fuse adjustment current source Ifuse2 is connected to the supply voltage VDD. The second terminal of the ninth switch M9 is connected to the first terminal of the tenth switch M10, and the second terminal of the tenth switch M10 is connected to signal ground. One terminal of the third capacitor C3 is connected to the first terminal of the tenth switch M10, and the other terminal of the third capacitor C3 is connected to the second terminal of the tenth switch M10.

[0111] When the external enable signal Φenable is valid, if the external clock signal Φclk has a rising edge, the ninth switch M9 is turned on and the tenth switch M10 is turned off. The second fuse adjustment current source Ifuse2 charges the third capacitor C3 through the ninth switch M9. After charging to the toggle level of the first buffer BUFF1, the first buffer BUFF1 outputs a valid switch control signal. If the external clock signal has a falling edge, the tenth switch M10 is turned on and the ninth switch M9 is turned off. The charge of the third capacitor C3 is quickly discharged through the tenth switch M10, and the first buffer BUFF1 outputs an invalid switch control signal. Therefore, the switch control signal only has a delay at the rising edge of the external clock signal, and the falling edges of the two are almost synchronized. This delay is determined by the second fuse adjustment current source Ifuse2.

[0112] The input of the first buffer BUFF1 is connected to the first terminal of the tenth switch M10. The output of the first buffer BUFF1 is connected to the input of the first level shifter LS1. The output of the first level shifter LS1 is connected to the control terminal of the high-side charging switch KB of the leap capacitor and is used to output the control signal Φb of the high-side charging switch KB. The output of the first buffer BUFF1 is also connected to the control terminal of the low-side charging switch KS of the leap capacitor and is used to output the control signal Φs of the low-side charging switch KS. Since the high-side charging switch KB of the leap capacitor can be an NMOS and its source is connected to the positive terminal of the leap capacitor Cfly, it needs a level higher than that node to reliably conduct. Therefore, it is driven after level shifting by the first level shifter LS1. The source of the low-side charging switch KS of the leap capacitor is connected to signal ground and can be directly driven by the output of the first buffer BUFF1.

[0113] In this embodiment of the invention, the ninth switch M9 can be a P-type MOS transistor, and the tenth switch M10 can be an N-type MOS transistor. Based on this, the first terminal of the ninth switch M9 is the source and the second terminal is the drain; the first terminal of the tenth switch M10 is the drain and the second terminal is the source.

[0114] In embodiments of the present invention, such as Figure 6 As shown, the dead time mutual exclusion control module 400 includes: a dead time generation unit 410 and an adaptive pulse width frequency control unit 420. The dead time generation unit 410 is connected to the third fuse adjustment current source Ifuse3 of the fuse adjustment unit 321, and the adaptive pulse width frequency control unit 420 is connected to the dead time generation unit 410.

[0115] Specifically, the dead time generation unit 410 is used to generate a dead time clock signal Φadj based on the external enable signal Φenable and the external clock signal Φclk, and adjust the delay of the dead time clock signal based on the output signal of the third fuse adjustment current source Ifuse3.

[0116] Specifically, the adaptive pulse width frequency control unit 420 is used to adaptively adjust the control signal of the logic control and drive module according to the dead time clock signal Φadj and the output protection signal, and adaptively adjust the pulse width and frequency of the control signal of the logic control and drive module 500, wherein the control signal of the logic control and drive module 500 includes a high-side control signal and a low-side control signal.

[0117] In this embodiment of the invention, the adaptive pulse width and frequency control unit 420 adaptively adjusts the pulse width and frequency of the high-side control signal and the low-side control signal according to the undervoltage protection signal, short-circuit protection signal and overvoltage protection signal in the output protection signal, thereby adaptively adjusting the conduction time of the charge pump output module under abnormal operating conditions such as output short circuit, output voltage undervoltage, and output voltage overvoltage.

[0118] In embodiments of the present invention, such as Figure 6 As shown, the dead time generation unit 410 includes a fourth inverter INV4, a second NAND gate NAND2, an eleventh switch M11, a twelfth switch M12, a fourth capacitor C4, and a second buffer BUFF2.

[0119] The input of the fourth inverter INV4 is used to input the external clock signal Φclk, and the output of the fourth inverter INV4 is connected to the first input of the second NAND gate NAND2. The second input of the second NAND gate NAND2 is used to input the external enable signal Φenable, and the output of the second NAND gate NAND2 is connected to the driving terminals of the eleventh switch M11 and the twelfth switch M12, respectively. The first terminal of the eleventh switch M11 is connected to one terminal of the third fuse adjustment current source Ifuse3, and the other terminal of the third fuse adjustment current source Ifuse3 is connected to the supply voltage VDD. The second terminal of the eleventh switch M11 is connected to the first terminal of the twelfth switch M12, and the second terminal of the twelfth switch M12 is connected to signal ground. One terminal of the fourth capacitor C4 is connected to the first terminal of the twelfth switch M12, and the other terminal of the fourth capacitor C4 is connected to the second terminal of the twelfth switch M12.

[0120] Specifically, when the external enable signal Φenable is valid, if the external clock signal Φclk has a falling edge, the eleventh switch M11 is turned on and the twelfth switch M12 is turned off. The third fuse adjustment current source Ifuse3 charges the fourth capacitor C4 through the eleventh switch M11. After charging to the toggle level of the second buffer BUFF2, the second buffer BUFF2 outputs a valid dead-time clock signal Φadj. If the external clock signal Φclk has a rising edge, the twelfth switch M12 is turned on and the eleventh switch M11 is turned off. The charge of the fourth capacitor C4 is quickly discharged through the twelfth switch M12, and the second buffer BUFF2 outputs an invalid dead-time clock signal Φadj. Therefore, the dead-time clock signal Φadj only has a delay at the falling edge of the external clock signal Φclk, and the rising edges of the two are almost synchronized. This delay is determined by the third fuse adjustment current source Ifuse3, thereby achieving dead-time mutual exclusion between the discharge and charging stages of the leap capacitor Cfly.

[0121] In this embodiment of the invention, the input terminal of the second buffer BUFF2 is connected to one end of the fourth capacitor C4, and the output terminal of the second buffer BUFF2 is connected to the adaptive pulse width frequency control unit 420.

[0122] In this embodiment of the invention, the eleventh switch M11 can be a P-type MOS transistor, and the twelfth switch M12 can be an N-type MOS transistor. Based on this, the first terminal of the eleventh switch M11 is the source and the second terminal is the drain; the first terminal of the twelfth switch M12 is the drain and the second terminal is the source.

[0123] In embodiments of the present invention, such as Figure 7 As shown, the adaptive pulse width frequency control unit 420 includes an interrupt control module 421, a delay control module 422, and a hiccup control module 423 connected in sequence.

[0124] The interrupt control module 421 is used to determine whether the charge pump output module needs to switch on or off based on the overvoltage protection signal. Specifically, the interrupt control module 421 receives a dead-time clock signal and an overvoltage protection signal. When the overvoltage protection signal is valid, it determines that the charge pump output module does not need to switch on or off and controls the charge pump output module to remain in the off state.

[0125] The delay control module 422 is used to determine whether the conduction time of the charge pump output module needs to be shortened based on the undervoltage protection signal. Specifically, the delay control module 422 receives the output signal of the interrupt control module and the undervoltage protection signal. When the undervoltage protection signal is valid, the conduction time of the charge pump output module is shortened to half of the logic low level time of the external clock signal.

[0126] The hiccup control module 423 is used to determine whether the charge pump output module needs to be intermittently turned on based on the short-circuit protection signal. Specifically, the hiccup control module 423 receives the output signal of the delay control module and the short-circuit protection signal. When the short-circuit protection signal is valid, it controls the charge pump output module to turn on once every external clock cycle, and the turn-on time each time is half of the logic low level time of the external clock signal.

[0127] It should be noted that the implementation of the adaptive pulse width frequency control unit 420 is not specifically limited in this embodiment of the invention. Programmable hardware, digital circuit structures, etc. that can achieve the above functions are all within the protection scope of this embodiment of the invention.

[0128] In embodiments of the present invention, such as Figure 8As shown, the charge pump output module 100 includes a flyby capacitor Cfly, an output capacitor Co, a high-side switch Khs, and a low-side switch Kls. The positive terminal of the flyby capacitor Cfly is connected to the first terminal of the high-side switch Khs, and the negative terminal of the flyby capacitor Cfly is connected to the first terminal of the low-side switch Kls. The second terminal of the high-side switch Khs is connected to the positive terminal of the output capacitor Co, and the second terminal of the low-side switch Kls is connected to the negative terminal of the output capacitor Co. The control terminals of both the high-side switch Khs and the low-side switch Kls are connected to the logic control and drive module 500.

[0129] In embodiments of the present invention, such as Figure 6 As shown, the logic control and drive module 500 includes a high-side logic control and drive unit 510 and a low-side logic control and drive unit 520. The high-side logic control and drive unit 510 is connected to the high-side switch Khs, and the low-side logic control and drive unit 520 is connected to the low-side switch Kls.

[0130] The high-side logic control and drive unit 510 is used to output a high-side drive signal Φhs according to the high-side control signal to control the on / off state of the high-side switch Khs. Specifically, in this embodiment of the invention, the high-side logic control and drive unit 510 can be implemented as a second level shifter LS2.

[0131] The low-side logic control and drive unit 520 is used to output a low-side drive signal Φls according to the low-side control signal to control the on / off state of the low-side switch Kls. Specifically, in this embodiment of the invention, the low-side logic control and drive unit 520 can be implemented as a third level shifter LS3.

[0132] Preferably, both the high-side switch Khs and the low-side switch Kls can be designed using NMOS to control the discharge phase of the flyby capacitor Cfly.

[0133] In this embodiment of the invention, a specific application example is given. (Specifically combined with...) Figures 8 to 15As shown, the external clock signal Φclk is a 1 MHz clock with a 50% duty cycle and an amplitude of 5 V; the preset charging voltage of the flying capacitor Cfly is 5 V; the SW voltage is 10 V; the flying capacitor Cfly is 1 nF, and the output capacitor Co is 10 nF. The flying capacitor detection unit 310 detects the voltage difference across the flying capacitor Cfly, that is, VB-VS; the threshold corresponding to the first-rate charging control signal Φfast is 2 V, the threshold corresponding to the second-rate charging control signal Φslow is 3.5 V, and the threshold corresponding to the third-rate charging control signal Φmiddle is 2 V to 3.5 V, that is, the first preset ratio is 40%, and the second preset ratio is 70%. The output voltage detection module 200 detects the voltage difference across the output capacitor Co, that is, VBST-SW; the threshold corresponding to the undervoltage protection signal Φuvlo is 3 V, the threshold corresponding to the short-circuit protection signal Φscp is 1 V, and the threshold corresponding to the overvoltage protection signal Φovp is 6 V.

[0134] Specifically, first, when the external enable signal Φenable is low, VB=VS=GND, and both the high-side switch Khs and the low-side switch Kls are turned off. When the external enable signal Φenable is high, the charge pump control circuit starts to operate. The output voltage detection module 200 and the flying capacitor detection unit 310 are not affected by the external clock signal Φclk. The external clock signal Φclk serves as a time axis control line to control the step-by-step charging control module 300 and the dead-time mutual exclusion control module 400.

[0135] In the embodiment of the present invention, the output voltage detection module 200 performs voltage division through the first resistor R1 and the second resistor R2, and after voltage stabilization and filtering by the first capacitor C1, detects the differential pressure vcomp1 between VBST and SW. vcomp1=[R2 / (R1+R2)]*(VBST-SW). Three comparators AMP1, AMP2 and AMP3 are connected to the rear end of vcomp1. When vcomp1<vref_uvlo (3 V), Φuvlo=1; when vcomp1<vref_scp (1 V), Φscp=1; when vcomp1>vref_ovp (6 V), Φovp=1.

[0136] The flying capacitor detection unit 310 performs voltage division via the third resistor R3 and the fourth resistor R4, and after voltage stabilization and filtering by the second capacitor C2, detects the differential pressure vcomp2 between VB and VS. vcomp2=[R4 / (R3+R4)]*(VB-VS). Two comparators AMP4 and AMP5 are further connected to the rear end of vcomp2. When vcomp2<vref_fast (2V), Φfast=1; when vcomp2>vref_slow (3.5V), Φslow=1; when Φfast =0 and Φslow =0, Φmiddle=1.

[0137] The fuse trimming unit 321 controls and trims the first fuse trimming current source Ifuse1, the second fuse trimming current source Ifuse2 and the third fuse trimming current source Ifuse3, which ensures the consistency of the time parameters between the step charging unit 320 and the dead zone logic control module 400. The eighth switching transistor M8 may specifically be an NMOS, which is controlled by the external enable signal Φenable. The first switching transistor M1, the second switching transistor M2, the third switching transistor M3 and the fourth switching transistor M4 form a current mirror, where M1 is the main path of the current mirror, and M2 to M4 are the branches of the current mirror. In the branches, the aspect ratio of M2 is the largest, the aspect ratio of M3 is the second largest, and the aspect ratio of M4 is the smallest. The first rate charging control signal Φfast, the first inverter INV1 and the fifth switching transistor M5 jointly control the on-off of the branch of the second switching transistor M2; the third rate charging control signal Φmiddle, the second inverter INV2 and the sixth switching transistor M6 jointly control the on-off of the branch of the third switching transistor M3; the second rate charging control signal Φslow, the third inverter INV3 and the seventh switching transistor M7 jointly control the on-off of the branch of the fourth switching transistor M4. The current in the branch of the second switching transistor M2 is the largest, the current in the branch of the third switching transistor M3 is the second largest, and the current in the branch of the fourth switching transistor M4 is the smallest.

[0138] The high-side charging switch KB and low-side charging switch KS of the leap capacitor control the charging phase of the leap capacitor, which can be specifically designed using NMOS. The external enable signal Φenable and the external clock signal Φclk are controlled by the NAND gate NAND1, combined with the inversion of the ninth switch M9 and the tenth switch M10, to generate the switching control signal Φs for the low-side charging switch KS. When Φenable=1, if a rising edge appears in Φclk, the ninth switch M9 is turned on, and the tenth switch M10 is turned off. The second fuse adjustment current source Ifuse2 flows through the ninth switch M9 to charge the third capacitor C3 until it reaches the toggling level of the first buffer BUFF1, after which Φs=1. When Φenable=1, if a falling edge appears in Φclk, the tenth switch M10 is turned on, and the ninth switch M9 is turned off. The charge on the third capacitor C3 is immediately discharged through the tenth switch M10, quickly becoming 0, and Φs=0. Therefore, it can be assumed that Φs only has a delay at the rising edge of Φclk, while the falling edges of the two are almost synchronized. After passing through the first level shifter LS1, Φs generates Φb, and the two are in phase.

[0139] The high-side switch Khs and low-side switch Kls control the discharge phase of the flyaway capacitor Cfly, which can be specifically designed using NMOS. Φenable and Φclk are controlled by the fourth inverter INV4 and the second NAND gate NAND2, combined with the inversion of the eleventh switch M11 and the twelfth switch M12, to generate switching signals. When Φenable=1, if a falling edge appears in Φclk, the eleventh switch M11 is turned on, and the twelfth switch M12 is turned off. The third fuse trimming current source Ifuse3 flows through the eleventh switch M11 to charge the fourth capacitor C4 until it reaches the toggling level of the second buffer BUFF2, after which Φadj=1; when Φenable=1, if a rising edge appears in Φclk, the twelfth switch M12 is turned on, and the eleventh switch M11 is turned off. The charge on the fourth capacitor C4 is immediately discharged through the twelfth switch M12, quickly becoming 0, and Φadj=0. Therefore, it can be assumed that Φadj only has a delay at the falling edge of Φclk, while the rising edges of the two are almost synchronous. After being controlled by adaptive pulse width digital control, Φadj is then passed through the second level shifter LS2 and the third level shifter LS3 to generate the high-side drive signal Φhs and the low-side drive signal Φls, which are in phase.

[0140] In this application example, during the logic high level phase of the external clock signal Φclk, the step-by-step charging control module 300 charges the leap capacitor Cfly; during the logic low level phase of the external clock signal Φclk, the leap capacitor Cfly discharges the output capacitor Co. As the voltage of the leap capacitor Cfly increases, the charging rate decreases, ultimately achieving a three-segment piecewise linear charging curve, thus achieving the effect of critical damping charging.

[0141] In embodiments of the present invention, such as Figure 11 As shown, under typical operating conditions, during the logic high level phase of the external clock signal Φclk, the Φb and Φs signals of the step-by-step charging unit control the KB and KS switches to close, and the high-side drive signal Φhs and low-side drive signal Φls of the dead-time mutual exclusion control module 400 control the KHS and KLS switches to open; during the logic low level phase of the external clock signal Φclk, the Φb and Φs signals of the step-by-step charging unit control the KB and KS switches to open, and the high-side drive signal Φhs and low-side drive signal Φls of the dead-time mutual exclusion control module 400 control the KHS and KLS switches to close.

[0142] In this application example, during the logic low level phase of the external clock signal Φclk, the dead-time mutual exclusion control module 400 dynamically adjusts the on-time of the high-side switch Khs and the low-side switch Kls according to the output voltage state. Φadj and Φovp first pass through the interrupt control module to determine whether the output stage needs to switch; then, together with Φuvlo, they pass through the delay control module to determine whether the output stage on-time needs to be halved; finally, together with Φscp, they pass through the hiccup control module to determine whether intermittent on-time is required. Figure 12 As shown, when the undervoltage protection signal Φuvlo, the short-circuit protection signal Φscp, and the overvoltage protection signal Φovp are all invalid, this is a typical operating condition. The conduction time of the high-side switch Khs and the low-side switch Kls is the logic low level time of the external clock signal Φclk, i.e., 500ns; Figure 13 As shown, when the undervoltage protection signal Φuvlo is valid, the conduction time of the high-side switch Khs and the low-side switch Kls is half the low-level time of the external clock signal Φclk, i.e., 250ns; Figure 14 As shown, when the overvoltage protection signal Φovp is valid, the high-side switch Khs and the low-side switch Kls remain in the off state; Figure 15 As shown, when the short-circuit protection signal Φscp is valid, the high-side switch Khs and the low-side switch Kls are turned on once every external clock cycle, and the turn-on time is 250ns each time, which greatly reduces the short-circuit current of the output capacitor Co.

[0143] The following example uses a level shifter to illustrate its working principle. Figure 9As shown, taking the first level shifter LS1 as an example, its pre-charge capacitor has been pre-charged with a voltage difference of 2V. When the input signal has a rising edge, its low-level domain output rises from 0V to the power supply voltage VDD of the digital gate, and its high-level domain output rises from 2V to VDD+2V; when the input signal has a falling edge, its low-level domain output drops from VDD to 0V, and its high-level domain output drops from VDD+2V to 2V, thereby controlling the high-side charging switch KB of the flying capacitor. It should be understood that the specific circuit structures of the second level shifter LS2 and the third level shifter LS3 can be implemented with reference to the circuit principle of the first level shifter LS1, and will not be described again in this embodiment of the invention.

[0144] It should be noted that in practical applications, the fuse adjustment unit can be used to adjust the three-stage charging rate of step charging; it can be expanded to four or more stages of step charging rate; the percentage threshold of step charging can be arbitrarily adjusted to control the inflection point of step charging; and the percentage threshold of output voltage detection can be arbitrarily adjusted to adjust the current limiting value and conversion efficiency under different output voltages.

[0145] In summary, the charge pump control circuit provided in this embodiment of the invention detects the output voltage and generates an output protection signal through an output voltage detection module. The dead-time mutual exclusion control module adaptively adjusts the conduction time of the charge pump output module based on the output protection signal, achieving adaptive protection under abnormal conditions such as output short circuit, output voltage undervoltage, and output voltage overvoltage. This reduces short-circuit power consumption and improves conversion efficiency. The step-by-step charging control module adjusts the charging rate step-by-step based on the leap capacitor voltage, causing the critical damping of the leap capacitor to increase during charging, reducing overshoot spikes. The fuse adjustment unit adjusts the charging rate and the delay of the switch control signal, ensuring the consistency of time parameters. Therefore, the overall reliability of the charge pump control circuit under extreme application conditions is improved, making it adaptable to various extreme application conditions.

[0146] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A charge pump control circuit, characterized in that, include: The module includes a charge pump output module, an output voltage detection module, a step-by-step charging control module, a dead-zone mutual exclusion control module, and a logic control and drive module. The output voltage detection module is connected to the charge pump output module, the dead zone mutual exclusion control module is connected to the output voltage detection module, the logic control and drive module and the step charging control module are both connected to the dead zone mutual exclusion control module, and the step charging control module and the logic control and drive module are both connected to the charge pump output module. The charge pump output module is used to charge and discharge the leap capacitor to output an output voltage higher than the power supply voltage. The output voltage detection module is used to detect the output voltage of the charge pump output module and generate an output protection signal based on the output voltage. The output protection signal includes at least an undervoltage protection signal, a short-circuit protection signal, and an overvoltage protection signal. The step-by-step charging control module is used to detect the voltage of the leap capacitor in the charge pump output module and adjust the charging rate of the leap capacitor step by step according to the voltage of the leap capacitor. The dead zone mutual exclusion control module is used to control the logic control and drive module according to the output protection signal, so as to adjust the conduction time of the charge pump output module; The logic control and drive module is used to output drive signals to control the on / off state of the charge pump output module.

2. The charge pump control circuit according to claim 1, characterized in that, The output voltage detection module includes a first comparator, a second comparator, a third comparator, a first resistor, a second resistor, and a first capacitor. One end of the first resistor is connected to the positive output terminal of the charge pump output module, the other end of the first resistor is connected to one end of the second resistor, the other end of the second resistor is connected to the negative output terminal of the charge pump output module, one end of the first capacitor is connected to one end of the second resistor, and the other end of the first capacitor is connected to the other end of the second resistor. The inverting input of the first comparator is connected to one end of the second resistor, the non-inverting input of the first comparator is connected to the undervoltage protection reference signal, and the output of the first comparator outputs the undervoltage protection signal. The inverting input of the second comparator is connected to one end of the second resistor, the non-inverting input of the second comparator is connected to the short-circuit protection reference signal, and the output of the second comparator outputs the short-circuit protection signal. The non-inverting input of the third comparator is connected to one end of the second resistor, the inverting input of the third comparator is connected to the overvoltage protection reference signal, and the output of the third comparator outputs the overvoltage protection signal.

3. The charge pump control circuit according to claim 1, characterized in that, The step-by-step charging control module includes a leap capacitor detection unit and a step-by-step charging unit. The step-by-step charging unit is connected to the leap capacitor detection unit, the leap capacitor detection unit is connected to the leap capacitor, and the step-by-step charging unit is connected to the dead zone mutual exclusion control module. The leap capacitor detection unit is used to detect the voltage of the leap capacitor and generate a charging rate control signal based on the voltage of the leap capacitor. A first rate charging control signal is generated when the voltage of the leap capacitor is lower than a first preset percentage of a preset voltage; a second rate charging control signal is generated when the voltage of the leap capacitor is higher than a second preset percentage of a preset voltage; and a third rate charging control signal is generated when the voltage of the leap capacitor is between the first preset percentage and the second preset percentage of the preset voltage. The first preset percentage is less than the second preset percentage and both are less than 1. The charging rate of the first rate charging control signal is greater than the charging rate of the third rate charging control signal, and the charging rate of the third rate charging control signal is greater than the charging rate of the second rate charging control signal. The step-by-step charging unit is used to adjust the charging rate of the leap capacitor step by step according to the charging rate control signal.

4. The charge pump control circuit according to claim 3, characterized in that, The leap capacitance detection unit includes a fourth comparator, a fifth comparator, a third resistor, a fourth resistor, a second capacitor, and a first NOR gate. One end of the third resistor is connected to the positive terminal of the leap capacitor, the other end of the third resistor is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the negative terminal of the leap capacitor, one end of the second capacitor is connected to one end of the fourth resistor, and the other end of the second capacitor is connected to the other end of the fourth resistor. The inverting input of the fourth comparator is connected to one end of the fourth resistor, the non-inverting input of the fourth comparator is connected to the first speed charging reference signal, the output of the fourth comparator is connected to the first input of the first NOR gate, and the fourth comparator is used to output the first rate charging control signal. The non-inverting input of the fifth comparator is connected to one end of the fourth resistor, the inverting input of the fifth comparator is connected to the second speed charging reference signal, the output of the fifth comparator is connected to the second input of the first NOR gate, and the fifth comparator is used to output the second rate charging control signal. The output of the first NOR gate is used to output the third rate charging control signal.

5. The charge pump control circuit according to claim 3, characterized in that, The step-by-step charging unit includes a fuse adjustment unit, a charging rate adjustment unit, and a leap capacitor charging switch control unit. The charging rate adjustment unit and the leap capacitor charging switch control unit are both connected to the fuse adjustment unit. The fuse adjustment unit includes a first fuse adjustment current source, a second fuse adjustment current source, and a third fuse adjustment current source. The first fuse adjustment current source is used to adjust the charging rate of the charging rate adjustment unit. The second fuse adjustment current source is used to determine the delay of the switch control signal for the charging stage of the leap capacitor. The third fuse adjustment current source is used to determine the delay of the switch control signal for the discharging stage of the leap capacitor. The charging rate adjustment unit is used to adjust the charging rate of the leap capacitor in steps according to the charging rate control signal and the output signal of the first fuse trimming current source when the external enable signal is valid, and output the adjusted leap capacitor charging signal. The leap capacitor charging switch control unit is used to generate a leap capacitor charging switch control signal based on the external clock signal, the output signal of the second fuse trimming current source, and the output signal of the dead zone mutual exclusion control module when the external enable signal is valid.

6. The charge pump control circuit according to claim 5, characterized in that, The charging rate adjustment unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first inverter, a second inverter, a third inverter, a high-side charging switch for the leap capacitor, and a low-side charging switch for the leap capacitor. The first terminal of the first switching transistor is connected to the power supply voltage, and the second terminal of the first switching transistor is connected to the driving terminal of the first switching transistor. The driving terminal of the second switching transistor is connected to the driving terminal of the first switching transistor, the first terminal of the second switching transistor is connected to the first terminal of the first switching transistor, and the second terminal of the second switching transistor is connected to the first terminal of the fifth switching transistor. The driving terminal of the third switch is connected to the driving terminal of the first switch, the first terminal of the third switch is connected to the first terminal of the first switch, and the second terminal of the third switch is connected to the first terminal of the sixth switch. The driving terminal of the fourth switch is connected to the driving terminal of the first switch, the first terminal of the fourth switch is connected to the first terminal of the first switch, and the second terminal of the fourth switch is connected to the first terminal of the seventh switch. The driving terminal of the fifth switch is connected to the output terminal of the first inverter, the input terminal of the first inverter is connected to the first rate charging control signal, and the second terminal of the fifth switch is connected to the first terminal of the high-side charging switch of the leap capacitor. The driving terminal of the sixth switch is connected to the output terminal of the second inverter, the input terminal of the second inverter is connected to the third rate charging control signal, and the second terminal of the sixth switch is connected to the first terminal of the high-side charging switch of the leap capacitor. The driving terminal of the seventh switch is connected to the output terminal of the third inverter, the input terminal of the third inverter is connected to the second rate charging control signal, and the second terminal of the seventh switch is connected to the first terminal of the high-side charging switch of the leap capacitor. The driving terminal of the eighth switch is connected to the external enable signal, the first terminal of the eighth switch is connected to the second terminal of the first switch, the second terminal of the eighth switch is connected to the first terminal of the first fuse adjustment current source, and the other terminal of the first fuse adjustment current source is connected to signal ground. The second terminal of the high-side charging switch of the leap capacitor is connected to the positive terminal of the leap capacitor, the second terminal of the low-side charging switch of the leap capacitor is connected to the negative terminal of the leap capacitor, the first terminal of the low-side charging switch of the leap capacitor is connected to signal ground, and the control terminals of the high-side charging switch and the low-side charging switch of the leap capacitor are both connected to the output terminal of the control unit of the leap capacitor charging switch.

7. The charge pump control circuit according to claim 5, characterized in that, The leap capacitor charging switch control unit includes a ninth switch, a tenth switch, a first NAND gate, a first buffer, a first level shifter, and a third capacitor. The first input terminal of the first NAND gate is connected to the external enable signal, the second input terminal of the first NAND gate is connected to the external clock signal, and the output terminal of the first NAND gate is connected to the driving terminals of the ninth and tenth switching transistors, respectively. The first terminal of the ninth switch is connected to one end of the second fuse adjustment current source, the other end of the second fuse adjustment current source is connected to the power supply voltage, the second terminal of the ninth switch is connected to the first terminal of the tenth switch, and the second terminal of the tenth switch is connected to signal ground. One end of the third capacitor is connected to the first end of the tenth switching transistor, and the other end of the third capacitor is connected to the second end of the tenth switching transistor. The input terminal of the first buffer is connected to the first terminal of the tenth switch transistor, the output terminal of the first buffer is connected to the input terminal of the first level shifter, the output terminal of the first level shifter is connected to the control terminal of the high-side charging switch of the leap capacitor and is used to output the control signal of the high-side charging switch of the leap capacitor, and the output terminal of the first buffer is also connected to the control terminal of the low-side charging switch of the leap capacitor and is used to output the control signal of the low-side charging switch of the leap capacitor.

8. The charge pump control circuit according to claim 1, characterized in that, The dead-time mutual exclusion control module includes: a dead-time generation unit and an adaptive pulse width frequency control unit. The dead-time generation unit is connected to the third fuse adjustment current source of the fuse adjustment unit, and the adaptive pulse width frequency control unit is connected to the dead-time generation unit. The dead time generation unit is used to generate a dead time clock signal based on an external enable signal and an external clock signal, and to adjust the delay of the dead time clock signal based on the output signal of the third fuse adjustment current source. The adaptive pulse width frequency control unit is used to adaptively adjust the control signal generated by the logic control and drive module according to the dead-time clock signal and the output protection signal, and adaptively adjust the pulse width and frequency of the control signal of the logic control and drive module, wherein the control signal of the logic control and drive module includes a high-side control signal and a low-side control signal.

9. The charge pump control circuit according to claim 8, characterized in that, The dead-time generation unit includes a fourth inverter, a second NAND gate, an eleventh switch, a twelfth switch, a fourth capacitor, and a second buffer. The input terminal of the fourth inverter is used to input an external clock signal, and the output terminal of the fourth inverter is connected to the first input terminal of the second NAND gate. The second input terminal of the second NAND gate is used to input an external enable signal, and the output terminal of the second NAND gate is connected to the driving terminals of the eleventh switch and the twelfth switch, respectively. The first terminal of the eleventh switch is connected to one terminal of the third fuse adjustment current source, and the other terminal of the third fuse adjustment current source is connected to the power supply voltage. The second terminal of the eleventh switch is connected to the first terminal of the twelfth switch, and the second terminal of the twelfth switch is connected to signal ground. One end of the fourth capacitor is connected to the first terminal of the twelfth switching transistor, and the other end of the fourth capacitor is connected to the second terminal of the twelfth switching transistor. The input terminal of the second buffer is connected to one end of the fourth capacitor, and the output terminal of the second buffer is connected to the adaptive pulse width frequency control unit.

10. The charge pump control circuit according to claim 1, characterized in that, The charge pump output module includes a flyaway capacitor, an output capacitor, a high-side switch, and a low-side switch; the positive terminal of the flyaway capacitor is connected to the first terminal of the high-side switch, the negative terminal of the flyaway capacitor is connected to the first terminal of the low-side switch, the second terminal of the high-side switch is connected to the positive terminal of the output capacitor, the second terminal of the low-side switch is connected to the negative terminal of the output capacitor, and the control terminals of the high-side switch and the low-side switch are both connected to the logic control and drive module. The logic control and drive module includes a high-side logic control and drive unit and a low-side logic control and drive unit. The high-side logic control and drive unit is connected to the high-side switch, and the low-side logic control and drive unit is connected to the low-side switch. The high-side logic control and drive unit is used to output a high-side drive signal according to the high-side control signal to control the on / off state of the high-side switch; The low-side logic control and drive unit is used to output a low-side drive signal according to the low-side control signal to control the on / off state of the low-side switch.

Images