Dynamic power switch network circuit, column segment control method, chip and electronic device

Abstract

The embodiment of the application discloses a dynamic power switch network circuit, a column segment control method, a chip and electronic equipment, relates to the integrated circuit power management technical field, and is convenient for improving the overall power supply adaptability of the power switch network. The circuit comprises: the output end of a start chain unit is connected to a power rail, and is used for pre-charging the power rail; a working chain unit is connected to the power rail, and is used for main charging the power rail after pre-charging is completed; the input end of a voltage detection module of a dynamic power management unit is connected to the power rail, the output end is connected to the control end of the start chain unit and the control end of a working chain control module, and is used for outputting a switching signal when it is detected that the power rail voltage reaches a preset threshold; the input end of a load detection module is connected to a load detection point, and the output end is connected to the control end of the working chain control module, and is used for outputting a selection signal for controlling the number of column segments of the working chain unit to be turned on. The application is suitable for the multi-working condition adaptive scene of the power switch network.

Description

Technical Field

[0001] This application relates to the field of integrated circuit power management technology, and in particular to a dynamic power switch network circuit, a segment control method, a chip, and an electronic device. Background Technology

[0002] In low-power system-on-chip design, the existing dual-chain power gating structure adopts a hierarchical wake-up strategy with a pre-power-up link and a main power-up link. The pre-power-up link uses a daisy chain topology with parallel power supply pins and serial switching signals to achieve initial charging. The main power-up link completes the final power-up by using parallel power supply pins and serial switching signals. It also relies on static timing logic with a fixed voltage threshold to trigger the main charging after the pre-charging is completed, so as to suppress the inrush current during the wake-up process.

[0003] However, as modern on-chip systems increasingly demand multi-condition adaptive energy efficiency management, the fixed static triggering logic in the above solution cannot dynamically adapt the power supply capacity according to load changes, resulting in poor overall power supply adaptability and low energy efficiency of the power switching network. Summary of the Invention

[0004] In view of this, embodiments of this application provide a dynamic power switch network circuit, column segment control method, chip, and electronic device to improve the overall power supply adaptability of the power switch network.

[0005] In a first aspect, embodiments of this application provide a dynamic power switching network circuit, the circuit comprising: a startup chain unit, the output of which is connected to a power rail, for pre-charging the power rail when the chip switches from sleep mode to working mode; a working chain unit, connected to the power rail via a working chain control module, for main charging the power rail after pre-charging; and a dynamic power management unit, including a voltage detection module and a load detection module, the input of which is connected to the power rail, and the output of which is connected to the control terminal of the startup chain unit and the control terminal of the working chain control module, for outputting a switching signal when the power rail voltage reaches a preset threshold; the input of which is connected to a load detection point, and the output of which is connected to the control terminal of the working chain control module, for outputting a selection signal for controlling the number of conducting column segments of the working chain unit; wherein, the load detection point is a signal node inside the chip used to collect real-time load information; the startup chain unit and the working chain unit are arranged in an interleaved column layout on the layout, and power rails of different voltage domains are routed adjacently and alternately with ground lines.

[0006] According to a specific implementation of an embodiment of this application, the startup chain unit includes at least two first switching transistors, which are arranged in rows and columns and divided into multiple column segments. The column segments are cascaded through mode switching nodes to form a reconfigurable startup chain. The startup chain unit is configured such that: within the same column segment, each of the first switching transistors is sequentially connected in series to conduct, so that the charging current is transmitted step by step along the path within the column; between column segments, the mode switching node switches to a first state or a second state. In the first state, the column segments are connected in series to conduct sequentially, and in the second state, the column segments are connected in parallel to conduct simultaneously.

[0007] According to a specific implementation of an embodiment of this application, the working chain unit includes at least two second switching transistors, which are arranged in rows and columns and divided into multiple column segments. Each column segment is connected in parallel through a working chain control module, and each switching transistor within each column is connected in series. The working chain unit is configured such that: within the same column segment, each second switching transistor is sequentially connected in series and turned on, so that the charging current is transmitted sequentially along the path within the column; each column segment is connected in parallel through the working chain control module and turned on in groups sequentially, with a time difference between different column segments; when the working chain unit performs main charging on the power rail, each column segment is turned on sequentially at a preset time interval; after the main charging is completed, the working chain control module controls each column segment in the working chain unit to turn on or off according to a selection signal.

[0008] According to a specific implementation of an embodiment of this application, the dynamic power management unit further includes a programmable timer, which is connected to the control terminal of the work chain control module and is used to set a preset time interval for each column segment of the work chain unit.

[0009] According to a specific implementation of an embodiment of this application, the voltage detection module is configured to: when the chip switches from sleep mode to working mode, the voltage detection module detects the power rail voltage in real time and compares the power rail voltage with a first preset threshold; when the power rail voltage rises to the first preset threshold, the switching signal is output.

[0010] According to a specific implementation of an embodiment of this application, the load detection module is configured as follows: after the chip enters the working mode, the load detection module obtains the real-time load information of the chip through the load detection point, and outputs the selection signal to the work chain control module according to the real-time load information; the work chain control module controls each column segment in the work chain unit to be turned on or off according to the selection signal; when the real-time load information is greater than a second preset threshold, the load detection module controls the work chain control module to turn on all column segments; when the real-time load information is less than the second preset threshold, the load detection module controls the work chain control module to turn on only some column segments.

[0011] Secondly, embodiments of this application also provide a column segment control method for a dynamic power switch network. The method includes: when the chip switches from sleep mode to working mode, pre-charging the power rail by turning on the power rail in units of column segments, and detecting the power rail voltage in real time; when the power rail voltage is detected to reach a first preset threshold, stopping the pre-charging, and turning on the power rail in units of column segments in sequence for main charging; wherein there is a conduction time difference between different column segments, and each switch in the same column segment is turned on in series step by step; after the main charging is completed, real-time load information is obtained, and the turning on or off of each column segment during the main charging process is controlled according to the real-time load information.

[0012] According to a specific implementation of this application, when the chip switches from sleep mode to working mode, the power rail is pre-charged by turning on the power rail step by step in units of column segments. This includes: controlling the series connection between each column segment so that each column segment is turned on sequentially in series, and controlling each switch transistor in the column segment to be turned on sequentially in series along the column direction within each column segment so that the charging current flows sequentially through each column segment and is transmitted step by step along the column path within each column segment; or, controlling the parallel connection between each column segment so that each column segment is turned on simultaneously in parallel, and controlling each switch transistor in the column segment to be turned on sequentially in series along the column direction within each column segment so that the charging current is simultaneously diverted to each column segment and transmitted step by step along the column path within each column segment.

[0013] According to a specific implementation of this application, after stopping the pre-charging when the power rail voltage reaches a first preset threshold, the method includes: dividing multiple columns into at least two groups, controlling each group of columns to start conducting sequentially at a preset time interval, wherein each column within the same group is conducted simultaneously, and the preset time interval between different groups is set by a programmable timer, and after each group of columns is conducted, waiting for the preset time interval before triggering the next group of columns to start conducting; within each column, controlling each switch transistor within the column to be connected in series step by step, so that the charging current is transmitted step by step along the path within each column, and there is a conduction time difference between different columns.

[0014] According to a specific implementation of an embodiment of this application, the step of acquiring real-time load information after the main charging is completed, and controlling the conduction or deactivation of each column segment during the main charging process based on the real-time load information, includes: continuously acquiring real-time load information of the chip after the main charging is completed; comparing the real-time load information with a second preset threshold; when the real-time load information is greater than the second preset threshold, controlling all column segments to remain on; when the real-time load information is less than the second preset threshold, controlling some column segments to be deactivated, and only keeping the remaining column segments on.

[0015] Thirdly, embodiments of this application also provide a chip, the chip comprising: a power rail; a logic circuit, the power supply terminal of the logic circuit being connected to the power rail; and a dynamic power switch network circuit, the dynamic power switch network circuit being the dynamic power switch network circuit described in any of the foregoing embodiments, the dynamic power switch network circuit being connected between the power rail and the power supply, and being used to pre-charge and main charge the power rail when the chip switches from sleep mode to working mode, and to control the number of columns participating in conduction in the dynamic power switch network circuit according to the real-time load information of the logic circuit.

[0016] Fourthly, embodiments of this application also provide an electronic device, the electronic device comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the column segment control method of the dynamic power switch network provided in any embodiment of this application.

[0017] The dynamic power switch network circuit, column segment control method, chip, and electronic device provided in the embodiments of this application acquire load information from the internal load detection points of the chip in real time through the load detection module in the dynamic power management unit and output a selection signal to control the number of conducting column segments in the working chain unit. This allows the output capability of the power switch network to be adjusted in real time according to load changes, achieving an improvement from static triggering to dynamic adaptation. Simultaneously, the staggered column layout of the start-up chain unit and the working chain unit, as well as the alternating setting of power rails and ground lines, effectively suppress coupling noise between different voltage domains and reduce the impact of parasitic parameters on power transmission. In summary, the power switch network of this application can dynamically adapt its power supply capability according to load changes, and can efficiently supply power in a better conduction state under different load conditions, thereby effectively improving the overall power supply adaptability of the power switch network. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a dynamic power switch network circuit provided for an embodiment of this application; Figure 2 This is a schematic diagram of the staggered layout of the power switch network columns provided in an embodiment of this application; Figure 3 A schematic diagram of an overall architecture of a dynamic power switch network circuit provided in an embodiment of this application; Figure 4 A schematic diagram of a specific implementation structure of the startup chain unit provided in this application embodiment; Figure 5 A schematic diagram of a specific circuit structure of a mode switching node provided in an embodiment of this application; Figure 6 A schematic diagram of a specific implementation structure of a work chain unit provided for an embodiment of this application; Figure 7 A schematic diagram of a specific structure of a work chain control module provided for an embodiment of this application; Figure 8 A schematic flowchart of a column segment control method for a dynamic power switch network provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0021] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0022] In low-power system-on-chip design, existing dual-chain power gating structures employ a hierarchical wake-up strategy with pre-power-up and main power-up links. However, this approach has several shortcomings: First, the parallel power pin topology in the pre-charge link still presents surge risks at the column level. This means that the instantaneous current spikes generated when multiple sleep transistors in the same column are simultaneously turned on are not effectively suppressed. While the pure series structure of the main charge link can limit the overall current rise rate, it results in a fixed wake-up speed, failing to meet the dynamic requirements of wake-up speed and surge suppression under different load conditions. Second, the single-column independent layout lacks well interconnects and substrate sharing optimization between columns, leading to low layout area utilization. Furthermore, the lack of systematic planning for power rail and ground traces results in significant parasitic resistance and inductance, further impacting power transmission efficiency and signal integrity. Third, relying solely on static triggering logic with a fixed voltage threshold means that the threshold is fixed once the chip is fabricated, making it impossible to detect changes in actual current demand under different operating conditions such as light, medium, and heavy loads. This results in redundant wake-up delays under light loads and insufficient surge suppression under heavy loads. Furthermore, while partial column interleaving layout technology has been applied to the layout optimization of memory cell arrays, it has not yet been applied to the layout of power gate transistors, and cannot solve the parasitic parameters and leakage current problems unique to power switching networks.

[0023] Based on this, this embodiment provides a dynamic power switch network circuit that collects load information in real time through a load detection module and dynamically adjusts the number of conducting column segments. Furthermore, it optimizes area utilization and parasitic parameters through the staggered layout of the start chain and working chain, thereby avoiding the aforementioned defects of the existing dual-chain structure.

[0024] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0025] In a first aspect, embodiments of this application provide a dynamic power switch network circuit, which facilitates improving the overall power supply adaptability of the power switch network.

[0026] like Figure 1 As shown, an embodiment of this application provides a dynamic power switch network circuit 1, including: a startup chain unit 11, a working chain unit 12, and a dynamic power management unit 13.

[0027] The startup chain unit 11 has its output terminal 110 connected to the power rail 2, used to pre-charge the power rail 2 when the chip switches from sleep mode to working mode. The working chain unit 12 is connected to the power rail 2 via the working chain control module 120, used to perform main charging on the power rail 2 after pre-charging. The dynamic power management unit 13 includes a voltage detection module 130 and a load detection module 131. The input terminal 1300 of the voltage detection module 130 is connected to the power rail 2, and the output terminal 1301 is connected to the control terminal 111 of the startup chain unit 11 and the working chain control module 120. The control terminal 1200 of the 20 is used to output a switching signal when the voltage of the power rail 2 is detected to reach a preset threshold; the input terminal 1310 of the load detection module 131 is connected to the load detection point 3, and the output terminal 1311 is connected to the control terminal 1200 of the working chain control module 120, which is used to output a selection signal to control the number of conducting column segments of the working chain unit 12; wherein, the load detection point 3 is a signal node inside the chip used to collect real-time load information; the start chain unit 11 and the working chain unit 12 are arranged in an interleaved column layout on the layout, and the power rails 2 of different voltage domains are adjacent to each other and alternately set with the ground line.

[0028] Specifically, the dynamic power switch network circuit 1 provided in this application embodiment mainly consists of three modules: a startup chain unit 11, a working chain unit 12, and a dynamic power management unit 13. In some examples, the startup chain unit 11 is composed of a small-size PMOS sleep transistor, with its input terminal connected to the RVDD power rail and its output terminal connected to the VDDP power rail, used to pre-charge the VDDP power rail when the chip switches from sleep mode to working mode; the working chain unit 12 is composed of a large-size PMOS sleep transistor, with its input terminal connected to the RVDD power rail and its output terminal connected to the VDDP power rail, used to perform main charging of the VDDP power rail after pre-charging; the dynamic power management unit 13 is connected to the control terminal 111 of the startup chain unit 11 and the control terminal 1200 of the working chain control module 120, and internally integrates... The system includes a voltage detection module 130 and a load detection module 131, which are used to control the timing of pre-charging or main charging and to dynamically adjust the power supply strategy according to the load. In some examples, the voltage detection module 130 can be implemented by a Schmitt trigger. The input terminal 1300 of the voltage detection module 130 is connected to the power rail 2, and the output terminal 1301 is connected to the control terminal 111 of the start-up chain unit 11 and the control terminal 1200 of the working chain logic control module 120, which is used to output a switching signal when the power rail voltage reaches a preset threshold. The input terminal 1310 of the load detection module 131 is connected to the load detection point 3. In some examples, the load detection point 3 is a signal node inside the chip used to collect real-time load information. It can be set at the power supply terminal of the core logic circuit or the output terminal of the current sampling circuit to obtain the chip's load information in real time.

[0029] The working process of the dynamic power switch network circuit provided in this application embodiment includes a pre-charging stage, a main charging stage, and a steady-state working stage.

[0030] During the pre-charging phase, when the chip switches from sleep mode to operating mode, the startup chain unit 11 first pre-charges the power rail 2. The startup chain unit 11 employs a dual serial daisy chain topology, combining intra-column serial and column-segment serial connections. Specifically, within the same column segment, each switch is sequentially connected in series, and between columns, they are sequentially connected in series. Through the current-limiting effect of the small-sized switches and the sequential connection mechanism of the serial topology, the amplitude of the initial inrush current is effectively limited. Simultaneously, the startup chain unit 11 can also switch to a parallel connection mode for each column segment to improve the pre-charging speed within the allowable surge range. During the pre-charging process, the input terminal 1300 of the voltage detection module 130 in the dynamic power management unit 13 monitors the voltage of the power rail 2 in real time and compares the power rail voltage with a preset threshold. When the voltage detection module 130 detects that the voltage of the power rail 2 rises to the preset threshold, its output terminal 1301 outputs a switching signal to the control terminal 111 of the start chain unit 11 and the control terminal 1200 of the working chain control module 120, controlling the start chain unit 11 to stop pre-charging and simultaneously controlling the working chain unit 12 to start entering the main charging stage.

[0031] During the main charging phase, the working chain unit 12 is turned on sequentially in groups of column segments. That is, the working chain control module 120 divides each column segment into at least two groups, and each group of column segments starts to conduct sequentially at a preset time interval. Each column segment in the same group is turned on simultaneously. After each group is turned on, it waits for a preset time interval before triggering the next group to start conducting, so that there is a time difference between different column segments. At the same time, within each column segment, each second switch is connected in series step by step to conduct, so that the charging current is transmitted step by step along the path within the column. Through the dual mechanism of inter-segment group delayed conduction and intra-segment sequential series conduction, the risk of surge current superposition caused by multiple columns being turned on simultaneously is effectively avoided, and the surge current is finely suppressed during the main charging process.

[0032] During steady-state operation, the load detection module 131 predicts the subsequent workload based on the acquired real-time load information and outputs a corresponding selection signal to the control terminal 1200 of the work chain control module 120 through its output terminal 1311. The work chain control module 120 controls the conduction or deactivation of each column segment in the work chain unit 12 according to the selection signal, thereby dynamically adjusting the number of column segments participating in power supply. In some examples, when the predicted load is large, all column segments are controlled to be turned on to ensure sufficient power supply capacity; when the predicted load is small, some redundant column segments are turned off, and only the required column segments are kept on to reduce power consumption, thereby realizing dynamic power consumption management of power supply on demand.

[0033] The dynamic power switch network circuit provided in the embodiments of this application pre-charges the power rail when the chip switches from sleep mode to working mode through the startup chain unit. This prevents excessive surge current from the power rail suddenly increasing from zero voltage to working voltage, which could damage the internal components of the chip and provide a stable voltage foundation for subsequent main charging. After the pre-charging is completed, the working chain unit takes over the main charging process. The voltage detection module in the dynamic power management unit monitors the power rail voltage in real time and outputs a switching signal when a preset threshold is reached to precisely control the timing switch between the startup chain and the working chain. At the same time, the load detection module outputs a selection signal based on the real-time load information collected from the load detection points inside the chip to control the operation. The number of conduction columns in the chain unit enables the power switch network's output capability to dynamically match the chip's real-time load requirements, avoiding redundant power consumption due to too many conduction columns under light loads and insufficient power supply due to too few conduction columns under heavy loads. The startup chain unit and the working chain unit adopt an interleaved column layout in the layout, and the power rails of different voltage domains are routed adjacently and alternately with the ground line, effectively reducing the impact of parasitic resistance and parasitic inductance on power transmission, suppressing coupling noise between different voltage domains, and improving power integrity and anti-interference capability. In summary, the power switch network of this application can provide efficient power supply with a better conduction state under different load conditions, thereby facilitating the improvement of the overall power supply adaptability of the power switch network.

[0034] Furthermore, this application achieves a balance between low surge and fast wake-up through a hierarchical power supply architecture of startup chain unit 11 and working chain unit 12. Startup chain unit 11 employs a reconfigurable topology to flexibly adapt to the varying needs of different operating conditions for surge suppression and wake-up speed. Working chain unit 12 uses a dual mechanism of grouped delayed conduction and tiered series connection within the column to suppress main charging surges. Simultaneously, dynamic power management unit 13 precisely controls the timing switching of pre-charging or main charging through a voltage detection module and replaces the traditional static triggering logic with a real-time feedback mechanism from a load detection module. This allows the output capability of the power switching network to adjust in real-time according to load changes, shutting down redundant column segments under light load to reduce power consumption and fully opening column segments under heavy load to ensure power supply capability. This achieves dynamic power management with on-demand power supply across the entire load range. Additionally, startup chain unit 11 and working chain unit 12 adopt a column-interleaved layout, with power rails and ground lines of different voltage domains alternately arranged, optimizing area utilization, reducing parasitic parameters, and suppressing latch-up effects. Through the synergistic optimization of the circuit architecture, dynamic control strategy and layout, this application effectively solves the problems of poor adaptability and low energy efficiency caused by fixed topology and static logic in the prior art. Ultimately, it achieves multi-objective synergistic optimization of inrush current suppression, wake-up speed, layout efficiency and power consumption management, and significantly improves the overall energy efficiency level of the power switching network.

[0035] At the layout level, the embodiments of this application have carried out collaborative optimization design of the startup chain unit and the working chain unit in terms of layout, so as to reduce parasitic parameters and improve power integrity. Figure 2 This is a schematic diagram of the staggered layout of the power switch network provided in an embodiment of this application, as shown below. Figure 2 As shown, the startup chain unit 11 and the working chain unit 12 are arranged in an alternating column layout. The startup chain transistor columns (startup terminals) and the working chain transistor columns (working terminals) are arranged alternately to form a uniformly distributed array structure. The startup terminals are located at the array edge or specific column positions, while the working terminals occupy the main area of ​​the array. Multiple working terminal columns are arranged continuously in the horizontal direction to achieve effective layout of the large-size working chain transistor array. In the power rail routing, the RVDD power rail and the VDDP power rail are routed adjacently, and the VSS ground line is alternately placed between each power rail, forming an alternating repeating arrangement pattern of "RVDD—VDDP—VSS—RVDD—VDDP—VSS—", effectively reducing power distributed impedance and parasitic parameters. Simultaneously, well regions within different column segments are interconnected to ensure continuity and suppress latch-up effects, providing a good physical foundation for the power switching network.

[0036] In one specific embodiment, the startup chain unit and the working chain unit are implemented using small-size PMOS and large-size PMOS respectively, and form a complete control link with hierarchical power supply and dynamic adaptation through a dynamic power management unit. Figure 3 This is a schematic diagram of an overall architecture of the dynamic power switch network circuit provided in an embodiment of this application, as shown below. Figure 3As shown, the dynamic power switching network circuit mainly consists of three modules: startup chain units (startup chain 0-1), working chain units (working chain 0-3), and a dynamic power management unit. The startup chain units are composed of small-sized PMOS sleep transistors, with their inputs connected to the RVDD power rail and their outputs connected to the VDDP power rail. They are used to pre-charge the VDDP when the chip wakes up. The startup chains are cascaded through serial-to-parallel converters, allowing the startup chain units to dynamically switch between a dual-serial daisy chain topology (in-column serial and column-segment serial) and a daisy chain topology (column-segment parallel and in-column serial) to achieve a dynamic balance between pre-charging speed and surge suppression. The working chain units are composed of large-sized PMOS sleep transistors, with their inputs connected to the RVDD power rail and their outputs connected to the VDDP power rail. The working chains are grouped and parallel controlled through a working chain logic control module, used for main charging of the VDDP after pre-charging. The dynamic power management unit is connected to the control terminals of the start-up chain unit and the working chain unit respectively. It integrates a Schmitt trigger and a working chain control module. The Schmitt trigger forms a voltage detection module, with its input connected to the power rail and its output connected to the control terminals of the start-up chain unit and the working chain logic control module. It is used to output a switching signal when the power rail voltage reaches a preset threshold, controlling the start-up chain unit to stop pre-charging and triggering the working chain unit to start main charging. The working chain control module receives the switching signal from the Schmitt trigger at its input and its output is connected to the control terminal of each working chain segment. It is used to control the sequential conduction of each segment and adjust the number of conducting segments, jointly realizing the function of pre-charging or main charging timing switching control and dynamically adjusting the power supply strategy according to the load.

[0037] In some embodiments, the startup chain unit 11 includes at least two first switching transistors, which are arranged in rows and columns and divided into multiple column segments. The column segments are cascaded through mode switching nodes to form a reconfigurable startup chain. The startup chain unit 11 is configured such that: within the same column segment, each of the first switching transistors is sequentially connected in series to conduct, so that the charging current is transmitted step by step along the path within the column; between column segments, the mode switching node switches to a first state or a second state. In the first state, the column segments are connected in series to conduct sequentially, and in the second state, the column segments are connected in parallel to conduct simultaneously.

[0038] In this embodiment, the startup chain unit 11 implements a reconfigurable topology through a mode switching node to adapt to the different requirements of surge suppression and wake-up speed under different operating conditions. Figure 4 A schematic diagram of a specific implementation structure of the startup chain unit provided in this application embodiment is shown below. Figure 4The startup chain unit 11 is composed of multiple small-sized PMOS (Weak PMOS) sleep transistors arranged in rows and columns and divided into multiple column segments. Each column segment is cascaded through a mode switching node, which can flexibly switch between two different topologies to form a reconfigurable startup chain.

[0039] The mode switching node in this embodiment adopts a serial-to-parallel converter structure to realize the dynamic switching of the start chain unit 11 between two topology states. Figure 5 A schematic diagram of a specific circuit structure of the mode switching node provided in the embodiments of this application is shown below. Figure 5 As shown, the serial-to-parallel converter includes multiple input terminals IN0 to IN2, a reference voltage terminal RVDD, and an output terminal OUT, which are used to realize the dynamic switching of the start-up chain unit between two topologies.

[0040] Its working principle is as follows: within the same column segment, the first switching transistors are connected in series sequentially, allowing the charging current to be transmitted step-by-step along the column path. That is, the current flows sequentially through the first switching transistor, the second switching transistor, and so on, until the end of the column segment. The step-by-step current limiting characteristic of the series topology suppresses the instantaneous surge spikes when a single column is turned on. Between column segments, the mode switching node can switch to either the first or second state according to system configuration instructions. In some examples, when the mode switching node is in serial output mode, i.e., the first state, the column segments are connected in series, and the charging current flows sequentially through the first column segment, the second column segment, and so on, until the last column segment, causing each column segment to be turned on sequentially. Combined with the step-by-step series conduction mechanism of the switching transistors within the column segment, a dual serial daisy chain topology of intra-column serial and column-segment serial is formed. In this dual-serial daisy chain topology, the charging current must pass through each stage sequentially, whether along the column direction or the column segment direction. Each conduction step is limited by the series resistor, thus suppressing the inrush current during pre-charging in the most conservative way. This is particularly suitable for surge-sensitive heavy load or high-reliability scenarios. When the mode switching node switches to parallel output mode, i.e., the second state, the signals from each input terminal are simultaneously output from the OUT terminal to each column segment. The columns are switched to a parallel connection, and the charging current is simultaneously distributed to each column segment, allowing each column segment to conduct in parallel at the same time. This significantly shortens the pre-charging time and improves the wake-up speed. At the same time, the switches within each column segment remain in series, meaning that although each column segment starts charging simultaneously, each column segment still conducts in series order, forming a daisy chain topology with parallel column segments and serial within columns. This daisy chain topology can effectively improve the pre-charging speed while ensuring that the inrush current does not exceed the limit, making it particularly suitable for light load or fast-response scenarios that are sensitive to wake-up time.

[0041] Specifically, when the serial-to-parallel converter is configured in serial output mode, the input signals pass through the internal logic sequentially and are output to the next column segment from the OUT terminal, forming a series connection between the column segments. The charging current flows through each column segment sequentially, realizing the serial conduction mode of the column segments to suppress the inrush current during the pre-charging process to the greatest extent. When the serial-to-parallel converter is configured in parallel output mode, the input signals are simultaneously output to each column segment from the OUT terminal, forming a parallel connection between the column segments. The charging current is simultaneously distributed to each column segment, realizing the parallel conduction mode of the column segments, effectively improving the pre-charging speed.

[0042] This embodiment, through the flexible switching between the two topology states via the aforementioned mode switching node, can achieve a dynamic balance between surge suppression and wake-up speed according to the actual application scenario. Specifically, in serial output mode, the inrush current during the pre-charging process is suppressed in the most conservative way, which is especially suitable for heavy load or high reliability scenarios that are sensitive to surges; in parallel output mode, the pre-charging speed is effectively improved while ensuring that the surge current does not exceed the limit, which is especially suitable for light load or fast response scenarios that are sensitive to wake-up time. This avoids the defect of the fixed topology structure in the prior art that cannot take into account both surge suppression and wake-up speed in the full load range, and effectively optimizes the chip wake-up performance.

[0043] In some embodiments, the working chain unit 12 includes at least two second switching transistors, which are arranged in rows and columns and divided into multiple column segments. Each column segment is connected in parallel through a working chain control module, and each switching transistor within each column is connected in series. The working chain unit 12 is configured such that: within the same column segment, each second switching transistor is connected in series step by step to conduct, so that the charging current is transmitted step by step along the path within the column; each column segment is connected in parallel through the working chain control module 120 and is turned on in groups sequentially, with a time difference between different column segments; when the working chain unit 12 performs main charging on the power rail 2, each column segment is turned on sequentially at a preset time interval; after the main charging is completed, the working chain control module 120 controls each column segment in the working chain unit 12 to turn on or off according to a selection signal.

[0044] In this embodiment, the working chain unit 12 is composed of a large-size PMOS transistor, and the working chain control module 120 realizes a hybrid topology that combines parallel connection between column segments and series connection within column segments, so as to balance the main charging speed and surge suppression. Figure 6 A schematic diagram of a specific implementation structure of the work chain unit provided in this application embodiment is shown below. Figure 6The working chain unit 12 is composed of multiple large-size PMOS (Strong PMOS) sleep transistors arranged in rows and columns and divided into multiple column segments. Its width-to-length ratio (W / L) is set to 80 / 1 to 120 / 1, which is 8 to 15 times that of the start-up chain transistors. Its on-resistance is much smaller than that of the small-size devices in the start-up chain unit, and it can provide sufficient current driving capability to meet the power supply requirements when the chip is working normally.

[0045] Figure 7 A schematic diagram of a specific structure of the work chain control module provided for an embodiment of this application is shown below. Figure 7 The workchain control module mainly includes a logic control module, a programmable timer, and a dynamic power management (DPM) detector. The input of the logic control module receives the Ready signal from the voltage detection module and the load information signal from the dynamic power management detector, and the output is connected to the control terminals PISleep0 to PISleep3 of each workchain segment.

[0046] The working process of the work chain unit 12 provided in this application embodiment includes two levels: the main charging stage and the steady-state working stage.

[0047] During the main charging phase, when the voltage detection module detects that the power rail voltage has reached a preset threshold, such as 90% of the reference voltage RVDD, and outputs a switching signal, the start-up chain unit 11 stops pre-charging, and the working chain unit 12 begins main charging of the power rail. When the logic control module receives a valid Ready signal, it initiates main charging timing control, dividing multiple columns into at least two groups. Each group of columns sequentially begins conduction according to a preset time interval set by a programmable timer. Within the same group, columns conduct simultaneously. After each group conducts, it waits for a preset time interval before triggering the next group to begin conduction, creating a time difference between different columns. In some examples, this preset time interval can be flexibly configured using a programmable timer to adapt to the varying surge suppression and wake-up speed requirements of different chip specifications and application scenarios, avoiding the superposition of surge currents caused by multiple columns conducting simultaneously. Simultaneously, within each column, each second switch is sequentially connected in series, allowing the charging current to be transmitted sequentially along the column path. The conduction of each switch stage generates a series current-limiting effect, further suppressing the surge spikes generated at the moment of single-column conduction.

[0048] After the chip enters the steady-state operating phase, the dynamic power consumption detector acquires the chip's load information in real time through the load detection point and outputs the load detection results to the logic control module. The logic control module controls the conduction or de-conduction of each column segment through each output terminal PISleep0 to PISleep3 according to the load detection results. In some cases, when the load detection module predicts that the subsequent workload is large, such as when the real-time load information is greater than the set threshold, i.e., a heavy load condition, the work chain control module 120 controls all column segments to be turned on to ensure sufficient power supply for the chip in high-performance operating conditions. When the load detection module predicts that the subsequent workload is small, such as when the real-time load information is less than the set threshold, i.e., a light or medium load condition, the work chain control module 120 turns off some redundant column segments and only keeps the required column segments on to reduce the static power consumption of the chip in light load conditions, thereby realizing dynamic power consumption management with power supply on demand.

[0049] Through the dual mechanisms of inter-segment grouped delayed conduction and intra-segment sequential series conduction, the work chain unit effectively suppresses inrush current during the main charging process while ensuring low on-resistance and sufficient power supply by utilizing large-size devices. This achieves coordinated optimization of inter-segment parallel acceleration and intra-segment serial current limiting. Simultaneously, through the coordinated operation of programmable timers and dynamic power consumption detectors, the work chain control module realizes end-to-end management from main charging timing control to steady-state load adaptation. Specifically, the programmable timer flexibly configures the column segment conduction delay to ensure that the main charging phase... It can achieve an optimal balance between surge suppression and wake-up speed according to application requirements. The dynamic power consumption detector can dynamically adjust the number of conducting columns according to load changes during the steady-state operation phase through real-time load monitoring and feedback. It can achieve adaptive power supply by keeping all columns open to ensure performance under heavy load and turning off redundant columns to reduce power consumption under light load. It avoids the power waste caused by keeping all columns on under light load due to fixed delay and static logic in existing technologies. It effectively reduces the average power consumption of the system across the entire load range and significantly improves the energy efficiency and operating condition adaptability of the power switching network.

[0050] In some embodiments, the dynamic power management unit 13 further includes a programmable timer connected to the control terminal of the work chain control module 120, which is used to set the preset time interval for each column segment of the work chain unit 12.

[0051] To further optimize the timing control accuracy of the group conduction of the work chain unit 12, this embodiment integrates a programmable timer in the dynamic power management unit. This programmable timer is connected to the control terminal of the work chain control module 120 and is used to set the preset time interval for the group conduction of each column segment of the work chain unit 12, thereby enabling flexible configuration of the column segment conduction delay during the main charging phase.

[0052] Its working principle is as follows: When the chip wakes up from sleep mode and begins main charging, the work chain control module 120 divides multiple segments into at least two groups. Each group of segments is turned on sequentially at a preset time interval. After the first group of segments is turned on, a programmable timer is started to count down. When the countdown reaches the preset time interval, the second group of segments is triggered to turn on, and so on, until all segments are turned on. In practical applications, chip designers or system developers can flexibly configure the time parameters of the programmable timer through software programming according to the different trade-offs between wake-up speed and surge suppression requirements of specific application scenarios. For example, in scenarios with strict limits on surge current, such as systems with poor power supply stability or applications sensitive to electromagnetic interference (EMI), a longer preset time interval can be set to allow each group of segments to turn on sequentially at a slower speed, thereby suppressing the surge current to a lower level. In scenarios with high requirements for wake-up speed, such as real-time systems that require fast response, a shorter preset time interval can be set to allow each group of segments to turn on sequentially quickly, thereby shortening the overall wake-up time.

[0053] With the introduction of the programmable timer, the group turn-on timing of the working chain unit 12 is no longer limited by a fixed hardware delay, but can be finely configured according to actual application requirements, achieving a precise and controllable dynamic balance between surge suppression and wake-up speed. At the same time, the time parameters of the programmable timer can be flexibly adjusted according to actual application requirements after the chip leaves the factory, without relying on fixed hardware parameters after the chip is fabricated, which significantly enhances the chip's adaptability to different application scenarios and design flexibility.

[0054] In some embodiments, the voltage detection module 130 is configured to: when the chip switches from sleep mode to working mode, the voltage detection module 130 detects the power rail voltage in real time and compares the power rail voltage with a first preset threshold; when the power rail voltage rises to the first preset threshold, the switching signal is output.

[0055] To achieve precise timing control for automatic switching to main charging after pre-charging in this embodiment, a voltage detection module 130 is included in the dynamic power management unit. In some examples, the input of the voltage detection module 130 is connected to the power rail VDDP, and the output is connected to the control terminal of the start-up chain unit and the control terminal of the work chain control module. It is used to detect the power rail voltage in real time and output a switching signal when it reaches a preset threshold, thereby providing a precise basis for determining the timing switch between pre-charging and main charging.

[0056] Its working principle is as follows: When the chip wakes up from sleep mode, the startup chain unit 11 begins to pre-charge the power rail, at which time the power rail voltage gradually rises from 0V. During this process, the voltage detection module 130 continuously monitors the instantaneous voltage value of the power rail and compares the instantaneous voltage value with a first preset threshold. The voltage detection module 130 integrates a Schmitt trigger, the positive threshold VT+ of which is set as the first preset threshold, and the first preset threshold is 90% of the reference voltage domain RVDD. For example, when RVDD=1.8V, the first preset threshold VT+ is calibrated to 1.62V. The setting of the first preset threshold is achieved through a stable reference signal provided by the reference voltage domain RVDD, which can effectively avoid inaccurate thresholds or false triggering caused by process deviations, voltage fluctuations, or temperature drift (PVT changes), ensuring the accuracy and reliability of the detection results. When the power rail voltage has not yet reached the first preset threshold, the output of the voltage detection module 130 remains in an invalid state, and the start-up chain unit continues to pre-charge the power rail. When the power rail voltage rises to or exceeds the first preset threshold, the Schmitt trigger is activated, and the output of the voltage detection module 130 immediately outputs a valid switching signal, i.e., a Ready signal, to the control terminals of the start-up chain unit and the working chain control module. Upon receiving the switching signal, the control terminal of the start-up chain unit controls the start-up chain unit to stop pre-charging; simultaneously, upon receiving the switching signal, the control terminal of the working chain control module controls the working chain unit to begin the main charging phase.

[0057] This embodiment achieves precise and reliable timing switching between the pre-charge stage and the main charge stage by using the voltage detection module 130 to monitor the power rail voltage in real time and determine the threshold of the Schmitt trigger. This avoids the problems of insufficient power rail voltage due to early switching and wake-up delay due to late switching, providing an accurate detection basis for the reliable execution of the graded power supply strategy. At the same time, it can maintain a stable threshold detection capability under PVT fluctuations, ensuring the wake-up reliability of the chip under different operating conditions.

[0058] In some embodiments, the load detection module 131 is configured to: after the chip enters the working mode, the load detection module 131 obtains the real-time load information of the chip through the load detection point 3, and outputs the selection signal to the work chain control module 120 according to the real-time load information; the work chain control module 120 controls each column segment in the work chain unit 12 to be turned on or off according to the selection signal; when the real-time load information is greater than a second preset threshold, the load detection module 131 controls the work chain control module 120 to turn on all column segments; when the real-time load information is less than the second preset threshold, the load detection module 131 controls the work chain control module 120 to turn on only some column segments.

[0059] To achieve on-demand power management after the chip enters steady-state operation, this embodiment of the application includes a load detection module 131 in the dynamic power management unit. In some examples, the input of the load detection module 131 is connected to the load detection point 3, and the output is connected to the control terminal of the work chain control module 120. This module is used to acquire the chip's load information in real time and output corresponding selection signals to the work chain control module 120 according to the load conditions, so as to control the conduction or cutoff of each column segment in the work chain unit 12. The load detection point 3 is a signal node inside the chip used to collect real-time load information, and can be specifically set at the power supply terminal of the core logic circuit or the output terminal of the current sampling circuit.

[0060] Its working principle is as follows: After the chip completes main charging and enters steady-state operation, load detection point 3 acquires the real-time load information of the chip through load monitoring point 3, and generates a corresponding selection signal based on the acquired real-time load information. This selection signal is then output to the work chain control module 120 through its output terminal. The load detection module 131 compares the acquired real-time load information with a second preset threshold, and outputs a corresponding selection signal to the work chain control module 120 based on the comparison result. When the real-time load information exceeds the second preset threshold, i.e., the chip is under heavy load, such as when the processor core is running at full speed or multiple functional modules are working simultaneously, requiring a large current supply to meet high-performance demands, the load detection module 131 outputs a corresponding selection signal to the work chain control module 120 through its output terminal, indicating that the current condition is heavy load. The work chain control module 120 controls all columns to be fully turned on based on this selection signal to ensure sufficient power supply to the chip under high-performance operating conditions. When the real-time load information is less than the second preset threshold, that is, when the chip is in a light or medium load condition, such as when the processor core is idle or only some functional modules are working and the required current is small, the load detection module 131 outputs a corresponding selection signal to the work chain control module 120 through its output terminal to indicate that the current condition is light or medium load. The work chain control module 120 shuts down some redundant column segments according to the selection signal and only keeps the required column segments on to avoid static power consumption waste caused by the full column segments being on.

[0061] Taking an exemplary scenario with four columns as an example, when the chip is under heavy load, the load detection module 131 controls the work chain control module 120 to turn on all four columns to ensure sufficient current supply. When the chip is under light load, the load detection module 131 controls the work chain control module 120 to turn on only three columns and turn off the redundant column to reduce power consumption, effectively reducing the static power consumption of the chip under light load. It should be noted that the load detection module 131 does not only perform detection once when the chip is powered on, but continuously monitors load changes throughout the entire operation of the chip, sensing changes in load status in real time. When the chip switches from light load to heavy load, the load detection module 131 responds to the load change in real time and regenerates the selection signal, controlling the work chain control module 120 to turn on more columns in a timely manner to meet the increased power supply demand. When the chip switches from heavy load to light load, the load detection module 131 also responds in real time and turns off the redundant column to save power consumption.

[0062] This embodiment achieves true closed-loop on-demand power management through the aforementioned continuous monitoring and dynamic adjustment mechanism. That is, all column segments are fully open under heavy load to ensure performance, and redundant column segments are turned off to reduce power consumption under light load. This avoids the power waste caused by the static conduction logic of existing technologies, which keeps all column segments on under light load. It effectively reduces the average power consumption of the system across the entire load range and significantly improves the energy efficiency and operating condition adaptability of the power switching network.

[0063] Secondly, embodiments of this application provide a column segment control method for a dynamic power switch network, which facilitates improving the overall power supply adaptability of the power switch network.

[0064] like Figure 8 As shown, embodiments of this application also provide a column segment control method for a dynamic power switch network, the method comprising: S11. When the chip switches from sleep mode to working mode, the power rail is pre-charged by turning on the power rail in segments and the voltage of the power rail is detected in real time. To address the technical shortcomings of existing dual-chain power gating structures that employ a fixed topology for the pre-power-on link and cannot achieve a dynamic balance between surge suppression and wake-up speed, this embodiment provides a reconfigurable pre-charge control method.

[0065] Its working principle is as follows: when the chip switches from sleep mode to working mode, it first starts to precharge the power rail. During the precharging process, the power rail is turned on step by step in column segment. That is, the charging current is transmitted step by step along the same column segment. The surge spike generated at the moment of conduction is suppressed by the step-by-step current limiting characteristics of the series topology. At the same time, the overall precharging speed is dynamically adjusted by selectively controlling the connection state between column segments.

[0066] During pre-charging, the connection status between columns can be controlled in two ways. Firstly, columns can be connected in series, allowing the charging current to flow through each column sequentially, and each column being turned on in series. In this case, the conduction of each switching transistor is limited by the series resistor, suppressing the inrush current during pre-charging in the most conservative way. Secondly, columns can be connected in parallel, allowing the charging current to be simultaneously distributed to each column, and each column being turned on in parallel, thus significantly shortening the pre-charging time. It should be noted that regardless of whether the columns are connected in series or parallel, the switching transistors within each column remain sequentially connected in series. Throughout the pre-charging process, the power rail voltage is monitored in real time and compared with a preset threshold. Pre-charging is considered complete when the power rail voltage rises to the preset threshold.

[0067] This embodiment enables the pre-charging phase to achieve a dynamic balance between surge suppression and wake-up speed based on the actual application scenario by flexibly switching between the two topology states. This avoids the problem of wake-up delay redundancy in fixed serial topology under light load, and also avoids the risk of insufficient surge suppression in fixed parallel topology under heavy load. Thus, while ensuring safe wake-up of the chip, it improves wake-up speed and operating condition adaptability.

[0068] S12. When the power rail voltage is detected to reach the first preset threshold, the pre-charging is stopped, and the power rail is turned on sequentially in groups of column segments to perform main charging; wherein there is a time difference between different column segments, and each switch in the same column segment is turned on in series step by step. This embodiment employs a dual control strategy during the main charging process, combining sequential grouping and cascading within the column, to achieve synergistic optimization of wake-up speed and surge suppression. Sequential grouping refers to dividing all column segments into at least two groups, with each group sequentially starting to conduct at preset time intervals, and all column segments within the same group conducting simultaneously. Cascading within the column refers to the cascading conduction of each switch along the column's internal direction within each column segment, allowing the charging current to be transmitted cascadingly along the column's internal path.

[0069] Its working principle is as follows: after pre-charging is completed, when the power rail voltage rises to the first preset threshold, pre-charging stops and the main charging phase is triggered. During the main charging process, a control strategy of sequential grouping is adopted. All columns are first divided into at least two groups. For example, four columns can be divided into a first group and a second group, each containing two columns. The columns in each group start conducting sequentially at a preset time interval. The columns within the same group conduct simultaneously. After each group conducts, it waits for a preset time interval before triggering the next group to start conducting, so that the columns in different groups have a clear conduction time difference. Taking four columns as an example, columns 0 and 1 in the first group conduct immediately upon entering the main charging phase. After a preset time interval, columns 2 and 3 in the second group begin conducting, thereby avoiding the superposition of surge current peaks generated when all four columns conduct simultaneously. Meanwhile, within each column segment, each switch is controlled to conduct in series step by step, so that the charging current is transmitted step by step along the path within the column. That is, the current flows through the first switch, the second switch and so on in the same column segment until the end of the column segment. The surge spike generated at the moment of single column conduction is further suppressed by the step-by-step current limiting effect of the series topology.

[0070] This embodiment utilizes a dual mechanism of inter-segment grouped delayed conduction and intra-segment tiered series conduction to achieve staggered conduction between columns during the main charging process. Specifically, inter-segment grouped delayed conduction avoids the superposition of surge currents caused by simultaneous conduction of multiple columns, while intra-segment tiered series conduction suppresses surge spikes during single-column conduction. The combined effect of these two mechanisms keeps the inrush current amplitude within a safe range during the main charging process. Simultaneously, because a large-size switching transistor is used in the main charging stage, its on-resistance is low, providing sufficient current drive capability to meet the power supply requirements during normal operation. Thus, while ensuring low on-resistance and sufficient power supply capability, surge current during the main charging process is effectively suppressed, achieving synergistic optimization of wake-up speed and surge suppression.

[0071] S13. After the main charging is completed, obtain real-time load information, and control the conduction or shutdown of each column segment during the main charging process according to the real-time load information.

[0072] After the main charging is completed, this embodiment further introduces a segment control mechanism based on real-time load to achieve dynamic management of power supply on demand.

[0073] Its working principle is as follows: After the main charging is completed and the chip enters the working state, it continuously acquires the chip's real-time load information. In some cases, this real-time load information can reflect the chip's power consumption requirements and operating status at the current moment, such as parameters like current magnitude, power consumption level, or module operating status. The real-time load information is compared with a set threshold. When the real-time load information is greater than the set threshold, i.e., the chip is in a heavy load condition, all columns are kept on to ensure sufficient power supply for the chip in high-performance operating conditions. When the real-time load information is less than the set threshold, i.e., the chip is in a light or medium load condition, some columns are turned off, leaving only the remaining columns on to avoid static power waste caused by all columns being on. It should be noted that this process is not just a single detection and configuration when the chip is powered on, but rather a continuous monitoring of load changes throughout the chip's entire operating process, dynamically adjusting the number of on columns in real time. That is, when the chip switches from a light load to a heavy load, more columns are turned on in time to meet the increased power supply demand; when the chip switches from a heavy load to a light load, redundant columns are turned off in time to save power.

[0074] The column segment control method for dynamic power switching networks provided in this application pre-charges the power rails when the chip switches from sleep mode to working mode using a startup chain unit. This prevents excessive surge current from the power rails suddenly increasing from zero voltage to the working voltage, which could damage internal chip components and provide a stable voltage foundation for subsequent main charging. After pre-charging, the working chain unit takes over the main charging process. The voltage detection module in the dynamic power management unit monitors the power rail voltage in real time and outputs a switching signal when a preset threshold is reached to precisely control the timing switch between the startup chain and the working chain. Simultaneously, the load detection module outputs a selection signal based on real-time load information collected from load detection points inside the chip. The number of conduction columns in the working chain unit is controlled to dynamically match the output capability of the power switch network with the real-time load demand of the chip, avoiding redundant power consumption caused by too many conduction columns under light load and insufficient power supply caused by too few conduction columns under heavy load. The startup chain unit and the working chain unit adopt an interleaved column layout in the layout, and the power rails of different voltage domains are routed adjacently and alternately with the ground line, which effectively reduces the impact of parasitic resistance and parasitic inductance on power transmission, suppresses coupling noise between different voltage domains, and improves power integrity and anti-interference capability. In summary, the power switch network of this application can provide efficient power supply with a better conduction state under different load conditions, thereby facilitating the improvement of the overall power supply adaptability of the power switch network.

[0075] In some embodiments, the step of pre-charging the power rail by sequentially turning on the power supply in columns when the chip switches from sleep mode to working mode includes: controlling the series connection between columns so that the columns are sequentially turned on in series, and controlling the switches in each column to be sequentially turned on in series along the column direction within each column so that the charging current flows sequentially through each column and is transmitted sequentially along the column path within each column; or, controlling the parallel connection between columns so that the columns are simultaneously turned on in parallel, and controlling the switches in each column to be sequentially turned on in series along the column direction within each column so that the charging current is simultaneously diverted to each column and transmitted sequentially along the column path within each column.

[0076] This embodiment provides two selectable column segment conduction control methods during the pre-charging phase to adapt to the varying requirements of surge suppression and wake-up speed under different operating conditions. The first method involves series connection between column segments, allowing the charging current to flow sequentially through each segment, with each segment conducting in series. The second method involves parallel connection between column segments, allowing the charging current to be simultaneously distributed to each segment, with each segment conducting in parallel. It should be noted that regardless of the method used, the switching transistors within each column segment remain connected in series, stage by stage.

[0077] Its working principle is as follows: When strict suppression of surge current is required, the first method is adopted, controlling the series connection between each column segment so that the charging current flows through each column segment sequentially. That is, the charging current first passes through the first column segment, then flows into the second column segment, and so on until the last column segment, so that each column segment is turned on sequentially in series. At the same time, within each column segment, the switching transistors within that column segment are controlled to be turned on in series step by step along the column direction. That is, the current flows sequentially through the first switching transistor, the second switching transistor, and so on until the end of the column segment, so that the charging current is transmitted step by step along the column path within each column segment. Through the dual series connection mechanism of inter-segment series connection and intra-segment series connection, the charging current must pass through step by step, whether along the column segment direction or along the column direction. Each step of conduction is subject to the current limiting effect of the series resistor, thereby suppressing the inrush current during the pre-charging process in the most conservative way.

[0078] When a faster pre-charging speed is required, a second approach is adopted. This involves controlling the parallel connection between each column segment, allowing the charging current to be simultaneously distributed to all segments. This ensures that the charging current reaches all segments at the same time, enabling them to conduct in parallel, thus significantly shortening the pre-charging time. Simultaneously, within each column segment, the switches are controlled to conduct sequentially along the column's internal path. While each column segment begins charging simultaneously, the switches within each segment conduct sequentially in series, allowing the charging current to propagate along the column's internal path. This hybrid conduction mechanism, combining parallel operation between columns and serial operation within columns, effectively improves the pre-charging speed while ensuring that inrush current does not exceed limits.

[0079] The two methods described in this embodiment can be flexibly selected according to the actual application scenario. For surge-sensitive scenarios, the first method is selected to suppress the inrush current to the maximum extent, which is especially suitable for heavy load or high reliability scenarios. For wake-up time-sensitive scenarios, the second method is selected to speed up the pre-charging speed, which is especially suitable for light load or fast response scenarios, thereby achieving a flexible balance between surge suppression and wake-up speed during the pre-charging stage.

[0080] In some embodiments, after stopping the pre-charging when the power rail voltage reaches a first preset threshold, the method includes: dividing multiple columns into at least two groups, controlling each group of columns to start conducting sequentially at a preset time interval, wherein each column in the same group is conducted simultaneously, and the preset time interval between different groups is set by a programmable timer, and after each group of columns is conducted, the preset time interval is waited for before triggering the next group of columns to start conducting; within each column, each switch in the column is controlled to be connected in series step by step, so that the charging current is transmitted step by step along the path within the column, and there is a conduction time difference between different columns.

[0081] In this embodiment, after stopping pre-charging and entering the main charging stage, a dual control strategy combining sequential grouping and series connection within the column is adopted to suppress surge current during the main charging process.

[0082] Its working principle is as follows: at the start of the main charging phase, multiple segments are first divided into at least two groups. Each group of segments begins to conduct sequentially at a preset time interval. That is, the first group of segments conducts immediately upon entering the main charging phase, and the second group of segments conducts only after the preset time interval, and so on, until all segments are conducted. Within the same group, segments conduct simultaneously. After each group conducts, it waits for the preset time interval before triggering the next group to conduct. This ensures a clear time difference between the segments in different groups, avoiding the superposition of surge current peaks caused by all segments conducting simultaneously. The preset time interval is set through a programmable timer. In some examples, this programmable timer can be flexibly configured with time parameters via software according to specific application scenarios. For example, a longer time interval can be set in surge-sensitive systems to complete the main charging more smoothly, while a shorter time interval can be set in systems with high wake-up speed requirements to accelerate the main charging process. Furthermore, within each column segment, the switching transistors within that column segment are controlled to conduct sequentially in series. That is, the current flows sequentially through the first switching transistor, the second switching transistor, and so on until the end of the column segment. This allows the charging current to be transmitted sequentially along the path within each column segment. The successive current limiting effect of the series topology further suppresses the surge spikes generated at the moment of single-column conduction.

[0083] This embodiment utilizes the dual mechanisms of inter-segment group delayed conduction and intra-segment sequential series conduction to achieve staggered conduction between each segment during the main charging process. Inter-segment group delayed conduction avoids the superposition of surge currents caused by multiple segments conducting simultaneously, while intra-segment sequential series conduction suppresses surge spikes during single-segment conduction. The combined effect of these two mechanisms controls the inrush current amplitude within a safe range during the main charging process, achieving an effective balance between wake-up speed and surge suppression during the main charging phase.

[0084] In some embodiments, the step of acquiring real-time load information after the main charging is completed, and controlling the conduction or deactivation of each column segment during the main charging process according to the real-time load information, includes: continuously acquiring real-time load information of the chip after the main charging is completed; comparing the real-time load information with a second preset threshold; when the real-time load information is greater than the second preset threshold, controlling all column segments to remain on; when the real-time load information is less than the second preset threshold, controlling some column segments to be deactivated, and only keeping the remaining column segments on.

[0085] After the main charging is completed, this embodiment further realizes the dynamic management of the column segment through real-time load monitoring, so as to optimize the balance between power consumption and power supply capacity across the entire load range.

[0086] Its working principle is as follows: After the main charging is completed, the chip enters the working state and begins to continuously acquire the chip's real-time load information. This real-time load information reflects the chip's power consumption requirements and working status at the current moment, such as parameters like current magnitude, power consumption level, or module working status. After acquiring the real-time load information, it is compared with a second preset threshold, and the corresponding column segment control strategy is executed according to the comparison result. In some examples, when the real-time load information is greater than the second preset threshold, it indicates that the chip is currently under heavy load, such as the processor core running at full speed or multiple functional modules working simultaneously, requiring a large current supply to meet high-performance requirements. At this time, all column segments are controlled to remain on to ensure sufficient power supply for the chip under high-performance working conditions. When the real-time load information is less than the second preset threshold, it indicates that the chip is currently under light or medium load, such as the processor core being idle or only some functional modules working, requiring less current. At this time, some column segments are controlled to turn off, leaving only the remaining column segments on to avoid static power waste caused by all column segments being on. Taking an exemplary scenario with four columns as an example, when the chip is under heavy load, all four columns remain on to ensure sufficient current supply; when the chip is under light load, only three columns are on, and the redundant column is off to reduce power consumption. It should be noted that this process is not just a single detection and configuration when the chip is powered on, but rather involves continuous monitoring of load changes throughout the chip's operation and dynamic adjustment of the number of on columns in real time.

[0087] This embodiment, through the aforementioned continuous monitoring and dynamic adjustment mechanism, can achieve on-demand power supply across the entire load range based on real-time load information, ensuring sufficient power supply capacity under heavy load and effectively reducing average power consumption under light load, thereby optimizing the energy efficiency and operating condition adaptability of the power switching network.

[0088] Thirdly, embodiments of this application also provide a chip that facilitates improving the overall power supply adaptability of the power switching network.

[0089] The chip includes: a power rail; a logic circuit, the power supply terminal of which is connected to the power rail; and a dynamic power switch network circuit, which is the dynamic power switch network circuit described in any of the foregoing embodiments. The dynamic power switch network circuit is connected between the power rail and the power supply, and is used to pre-charge and main charge the power rail when the chip switches from sleep mode to working mode, and to control the number of columns participating in conduction in the dynamic power switch network circuit according to the real-time load information of the logic circuit.

[0090] Fourthly, embodiments of this application also provide an electronic device that facilitates improved overall power supply adaptability of a power switching network.

[0091] like Figure 9 As shown, the electronic device provided in the embodiments of this application may include: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55, wherein the circuit board 54 is disposed inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are disposed on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, for executing the column segment control method of the dynamic power switch network provided in any of the foregoing embodiments.

[0092] For details on the specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running executable program code, please refer to the description of the foregoing embodiments, which will not be repeated here.

[0093] Based on the above technical solution, in terms of balancing surge suppression and wake-up speed, this application uses a small-size PMOS sleep transistor in the startup chain. It utilizes the large on-resistance characteristic of the transistor to limit the initial inrush current amplitude when each switch is turned on. At the same time, it achieves flexible switching between dual-serial daisy chain topology (intra-column serial and column-segment serial) and daisy chain topology (column-segment parallel and intra-column serial) through mode switching nodes. This optimizes the layout and allows for flexible adjustment of the balance between pre-charge speed and surge suppression through software configuration according to the actual application scenario. It ensures that the power rail is pre-charged to 90% of the reference voltage to complete the pre-charge preparation while keeping the surge current within a safe range. In terms of load adaptation and power management, the working chain uses large-size PMOS sleep transistors to provide sufficient current drive capability, and dynamically detects VDDP through a Schmitt trigger integrated in the dynamic power management unit. When VDDP reaches 90% of RVDD, a Ready signal is output to precisely control the timing switch from pre-charge to main charge. The dynamic power consumption detector in the dynamic power management unit calculates and predicts subsequent load conditions based on real-time load, and can adapt to light load, medium load and heavy load conditions to control the working chain segments. Under heavy load conditions, all working chain segments are turned on to ensure sufficient power supply capability, and under medium and light load conditions, some segments are turned off to reduce power consumption. This effectively suppresses inrush current during power-on and saves power consumption under light load conditions, thus achieving synergistic optimization of inrush current suppression, wake-up speed and power management across the entire load range.

[0094] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0095] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0096] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0097] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0098] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A dynamic power switching network circuit, characterized in that, The circuit includes: A startup chain unit, the output of which is connected to the power rail, is used to precharge the power rail when the chip switches from sleep mode to working mode. A working chain unit, which is connected to the power rail via a working chain control module, is used to perform main charging on the power rail after pre-charging is completed; The dynamic power management unit includes a voltage detection module and a load detection module. The input terminal of the voltage detection module is connected to the power rail, and the output terminal is connected to the control terminal of the start-up chain unit and the control terminal of the work chain control module. It is used to output a switching signal when the voltage of the power rail reaches a preset threshold. The input terminal of the load detection module is connected to the load detection point, and the output terminal is connected to the control terminal of the work chain control module. It is used to output a selection signal to control the number of conducting columns of the work chain unit. The load detection point is a signal node inside the chip used to collect real-time load information; the startup chain unit and the working chain unit are arranged in an interleaved column layout on the layout, and the power rails and ground lines of different voltage domains are arranged alternately.

2. The dynamic power switch network circuit according to claim 1, characterized in that, The startup chain unit includes at least two first switching transistors, which are arranged in rows and columns and divided into multiple column segments. The column segments are cascaded through mode switching nodes to form a reconfigurable startup chain. The start-up chain unit is configured such that: within the same column segment, each of the first switching transistors is sequentially connected in series to conduct, so that the charging current is transmitted step by step along the path within the column; between column segments, the mode switching node switches to a first state or a second state; in the first state, the column segments are connected in series to conduct sequentially; in the second state, the column segments are connected in parallel to conduct simultaneously.

3. The dynamic power switch network circuit according to claim 1, characterized in that, The work chain unit includes at least two second switching transistors, which are arranged in rows and columns and divided into multiple column segments. Each column segment is connected in parallel via a work chain control module, and the switching transistors within each column are connected in series. The work chain unit is configured as follows: Within the same column segment, each of the second switching transistors is connected in series and turned on one after another, so that the charging current is transmitted step by step along the path within the column. Each column segment is connected in parallel through the work chain control module and is turned on in groups sequentially, with a time difference between different column segments; When the working chain unit performs main charging on the power rail, each column segment is turned on sequentially at a preset time interval; After the main charging is completed, the working chain control module controls each column segment in the working chain unit to be turned on or off according to the selection signal.

4. The dynamic power switch network circuit according to claim 1, characterized in that, The dynamic power management unit also includes a programmable timer, which is connected to the control terminal of the work chain control module and is used to set the preset time interval for each column segment of the work chain unit.

5. The dynamic power switch network circuit according to claim 1, characterized in that, The voltage detection module is configured to: when the chip switches from sleep mode to working mode, the voltage detection module detects the power rail voltage in real time and compares the power rail voltage with a first preset threshold. When the power rail voltage rises to the first preset threshold, the switching signal is output.

6. The dynamic power switch network circuit according to claim 1, characterized in that, The load detection module is configured as follows: After the chip enters the working mode, the load detection module obtains the real-time load information of the chip through the load detection point, and outputs the selection signal to the work chain control module according to the real-time load information; The work chain control module controls each column segment in the work chain unit to be turned on or off according to the selection signal. When the real-time load information is greater than the second preset threshold, the load detection module controls the work chain control module to turn on all column segments. When the real-time load information is less than the second preset threshold, the load detection module controls the work chain control module to turn on only some column segments.

7. A column segment control method for a dynamic power switch network, characterized in that, The method includes: When the chip switches from sleep mode to working mode, the power rail is pre-charged by turning on the power rail in segments and the voltage of the power rail is detected in real time. When the power rail voltage is detected to reach the first preset threshold, the pre-charging is stopped, and the power rail is turned on sequentially in groups of columns to perform main charging; wherein there is a time difference between different columns, and each switch in the same column is turned on in series step by step. After the main charging is completed, real-time load information is obtained, and the conduction or shutdown of each column segment during the main charging process is controlled according to the real-time load information.

8. The column segment control method for a dynamic power switch network according to claim 7, characterized in that, The process of pre-charging the power rails by sequentially turning them on in column segments when the chip switches from sleep mode to working mode includes: The series connection between each column segment is controlled so that each column segment is turned on sequentially. Within each column segment, each switch transistor within the column segment is turned on sequentially along the column direction so that the charging current flows through each column segment sequentially and is transmitted step by step along the column path within each column segment. or, The parallel connection between each column segment is controlled so that each column segment is simultaneously and in parallel. Within each column segment, each switch transistor within the column segment is controlled to be connected in series step by step along the column direction so that the charging current is simultaneously diverted to each column segment and transmitted step by step along the column path within each column segment.

9. The column segment control method for a dynamic power switch network according to claim 7, characterized in that, After stopping the pre-charging when the power rail voltage is detected to reach a first preset threshold, the following steps are included: Multiple column segments are divided into at least two groups, and each group of column segments is controlled to start conducting sequentially at a preset time interval. Within the same group, each column segment is conducted simultaneously, and the preset time interval between different groups is set by a programmable timer. After each group of column segments is conducted, it waits for the preset time interval before triggering the next group of column segments to start conducting. Within each column segment, the switching transistors within the control column segment are connected in series and turned on one by one, so that the charging current is transmitted step by step along the path within the column segment, and there is a time difference between different column segments.

10. The column segment control method for a dynamic power switch network according to claim 7, characterized in that, The step of acquiring real-time load information after the main charging is completed, and controlling the on / off of each column segment during the main charging process based on the real-time load information, includes: After the main charging is completed, the chip's real-time load information is continuously acquired; The real-time load information is compared with a second preset threshold. When the real-time load information is greater than the second preset threshold, control all column segments to remain on. When the real-time load information is less than the second preset threshold, the control section of the column segment is turned off, and only the remaining column segment is kept on.

11. A chip, characterized in that, The chip includes: Power rail; A logic circuit, wherein the power supply terminal of the logic circuit is connected to the power rail; A dynamic power switch network circuit, wherein the dynamic power switch network circuit is any one of the dynamic power switch network circuits in claims 1 to 6, the dynamic power switch network circuit is connected between the power rail and the power supply, and is used to precharge and main charge the power rail when the chip switches from sleep mode to working mode, and control the number of column segments participating in conduction in the dynamic power switch network circuit according to the real-time load information of the logic circuit.

12. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the column segment control method of the dynamic power switch network according to any one of claims 7 to 10.

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