An adjustable power supply system for a semiconductor wafer dicing machine

Abstract

The application discloses a kind of adjustable power supply systems for semiconductor wafer dicing machine, it is related to power supply technical field, including BOOST boost circuit, FPGA control module and voltage regulation circuit.FPGA is output process setting voltage by DAC, and output voltage is sampled in real time by ADC and is closed loop correction;The operational amplifier in voltage regulation module will process setting voltage and output voltage division signal are summed after analog domain and sent into the feedback input end of BOOST boost chip, form the dual-speed closed loop architecture of analog fast loop and digital slow loop combination.Analog fast loop response time is microsecond level, responsible for inhibiting the voltage fluctuation caused by load mutation;Digital slow loop update period is millisecond level, responsible for adjusting steady state operating point according to process parameters.The application simultaneously realizes fast dynamic response, high-precision steady-state regulation and multi-scene flexible adaptation on single-stage BOOST topology, and has perfect industrial-grade protection capability.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and in particular to an adjustable power supply system for a semiconductor wafer dicing machine. Background Technology

[0002] Semiconductor wafer dicing machines are key equipment in the integrated circuit packaging process. They use an air-static electric spindle (30k–60krpm) to drive diamond blades along the dicing path to dic the wafer. A high-precision stage (positioning accuracy ±3μm) completes the feed motion. Simultaneously, some dicing machines integrate an EDM (Electrical Discharge) trimming unit, which utilizes the principle of pulsed micro-discharge thermal erosion to clean metal chips, sintered burrs, and carbon deposits from the blade and tooling surfaces without mechanical force, ensuring dicing quality.

[0003] The operating cycle time of a dicing mill dictates the unique characteristics of its power supply system: the bus load changes drastically during spindle start / stop (the step amplitude can reach more than 50% of the rated current); micro-discharge arcing during EDM trimming introduces nanosecond-level disturbances into the bus; the feed drive grating ruler is extremely sensitive to bus ripple (ripple coupling to position feedback directly affects ±3μm positioning accuracy); and any voltage drop or overshoot in the bus can cause wafer edge chipping or even breakage, resulting in irreversible losses. Therefore, the dicing mill imposes the following stringent requirements on its adjustable power supply system: 1. The output voltage is adjustable, and the adjustment accuracy is better than 0.1V; 2. Continuous output is adjustable, covering three working conditions: spindle servo (typical 48V), feed drive (typical 24V), and EDM dressing (typical 60V); 3. Low ripple noise; bus ripple must be controlled below 20mVpp (20Hz~20MHz bandwidth). 4. Short load step recovery time: Under the disturbance of spindle start-up and shutdown or tool arcing, the bus voltage drop or overshoot recovery time must be less than 500μs.

[0004] Currently, existing power supply solutions for dicing machines are mainly divided into two categories: Category 1: Traditional Analog / Linear Solutions. Some low- to mid-range dicing machines still use traditional linear regulated power supplies or switching power supplies based on analog PWM control. These power supplies have inherent drawbacks such as large size, low efficiency (typically 70%–80%), and slow dynamic response (load step recovery time is usually above milliseconds), making it difficult to simultaneously meet the three indicators mentioned above. Furthermore, pure analog solutions lack digital control capabilities, failing to adjust output parameters in real time according to different process requirements of the spindle / feed / tool ​​dressing, thus limiting the intelligence and adaptability of the equipment.

[0005] Category Two: Digital Control Schemes. With the development of digital power supply technology, high-end equipment has gradually adopted digital control power supply architectures. For example, CN219718091U discloses an FPGA-controlled LC series resonant constant current full-bridge high-voltage power supply, achieving low ripple output; CN120848670A discloses an FPGA+DAC+error amplifier voltage tracking Boost power supply with a step ≤0.1V and response ≤10ms; CN122159676A discloses a high-voltage module with front-stage DCDC coarse adjustment and rear-stage FPGA full-bridge fine adjustment, employing two-stage coordinated voltage regulation; CN111431432A discloses an FPGA-controlled Boost charging + RC discharging micro-electro-discharge pulse power supply; CN121939818A discloses an STM32-controlled flyback EDM-assisted milling power supply. These schemes demonstrate that digital control switching power supplies have achieved a high level of performance in wide-range voltage regulation, low ripple, and fast protection.

[0006] However, when the above-mentioned digital control scheme is applied to the specific scenario of a dicing machine, the following unresolved issues still exist: (1) Mismatch between topology and application scenario: Complex topologies such as resonant full bridge and two-stage cascade are suitable for high voltage and low current scenarios such as instruments / detectors / optical modules. For the dicing machine spindle servo, feed drive and EDM tool repair sharing the same front bus and needing to be continuously adjustable in a wide range of medium voltage (24V~60V), there are problems of topology redundancy, high cost and complicated debugging.

[0007] (2) Lack of collaborative design for composite loads of dicing machine: Existing digital power supply solutions are either geared to single-function EDM pulses (such as CN111431432A, CN121939818A) or to instrument bias power supply (such as CN120848670A, CN122159676A). There is no design for the three different types of loads of dicing machine, namely "spindle servo + feed drive + EDM trimmer", to be powered from the same source in the same equipment and the output voltage curve needs to be switched in real time according to the process cycle.

[0008] (3) Response delay of pure digital loop under load change conditions: Existing all-digital PWM closed-loop solutions (such as CN209375463U) rely on the serial path of ADC sampling → FPGA calculation → PWM update. When load steps occur, such as spindle start-stop, tool trimming arc start, etc., there is a sampling-calculation-update delay (typically hundreds of microseconds to several milliseconds). The output voltage drop / overshoot recovery time is long, which directly affects the cutting accuracy.

[0009] (4) Insufficient protection in industrial settings. The above-mentioned digital solutions are mostly geared towards laboratory or clean instrument environments, and lack system-level protection designs for harsh working conditions such as power grid surges, power-on impacts, multi-axis servo EMI coupling, and reverse power connection in dicing machine workshops. Summary of the Invention

[0010] To address the shortcomings of the existing technology, this invention aims to provide an adjustable power supply system for semiconductor wafer dicing machines. It combines a single-stage BOOST boost topology with FPGA digital process adaptation and introduces an analog summing feedback circuit to achieve dual-speed closed-loop control, thereby meeting the stringent requirements of dicing machines for multiple loads to be powered from the same source.

[0011] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: An adjustable power supply system for a semiconductor wafer dicing machine, comprising: The BOOST boost circuit includes a BOOST boost chip, which has a feedback input terminal; The FPGA control module includes an FPGA chip, a DAC chip, and an ADC chip. The FPGA chip outputs a process-defined voltage through the DAC chip and samples the output voltage of the BOOST boost circuit in real time through the ADC chip. The sampled value is compared with a preset target value, and the input digital quantity of the DAC chip is corrected in a closed loop based on the comparison result. The voltage regulation circuit includes an operational amplifier. The inverting input of the operational amplifier is connected to both the output of the DAC chip and the output voltage divider of the BOOST boost circuit. The output of the operational amplifier is connected to the feedback input of the BOOST boost chip. The operational amplifier sums the process setting voltage with the output voltage divider signal of the BOOST boost circuit in the analog domain, generates an analog sum signal, and sends it to the feedback input terminal of the BOOST boost chip. The BOOST boost chip adjusts the output duty cycle based on the comparison result between the analog summation signal and the internal reference voltage, forming a dual-speed closed-loop architecture that combines an analog fast loop and a digital slow loop. The analog fast loop consists of an operational amplifier, the feedback input terminal of the BOOST boost chip, and the error amplifier and PWM comparator inside the BOOST boost chip, with a response time in the microsecond range. The digital slow loop consists of an FPGA chip, an ADC chip, and a DAC chip, with an update cycle in the millisecond range.

[0012] In a preferred embodiment of the present invention, the adjustable power supply system further includes an input reverse connection protection circuit, comprising: The first and second relays are connected in parallel. The reverse connection protection diodes are connected in series with the first and second relays respectively. They are used to turn on and close the first and second relays when the power supply is connected in the correct direction, and to turn off and open the first and second relays when the power supply is connected in the reverse direction. A glass tube fuse is connected in series with the power input terminal; Current-limiting resistors are connected in series in the drive coil circuits of the first and second relays, respectively. A freewheeling diode is connected in parallel across the drive coils of the first and second relays, respectively. The load terminals of the first and second relays are connected in parallel to carry a load current greater than 5A.

[0013] In a preferred embodiment of the present invention, a power supply filter circuit is provided before the input terminal of the BOOST boost circuit, including: An NTC thermistor is connected in series in the power input circuit to suppress power-on surge current. A varistor is connected in parallel to the power input circuit to absorb lightning strikes or large energy surges. A bidirectional TVS diode, connected in parallel to the power input circuit, is used to absorb high-frequency spikes, and its response speed is faster than that of a varistor. A common-mode inductor, connected in series in the power input circuit, is used to suppress common-mode noise; Multiple electrolytic capacitors are connected in parallel with MLCC capacitors for output energy storage and ripple suppression.

[0014] In a preferred embodiment of the present invention, the voltage regulation circuit further includes: The first-stage operational amplifier receives the output voltage divider signal from the BOOST boost circuit through the first resistor and the process setting voltage from the DAC chip through the second resistor at its inverting input terminal. Its output terminal outputs the sum and inverted signal of the two signals. The second-stage operational amplifier has its input connected to the output of the first-stage operational amplifier. It is used to invert and amplify the summation and inverted signal again before outputting an analog summation signal. A bidirectional TVS protection diode is connected in parallel between the output of the second-stage operational amplifier and ground to clamp the amplitude of the analog summation signal and protect the feedback input of the BOOST boost chip from overvoltage damage.

[0015] In a preferred embodiment of the present invention, the FPGA chip in the FPGA control module communicates with the DAC chip and the ADC chip via the SPI bus. The ADC chip is a 16-bit analog-to-digital converter used to acquire the output voltage of the BOOST boost circuit in real time at a sampling rate of not less than 500kSPS; The FPGA chip sends the set voltage value to the DAC chip with an update cycle of 1ms to 10ms.

[0016] In a preferred embodiment of the present invention, the adjustable power supply system is a single-channel BOOST boost output, and its output bus is led to the DC side of the spindle servo driver, the DC side of the feed servo driver and the DC input side of the EDM trimming pulse module through the internal power distribution bus of the dicing machine.

[0017] Specifically, the FPGA control module has at least three sets of output voltage setting curves pre-stored, corresponding to the dicing machine spindle servo mode, feed drive mode and EDM tool dressing mode, respectively. The FPGA control module has a mode selection input terminal for receiving external mode commands and selecting one set from at least three sets of output voltage setting curves as the current DAC output target according to the external mode commands, so as to change the process setting voltage of the digital slow loop. During the switching process, the FPGA control module smoothly transitions the DAC output from the current value to the new target value at a slope of no more than 1V / ms.

[0018] More specifically, the output voltage setting curve for the spindle servo mode is a 48V constant voltage curve, with a 200ms soft-start ramp. The output voltage setting curve of the feed drive mode is a 24V constant voltage curve, with a 50ms soft start ramp. The output voltage setting curve of the EDM trimming mode is a 60V reference voltage curve. In trimming mode, the FPGA control module performs adaptive fine-tuning of the gap in 0.1V steps within ±2.5V of the 60V reference voltage curve based on the gap voltage sampled by the ADC, as part of the closed-loop correction of the digital slow loop.

[0019] In a preferred embodiment of the present invention, a temperature sensor is provided on the power switch of the BOOST boost circuit, and the output terminal of the temperature sensor is connected to the FPGA control module. The FPGA control module reads the temperature value in 1ms cycles. When the temperature exceeds 85℃, the PWM duty cycle is reduced in 5% steps. When the temperature exceeds 95℃, the output is turned off.

[0020] In a preferred embodiment of the present invention, the input reverse connection protection circuit, the BOOST boost circuit, the FPGA control module and the voltage regulation circuit are respectively set on independent PCB boards, and the PCB boards are interconnected through inter-board connectors.

[0021] Beneficial effects of this invention:

[0022] 1. Balancing dynamic response and steady-state accuracy, the system adopts an architecture of "analog domain summation + dual-loop shared FB node". The analog fast loop responds to load changes in microseconds, while the digital slow loop performs high-precision closed-loop correction of the output voltage in milliseconds. The two do not interfere with each other, thus solving the contradiction between fast response and process programmability in existing technologies.

[0023] 2. Flexible adaptation to multiple scenarios: The FPGA has three sets of output voltage setting curves pre-stored in the spindle servo, feed drive and EDM tool trimming. It can be switched with one click according to the external mode command. The switching process is smooth with a slope of no more than 1V / ms. The bus voltage is uninterrupted and does not drop to zero. One power supply can meet the power supply requirements of the three loads of the dicing machine.

[0024] 3. Industrial-grade protection and reliability: The input reverse connection protection module uses dual relays in parallel with reverse connection protection diodes, resulting in low on-resistance and low heat generation; the multi-stage filtering and surge protection circuit consists of NTC thermistors, varistors, bidirectional TVS diodes, common-mode inductors, and multi-stage capacitors, achieving full-link protection including power-on surge suppression, lightning strike absorption, high-frequency clamping, and EMI filtering.

[0025] 4. Comprehensive protection functions: A temperature sensor is installed on the power switch tube, and the FPGA reads the temperature value in 1ms cycle. It derating when the temperature exceeds 85℃ and shutting down when the temperature exceeds 95℃. The RC spike absorption circuit protects the MOSFET from overvoltage breakdown. The bidirectional TVS tube clamps the sampling node voltage to protect the ADC acquisition circuit.

[0026] 5. Modular design for easy maintenance. Each functional module is set on an independent PCB board and interconnected through inter-board connectors. If any module fails, it can be replaced individually without affecting the power supply sequence of other modules. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a block diagram of an adjustable power supply system used in a semiconductor wafer dicing machine. Figure 2 This is the schematic diagram of a DAC circuit. Figure 3 This is one of the schematic diagrams for a BOOST boost circuit; Figure 4 This is the second schematic diagram of a BOOST boost circuit. Figure 5 This is a schematic diagram of a voltage regulation circuit. Figure 6 Schematic diagram of the input reverse connection protection circuit; Figure 7 This is a schematic diagram of a power supply filter circuit. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described herein, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0030] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0031] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0032] To fully understand this invention, a detailed structure will be presented in the following description to illustrate the technical solution proposed by this invention. Optional embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0033] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0034] Example 1

[0035] Research has revealed an inherent, unrecognized contradiction when existing digitally controlled adjustable power supplies are applied to semiconductor wafer dicing machines: it is difficult to simultaneously achieve both load step response speed and programmability of process parameters.

[0036] Specifically, pure digital closed-loop solutions (such as CN209375463U) achieve voltage regulation through a serial path of ADC sampling → FPGA calculation → PWM update. Although this path offers programmable process parameters, it suffers from sampling-calculation-update delays of hundreds of microseconds to milliseconds. During load jumps such as spindle start-stop and tool trimming, the output voltage drop / overshoot recovery time is long, failing to meet the stringent requirements of dicing machines for bus voltage stability. Pure analog closed-loop solutions (such as traditional linear regulated power supplies) offer fast response times (microseconds), but lack digital control capabilities, unable to adjust output parameters in real time according to different process requirements of the spindle, feed, and tool trimming. While DAC + error amplifier solutions (such as CN120848670A) introduce digital settings, the error amplifier's comparison function means the DAC output serves only as a fixed reference and cannot be integrated with the output voltage divider signal in the analog domain, essentially remaining a single-loop control architecture.

[0037] To address the aforementioned contradictions, this invention proposes a novel control architecture: the process setting voltage output from the FPGA-DAC is directly summed with the output voltage divider signal of the BOOST boost circuit in the analog domain. The summation result is then fed into the feedback input of the BOOST boost chip, forming a dual-speed closed-loop architecture combining an analog fast loop and a digital slow loop. The analog fast loop consists of an operational amplifier, the feedback input of the BOOST boost chip, and an internal error amplifier and PWM comparator, with a response time in the microsecond range, responsible for suppressing voltage fluctuations caused by sudden load changes. The digital slow loop consists of an FPGA chip, an ADC chip, and a DAC chip, with an update cycle in the millisecond range, responsible for adjusting the steady-state operating point according to process parameters. Both loops share the same feedback input node, and because their time scales differ by three orders of magnitude, the update of the digital slow loop does not interfere with the load response of the analog fast loop.

[0038] This invention is based on a technical concept that is completely different from the prior art, which enables the simultaneous realization of microsecond-level load step response capability and millisecond-level process parameter programmability on a single-stage BOOST topology. The technical solution of this invention will be described in detail below.

[0039] This invention provides an adjustable power supply system for a semiconductor wafer dicing machine, such as... Figure 1 As shown, the system includes at least: a BOOST boost circuit, an FPGA control module, and a voltage regulation circuit.

[0040] The BOOST boost circuit includes a BOOST boost chip, which has a feedback input terminal.

[0041] The FPGA control module includes an FPGA chip, a DAC chip, and an ADC chip. The FPGA chip outputs a process-defined voltage through the DAC chip and samples the output voltage of the BOOST boost circuit in real time through the ADC chip. The sampled value is compared with a preset target value, and the input digital quantity of the DAC chip is corrected in a closed loop based on the comparison result.

[0042] The voltage regulation circuit includes an operational amplifier. The inverting input of the operational amplifier is connected to both the output of the DAC chip and the output voltage divider of the BOOST boost circuit. The output of the operational amplifier is connected to the feedback input of the BOOST boost chip.

[0043] The operational amplifier sums the process setting voltage with the output voltage divider signal of the BOOST boost circuit in the analog domain, generates an analog sum signal, and sends it to the feedback input terminal of the BOOST boost chip.

[0044] The BOOST boost chip adjusts the output duty cycle based on the comparison result between the analog summation signal and the internal reference voltage, forming a dual-speed closed-loop architecture that combines an analog fast loop and a digital slow loop. The analog fast loop consists of an operational amplifier, the feedback input terminal of the BOOST boost chip, and the error amplifier and PWM comparator inside the BOOST boost chip, with a response time in the microsecond range. The digital slow loop consists of an FPGA chip, an ADC chip, and a DAC chip, with an update cycle in the millisecond range.

[0045] The core operating principle of the aforementioned adjustable power supply system is as follows:

[0046] After the system powers on, the FPGA control module calculates the analog voltage value (i.e., the process-defined voltage POW_ADJ) that the DAC chip should output based on the preset target value (e.g., 48V) and circuit parameters such as the voltage division ratio of the BOOST boost circuit and the summing gain of the operational amplifier. The module then writes the corresponding digital value to the DAC chip via the SPI bus. The DAC chip converts this digital value into the analog voltage POW_ADJ and outputs it to the inverting input of the operational amplifier in the voltage regulation circuit.

[0047] Meanwhile, the output voltage of the BOOST boost circuit is stepped down by a voltage divider network to obtain the output voltage divider signal CV_Part, which is also input to the inverting input of the operational amplifier. The operational amplifier directly sums the process setting voltage POW_ADJ and the output voltage divider signal CV_Part in the analog domain to generate an analog summation signal Pow_Vfb, which is directly sent to the feedback input terminal FB of the BOOST boost chip.

[0048] The BOOST boost chip compares the received analog summation signal Pow_Vfb with its internal reference voltage (typically 1.265V), and adjusts the internal PWM duty cycle according to the comparison result, thereby controlling the switching action of the power MOSFET to achieve boost output.

[0049] In the above process, two closed-loop control loops with different time scales are formed:

[0050] The first loop is an analog fast loop. When a sudden change occurs in the load (such as spindle start / stop or tool trimming arcing), the change in output voltage is directly reflected at the input of the operational amplifier through a voltage divider network. After summation, Pow_Vfb is immediately changed. The error amplifier and PWM comparator inside the BOOST chip respond within microseconds, adjusting the duty cycle to suppress voltage drops or overshoot. This path does not involve ADC sampling, FPGA calculation, or DAC updates, therefore the response time is in the microsecond range.

[0051] The second loop is the digital slow loop. The FPGA chip uses the ADC chip to sample the actual output voltage V_Sense of the BOOST boost circuit in real time at a sampling rate of 500kSPS, comparing the sampled value with a preset target value. If a deviation exists, the FPGA runs a PI algorithm to calculate the correction amount, adjusts the input digital value of the DAC chip, thereby changing the process set voltage POW_ADJ, so that the actual output voltage approaches the preset target value. The update cycle of this path is in the millisecond range, much slower than the response time of the analog fast loop, therefore the digital slow loop will not interfere with the load response of the analog fast loop.

[0052] The two loops share the same feedback input node (FB): the analog fast loop is responsible for suppressing voltage fluctuations caused by sudden load changes, while the digital slow loop is responsible for adjusting the steady-state operating point according to process parameters. Because their time scales differ by three orders of magnitude, they do not interfere with each other and work collaboratively.

[0053] Compared with existing technologies, the above-mentioned adjustable power supply system has the following significant technical advantages:

[0054] First, it balances dynamic response and steady-state accuracy by adopting an architecture of "analog domain summation + dual-loop shared FB node," preserving the microsecond-level response speed of the analog feedback loop. This enables rapid suppression of voltage drops and overshoots under load step conditions (measured load step recovery time <200μs). Simultaneously, the FPGA monitors the output voltage in real time via a 16-bit ADC at a 500kSPS sampling rate, performing closed-loop correction of the DAC output with millisecond-level cycles to achieve high-precision steady-state regulation. This collaborative mechanism of "analog fast and environmentally friendly dynamics, digital slow and environmentally friendly precision" resolves the inherent contradiction in existing technologies where "fast response and process programmability are difficult to achieve simultaneously."

[0055] Secondly, the topology is simple and the cost is low. It adopts a single-stage BOOST topology, which can achieve low ripple output (measured <8mVpp) without the need for complex topologies such as resonant full bridge or two-stage cascade. This significantly reduces circuit complexity and manufacturing cost, while improving system reliability and debugging convenience.

[0056] Third, the control architecture is universal and scalable. By introducing the process-defined voltage of the DAC output at the inverting input of the operational amplifier, non-intrusive intervention on the FB pin of the BOOST boost chip is achieved. The FPGA only needs to change the DAC output to continuously and smoothly adjust the output voltage without changing any hardware parameters. This architecture naturally supports multi-mode switching, soft start, voltage ramping, and other functions, and can flexibly adapt to different process requirements.

[0057] Fourth, industrial-grade reliability and anti-interference capabilities: the presence of the analog fast loop makes the system insensitive to disturbances in digital components such as ADC sampling delay, FPGA calculation jitter, and communication interference, maintaining stable output even in harsh industrial electromagnetic environments. Simultaneously, the operational amplifier summing circuit itself has excellent common-mode rejection ratio, effectively suppressing the impact of common-mode noise on the feedback signal.

[0058] The following section will introduce each circuit module and its optimized circuit in detail.

[0059] I. DAC Circuit

[0060] See Figure 2 As shown, the DAC chip U7 communicates with the FPGA chip via the SPI bus. Figure 2 (Not shown) Connections. The SPI bus includes a data line POW_DATA, a clock line POW_CLK, and a chip select line POW_CS. Current-limiting resistors R41, R42, and R43 are connected in series on the three signal lines to suppress signal overshoot and electromagnetic radiation.

[0061] The analog voltage output of DAC chip U7 is connected to a voltage divider network composed of resistors R25, R26, and R27, which also limits the output current. One end of R25 is connected to the DAC output, and the other end is connected to the non-inverting input of operational amplifier U8. It is also connected to analog ground AGND through resistors R26 and R27. A filter capacitor C46 is connected in parallel in the series branch of resistors R26 and R27 to filter out high-frequency interference signals in the output.

[0062] Operational amplifier U8 is configured as a voltage follower. Its non-inverting input receives the signal from the voltage divider network, and its inverting input is directly connected to its output, forming unity-gain negative feedback. The output voltage POW_ADJ of operational amplifier U8 is sent to the inverting input of the first-stage operational amplifier in the voltage regulation circuit.

[0063] When the system is operating, the FPGA chip calculates the digital quantity that the DAC chip U7 should output based on the preset target voltage value corresponding to the current process mode, and writes this digital quantity to the DAC chip U7 via the SPI bus. The DAC chip U7 then converts this digital quantity into the corresponding analog voltage and outputs it from the analog output terminal.

[0064] The analog voltage first passes through a voltage divider network consisting of R25, R26, and R27. This voltage divider network attenuates the DAC output voltage according to a fixed division ratio, making it compatible with the input voltage range of the subsequent operational amplifier. Furthermore, R25 limits the short-circuit current in case of an accidental short circuit or overcurrent at the DAC output, protecting the DAC chip from damage.

[0065] The voltage signal after voltage division enters the non-inverting input of operational amplifier U8. Since U8 is configured as a voltage follower, its output voltage strictly follows the voltage at the non-inverting input, while providing extremely low output impedance and high input impedance. This buffering effect allows the DAC output signal to stably drive the subsequent load (i.e., the summing operational amplifier in the voltage regulation circuit) without being affected by changes in the impedance of the subsequent load. Finally, the voltage signal after voltage division and buffering is output as the process set voltage POW_ADJ.

[0066] II. BOOST boost circuit

[0067] like Figure 3 With the boost converter chip U6 as its core, its peripheral power circuitry includes inductor L8, power MOSFETs Q1 and Q2, anti-reverse current diode D7, RC peak absorption circuit (R8, C31), RC compensation network (R19, C44), and output capacitor bank (see [link]). Figure 4 ) and the voltage divider sampling network.

[0068] The input power supply +24VP is connected to one end of inductor L8. The other end of inductor L8 is connected to the drains of Q1 and Q2 (the drains of the two transistors are connected in parallel) and the anode of diode D7. The sources of Q1 and Q2 are connected in parallel and then connected to PGND through resistors (R20 and R21 in parallel). The cathode of D7 is connected to the output terminal OUT, and the output terminal OUT is connected to a multi-stage parallel output capacitor bank (see...). Figure 4 Connect to PGND.

[0069] The pin connections of the boost chip U6 are as follows: the BIAS pin (pin 1) is connected to the input power supply +24VP via resistor R29 to provide bias voltage for the chip; the GATE pin (pin 4) outputs the drive signal and is connected to the gates of Q1 and Q2 via gate drive resistors R12 and R14 respectively; the PGND pin (pin 5) and AGND pin (pin 6) are both connected to DGND; the COMP pin (pin 8) is connected to DGND via resistor R19 and capacitor C44 in series to form an RC compensation network; the FB pin (pin 10) receives the analog summation signal Pow_Vfb.

[0070] The RC spike absorption circuit consists of a resistor R8 and a capacitor C31 connected in series and in parallel across the diode D7. It is used to absorb the voltage spikes generated by the inductor L8 when Q1 and Q2 are turned off, protecting the power MOSFET from overvoltage breakdown.

[0071] The voltage divider sampling network is located in Figure 4 middle. Figure 3 The output terminal OUT is filtered by a multi-stage parallel output capacitor bank to obtain a stable DC output voltage CV_Pow. The output terminal OUT also serves as the input to a voltage divider sampling network, with a voltage divider connected in series by resistors R10, R15, and R23: one end of R10 is connected to OUT, the other end to one end of R15, the other end of R15 is connected to one end of R23 and the sampling node V_Sense, and the other end of R23 is connected to DGND. The sampling node V_Sense is located between R15 and R23; the voltage at this node is the voltage divider sample value of the output voltage, which is sent to the ADC chip in the FPGA control module.

[0072] The sampling node V_Sense is also connected to one end of the bidirectional TVS diode D10, and the other end of D10 is connected to DGND to clamp the voltage of the sampling node V_Sense and prevent high voltage spikes caused by instantaneous surges from damaging the ADC acquisition circuit connected later.

[0073] The CV_Pow node is also connected to the anode of indicator D24 via current-limiting resistors R92 and R93 in series. The cathode of D24 is connected to PGND. R92 and R93 are used to limit the current flowing through D24 to prevent the indicator from being damaged by overcurrent.

[0074] The operation of a BOOST boost circuit is divided into an energy storage stage and an energy release stage.

[0075] During the energy storage phase, the gate pin (pin 4) of the boost converter chip U6 outputs a high level, driving Q1 and Q2 to conduct simultaneously. The input power supply +24VP flows through inductor L8 and the conducting Q1 and Q2 to PGND, forming a charging circuit. The current in inductor L8 rises linearly, converting electrical energy into magnetic energy stored in the inductor. At this time, the anode voltage of diode D7 is pulled down to near the PGND potential, while the cathode voltage is the output voltage. Therefore, D7 is reverse biased and cut off, and the output terminal OUT discharges to the load through the output capacitor bank to maintain the voltage. Diode D7 can prevent current backflow and ensure unidirectional energy transfer.

[0076] During the energy release phase, the gate pin (pin 4) of the boost chip U6 outputs a low level, and Q1 and Q2 are simultaneously turned off. Since the current in inductor L8 cannot change abruptly, its induced electromotive force changes direction to negative on the left and positive on the right, forcing diode D7 to be forward biased and turned on. The magnetic energy stored in inductor L8 is converted into electrical energy, which is superimposed on the input power supply voltage +24VP and released to the output terminal OUT and the load via D7, achieving the boost effect. At the same time, the output capacitor bank is simultaneously charged, replenishing the energy released in the previous stage.

[0077] The boost converter chip U6 receives the analog summation signal Pow_Vfb through its FB pin (pin 10) to control the output voltage. The chip's negative feedback logic works as follows: in steady state, the voltage at the FB pin is forced to equal the internal reference voltage of 1.265V. When Pow_Vfb is greater than 1.265V, the boost converter reduces the PWM duty cycle, shortens the on-time of Q1 and Q2, reduces inductor energy storage, and thus lowers the output voltage. When Pow_Vfb is less than 1.265V, the boost converter increases the PWM duty cycle, extends the on-time of Q1 and Q2, increases inductor energy storage, and thus raises the output voltage. Through this negative feedback regulation mechanism, the output voltage is stabilized at the value determined by the comparison between Pow_Vfb and the 1.265V reference.

[0078] The analog summation signal Pow_Vfb is generated by the voltage regulation circuit. This signal is the result of summing the process setting voltage POW_ADJ output by the DAC chip and the voltage divider signal CV_Part output by the BOOST boost circuit in the analog domain. Therefore, the FPGA can indirectly control Pow_Vfb by changing the DAC output, thereby adjusting the output voltage of the BOOST boost circuit.

[0079] The voltage divider sampling network (R10, R15, and R23) proportionally reduces the OUT voltage, obtaining the voltage divider sampling voltage at the sampling node V_Sense. This voltage is sampled by the ADC chip and input to the FPGA. The FPGA calculates the actual value of the current output voltage and compares it with the preset target value. By adjusting the output voltage of the DAC chip (i.e., the process setting voltage POW_ADJ), Pow_Vfb is indirectly changed, realizing the closed-loop correction of the output voltage by the digital slow loop.

[0080] Compared to conventional designs, the above-mentioned designs have the following technical advantages:

[0081] First, it has strong power expansion capability. Q1 and Q2 adopt a source-source and drain-drain parallel connection method, which can effectively increase the output current capability, reduce the on-resistance, and reduce the conduction loss, making it suitable for high-power load scenarios such as dicing machine spindle servo.

[0082] Secondly, it offers high voltage regulation accuracy and flexible voltage adjustment. The boost chip U6 receives the analog summation signal Pow_Vfb through the FB pin. This signal integrates the process setting voltage of the DAC output and the output voltage divider signal, allowing the FPGA to precisely adjust the output voltage through a digital slow loop while retaining the fast response capability of the chip's internal analog fast loop.

[0083] Third, the loop stability is strong. The external RC compensation network (R19 and C44) connected to the COMP pin effectively improves the phase margin of the control loop, avoids loop oscillation, and ensures low ripple characteristics and fast load step recovery capability of the output voltage.

[0084] Fourth, comprehensive protection features. An RC spike absorption circuit protects the power MOSFET from overvoltage breakdown; a bidirectional TVS diode clamps the sampling node voltage, protecting the ADC acquisition circuit; a current-limiting resistor protects the indicator light; and a multi-stage output capacitor bank reduces the equivalent series resistance, enhancing energy storage and filtering capabilities.

[0085] Because the current is very large when the MOSFET is switching, it generates a lot of heat. A temperature sensor is installed on the power switch of the BOOST boost circuit. The output of the temperature sensor is connected to the FPGA control module. The FPGA control module reads the temperature value in 1ms cycles. When the temperature exceeds 85℃, the PWM duty cycle is reduced in 5% steps. When the temperature exceeds 95℃, the output is turned off.

[0086] III. Voltage Regulation Circuit

[0087] like Figure 5 As shown, the overall architecture mainly consists of two cascaded operational amplifiers (U9A and U9B), a multi-channel resistor network, and peripheral components such as capacitors and TVS diodes.

[0088] Specifically, the input signal CV_Pow is first connected to a voltage divider network composed of resistors R31, R32, and R36. The output terminal between R32 and R36 is defined as the CV_Part node, which is input to the inverting input terminal of the first-stage operational amplifier U9A. At the same time, the DAC output signal POW_ADJ from the digital slow loop is also connected to the inverting input terminal of the first-stage operational amplifier U9A through resistor R29. The non-inverting input terminal (pin 3) of U9A is connected to DGND through resistor R38. The feedback loop is formed by resistor R28 connecting the output terminal (pin 1) and the inverting input terminal (pin 2). U9A is powered by a dual ±5VD power supply (pin 8 connected to +5VD, pin 4 connected to -5VD).

[0089] The output of U9A, after passing through resistor R34, is fed into the inverting input (pin 6) of the second-stage operational amplifier U9B. The non-inverting input (pin 5) of U9B is grounded through resistors R37 and R39. The feedback loop is formed by resistor R30 connecting the output (pin 7) and the inverting input (pin 6). Finally, the output of U9B outputs the Pow_Vfb signal through the current-limiting resistor R35. This signal passes through the parallel filter capacitor C48 and the bidirectional TVS protection transistor D11, and is finally connected to DGND. In addition, filter capacitors C50 and C51 are connected in parallel to DGND at the ±5VD power supply terminals to ensure the stability of the op-amp's power supply.

[0090] The aforementioned voltage regulation circuit undertakes the crucial task of analog domain signal fusion and buffer amplification, serving as the core bridge in the entire dual-loop architecture of "digital slow loop → analog slow loop → analog fast loop". In actual operation, CV_Pow represents the current actual output voltage of the BOOST boost circuit (feedback source of the analog fast loop), while POW_ADJ represents the target voltage set by the FPGA according to system requirements (instruction of the digital slow loop). These two signals are summed at the inverting input of U9A. By setting appropriate resistor ratios (R29, R31, R32, R33, R28), the difference between the actual voltage and the target voltage can be proportionally amplified or inverted and superimposed. Subsequently, the signal enters U9B for further buffering or gain adjustment (determined by R30, R37, R39), ultimately outputting Pow_Vfb.

[0091] The Pow_Vfb signal is fed into the FB pin (pin 10) of the boost chip U6. The BOOST chip internally uses an "analog fast loop," which uses 1.265V as a reference and rapidly adjusts the PWM duty cycle (controlling the on-time of Q1 / Q2) by comparing Pow_Vfb with this reference, achieving a microsecond / millisecond-level dynamic voltage response. This circuit, acting as an "analog slow loop," smoothly merges the process setting voltage POW_ADJ output from the digital slow loop (FPGA) with the actual feedback CV_Pow in the analog domain to generate the final feedback signal Pow_Vfb. The three work together: the digital slow loop (FPGA) sets the target, the analog slow loop (this circuit) performs fusion and fine-tuning, and the analog fast loop (BOOST chip) executes quickly. This method does not modify the internal reference or parameters of the BOOST chip; it only intervenes through the feedback path, achieving non-intrusive closed-loop control.

[0092] Compared with conventional simple resistor voltage divider feedback, the voltage regulation circuit described above exhibits higher system performance and robustness.

[0093] First, it features non-invasive intervention and strong compatibility. Conventional resistor voltage dividers directly modify the sampling voltage of the FB pin, while this circuit uses operational amplifiers to sum and amplify, integrating digital instructions and analog feedback in the analog domain before sending them to the FB pin. This does not intrude into the BOOST chip and can be adapted to different models of BOOST chips, as long as the FB pin is a voltage feedback type.

[0094] Secondly, the dual closed-loop architecture perfectly balances accuracy and speed. The digital slow loop provides high-resolution voltage setting to ensure steady-state accuracy; the analog fast loop provides high-speed dynamic response to cope with load changes; and the analog slow loop (this circuit) acts as a bridge to smooth the connection between digital signals and analog feedback, avoiding direct interference of digital noise with the analog fast loop. At the same time, the low-pass filter network composed of R35 and C48 effectively reduces high-frequency ripple, making Pow_Vfb more stable.

[0095] Third, flexible gain and filtering design. The resistor network around the op-amp (such as R28, R30, R37, etc.) can be flexibly set with summation ratio and amplification factor to adapt to different voltage ranges; the dual power supply (±5VD) enhances the linearity of the op-amp, enabling it to process signals stably.

[0096] Fourth, the protection mechanism is comprehensive and highly reliable. D11 (TVS transistor) is used to clamp the extreme value of Pow_Vfb to prevent electrostatic discharge or surge damage to the FB pin of the BOOST chip; resistors such as R31 and R37 provide isolation to prevent overcurrent damage to the op-amp; capacitors C50 and C51 connected in parallel at the ±5VD power supply terminal provide good power supply decoupling and filtering.

[0097] Fifth, excellent industrial-grade adaptability. For industrial scenarios with strong interference and high reliability, such as dicing machines, this circuit effectively isolates digital noise through an "analog slow loop," and multi-stage RC filtering and TVS protection significantly improve immunity. The dual operational amplifier cascade structure has strong common-mode interference immunity, making it very suitable for the stringent requirements of multiple power supplies or complex ground planes (such as PGND and DGND separation).

[0098] IV. FPGA Control Module

[0099] The FPGA control module includes an FPGA chip, a DAC chip, and an ADC chip. The FPGA chip communicates with the DAC chip and the ADC chip via an SPI bus.

[0100] The ADC chip is a 16-bit analog-to-digital converter used to acquire the output voltage of the BOOST boost circuit in real time at a sampling rate of no less than 500kSPS. The theoretical resolution of the 16-bit ADC at full scale of 60V is approximately 0.0009V. Combined with the 500kSPS sampling rate, this means that the FPGA can acquire an accurate value of the output voltage every 2 microseconds, thus enabling the digital slow loop to have millivolt-level voltage detection capability.

[0101] The FPGA chip sends the set voltage value to the DAC chip with an update cycle of 1ms to 10ms. The update cycle of 1ms to 10ms means that the digital slow loop will not interfere with the analog fast loop's rapid response to load changes, and the two form a natural isolation on the time scale.

[0102] In summary, the combination of three parameters—16-bit ADC, 500kSPS sampling rate, and 1ms to 10ms update cycle—constitutes a complete and self-consistent digital slow-loop parameter system. These parameters are reasonably matched to the actual operating conditions of the dicing machine (spindle start-stop time is typically in the tens of milliseconds range, and tool trimming cycle is in the hundreds of microseconds range), clarifying the accuracy, speed, and time isolation relationship between the digital slow loop and the analog fast loop, providing quantifiable and verifiable technical support for the entire dual-speed closed-loop architecture.

[0103] V. Input Reverse Connection Protection Circuit

[0104] like Figure 6As shown, input terminal J1 is connected to +24V_IN and GND_IN. The +24V_IN line is connected in series with a glass tube fuse P1 (φ5.2x20mm), the anodes of two parallel reverse-polarity protection diodes D1 and D2 (model M7), and the normally open contact NO (pin 5) of relays K1 and K2. The relay model is ORWH-SH-124D1F,000, with a drive coil voltage of 24V, matching the input power supply voltage. Its load terminal supports 125VAC / 15A. To increase the load current, two relays are used in parallel. Diode D1 is connected to the coil terminal (pin 1) of relay K1 via current-limiting resistor R1 (1.2K). The normally closed contact NC (pin 4) of K1 is connected to GND_IN. Simultaneously, freewheeling diode D22 is connected in parallel between the coil terminal of K1 and the normally closed contact NC. Diode D2 is connected to the coil terminal (pin 1) of relay K2 via current-limiting resistor R3 (1.2K). The normally closed contact NC (pin 4) of K2 is connected to GND_IN. Simultaneously, freewheeling diode D23 is connected in parallel between the coil terminal of K2 and the normally closed contact NC. Furthermore, the +24V power supply is also connected to the anode of LED D3 via current-limiting resistor R2 (10K). The cathode of D3 is grounded, serving as a power-on status indicator.

[0105] The working principle of the input reverse connection protection circuit is based on the unidirectional conductivity of diodes and the switching characteristics of relays: When the external 24V power supply is connected in the positive direction, the current flows smoothly through the fuse P1, diodes D1 and D2, and reaches the main output node (K1 and K2 coil terminals). At this time, the main output node receives a positive voltage, which energizes the coils of the two parallel relays K1 and K2, generating a magnetic field and closing the contacts, thus allowing the input power supply to be connected to the downstream system without loss. Simultaneously, the +24V power supply illuminates indicator D3 via R2, indicating that the system is powered on normally. If the external power supply polarity is reversed, diodes D1 and D2 are in a reverse cutoff state, blocking the current path, resulting in no voltage at the main output node, de-energizing the coils of relays K1 and K2, opening the contacts, preventing the system from being powered on, and indicator D3 also does not light up, thus effectively cutting off the impact of reverse current on the downstream circuit. At the moment the relays turn off, the magnetic energy stored in the coils forms a discharge circuit through the parallel freewheeling diodes D22 and D23, absorbing the self-induced high voltage and protecting the relay contacts from arc erosion.

[0106] The circuit design boasts several technical advantages: First, extremely low conduction loss. By utilizing the minimal on-resistance after the relay contacts close, it replaces the large on-state voltage drop in the traditional Schottky diode series scheme, significantly reducing heat generation under high current, making it particularly suitable for high-power industrial applications such as dicing machines. Second, high reliability and dual protection. The front-end fuse P1 provides overcurrent protection, while the parallel relay design at the rear not only doubles the load current capacity (supporting 125VAC / 15A and above) but also provides hardware-level redundancy, ensuring the system continues to operate even if a single relay fails. Finally, comprehensive detail protection. An independent indicator light circuit provides intuitive power-on status feedback, while a dedicated freewheeling diode network ensures the safety and lifespan of the relay drive. The overall solution perfectly balances high efficiency and industrial-grade high reliability while preventing reverse connection.

[0107] VI. Power Supply Filtering Circuit

[0108] like Figure 7 As shown, the power supply filter circuit is located between the system power input terminal and the BOOST boost circuit. It consists of an NTC thermistor, a varistor, a bidirectional TVS diode, a common-mode inductor, a Y capacitor, an X capacitor, and a multi-stage parallel output energy storage capacitor, forming a complete five-level protection system: "power-on surge suppression - lightning strike large energy absorption - high-frequency spike clamping - common-mode / differential-mode EMI filtering - output energy storage and ripple suppression".

[0109] The device connections are as follows: The +24V power input enters the main circuit through NTC thermistors RT1, RT2, and RT3 (model NTC10D-15); the varistor VDR1 (model 471KD10) is connected in parallel between the positive and negative power lines, located after the NTC; the bidirectional TVS diode D4 (model SMBJ33CA) is also connected in parallel between the positive and negative power lines, located after VDR1; the common mode inductor L1 (model 1mH@10A) is connected in series in the positive and negative power circuits, with a 100nF X capacitor placed before and after it, bridging the positive and negative power lines. At the same time, the common mode inductor is connected to the PE protection ground through two Y capacitors before and after it. After passing through the common-mode inductor, the power supply enters the output energy storage stage, which consists of two 1000μF electrolytic capacitors C1 and C2 connected in parallel with four 22μF MLCC capacitors and four 10μF MLCC capacitors to form a low ESR energy storage network, which is finally output to the +24VP node of the back-end BOOST module.

[0110] In terms of operating principle, this circuit has a clear division of labor in terms of time and energy levels. At power-on, the NTC thermistors RT1, RT2, and RT3 are in a cold, high-resistance state, limiting the charging surge current to the large-capacity electrolytic capacitors in the subsequent stages. As they heat up, their resistance rapidly decreases, reducing steady-state conduction losses. When a lightning strike or a large power grid surge occurs at the input, the varistor VDR1 experiences a sharp drop in resistance after the voltage exceeds the 47V threshold, absorbing kiloampere-level surge currents. Although its response is in the microsecond range and its clamping accuracy is not high, it is capable of discharging large amounts of energy. Almost simultaneously, the bidirectional TVS diode D4 responds at a picosecond speed, clamping the residual high-frequency spikes below 53.3V, protecting the sensitive devices in the subsequent stages. Because the TVS has limited power dissipation, it does not compete with the varistor for large energy; it only compensates for high-frequency shortcomings. The common-mode inductor L1 presents high impedance to common-mode interference, working in conjunction with the 100nF π-shaped structure before and after. The X capacitor and the Y capacitor connected across PE choke and discharge common-mode noise to ground, while the X capacitor also provides differential-mode filtering. The last stage is provided by a 1000μF electrolytic capacitor for low-speed, high-energy storage. The 22μF and 10μF MLCC capacitors cover the high-frequency ripple near the 100kHz switching frequency with their extremely low ESR. The parallel connection of the two capacitors significantly reduces the equivalent series resistance and improves the load transient response.

[0111] In terms of technical advantages, this circuit achieves a multi-level, synergistic, and mutually reinforcing protection effect. The NTC (Network Transistor) passively addresses power-on surges, avoiding the risk of mechanical relay contact sticking. The varistor and TVS (Transient Voltage Suppressor) form a golden combination of "slow absorption + fast clamping," resisting both high energy and high-frequency spikes, overcoming the limitations of single-component devices. The common-mode inductor plus π-type EMI topology meets the stringent standards of industrial equipment for conducted interference, and the Y-capacitor has a clear discharge path. The parallel connection of the output stage electrolytic capacitor and MLCC (Multi-Layer Cylinder Capacitor) complements each other in terms of capacitance and high-frequency impedance, providing a clean busbar with low ripple and low internal resistance for the BOOST preamplifier. The overall solution is particularly suitable for the complex power grid environment of semiconductor wafer dicing machine workshops, frequent servo spindle start-stop surges, and strong high-frequency interference from EDM (Electrical Discharge Machining) tools, achieving comprehensive protection for industrial-grade power inputs while maintaining cost control.

[0112] Example 2

[0113] Based on Example 1, "Dual-speed closed-loop architecture combining analog fast loop and digital slow loop", this example further proposes a multi-mode output voltage curve switching scheme to meet the actual process requirements of semiconductor wafer dicing machines.

[0114] As mentioned earlier, a dicing machine needs to complete three processes in a complete cycle: spindle start-up, feed motion, and EDM trimming. These three processes have very different requirements for bus voltage: the spindle servo drive requires a constant voltage output of 48V, the feed drive requires a constant voltage output of 24V, and the EDM trimming requires a reference voltage of 60V with the ability to adaptively adjust the gap.

[0115] In existing technologies, each load is typically equipped with a separate power supply module, which not only increases system cost and space occupation but also brings challenges to the coordinated control of multiple power supplies. After in-depth research, it was found that by leveraging the millisecond-level update capability of the digital slow loop in the aforementioned dual-closed-loop architecture, multiple output voltage setting curves can be pre-stored within a single power supply via an FPGA and switched in real time according to external mode commands, thereby simultaneously meeting the power supply requirements of three types of loads with a single BOOST output.

[0116] The BOOST boost circuit in Example 1 is a single-channel BOOST boost output. Its output bus is led through the internal power distribution bus of the dicing machine to the DC side of the spindle servo driver, the DC side of the feed servo driver, and the DC input side of the EDM trimming pulse module. The typical process cycle of the dicing machine is: spindle start → feed movement → trimming and cleaning after reaching the destination → feed continuation → cycle. The three loads occupy this bus in a time-sharing manner according to the process cycle, so time-sharing power supply from a single bus is feasible in terms of both power and time. The following is a detailed description of this scheme with reference to specific embodiments.

[0117] The FPGA control module has three pre-stored output voltage setting curves, corresponding to the dicing machine spindle servo mode, feed drive mode, and EDM dressing mode, respectively. Each curve is stored in the Block RAM inside the FPGA chip with 256 discrete points. The horizontal axis represents the normalized process progress (0% to 100%), and the vertical axis represents the target output voltage value.

[0118] The FPGA chip has a mode selection input, which is a 2-bit GPIO interface (Mode[1:0]), connected to the dicing machine PLC via hard-wired level or RS485 Modbus register. The mode encoding is defined as follows: 00 corresponds to spindle servo mode, 01 corresponds to feed drive mode, 10 corresponds to EDM tool dressing mode, and 11 corresponds to standby or idle mode.

[0119] The FPGA chip communicates with the DAC and ADC chips via the SPI bus. The output of the DAC chip is connected to the inverting input of the first-stage operational amplifier in the voltage regulation circuit, used to output the process setting voltage POW_ADJ. The input of the ADC chip is connected to the output voltage divider node V_Sense of the BOOST boost circuit, used to sample the actual output voltage in real time.

[0120] After the system powers on, the FPGA chip first receives external mode commands through the mode selection input. When the dicing machine PLC sends a spindle servo mode command, the FPGA chip retrieves the output voltage setting curve of the spindle servo mode from its internal Block RAM, looks up the target voltage value (e.g., 48V) according to the current process progress, converts this target value into a DAC digital value, and writes it to the DAC chip via the SPI bus. The DAC chip then outputs the corresponding process setting voltage POW_ADJ. This voltage is summed with the output voltage divider signal by the voltage regulation circuit and sent to the FB pin of the BOOST boost chip to stabilize the output voltage at 48V. It also includes a 200ms soft-start ramp to match the slow acceleration requirement of the air-static electric spindle and avoid bearing damage caused by rapid acceleration.

[0121] When the dicing machine PLC sends a feed drive mode command, the FPGA chip switches to the output voltage setting curve of the feed drive mode, looks up the target voltage value (e.g., 24V) in the table, and smoothly transitions the DAC output from the current value to the new target value with a slope not exceeding 1V / ms. This process ensures that the bus voltage does not experience a step jump, avoiding impact on the feed servo driver. The feed drive mode is equipped with a 50ms soft-start ramp to match the fast response requirements of the worktable while avoiding current surges.

[0122] When the dicing machine PLC sends an EDM trimming mode command, the FPGA chip switches to the output voltage setting curve for EDM trimming mode, looks up the reference voltage value (e.g., 60V) from the table, and smoothly transitions the DAC output from the current value to the new target value with a slope not exceeding 1V / ms. In trimming mode, the FPGA chip performs adaptive gap fine-tuning in 0.1V steps within ±2.5V of the 60V reference voltage curve based on the gap voltage sampled in real time by the ADC chip. This is part of the closed-loop correction of the digital slow loop, ensuring stable micro-discharge energy and improving the trimming and cleaning effect.

[0123] During the three mode switching processes, the bus voltage remained continuous without any drop or overshoot exceeding 0.5V. The entire switching process took less than 50ms, meeting the cycle time requirements of the dicing machine.

[0124] Compared to conventional single-voltage output solutions, this three-curve switching implementation has the following significant technical advantages:

[0125] First, it offers flexible adaptation to multiple scenarios. By using three pre-stored output voltage setting curves within the FPGA, a single power supply can simultaneously serve the three main loads of the dicing machine (spindle servo, feed drive, and EDM tool dressing), eliminating the need for a separate power supply module for each load and significantly reducing system cost and space requirements.

[0126] Second, the transition is smooth and shock-free. During the switching process, the DAC output smoothly transitions from the current value to the new target value at a slope of no more than 1V / ms, ensuring that the bus voltage does not experience a step jump, avoiding impact on the spindle, feed, and trimmer loads, and ensuring the cutting accuracy and process stability of the dicing machine.

[0127] Third, adaptive gap fine-tuning. In EDM trimming mode, the FPGA makes fine-tuning steps of 0.1V within ±2.5V of the 60V reference voltage curve based on the gap voltage sampled by the ADC, achieving precise control of micro-discharge energy, improving trimming and cleaning effects, and extending blade life.

[0128] Fourth, the process parameters are programmable. Each set of curves is stored in Block RAM with 256 discrete points. The horizontal axis represents the normalized process progress, and the vertical axis represents the target output voltage value. This allows the process parameters to be flexibly adjusted via software to adapt to the different needs of different materials and operating conditions.

[0129] As can be seen from the above implementation, its implementation relies solely on the lookup operation of the FPGA's internal Block RAM and the smooth transition control of the DAC output, both of which are mature technologies in the field of digital control. However, the reason why this solution has not been adopted in the power supply of a dicing machine, after analysis, is due to the following two points:

[0130] First, existing technologies have failed to recognize the scenario where the three loads of the dicing machine—spindle servo, feed drive, and EDM tool dressing—are powered from the same source and need to be switched in time according to the process cycle.

[0131] Existing digital power supply solutions, whether designed for single-task EDM (such as CN111431432A and CN121939818A) or for instrument bias power supply (such as CN120848670A and CN122159676A), are not specifically designed for the dicing cutter. The dicing cutter's operating cycle dictates that its power supply system needs to sequentially provide different voltages on the same bus for spindle start (48V), feed motion (24V), and EDM trimming (60V), and the switching process must be smooth and shock-free. This complex operating condition is not recognized or resolved in existing technologies; therefore, a three-curve switching scheme is naturally out of the question.

[0132] Secondly, the effective implementation of the three curve switching schemes relies heavily on the "analog fast loop + digital slow loop" dual closed-loop architecture of this invention.

[0133] In conventional pure digital loop schemes (such as CN209375463U), voltage switching relies entirely on the serial path of ADC sampling → FPGA calculation → PWM update. This switching process involves sampling-calculation-update delays of hundreds of microseconds to milliseconds, easily leading to bus voltage drops or overshoots, failing to meet the stringent voltage stability requirements of dicing machines. Conventional pure analog loop schemes lack the capability for digital curve switching altogether. Only with a dual closed-loop architecture of "analog fast loop + digital slow loop," where the digital slow loop handles millisecond-level process parameter adjustments and the analog fast loop handles microsecond-level load fluctuation suppression, can the three curve switching schemes be successfully implemented while ensuring voltage stability. In other words, the dual closed-loop architecture of Example 1 is the physical basis and prerequisite for the three curve switching schemes; without this architecture, simple curve switching would lose its practical meaning.

[0134] Therefore, the three curve switching schemes in this embodiment are not a simple combination or deterioration of the existing technology, but a systematic and innovative design based on a deep understanding of the specific working conditions of the dicing machine and relying on the dual closed-loop architecture of Embodiment 1.

[0135] The above description is merely a specific embodiment of the present invention or an explanation of that embodiment. The scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An adjustable power supply system for a semiconductor wafer dicing machine, characterized in that, include: The BOOST boost circuit includes a BOOST boost chip, which has a feedback input terminal; The FPGA control module includes an FPGA chip, a DAC chip, and an ADC chip. The FPGA chip outputs a process-defined voltage through the DAC chip and samples the output voltage of the BOOST boost circuit in real time through the ADC chip. The sampled value is compared with a preset target value, and the input digital quantity of the DAC chip is corrected in a closed loop based on the comparison result. The voltage regulation circuit includes an operational amplifier. The inverting input of the operational amplifier is connected to both the output of the DAC chip and the output voltage divider of the BOOST boost circuit. The output of the operational amplifier is connected to the feedback input of the BOOST boost chip. The operational amplifier sums the process setting voltage with the output voltage divider signal of the BOOST boost circuit in the analog domain, generates an analog sum signal, and sends it to the feedback input terminal of the BOOST boost chip. The BOOST boost chip adjusts the output duty cycle based on the comparison result between the analog summation signal and the internal reference voltage, forming a dual-speed closed-loop architecture that combines an analog fast loop and a digital slow loop. The analog fast loop consists of an operational amplifier, the feedback input terminal of the BOOST boost chip, and the error amplifier and PWM comparator inside the BOOST boost chip, with a response time in the microsecond range. The digital slow loop consists of an FPGA chip, an ADC chip, and a DAC chip, with an update cycle in the millisecond range.

2. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 1, characterized in that, It also includes an input reverse connection protection circuit, including: The first and second relays are connected in parallel. The reverse connection protection diodes are connected in series with the first and second relays respectively. They are used to turn on and close the first and second relays when the power supply is connected in the correct direction, and to turn off and open the first and second relays when the power supply is connected in the reverse direction. A glass tube fuse is connected in series with the power input terminal; Current-limiting resistors are connected in series in the drive coil circuits of the first and second relays, respectively. A freewheeling diode is connected in parallel across the drive coils of the first and second relays, respectively. The load terminals of the first and second relays are connected in parallel to carry a load current greater than 5A.

3. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 1, characterized in that, A power supply filter circuit is installed before the input of the BOOST boost circuit, including: An NTC thermistor is connected in series in the power input circuit to suppress power-on surge current. A varistor is connected in parallel to the power input circuit to absorb lightning strikes or large energy surges. A bidirectional TVS diode, connected in parallel to the power input circuit, is used to absorb high-frequency spikes, and its response speed is faster than that of a varistor. A common-mode inductor, connected in series in the power input circuit, is used to suppress common-mode noise; Multiple electrolytic capacitors are connected in parallel with MLCC capacitors for output energy storage and ripple suppression.

4. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 1, characterized in that, The voltage regulation circuit also includes: The first-stage operational amplifier receives the output voltage divider signal from the BOOST boost circuit through the first resistor and the process setting voltage from the DAC chip through the second resistor at its inverting input terminal. Its output terminal outputs the sum and inverted signal of the two signals. The second-stage operational amplifier has its input connected to the output of the first-stage operational amplifier. It is used to invert and amplify the summation and inverted signal again before outputting an analog summation signal. A bidirectional TVS protection diode is connected in parallel between the output of the second-stage operational amplifier and ground to clamp the amplitude of the analog summation signal and protect the feedback input of the BOOST boost chip from overvoltage damage.

5. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 1, characterized in that, The FPGA chip in the FPGA control module communicates with the DAC chip and ADC chip via the SPI bus; The ADC chip is a 16-bit analog-to-digital converter used to acquire the output voltage of the BOOST boost circuit in real time at a sampling rate of not less than 500kSPS; The FPGA chip sends the set voltage value to the DAC chip with an update cycle of 1ms to 10ms.

6. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 1, characterized in that, The adjustable power supply system is a single-channel BOOST boost output, and its output bus is led to the DC side of the spindle servo driver, the DC side of the feed servo driver, and the DC input side of the EDM trimmer pulse module through the internal power distribution bus of the dicing machine.

7. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 6, characterized in that, The FPGA control module has at least three sets of output voltage setting curves pre-stored, corresponding to the dicing machine spindle servo mode, feed drive mode and EDM tool dressing mode respectively. The FPGA control module has a mode selection input terminal for receiving external mode commands and selecting one set from at least three sets of output voltage setting curves as the current DAC output target according to the external mode commands, so as to change the process setting voltage of the digital slow loop. During the switching process, the FPGA control module smoothly transitions the DAC output from the current value to the new target value at a slope of no more than 1V / ms.

8. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 7, characterized in that, The output voltage setting curve for spindle servo mode is a 48V constant voltage curve, with a 200ms soft start ramp. The output voltage setting curve of the feed drive mode is a 24V constant voltage curve, with a 50ms soft start ramp. The output voltage setting curve of the EDM trimming mode is a 60V reference voltage curve. In trimming mode, the FPGA control module performs adaptive fine-tuning of the gap in 0.1V steps within ±2.5V of the 60V reference voltage curve based on the gap voltage sampled by the ADC, as part of the closed-loop correction of the digital slow loop.

9. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 1, characterized in that, A temperature sensor is installed on the power switch of the BOOST boost circuit, and the output of the temperature sensor is connected to the FPGA control module. The FPGA control module reads the temperature value in 1ms cycles. When the temperature exceeds 85℃, the PWM duty cycle is reduced in 5% steps. When the temperature exceeds 95℃, the output is turned off.

10. The adjustable power supply system for a semiconductor wafer dicing machine according to claim 1, characterized in that, The input reverse connection protection circuit, BOOST boost circuit, FPGA control module and voltage regulation circuit are each set on an independent PCB board, and the PCB boards are interconnected through inter-board connectors.

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