An optimal control and modulation method for Vienna rectifier parallel system

Abstract

The embodiment of the application provides a kind of optimization control and modulation method suitable for Vienna rectifier parallel system, it is related to optimization control and modulation technical field, this method includes: sampling the direct current output voltage, alternating current input voltage and current of each rectifier, and it is run to steady state by double closed loop control;DC bus voltage is controlled by host rectifier, and the power output to load by each rectifier is balanced by load feedforward control method;In each control cycle, three-phase grid current is collected, the sum of three-phase current is calculated, and it is recorded as zero sequence circulating current component;The difference between the zero sequence circulating current component and the given value is calculated by proportional regulator to obtain the first zero sequence voltage component;The first zero sequence voltage component is superimposed into three-phase modulation voltage to suppress the zero sequence circulating current between parallel rectifiers.This method eliminates the current distortion in zero-crossing region from the angle of control method, reduces the harmonic content of grid-side current, and improves the input current quality.

Description

Technical Field

[0001] This application relates to the field of optimization control and modulation technology, and in particular to an optimization control and modulation method applicable to Vienna rectifier parallel systems. Background Technology

[0002] As power conversion technology advances towards higher efficiency and higher power density, three-level Vienna rectifiers have become the mainstream topology in medium- and high-voltage high-power AC / DC conversion due to their advantages such as simple topology, low device stress, and low input current harmonics. In applications requiring system expansion or redundant operation, multiple Vienna rectifiers are often connected in parallel along a common AC bus and a common DC bus. However, parallel systems face multiple technical challenges, including power balancing, zero-sequence circulating current suppression, neutral point voltage balance, and grid-side current quality control. Failure in any of these aspects can lead to reduced system efficiency, device overload, or even failure.

[0003] Chinese invention patent application publication number CN119210179A, published on December 27, 2024, provides a control method for parallel power equalization distribution of a modular three-level grid-connected rectifier. This method sets the master and slave units through DIP switches, adopts a control architecture that uses the master voltage outer loop to cooperate with the slave to cut off the voltage outer loop, and combines a load output power feedforward strategy to achieve balanced distribution of output power of each module under common AC and DC bus conditions.

[0004] While this method mentions suppressing zero-sequence circulating current introduced by the difference in modulation voltage between multiple modules by injecting half of the intermediate phase of the grid voltage, its suppression method is an open-loop feedforward control. The compensation amount is only based on the sorting result of the three-phase grid voltage and does not detect the actual circulating current state of each module in real time. When system parameters drift, line impedance is inconsistent, or load changes dynamically, the open-loop compensation amount cannot adaptively adjust to follow the real-time changes in circulating current, resulting in limitations in both circulating current suppression accuracy and dynamic response capability. Summary of the Invention

[0005] In view of this, this application provides an optimized control and modulation method for Vienna rectifier parallel systems to address the problem that, in existing technologies where multiple rectifiers operate in parallel on a common DC bus, differences in modulation waveforms, DC-side voltages, and line impedances among modules inevitably lead to zero-sequence circulating current paths between modules. These zero-sequence circulating currents, superimposed on the load current, are difficult to separate directly from the phase currents, and conventional current closed-loop control has limited effectiveness in suppressing them. The presence of these circulating currents not only increases power device losses but may also cause current distribution imbalances between modules, affecting the reliability of the parallel system.

[0006] In a first aspect, embodiments of this application provide an optimized control and modulation method suitable for a Vienna rectifier parallel system, including: The DC output voltage, AC input voltage, and current of each rectifier are sampled and operated to a steady state via dual closed-loop control. The DC bus voltage is controlled by the main rectifier, and the power output from each rectifier to the load is balanced by the load feedforward control method. During each control cycle, the three-phase grid current is collected, the sum of the three-phase current is calculated, and it is recorded as the zero-sequence circulating current component. The first zero-sequence voltage component is obtained by subtracting the zero-sequence circulating current component from the given value and then calculating it using a proportional regulator. The first zero-sequence voltage component is superimposed on the three-phase modulation voltage to suppress the zero-sequence circulating current between parallel rectifiers.

[0007] In one possible implementation, the step of subtracting the zero-sequence circulating current component from a given value and calculating the first zero-sequence voltage component via a proportional regulator includes: in, This is the first zero-sequence voltage component; This is a proportionality coefficient, and its value is negatively correlated with the load power of the rectifier. This is the zero-sequence circulating component; For a given value; The proportional regulator performs a calculation once per control cycle to suppress zero-sequence circulating current cycle by cycle.

[0008] In one possible implementation, the scaling factor Take the first value under no-load conditions. Take the second value under rated load conditions. And the first value is greater than the second value; Under residual load conditions, the proportional coefficient The calculation model is shown below: in, Rated load power; This represents the current load power.

[0009] One possible implementation also includes: Calculation of delayed reactive current based on Vienna rectifier topology constraints: in, This is the lagging reactive current; The angular frequency of the grid voltage; The inductance of the input filter inductor on the AC side of the Vienna rectifier; This represents the d-axis component of the grid voltage. The d-axis component of the desired value of the inner current loop; The lagging reactive current is injected into the control loop as the q-axis setpoint of the inner current loop. Delayed reactive current and the d-axis component of the expected value of the inner current loop After inverse Park transform and inverse Clarke transform, the three-phase modulated voltage is obtained.

[0010] One possible implementation also includes: During the fundamental frequency period, the voltages of the upper and lower capacitors on the DC side are collected, and the average value of the upper and lower capacitor voltages during the fundamental frequency period is calculated. The second zero-sequence voltage component is calculated by using the average value of the upper and lower capacitor voltages within the fundamental period and a PI regulator. Based on the amplitude ranking of the three-phase modulation voltage, the second zero-sequence voltage component is dynamically limited; The second zero-sequence voltage component after dynamic limiting is superimposed on the three-phase modulation voltage to suppress the DC offset of the midpoint voltage.

[0011] In one possible implementation, the dynamic limiting of the second zero-sequence voltage component includes: in, for Phase modulation voltage, i.e., the three-phase modulation voltage before the second zero-sequence voltage component is superimposed. for Phase modulation voltage, for Phase modulation voltage, for Phase modulation voltage; This is the second zero-sequence voltage component; This is the voltage across the capacitor on the DC side; This is the voltage of the capacitor on the DC side.

[0012] In one possible implementation, the first zero-sequence voltage component and the second zero-sequence voltage component are generated independently and then superimposed on the three-phase modulation voltage, specifically as follows: The calculation and superposition of the first zero-sequence voltage component are performed in each control cycle; The mean value calculation of the second zero-sequence voltage component is performed once in each fundamental cycle. The PI regulator completes the regulation operation in the next control cycle after calculating the mean deviation in each fundamental cycle, and superimposes the generated second zero-sequence voltage component into the three-phase modulation voltage.

[0013] Secondly, embodiments of this application provide an optimized control and modulation system suitable for a Vienna rectifier parallel system. The system is applicable to the optimized control and modulation method described in the first aspect, including: The data acquisition module is used to sample the DC output voltage, AC input voltage and current of each rectifier, and operate it to a steady state through dual closed-loop control; The power regulation module is used to control the DC bus voltage by the main rectifier and balance the power output from each rectifier to the load through the load feedforward control method. The data processing module includes: The first calculation unit is used to collect the three-phase grid current in each control cycle, calculate the sum of the three-phase current, and record it as the zero-sequence circulating current component. The second calculation unit is used to calculate the first zero-sequence voltage component by subtracting the zero-sequence circulating current component from the given value and then using a proportional regulator. The zero-sequence voltage superposition unit superimposes the first zero-sequence voltage component onto the three-phase modulation voltage to suppress the zero-sequence circulating current between parallel rectifiers.

[0014] Thirdly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is used to implement the method described in the first aspect.

[0015] Fourthly, embodiments of this application provide a power device, including: a processor, and a memory communicatively connected to the processor, wherein the memory stores a computer program; When the processor executes a computer program, it implements the method described in the first aspect.

[0016] In this embodiment, to address the modulation constraints caused by the current direction of the Vienna rectifier, the space vector modulation timing is corrected by directional injection of reactive current, eliminating infeasible vectors in the zero-crossing region and effectively suppressing grid-side current zero-crossing distortion. This method effectively eliminates zero-crossing current distortion at the control level, reduces grid-side current harmonic content, and improves input current quality.

[0017] This application employs zero-sequence voltage suppression with adaptive proportional coefficient to suppress zero-sequence circulating current between parallel rectifiers, while simultaneously suppressing DC offset of the midpoint voltage by adjusting the mean deviation of the midpoint voltage within the fundamental period. The two control loops are independent of each other, achieving coordinated optimal control of zero-sequence circulating current suppression and midpoint potential balance, effectively improving the operational stability of the system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating an optimized control and modulation method for a Vienna rectifier parallel system provided in this application embodiment; Figure 2 This is a control block diagram of the host mode in a rectifier system provided in an embodiment of this application; Figure 3 This is a control block diagram of the slave mode in a rectifier system provided in an embodiment of this application; Figure 4 Main circuit diagram of a single Vienna rectifier provided in an embodiment of this application; Figure 5 The main circuit diagram of multiple Vienna rectifiers connected in parallel is provided for embodiments of this application; Figure 6(a) shows the experimental waveform of the closing process of the traditional dual-PI control method under ideal operating conditions; Figure 6(b) is an experimental waveform diagram of the closing process of the control method proposed in the parallel rectifier system provided in the embodiment of this application under ideal operating conditions; Figure 7(a) shows the experimental waveform of the closing process under sampling error using the traditional dual-PI control method; Figure 7(b) is an experimental waveform diagram of the closing process of the control method proposed in the parallel rectifier system provided in the embodiment of this application under sampling error; Figure 8 Experimental waveform diagram of the load change process under sampling error in the rectifier parallel system provided in the embodiments of this application; Figure 9 This is a schematic diagram of the structure of a power device provided in an embodiment of this application. Detailed Implementation

[0020] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0021] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0022] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms "a," "say," and "this" as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0023] It should be understood that the terms used in this document are merely descriptive of the relationships between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0024] like Figure 1 As shown in the embodiment of this application, an optimized control and modulation method suitable for Vienna rectifier parallel systems is provided, including: S101 steady-state voltage build-up and synchronous modulation, S102 load feedforward power balancing, S103 reactive power injection zero-crossing distortion suppression, S104 high-frequency zero-sequence circulating current suppression, and S105 low-frequency midpoint potential equalization. The implementation process of each step in this embodiment is as follows: The S101 steady-state voltage build-up and synchronous modulation samples the DC output voltage, AC input voltage, and current of each rectifier and uses dual closed-loop control to bring the rectifier to a steady state.

[0025] In this embodiment, each rectifier is set with a rectifier number via a DIP switch. The host computer selects the rectifier with the smallest number from all parallel rectifiers as the master, and the remaining rectifiers as slaves.

[0026] In other embodiments, the rectifier numbering method is not limited to DIP switches, but can also be implemented through software configuration, communication address configuration or other hardware configuration methods. The master selection method is not limited to the smallest number, as long as the control relationship between the master and slave can be determined in the parallel system.

[0027] Set the desired value of the DC output voltage. The expected value of the DC output voltage The maximum value is less than the withstand voltage of the DC side bus capacitor, and the minimum value satisfies the condition that the modulation index is greater than the preset value.

[0028] In this embodiment, the expected value of the DC output voltage is... The desired value of the DC output voltage is issued by the host computer or set according to user requirements. The operating range of the grid-connected rectifier needs to be met, and its minimum value should satisfy the modulation index being greater than a preset value. For example, when the effective value of the AC input phase voltage is 220V, it can be determined based on the peak AC voltage and the modulation method. If the SVPWM linear modulation range or the voltage utilization improvement after zero-sequence voltage injection is considered, the expected value of the DC output voltage is... The value of should satisfy the condition that the modulation index is greater than 1.154.

[0029] Expected value of DC output voltage The maximum value should be less than the withstand voltage of the DC-side bus capacitor. For example, in this embodiment, the withstand voltage of a single DC-side bus capacitor is 550V. If the DC side is composed of n capacitors connected in series or divided by voltage, the total withstand voltage of the DC-side bus capacitor is expressed as 550nV, where n is the number of DC-side bus capacitors.

[0030] In this embodiment, the expected value of the DC output voltage It is specifically configured according to user needs.

[0031] like Figure 2 and Figure 3 As shown, the process of achieving steady state through dual closed-loop control includes the following steps: Voltage outer loop: Collects the actual voltage of the DC bus. Compare it with the expected value of the preset DC bus voltage. The difference is calculated to obtain the voltage error signal, which is then input into the outer voltage loop PI regulator to obtain the expected current value of the DC-side capacitor. The expected current of the DC-side capacitor Used to provide the d-axis current setpoint for the inner current loop when unloaded.

[0032] Generating Modulated Voltages: The inner current loop controller calculates the d-axis and q-axis modulated voltages based on the deviation between the d-axis current setpoint and the actual feedback value, combined with the q-axis current control output. The d-axis and q-axis modulated voltages are then subjected to inverse Park and inverse Clarke transformations to obtain the modulated voltages in the three-phase stationary coordinates (i.e., the three-phase modulated voltages). , and .

[0033] Injecting intermediate grid voltage: The three-phase grid voltages are sorted to obtain the intermediate grid voltage. in, This is the intermediate grid voltage; , , These represent the three-phase grid voltages; This is for calculating the intermediate value.

[0034] Intermediate grid voltage is injected into the three-phase modulated voltage respectively. Half of the voltage allows the output DC voltage of each rectifier to stably track the given voltage set by the user.

[0035] In this embodiment, the steady state refers to the actual voltage of the DC bus. The expected value of the DC bus voltage The voltage error signal between them converges to the preset range, and the effective value of the AC input current fluctuates less than the preset threshold within several consecutive power frequency cycles.

[0036] The S102 load feedforward power balance is achieved by the rectifier operating in master mode controlling the DC bus voltage of the entire parallel system, while the rectifier operating in slave mode cuts off its own voltage outer loop and independently controls its output power only through the load feedforward control method, so as to achieve a balanced distribution of power output from each rectifier to the load.

[0037] In this embodiment, if it is in host mode, after sequentially energizing the bypass relay and the main relay, the DC bus voltage of the entire system is controlled by the rectifier in host mode, and the power output to the load is controlled by the load feedforward control method.

[0038] This embodiment first collects the voltage of the upper and lower capacitors on the DC side. , Add the two together to obtain the actual voltage of the DC bus. Then, the actual voltage of the DC bus... The expected value of the DC bus voltage The voltage error signal is obtained by performing a difference calculation. Finally, the voltage error signal is input to the voltage outer loop PI regulator to obtain the expected value of the DC-side capacitor current. .

[0039] Under ideal control conditions that neglect inherent losses such as converter switching losses and line losses, the active power on the AC side... DC side active power At all times, the system is in equilibrium, satisfying the following power conservation equation: Right now, in, This represents the d-axis component of the grid voltage. The current in the grid is the d-axis. This is the actual voltage of the DC bus; This represents the total current of the DC bus.

[0040] According to Kirchhoff's Current Law (KCL) for DC bus nodes, the total current of the DC bus is the sum of the current of the DC-side capacitors and the total DC-side load current, satisfying the current topology relationship: in, This represents the total current of the DC bus. This represents the expected current of the DC-side capacitor. This is the sampled value of the DC-side load current.

[0041] Combining the aforementioned power conservation equations, the formula for calculating the expected value of the inner current loop in host mode is obtained as follows: in, The d-axis component of the desired value of the inner current loop; This represents the expected value of the DC bus voltage. This represents the expected current of the DC-side capacitor. This is a sampled value of the DC-side load current; This represents the d-axis component of the grid voltage.

[0042] In traditional dual-loop control methods, achieving balanced power distribution typically requires manually adjusting and setting multiple proportional coefficients (such as the voltage outer loop PI parameter, droop control coefficient, and power distribution coefficient). Setting these coefficients often relies on the engineer's experience and repeated adjustments. By adopting the above-described approach, this embodiment can directly derive the d-axis component of the desired current inner loop value based on analytical calculations using a physical model. No additional, manually set ratio coefficients are required.

[0043] In slave mode, after sequentially engaging the bypass relay and the main relay, the voltage outer loop of slave mode is disconnected. Power output to the load is controlled solely through load feedforward control. In this mode, slave mode no longer handles DC bus voltage control; therefore, the expected current of the DC-side capacitor output by the voltage outer loop PI regulator is... When set to zero, only the load current feedforward term participates in the control.

[0044] Combining the aforementioned power conservation equations, and considering the expected value of the current in the DC-side capacitor... Setting it to zero, the formula for calculating the expected value of the inner current loop in slave mode is as follows: in, The d-axis component of the desired value of the inner current loop; This represents the expected value of the DC bus voltage. This is a sampled value of the DC-side load current; This represents the d-axis component of the grid voltage.

[0045] In slave mode, the load feedforward control directly calculates the inner current setpoint based on the load current sampling value, without needing to go through the voltage outer loop hysteresis adjustment. Its output voltage sampling value no longer participates in the calculation of the inner current setpoint, thus essentially eliminating the power flow between modules caused by the output voltage sampling error.

[0046] S103 reactive power injection zero-crossing distortion suppression: Based on the Vienna rectifier topology constraints, the lagging reactive current is calculated, and the AC current zero-crossing distortion is eliminated by injecting this reactive current.

[0047] In the Vienna rectifier topology, the power switching devices are unidirectional conductors (such as IGBTs connected in series with diodes), and their modulation characteristics are constrained by the current direction. When the grid-side current crosses zero, the current direction reverses, and the modulation vector enters the infeasible region, causing a deviation between the actual output voltage and the command voltage. This results in current zero-crossing distortion and increases the harmonic content of the input current.

[0048] In this embodiment, the rectifier input voltage vector is controlled. With current vector The principle of in-phase (i.e., unity power factor) is achieved by injecting an appropriate amount of lagging reactive current into the inner current loop. This causes the current vector to actively deviate from the pure active state in the zero-crossing interval, pulling the modulation vector back from the infeasible region to the feasible modulation range, thereby eliminating the grid-side current zero-crossing distortion from the control method level and improving the input current waveform quality.

[0049] This embodiment uses the steady-state control equation in the dq coordinate system and the d-axis component of the desired value of the inner current loop. Solve for the q-axis component of the desired value of the inner current loop. This refers to the lagging reactive current.

[0050] The voltage equation in the dq coordinate system is: in, The d-axis component of the input voltage of the Vienna rectifier is the projection of the AC side voltage vector of the rectifier onto the d-axis. This is the q-axis component of the input voltage of the Vienna rectifier, i.e., the projection of the AC side voltage vector of the rectifier onto the q-axis. This represents the d-axis component of the grid voltage. This represents the q-axis component of the grid voltage. The angular frequency of the grid voltage; The inductance of the input filter inductor on the AC side of the Vienna rectifier; This represents the d-axis grid current, i.e., the active current component. This represents the q-axis grid current, i.e., the reactive current component.

[0051] In this embodiment, the grid voltage vector is oriented along the d-axis, i.e. , Furthermore, the control objective is unity power factor, requiring the rectifier input voltage vector to be... With current vector Since they are in phase, the following relationship holds: in, The d-axis component of the input voltage of the Vienna rectifier is the projection of the AC side voltage vector of the rectifier onto the d-axis. This is the q-axis component of the input voltage of the Vienna rectifier, i.e., the projection of the AC side voltage vector of the rectifier onto the q-axis. This represents the d-axis grid current, i.e., the active current component. This represents the q-axis grid current, i.e., the reactive current component.

[0052] Substituting the dq-axis voltage equation into the above phase relationship, and combining it with the d-axis component of the inner current loop... The formula for calculating the lagging reactive current can be derived as follows: in, The q-axis component of the desired value of the inner current loop is the lagging reactive current. The angular frequency of the grid voltage; The inductance of the input filter inductor on the AC side of the Vienna rectifier; This represents the d-axis component of the grid voltage. The d-axis component represents the desired value of the inner current loop.

[0053] q-axis component of the desired value in the inner current loop In the calculation formula, this embodiment constructs constraints in the radical expression to make the radical expression within the radical expression... This holds true consistently, thus ensuring that the injected lagging reactive current has a real solution under any load condition, and that the q-axis component of the expected current value is constant. A negative value indicates a lagging reactive current.

[0054] Delayed reactive current d-axis component of the desired value of the inner current loop As the given value of the inner current loop, the given value of the inner current loop is decoupled by the PI regulator to obtain the voltage given value. The voltage given value is then subjected to inverse Park transform and inverse Clarke transform to obtain the three-phase modulated voltage superimposed with reactive power injection, which is then sent to the PWM modulator to generate the switching signal.

[0055] In this embodiment, the mechanism for eliminating zero-crossing distortion of the current is as follows: In the zero-crossing region of the grid-side current, the current amplitude is small. Theoretically, the requirement that the modulation voltage and current be in phase causes the modulation vector to enter the infeasible region of the Vienna rectifier topology (i.e., the required voltage vector cannot be synthesized). By actively injecting lagging reactive current, the phase of the current vector in the zero-crossing region is shifted, which is equivalent to shifting the modulation vector to the feasible modulation region. This allows the PWM modulator to correctly synthesize the required voltage vector, thereby eliminating grid-side zero-crossing distortion at the control method level and improving the quality of the input current waveform.

[0056] By adopting the above solution, this embodiment can solve the inherent zero-crossing distortion problem of Vienna rectifiers from the control method level without increasing any hardware costs.

[0057] The S104 high-frequency zero-sequence circulating current suppression suppresses zero-sequence circulating current between rectifiers by using a zero-sequence voltage with an adaptive proportional coefficient during the control cycle.

[0058] When multiple Vienna rectifiers are connected in parallel with a common AC bus and a common DC bus, a zero-sequence circulating current path is formed between the rectifier modules due to differences in modulation waveforms, inconsistencies in DC-side voltages, and unbalanced line impedances. This zero-sequence circulating current is superimposed on the phase current and is difficult to separate directly from it. Conventional current closed-loop control has limited effectiveness in suppressing it. The presence of this zero-sequence circulating current not only increases power device losses but may also lead to current distribution imbalances between modules, threatening the safe and reliable operation of the parallel system.

[0059] To suppress zero-sequence circulating current, this embodiment performs the following steps in each control cycle: Collect three-phase power grid current The sum of the three-phase currents is calculated in real time and denoted as the zero-sequence circulating current component: in, The sum of the three-phase currents represents the instantaneous value of the zero-sequence circulating current component. In an ideal three-phase symmetrical system, the sum of the three-phase currents is zero; when zero-sequence circulating current exists, the sum of the three-phase currents is not zero.

[0060] The first zero-sequence voltage component is obtained by subtracting the zero-sequence circulating current component from its given value and then calculating it using a proportional controller. in, This is the first zero-sequence voltage component; This is a proportionality coefficient, and its value is negatively correlated with the load power of the rectifier. This is the zero-sequence circulating component; This is a given value that can be set according to user needs.

[0061] This embodiment employs an adaptive proportional coefficient strategy, adjusting the proportional coefficient in real time according to the rectifier's load status. The size is as follows: Under no-load conditions, the circulating current energy is relatively small, but the system is highly sensitive to disturbances, requiring a large proportional gain to ensure a fast response. In this case, the proportional gain... Take the first value In this embodiment, the first value Under rated load conditions (rated power of 5kW in this embodiment), the circulating current energy is relatively large, requiring a smaller proportional coefficient to avoid over-adjustment and oscillation. In this case, the proportional coefficient... Take the second value In this embodiment, the second value .

[0062] Under other load conditions, the proportional coefficient The value is calculated by linearly interpolating the current load power between the no-load value and the rated value, using the following formula: in, Rated load power; The current load power is calculated from the sampled values ​​of the DC side voltage and load current.

[0063] As shown in the above formula, when the load power increases from no-load to rated load, the proportionality coefficient... The proportional coefficient is monotonically decreased from 0.2 to 0.05, achieving adaptive adjustment as the load changes.

[0064] The calculated first zero-sequence voltage component is superimposed on the three-phase modulation voltage to suppress the zero-sequence circulating current between parallel rectifiers, specifically as follows: in, The three-phase modulation voltage before superposition; This is the three-phase modulated voltage after superimposing the first zero-sequence voltage component. The first zero-sequence voltage component manifests as a common-mode component in the three-phase modulated voltage. Its mechanism is as follows: by adjusting the zero-sequence component of the modulation wave of each rectifier, the common-mode component of the AC side voltage of each module is changed, thereby suppressing the generation and propagation of zero-sequence circulating current.

[0065] The S105 low-frequency midpoint potential equalization suppresses the DC offset of the midpoint voltage by controlling the deviation of the mean midpoint voltage within the low-frequency time dimension of the fundamental period, thereby achieving coordinated control of the zero-sequence circulating current and the midpoint voltage.

[0066] The DC side of a three-level Vienna rectifier consists of two sets of capacitors connected in series, with the midpoint serving as the zero-level output terminal. Due to factors such as differences in the parameters of the upper and lower capacitors, load imbalance, and the injection of zero-sequence components in the modulation wave, the midpoint voltage is prone to DC offset, i.e., the voltage between the upper and lower capacitors... and The voltages are not equal. Midpoint voltage deviation can lead to problems such as reduced DC-side voltage utilization, uneven voltage stress on switching devices, and output waveform distortion. In severe cases, it may cause overvoltage damage to power devices.

[0067] In this embodiment, to suppress the DC offset of the midpoint voltage, the following steps are performed in the low-frequency time dimension of the fundamental period: Collect DC side upper and lower capacitor voltages and Calculate the average value of the upper and lower capacitor voltages within one fundamental frequency cycle (20ms for 50Hz power frequency): in, The voltage of the capacitor on the DC side The average value; DC side capacitor voltage The average value; The number of sampling points within one fundamental frequency period. and These are the instantaneous values ​​of the upper and lower capacitor voltages at the kth sampling time, respectively.

[0068] The DC offset of the midpoint voltage is obtained by subtracting the average values ​​of the upper and lower capacitor voltages. in, This represents the DC offset of the midpoint voltage. The voltage of the capacitor on the DC side The average value; DC side capacitor voltage The average value.

[0069] DC offset of the midpoint voltage As the input to the PI regulator, the second zero-sequence voltage component, after being processed by the PI regulator, is used to suppress the DC offset of the midpoint voltage. in, This is the second zero-sequence voltage component; This is the proportional gain of the PI controller, with a value ranging from 0.1 to 1.0. This is the integral coefficient of the PI controller, with a value ranging from 5 to 20. This represents the DC offset of the midpoint voltage. For the Laplace operator.

[0070] In this embodiment, the PI regulator completes a mean deviation calculation once in each fundamental cycle and outputs the adjustment result at the beginning of the next control cycle, so that the generated second zero-sequence voltage component... It acts on the subsequent modulation process.

[0071] To prevent the injection of a second zero-sequence voltage component Excessive voltage can lead to polarity reversal or overmodulation of the modulated wave. This embodiment also addresses the second zero-sequence voltage component. Dynamic amplitude limiting is performed, specifically as follows: against Phase modulation voltage Superimposed second zero-sequence voltage component The following constraints are set for the modulated voltage after modulation: in, for Phase modulation voltage, i.e., the three-phase modulation voltage before the second zero-sequence voltage component is superimposed. for Phase modulation voltage, for Phase modulation voltage, for Phase modulation voltage; This is the second zero-sequence voltage component; This is the voltage across the capacitor on the DC side; This is the voltage of the capacitor on the DC side.

[0072] In this embodiment, dynamic limiting is performed based on the ranking of the amplitudes of the three-phase modulation voltages: when the amplitude of a certain phase modulation voltage is the largest or smallest, the phase is preferentially limited to ensure that all three-phase modulation voltages meet the above conditions. If the calculated second zero-sequence voltage component... If the amplitude exceeds the limit, it will be clamped to the boundary value to prevent modulation distortion.

[0073] The second zero-sequence voltage component, after dynamic limiting, is superimposed onto the three-phase modulation voltage to suppress DC offset of the midpoint voltage, specifically as follows: in, This is the three-phase modulation voltage that is ultimately sent to the PWM modulator; This is the three-phase modulation voltage after superimposing the first zero-sequence voltage component; This is the second zero-sequence voltage component.

[0074] In this embodiment, the zero-sequence component and the first zero-sequence voltage component are generated independently. Second zero sequence voltage component The two are superimposed on the three-phase modulation voltage, realizing the coordination of zero-sequence circulating current suppression and active control of the midpoint voltage.

[0075] The first zero-sequence voltage component and the second zero-sequence voltage component are generated independently and then superimposed on the three-phase modulation voltage, specifically as follows: The first zero-sequence voltage component comes from the zero-sequence circulating current suppression stage. Its task is to respond quickly to changes in circulating current in each control cycle. Therefore, the calculation and superposition are performed in each control cycle, so that the zero-sequence circulating current can be suppressed in real time on a cycle-by-cycle basis.

[0076] The second zero-sequence voltage component comes from the midpoint potential equalization stage. Considering that the DC offset of the midpoint voltage changes slowly and instantaneous ripple interference needs to be filtered out, its mean value is calculated once in each fundamental frequency cycle. The PI regulator outputs the regulation result in the next control cycle after the mean deviation calculation is completed and adds the second zero-sequence voltage component to the modulation voltage.

[0077] The above scheme ensures that the circulating current suppression performed within the control cycle is not affected by the lag of the midpoint equalization adjustment performed within the fundamental cycle. Similarly, the midpoint equalization adjustment is not affected by the instantaneous fluctuations of the circulating current suppression. The two control loops are naturally decoupled in the time dimension and are ultimately superimposed on the three-phase modulation voltage, achieving coordinated optimal control of zero-sequence circulating current suppression and midpoint voltage balance.

[0078] See Figure 4 and Figure 5 The embodiments of this application provide main circuit diagrams for a single Vienna rectifier and multiple Vienna rectifiers connected in parallel. A single Vienna rectifier mainly includes a three-phase power grid, an input filter, an AC main bypass relay, a three-level IGBT, a DC electrolytic capacitor, and a DC main bypass relay. Multiple rectifiers share a common AC input and a common DC output, resulting in a zero-sequence circulating current loop.

[0079] See Figures 6(a), 6(b), 7(a), 7(b) and Figure 8 The experimental waveform diagram of the rectifier parallel system provided in this application embodiment shows that channel 1 is the three-phase grid current in host mode. Two channels are for three-phase grid current in slave mode. The three channels represent the sum of the three-phase currents in slave mode. The 4 channels are for the DC-side upper and lower capacitor voltages in host mode. and As can be seen from Figure 6(a), under ideal operating conditions, when using the traditional dual-PI control method, the closing process of the Vienna rectifier parallel system is slow and the DC side voltage drop is large, reaching up to 30V. As can be seen from Figure 6(b), under ideal operating conditions, when using the proposed method, the closing process of the Vienna rectifier parallel system is fast and the voltage fluctuation is extremely small, much less than 1%. As shown in Figure 7(a), when using the traditional dual-PI control method under the condition of sampling error, the Vienna rectifiers have a slow response speed during the closing process, and the DC side voltage drops by up to 30V. On the other hand, the power distribution is completely unbalanced, with only a single rectifier providing most of the power, which can easily lead to thermal failure of a single rectifier module in the parallel system, or even an avalanche effect. As shown in Figure 7(b), when using the proposed control method under the condition of sampling error, the closing process has a fast response speed, and the DC side voltage and midpoint voltage fluctuations are minimal. In addition, the zero-sequence circulating current between the parallel rectifiers is small, and the power distribution is balanced, which fully meets the operating requirements of the parallel system. Figure 8 The experimental results of the proposed control method under the condition of sampling error change from half load to full load show that the proposed method has a fast dynamic response speed, small DC side voltage fluctuation, small zero-sequence circulating current between modules, and balanced power distribution under dynamic load conditions, and can still meet the high reliability operation requirements of parallel systems well.

[0080] Corresponding to the above embodiments, this application also provides an optimized control and modulation system suitable for Vienna rectifier parallel systems, the system including a data acquisition module, a power regulation module and a data processing module.

[0081] The data acquisition module is used to sample the DC output voltage, AC input voltage and current of each rectifier. The collected electrical quantities are controlled by a double closed loop to make each rectifier run to a steady state.

[0082] The power regulation module is responsible for controlling the DC bus voltage of the entire parallel system by the main rectifier, and at the same time, it balances the power output from each rectifier to the load through the load feedforward control method.

[0083] In master mode, the rectifier collects the voltages of the upper and lower capacitors on the DC side and performs addition to obtain the actual value of the DC bus voltage. The difference between this value and the preset expected value is then used by a PI regulator to obtain the expected value of the DC side capacitor current. Finally, the power conservation equation and Kirchhoff's current law are used to calculate the d-axis setpoint of the current inner loop. In slave mode, the rectifier disconnects its own voltage outer loop and calculates the current inner loop setpoint independently only by the load feedforward control method. This effectively avoids power distribution imbalance caused by output voltage sampling errors and achieves accurate and even distribution of output power among the rectifiers.

[0084] The data processing module includes a first calculation unit, a second calculation unit, and a zero-sequence voltage superposition unit.

[0085] The first calculation unit is used to collect the three-phase grid current in each control cycle, calculate the sum of the three-phase current, record it as the zero-sequence circulating current component, and detect the instantaneous state of the zero-sequence circulating current between parallel rectifiers in real time.

[0086] The second calculation unit is used to calculate the first zero-sequence voltage component by subtracting the zero-sequence circulating current component from a given value and then using a proportional regulator.

[0087] The zero-sequence voltage superposition unit is used to superimpose the calculated first zero-sequence voltage component onto the three-phase modulation voltage. By changing the common-mode component of the modulation wave of each rectifier, the zero-sequence circulating current between parallel rectifiers is suppressed, thereby effectively avoiding the additional losses caused by the circulating current and the imbalance of current distribution between modules.

[0088] Corresponding to the above embodiments, this application also provides a power device, which includes the optimized control and modulation system suitable for Vienna rectifier parallel systems.

[0089] See Figure 9 This is a structural schematic diagram of a power device provided in an embodiment of this application. Figure 9 As shown, the power device 30 may include a processor 301, a memory 302, and a communication unit 303. These components communicate via one or more buses. Those skilled in the art will understand that the power device structure shown in the figure does not constitute a limitation on the embodiments of this application. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0090] The communication unit 303 is used to establish a communication channel, thereby enabling the power equipment to communicate with other equipment.

[0091] Processor 301 serves as the control center of the power equipment, connecting various parts of the equipment via interfaces and lines. It executes software programs and / or modules stored in memory 302, and calls data stored in memory to perform various functions and / or process data. The processor may be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, processor 301 may consist only of a central processing unit (CPU). In this embodiment, the CPU may have a single processing core or include multiple processing cores.

[0092] Memory 302 is used to store the execution instructions of processor 301. Memory 302 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0093] When the execution instructions in memory 302 are executed by processor 301, the power device 30 is able to perform some or all of the steps in the above method embodiments.

[0094] Corresponding to the above embodiments, this application also provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, wherein when the program runs, it can control the device where the computer-readable storage medium is located to execute some or all of the steps in the above method embodiments. In specific implementation, the computer-readable storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0095] Corresponding to the above embodiments, this application also provides a computer program product containing executable instructions that, when executed on a computer, cause the computer to perform some or all of the steps in the above method embodiments.

[0096] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0097] Those skilled in the art will recognize that the units and algorithm steps described in the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of electronic hardware and software. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0098] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0099] In the several embodiments provided in this application, any function, if implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0100] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. An optimized control and modulation method for a parallel rectifier system in Vienna, comprising: The DC output voltage, AC input voltage, and current of each rectifier are sampled and operated to a steady state via dual closed-loop control. The DC bus voltage is controlled by the main rectifier, and the power output from each rectifier to the load is balanced through a load feedforward control method; characterized in that it further includes: During each control cycle, the three-phase grid current is collected, the sum of the three-phase current is calculated, and it is recorded as the zero-sequence circulating current component. The first zero-sequence voltage component is obtained by subtracting the zero-sequence circulating current component from the given value and then calculating it using a proportional regulator. The first zero-sequence voltage component is superimposed on the three-phase modulation voltage to suppress the zero-sequence circulating current between parallel rectifiers.

2. The optimized control and modulation method for Vienna rectifier parallel systems according to claim 1, characterized in that, The step of subtracting the zero-sequence circulating current component from a given value and calculating the first zero-sequence voltage component via a proportional regulator includes: in, This is the first zero-sequence voltage component; This is a proportionality coefficient, and its value is negatively correlated with the load power of the rectifier. This is the zero-sequence circulating component; For a given value; The proportional regulator performs a calculation once per control cycle to suppress zero-sequence circulating current cycle by cycle.

3. The optimized control and modulation method for Vienna rectifier parallel systems according to claim 2, characterized in that, The proportionality coefficient Take the first value under no-load conditions. Take the second value under rated load conditions. And the first value is greater than the second value; Under residual load conditions, the proportional coefficient The calculation model is shown below: in, Rated load power; This represents the current load power.

4. The optimized control and modulation method for Vienna rectifier parallel systems according to claim 1, characterized in that, Also includes: Calculation of delayed reactive current based on Vienna rectifier topology constraints: in, This is the lagging reactive current; The angular frequency of the grid voltage; The inductance of the input filter inductor on the AC side of the Vienna rectifier; This represents the d-axis component of the grid voltage. The d-axis component of the desired value of the inner current loop; The lagging reactive current is injected into the control loop as the q-axis setpoint of the inner current loop. Delayed reactive current and the d-axis component of the expected value of the inner current loop After inverse Park transform and inverse Clarke transform, the three-phase modulated voltage is obtained.

5. The optimized control and modulation method for Vienna rectifier parallel systems according to claim 4, characterized in that, Also includes: During the fundamental frequency period, the voltages of the upper and lower capacitors on the DC side are collected, and the average value of the upper and lower capacitor voltages during the fundamental frequency period is calculated. The second zero-sequence voltage component is calculated by using the average value of the upper and lower capacitor voltages within the fundamental period and a PI regulator. Based on the amplitude ranking of the three-phase modulation voltage, the second zero-sequence voltage component is dynamically limited; The second zero-sequence voltage component after dynamic limiting is superimposed on the three-phase modulation voltage to suppress the DC offset of the midpoint voltage.

6. The optimized control and modulation method for Vienna rectifier parallel systems according to claim 5, characterized in that, The dynamic limiting of the second zero-sequence voltage component includes: in, for Phase modulation voltage, i.e., the three-phase modulation voltage before the second zero-sequence voltage component is superimposed. for Phase modulation voltage, for Phase modulation voltage, for Phase modulation voltage; This is the second zero-sequence voltage component; This is the voltage across the capacitor on the DC side; This is the voltage of the capacitor on the DC side.

7. The optimized control and modulation method for Vienna rectifier parallel systems according to claim 5, characterized in that, The first zero-sequence voltage component and the second zero-sequence voltage component are generated independently and then superimposed on the three-phase modulation voltage, specifically as follows: The calculation and superposition of the first zero-sequence voltage component are performed in each control cycle; The mean value calculation of the second zero-sequence voltage component is performed once in each fundamental cycle. After the PI regulator calculates the mean deviation in each fundamental cycle, it completes the regulation operation in the next control cycle and superimposes the generated second zero-sequence voltage component into the three-phase modulation voltage.

8. An optimized control and modulation system for a parallel Vienna rectifier system, the system being applicable to the optimized control and modulation method as described in any one of claims 1-7, comprising: The system includes a data acquisition module for sampling the DC output voltage, AC input voltage, and current of each rectifier, and operating it to a steady state via dual closed-loop control; a power regulation module for controlling the DC bus voltage via the main rectifier and balancing the power output from each rectifier to the load through a load feedforward control method; and a data processing module comprising: The first calculation unit is used to collect the three-phase grid current in each control cycle, calculate the sum of the three-phase current, and record it as the zero-sequence circulating current component. The second calculation unit is used to calculate the first zero-sequence voltage component by subtracting the zero-sequence circulating current component from the given value and then using a proportional regulator. The zero-sequence voltage superposition unit superimposes the first zero-sequence voltage component onto the three-phase modulation voltage to suppress the zero-sequence circulating current between parallel rectifiers.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program is used to implement the method as described in any one of claims 1-7.

10. An electrical device, comprising: A processor, and a memory communicatively connected to the processor, the memory storing a computer program, characterized in that, when the processor executes the computer program, it implements the method as described in any one of claims 1-7.

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