Three-level inverter

Abstract

The application provides a three-level inverter, comprising a fault detection module and at least one bridge arm, each bridge arm in the at least one bridge arm comprising a first switch tube and a fourth switch tube, and a second switch tube and a third switch tube being connected in series between a midpoint of each bridge arm and a neutral point of the inverter. The fault detection module is used for: in the case that the second switch tube is turned on, the first switch tube and the fourth switch tube are both turned off, and the output voltage of the bridge arm is greater than a first voltage threshold and the direction of the bridge arm current is positive, determining that the first switch tube is faulty, and the first voltage threshold is greater than zero voltage and less than a positive bus voltage, so that the fault detection of the switch tube can be realized, the specific faulty switch tube can be located, and the accuracy is high and the detection efficiency is high.

Description

Technical Field

[0001] This application relates to the field of electronic power technology, and in particular to a three-level inverter. Background Technology

[0002] Three-level inverters are based on three fixed-level pulse width modulation (PWM) circuits. In recent years, with the development of power electronics technology in the power industry, three-level inverters have been widely used in power electronics fields, including photovoltaic inverters, wind power converters, high-voltage frequency converters, uninterruptible power systems (UPS), active power filters (APF), static var generators (SVG), and high-frequency power supplies. Generally, a three-level inverter includes at least one bridge arm. By controlling the on / off state of the switching transistors in the bridge arm, the three-level inverter outputs stable voltage and current to downstream circuits (such as loads). However, during the operation of a three-level inverter, short-circuit faults may occur in the switching transistors of the bridge arm. This can lead to uncontrolled current in the bridge arm and excessive turn-off voltage stress on other unfaulty switching transistors. Therefore, it is necessary to check the normality of the switching transistors in the three-level inverter to prevent short-circuit faults that could endanger equipment safety. Fault detection schemes for three-level inverters typically utilize the desaturation characteristics of the switching transistors during a short circuit. However, when a switching transistor is short-circuited, the short-circuit current is many times its rated current. Prolonged high current can easily damage other components. Therefore, how to quickly and promptly identify switching transistor faults and prevent the fault from escalating and threatening equipment safety is one of the urgent technical problems that needs to be solved. Summary of the Invention

[0003] This application provides a three-level inverter that can perform real-time fault detection, enabling timely detection of faults in the switching transistors within the three-level inverter. The fault detection efficiency is high and the reliability is high.

[0004] This application provides a three-level inverter, which includes a fault detection module and at least one bridge arm. Each bridge arm includes a first switch and a fourth switch. A second switch and a third switch are connected in series between the midpoint of each bridge arm and the neutral point of the inverter. Here, the series connection terminal of the first and fourth switches is the midpoint of the bridge arm, i.e., the output terminal of the bridge arm, and the voltage at the output terminal of the bridge arm is the output voltage of the bridge arm. The midpoint of each bridge arm can be connected to the neutral point of the inverter through a second and third switch connected in reverse series; that is, the series connection terminal of the first and fourth switches is connected to the neutral point of the inverter through a second and third switch connected in reverse series. Here, the reverse series connection of the second and third switches can be achieved by the diodes connected in parallel on the second and third switches having opposite directions of current conduction. In other words, the diodes connected in parallel on the second and third switches have opposite current conduction directions. The diodes connected in parallel on the second and third switches can be reverse diodes included in the second and third switches. For example, the diode connected in parallel with the second switch can conduct current flowing from the neutral point of the inverter to the midpoint of the bridge arm, while the diode connected in parallel with the third switch can conduct current flowing from the midpoint of the bridge arm to the neutral point of the inverter. Here, the second and third switches connected in reverse series can be either connected to the neutral point of the inverter or the second switch can be connected to the neutral point of the inverter; there is no restriction. Further, the fault detection module is used to: determine that the first switch is faulty when the output voltage of the bridge arm is greater than a first voltage threshold and the direction of the bridge arm current is positive, provided that the second switch is on and the first and fourth switches are off; the first voltage threshold is greater than zero voltage and less than the positive bus voltage. Here, the direction of the bridge arm current flowing out of the midpoint of the bridge arm can be considered the positive direction, and the direction of the bridge arm current flowing into the midpoint of the bridge arm can be considered the negative direction. In this application, during the operation of the three-level inverter, when no short-circuit fault occurs in the switching transistors of the bridge arm, the output voltage and current direction of the bridge arm can be predetermined. Therefore, when a short-circuit fault occurs in a switching transistor of the bridge arm, it may cause an error in the path of the bridge arm current, leading to a change in the direction of the bridge arm current, and the output voltage of the bridge arm may also be abnormal. When the second switching transistor is on and the first and fourth switching transistors are off, a short-circuit fault can be detected in the first switching transistor based on the output voltage and current direction of the bridge arm. That is, when the output voltage of the bridge arm is greater than a first voltage threshold and the direction of the bridge arm current is positive, a short-circuit fault can be determined in the first switching transistor. It is evident that the fault detection module can detect the output voltage and current direction of the bridge arm in real time, and thus, based on the magnitude of the output voltage and the direction of the current, fault detection of the switching transistor can be achieved under various operating states of the switching transistor. It can also locate the specific short-circuited switching transistor, resulting in high detection efficiency and strong reliability.

[0005] In one possible implementation, the fault detection module is further configured to: determine that the fourth switch is faulty when the output voltage of the bridge arm is less than the second voltage threshold and the direction of the bridge arm current is negative, provided that the third switch is on and both the first and fourth switches are off; the second reference voltage is greater than the negative bus voltage and less than zero voltage. In this application, when the third switch is on and both the first and fourth switches are off, the operating state of the first, second, third, and fourth switches can be determined to be either the first, second, and fourth switches being off and the third switch being on, or the second and third switches being on and the first and fourth switches being off. In both of these operating states, when the fourth switch is off and there is no short-circuit fault, no current flows through it. Therefore, when the fourth switch is short-circuited, the output terminal of the bridge arm is connected to the negative DC bus, causing the output voltage of the bridge arm to be less than the second reference voltage, and the direction of the bridge arm current to be negative, i.e., the bridge arm current flows into the midpoint of the bridge arm (i.e., the output terminal of the bridge arm). As can be seen, the fault detection module can detect faults in the fourth switch tube when the third switch tube is on and the first and fourth switch tubes are off, by using the direction of the bridge arm current and the magnitude of the bridge arm output voltage. This allows it to determine whether the fourth switch tube has a short circuit fault. It can not only detect switch tube faults in three-level inverters, but also locate the specific faulty switch tube, which can improve the reliability of fault detection, and has a fast response speed and low cost.

[0006] In one possible implementation, the fault detection module is further configured to: determine that the second switch is faulty when the third switch is on and both the first and second switches are off, and the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, and the direction of the bridge arm current is positive; the second reference voltage is greater than the negative bus voltage and less than zero voltage. In this application, when the first and second switches are off, the operating state of the first, second, third, and fourth switches can be determined to be either all three switches off and the third switch on, or the first and second switches off and the third and fourth switches on. In both operating states described above, when the second switch experiences a short-circuit fault, it can be determined that the direction of the bridge arm current is positive and the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage. Therefore, the fault detection module can detect the direction of the bridge arm current and the output voltage of the bridge arm in real time during the operation of the three-level inverter. With the first and second switches off and the third switch on, if the direction of the bridge arm current is detected as flowing out of the bridge arm and the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, a short-circuit fault in the second switch is determined. It is evident that fault detection of the switch can be achieved based on the direction of the bridge arm current and the output voltage of the bridge arm, preventing large short-circuit currents from flowing through other switches and effectively avoiding damage to other components.

[0007] In one possible implementation, the fault detection module is further configured to: determine that the third switch is faulty when, with the second switch on and the third and fourth switches off, the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, and the direction of the bridge arm current is negative; the second reference voltage is greater than the negative bus voltage and less than zero voltage. In this application, when the second switch is on and the third and fourth switches are off, it can be determined that the operating state of the first, second, third, and fourth switches can be either the second switch on and all three switches off, or the first and second switches on and the third and fourth switches off. In both operating states described above, when the third switch experiences a short-circuit fault, it can be determined that the direction of the bridge arm current is negative and the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage. Therefore, the fault detection module can detect the direction of the bridge arm current and the output voltage of the bridge arm in real time during the operation of the three-level inverter, and perform fault detection on the third switch based on the direction of the bridge arm current and the output voltage of the bridge arm. It is evident that fault detection of the switch can be achieved based on the direction of the bridge arm current and the output voltage of the bridge arm, offering advantages such as fast detection speed, high reliability, and low cost.

[0008] In one possible implementation, the fault detection module is further configured to: determine that the fourth switch is faulty when the output voltage of the bridge arm is less than the second reference voltage and the direction of the bridge arm current is positive, provided that the second switch is on and the fourth switch is off; the second reference voltage is greater than the negative bus voltage and less than zero voltage. In this application, when the second switch is on and the fourth switch is off, the operating states of the first, second, third, and fourth switches can be: the second switch is on, and all three switches are off; or the first and second switches are on, and the third and fourth switches are off; or the second and third switches are on, and the first and fourth switches are off. In all three operating states, when the fourth switch is not faulty, the bridge arm current will not flow through it. When the fourth switch experiences a short-circuit fault, the bridge arm current flows through it, the output voltage of the bridge arm is less than the second reference voltage, and the direction of the bridge arm current is positive. Therefore, the fault detection module can detect whether the fourth switch is faulty based on the magnitude of the bridge arm's output voltage and the direction of the bridge arm current, with high accuracy and strong reliability.

[0009] In one possible implementation, the fault detection module is further configured to: determine that the first switch is faulty when the output voltage of the bridge arm is greater than the first reference voltage and the direction of the bridge arm current is negative, provided that the third switch is on and the first switch is off. In this application, when the third switch is on and the first switch is off, the operating states of the first, second, third, and fourth switches can be: the third switch is on and all three switches are off; the third and fourth switches are on and the first and second switches are off; or the second and third switches are on and the first and fourth switches are off. In these three operating states, the midpoint of the bridge arm is connected to the positive DC bus, causing the output voltage of the bridge arm to be greater than the first reference voltage and the direction of the bridge arm current to be negative, i.e., the bridge arm current flows out of the midpoint of the bridge arm. As can be seen, the fault detection module can detect faults in the first switching transistor when the third switching transistor is on and the first switching transistor is off by using the direction of the bridge arm current and the output voltage of the bridge arm. This allows it to determine whether the first switching transistor has a short circuit fault. It can not only detect switching transistor faults in the three-level inverter, but also locate the specific faulty switching transistor, which can improve the reliability of fault detection, and has a fast response speed and low cost.

[0010] In one possible implementation, the fault detection module is further configured to: determine that the third switch is faulty when the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, provided that the first and second switches are on; the second reference voltage is greater than the negative bus voltage and less than zero voltage. In this application, when the first and second switches are on, it can be determined that the operating state of the first, second, third, and fourth switches is that the first and second switches are on, and the third and fourth switches are off. Under these operating states, when the third switch experiences a short-circuit fault, the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage. Therefore, the fault detection module can detect the output voltage of the bridge arm in real time during the operation of the three-level inverter and detect whether a short-circuit fault has occurred in the third switch based on the bridge arm's output voltage. It is evident that fault detection of the switches can be achieved using only the output voltage of the bridge arm, resulting in fast diagnosis and low cost.

[0011] In one possible implementation, the fault detection module is further configured to: determine that the fourth switch is faulty when the output voltage of the bridge arm is less than the second reference voltage, provided that the first and second switches are on; the second reference voltage is greater than the negative bus voltage and less than zero voltage. In this application, when the first and second switches are on, it can be determined that the operating state of the first, second, third, and fourth switches can be that the first and second switches are on, and the third and fourth switches are off. Under these operating states, when the fourth switch experiences a short-circuit fault, the midpoint of the bridge arm is connected to the negative DC bus, causing the output voltage of the bridge arm to be less than the second reference voltage. Therefore, during the operation of the three-level inverter, the fault detection module can detect the output voltage of the bridge arm in real time and locate the fault in the fourth switch when the output voltage of the bridge arm is less than the second reference voltage, offering advantages such as good diagnostic effect and fast detection speed.

[0012] In one possible implementation, the fault detection module is further configured to: determine that the first switch is faulty when the output voltage of the bridge arm is greater than the first reference voltage, provided that the third and fourth switches are on. In this application, when the third and fourth switches are on, it can be determined that the operating state of the first, second, third, and fourth switches can be that the first and second switches are off, and the third and fourth switches are on. Under this operating state, when the first switch experiences a short-circuit fault, the midpoint of the bridge arm is connected to the positive DC bus, causing the bridge arm's output voltage to exceed the first reference voltage. Therefore, the fault detection module can detect the bridge arm's output voltage in real time during the operation of the three-level inverter and detect whether the first switch has a short-circuit fault based on the bridge arm's output voltage. It is evident that when the fourth switch is on, only the bridge arm's output voltage is needed to detect the fault in the first switch, resulting in a short diagnosis time and fast detection speed.

[0013] In one possible implementation, the fault detection module is further configured to: determine that the second switch is faulty when the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, provided that the third and fourth switches are on; the second reference voltage is greater than the negative bus voltage and less than zero voltage. In this application, when the third and fourth switches are on, it can be determined that the operating state of the first, second, third, and fourth switches can be that the first and second switches are off, and the third and fourth switches are on. Under these operating states, when a short-circuit fault occurs in the second switch, the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage. Therefore, when the third and fourth switches are on, only the output voltage of the bridge arm is needed to detect the fault in the second switch, resulting in a short diagnosis time and fast detection speed. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the desaturation detection principle provided in this application;

[0015] Figure 2 This is a structural schematic diagram of the three-level inverter provided in this application;

[0016] Figure 3 This is a timing diagram of the three-level inverter provided in this application;

[0017] Figure 4a This is a schematic diagram of the current flow direction of the bridge arm current provided in this application;

[0018] Figure 4b This is another schematic diagram of the current flow direction of the bridge arm current provided in this application;

[0019] Figure 4c This is another schematic diagram of the current flow direction of the bridge arm current provided in this application;

[0020] Figure 4d This is another schematic diagram of the current flow direction of the bridge arm current provided in this application;

[0021] Figure 4e This is another schematic diagram of the current flow direction of the bridge arm current provided in this application;

[0022] Figure 5 This is another structural schematic diagram of the three-level inverter provided in this application;

[0023] Figure 6 This is a timing diagram of the three-level inverter provided in this application;

[0024] Figure 7 This is another structural schematic diagram of the three-level inverter provided in this application;

[0025] Figure 8 This is another structural schematic diagram of the three-level inverter provided in this application;

[0026] Figure 9 This is another structural schematic diagram of the three-level inverter provided in this application;

[0027] Figure 10 This is another structural schematic diagram of the three-level inverter provided in this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] With the rapid development of power electronics technology, three-level inverters are increasingly widely used in uninterruptible power supplies, active filters, and photovoltaic charging systems. During the operation of a three-level inverter, switching transistor failures may occur, such as topology shoot-through due to short circuits in the switching transistors, bus short circuits, and overcurrent damage to the switching transistors. It should be noted that the aforementioned switching transistors can be insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), gate-turn-off thyristors (GTOs), integrated-gate-commutated thyristors (IGCTs), etc.

[0030] Existing fault detection methods for three-level inverter switching transistors mainly involve desaturation detection of the transistor's voltage during a shoot-through short circuit in the bridge arm. For ease of description, the desaturation detection principle will be explained using an IGBT as an example. For IGBT-type switching transistors, it is possible to detect whether the voltage Vce between its collector and emitter has exited the saturation region. See [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram illustrating the desaturation detection principle provided in this application. For example... Figure 1 As shown, the horizontal axis represents the voltage Vce between the collector and emitter of the switching transistor, and the vertical axis represents the collector current Ic. The multiple solid curves represent the switching transistor's characteristic curves for different gate voltages; in other words, each solid line corresponds to a different static drive voltage. The left side of the dashed line represents the saturation region, and the right side represents the linear region. When the switching transistor is operating normally, it should be working in the saturation region, such as... Figure 1 Point P1 is shown. At this point, the Vce of the switching transistor is relatively small, typically 2 to 3V, and the operating current (e.g., rated current) Inormal of the switching transistor is also relatively small. When a shoot-through short circuit occurs in the bridge arm containing this switching transistor, the transistor will bear most of the voltage between the DC buses, causing the Vce of the switching transistor to increase. At this time, the operating point of the switching transistor falls into the linear region. For example, when the static drive voltage of the switching transistor is 12V and no shoot-through short circuit occurs, the switching transistor should operate in the linear region as shown. Figure 1Point P1 is shown. When a shoot-through short circuit occurs in the bridge arm containing the switching transistor, the Vce of the switching transistor increases because it bears most of the voltage between the DC buses, and the short-circuit current Isc flowing through the switching transistor also increases, typically 4 to 7 times the rated current, i.e., Isc = (4~7) * Inormal. For example, the static drive voltage of the switching transistor is 12V. When a shoot-through short circuit occurs in the bridge arm containing the switching transistor, the operating point of the switching transistor changes from point P1 to point P2. At this time, the Vce of the switching transistor is larger than when the switching transistor is operating in the linear region.

[0031] As can be seen, the process of the switching transistor's operating point changing from P1 to P2 is called desaturation. Fault detection of the switching transistor can be achieved through the desaturation detection principle. However, because the short-circuit current of the switching transistor is relatively large, if the short-circuit current persists for a long time, it may damage other normally functioning components. Therefore, to prevent the spread of switching transistor faults and ensure equipment safety, it is necessary to detect switching transistor faults promptly during the operation of the three-level inverter, and then quickly implement protective measures when a fault occurs.

[0032] See Figure 2 , Figure 2 This is a structural schematic diagram of the three-level inverter provided in this application. Figure 2 As shown, the three-level inverter includes a fault detection module and at least one bridge arm (taking phase A as an example). Each bridge arm includes a first switch Q11 and a fourth switch Q14. The midpoint of each bridge arm (the midpoint of phase A can be denoted as O1) is connected in series with the neutral point of the inverter via a second switch Q12 and a third switch Q13. Here, the series connection terminal of Q11 and Q14 is O1, i.e., the midpoint of the bridge arm, and the voltage at O1 is the output voltage of the bridge arm. Figure 2As shown, the three-level inverter may also include a first capacitor C1 and a second capacitor C2 connected in series. C1 is connected to the positive DC bus BUS+, and C2 is connected to the negative DC bus BUS-. C1 and C2 are connected in series between BUS+ and BUS-. Here, one end of C1 is connected to BUS+, the other end of C1 is connected to one end of C2, and the other end of C2 is connected to BUS-. The connection point between the other end of C1 and one end of C2 is the series connection terminal of C1 and C2. The series connection of C1 and C2 can divide the voltage between the DC buses into three levels: the positive bus voltage +Vbus, the negative bus voltage -Vbus, and the voltage at the series connection terminal of C1 and C2. When the capacitance values ​​of C1 and C2 are equal, the voltage at the series connection terminal of C1 and C2 is zero. In one feasible embodiment, when the three-level inverter includes three bridge arms, such as phase A, phase B, and phase C, the midpoints of phase A, phase B, and phase C can be connected together via a second and a third switch in reverse series to form a common terminal, which is called the neutral point N. The series connection terminals of C1 and C2 are also connected to the neutral point N. When the three-level inverter includes only one bridge arm, the series connection terminals of C1 and C2 can be the same as the neutral point N of the three-level inverter. The bridge arm may include Q11, Q12, Q13, and Q14. Q11 and Q14 are connected in series and then in parallel across the two ends of the series-connected C1 and C2. The series connection terminals of Q11 and Q14 are connected to the series connection terminals of C1 and C2 via the reverse-connected Q12 and Q13, that is, the series connection terminals of Q11 and Q14 are connected to the neutral point N via the reverse-connected Q12 and Q13. Here, the reverse series connection of Q12 and Q13 can mean that the diodes connected in parallel on Q12 and Q13 have opposite directions of current conduction. In other words, the diodes connected in parallel on Q12 and Q13 have opposite current conduction directions. These diodes can be reverse-biased diodes included in Q12 and Q13. For example, the diode connected in parallel on Q12 can conduct current flowing from the series connection of C1 and C2 to the series connection of Q11 and Q14, while the diode connected in parallel on Q13 can conduct current flowing from the series connection of Q11 and Q14 to the series connection of C1 and C2. In this reverse series connection of Q12 and Q13, Q13 can be connected to the connection of C1 and C2, or Q12 can be connected to the connection of C1 and C2. This embodiment uses the connection of Q12 to C1 and C2 as an example, which will not be elaborated further below.

[0033] like Figure 2As shown, short circuits may occur in the switching transistors of each bridge arm. For example, if Q11 is short-circuited and Q12 is conducting while the DC bus is receiving normal power, this will cause a short circuit in BUS+, preventing C1 from charging properly and causing Q12 to experience excessive short-circuit current, thus affecting the normal operation of the three-level inverter. Alternatively, if Q11 is short-circuited and Q14 is conducting while the DC bus is receiving normal power, this will cause a shoot-through short circuit in the bridge arm, preventing both C1 and C2 from charging properly and causing Q14 to experience excessive short-circuit current, also affecting the normal operation of the three-level inverter. Therefore, during the operation of the three-level inverter, it is necessary to promptly identify any faults in the switching transistors to prevent short-circuit faults in the switching transistors due to short circuits, which could endanger equipment safety.

[0034] In some feasible implementations, the fault detection module can determine that the first switch is faulty when the output voltage of the bridge arm is greater than a first voltage threshold and the direction of the bridge arm current is positive, provided that the second switch is turned on and the first and fourth switches are turned off. The first voltage threshold is greater than zero voltage and less than the positive bus voltage.

[0035] Here, the fault detection module can be various hardware chips with processing capabilities, including but not limited to central processing units (CPUs), microcontroller units (MCUs), digital signal processing (DSP) chips, field-programmable gate array (FPGA) chips, microcontrollers, and combinations of various control chips, etc. Specific limitations are not specified here. The fault detection module can acquire the bridge arm current and the bridge arm output voltage, and can also obtain the drive signals of each switch in the bridge arm. By analyzing the drive signals of each switch, the operating state of each switch is determined, and fault detection of the switch is achieved based on the bridge arm current and the bridge arm output voltage, or, based on the bridge arm output voltage.

[0036] It should be understood that during the operation of a three-level inverter, short-circuit faults may occur in the switching transistors of the bridge arm. This may cause errors in the current path of the bridge arm, changes in the direction of the current, and excessive turn-off voltage stress on other unfaulted switching transistors in the bridge arm. Therefore, it is necessary to check the normality of the switching transistors in the three-level inverter to prevent short-circuit faults due to the presence of short circuits, which could endanger equipment safety. The switching transistors in the bridge arm can be controlled to switch between on and off states, allowing the three-level inverter to operate in different states. In each state, the switching transistors within the bridge arm are in different operating states. When all switching transistors within the bridge arm are functioning correctly, the voltage of O1 (i.e., the output voltage of the bridge arm) is the same as the desired output voltage. When a short-circuit fault exists in a switching transistor within the bridge arm, the current path of the bridge arm may differ from the normal current path, and the direction of the current may also differ. In this case, the output voltage of the bridge arm will also differ from the desired output voltage. Therefore, the fault detection module can detect the output voltage and current direction of the bridge arm in real time. Based on the magnitude of the output voltage and the direction of the current, fault detection of the switching transistors can be achieved, and the specific short-circuited switching transistor can be located. This method offers high detection efficiency and reliability. It is evident that the fault detection module can perform real-time detection of faulty switching transistors during the operation of a three-level inverter, quickly and promptly identifying short-circuit faults in the switching transistors. This prevents serious faults such as bus short circuits and short-circuit fault propagation caused by prolonged short-circuit currents resulting from switching transistor faults, which could endanger equipment safety and thus improve the reliability of the three-level inverter.

[0037] See Figure 3 , Figure 3 This is a timing diagram of the three-level inverter provided in this application. Figure 3 As shown, the enable signal (EN) can be used to control the output voltage of the bridge arm to be in the positive or negative half-cycle. When EN is high, the output voltage of the bridge arm is in the positive half-cycle; when EN is low, the output voltage of the bridge arm is in the negative half-cycle. PWM1 and PWM2 are two complementary drive signals with dead time. PWM1 and PWM2 can be used to generate four drive signals that change according to certain logic. These four drive signals are used to drive the four switches Q11, Q12, Q13, and Q14 in the bridge arm to operate according to switching logic. Specifically, PWM1 can generate drive signals to control the on and off of Q11 and Q14, i.e., PWM_Q11 and PWM_Q14; PWM2 can generate drive signals to control the on and off of Q12 and Q13, i.e., PWM_Q12 and PWM_Q13.

[0038] like Figure 3As shown, when EN is high, the bridge arm's output voltage is in the positive half-cycle, meaning the output voltage is positive. At this time, Q12 is normally on, Q14 is normally off, and Q11 and Q13 generate complementary waveforms. Here, complementary waveform generation can be considered as Q11 and Q13 conducting complementaryly, and the time when both Q11 and Q13 are off is the dead time. It should be understood that the fault detection module can obtain the operating state of each switch based on its corresponding drive signal, and can also determine whether the bridge arm's output voltage is in the positive or negative half-cycle based on the enable signal. Taking PWM_Q11 as an example, PWM_Q11 includes rising and falling edges. That is, when PWM_Q11 is high, Q11 conducts; when PWM_Q11 is low, Q11 is off. When EN is low, the bridge arm's output voltage is in the negative half-cycle, meaning the output voltage is negative. Q13 is normally on, Q11 is normally off, and Q12 and Q14 generate complementary waveforms. Here, complementary wave generation can be considered as Q12 and Q14 being complementaryly turned on, and the time when both Q12 and Q14 are turned off is the dead time. Specifically, the operating state of the switching transistors can be seen in Table 1 below. Table 1 is a table of the operating states of the switching transistors. In Table 1, "1" indicates that the operating state of the switching transistor is on, and "0" indicates that the operating state of the switching transistor is off.

[0039] Table 1

[0040]

[0041] As shown in Table 1, when the three-level inverter is operating, there are five possible combinations of operating states for Q11, Q12, Q13, and Q14, namely 1100, 0100, 0110, 0010, and 0011. Specifically, when the output voltage of the bridge arm is positive, Q12 is normally on, Q11 and Q13 generate complementary waveforms, and Q14 is off. In this case, when Q11 is off, the combinations of operating states for Q11, Q12, Q13, and Q14 are 0100 and 0110. Here, 0100 represents Q12 being on and Q11, Q13, and Q14 being off, while 0110 represents Q12 and Q13 being on and Q11 and Q14 being off. When Q13 is off, the possible combinations of operating states for Q11, Q12, Q13, and Q14 are 0100 and 1100, where 1100 indicates that Q11 and Q12 are on and Q13 and Q14 are off. When Q11 is on, the possible combination of operating states for Q11, Q12, Q13, and Q14 is 1100. When the output voltage of the bridge arm is negative, Q13 is normally on, Q12 and Q14 generate complementary waveforms, and Q12 is off. In this case, when Q12 is off, the possible combinations of operating states for Q11, Q12, Q13, and Q14 are 0010 and 0011. 0010 indicates that Q13 is on and Q11, Q12, and Q14 are off, while 0011 indicates that Q13 and Q14 are on and Q11 and Q12 are off. When Q14 is off, the combined operating states of Q11, Q12, Q13, and Q14 are 0110 and 0010. When Q14 is on, the combined operating states of Q11, Q12, Q13, and Q14 are 0011.

[0042] In some feasible implementations, the fault detection module can be connected to O1 to sample the arm current in real time and determine the direction of the arm current. Optionally, after sampling the arm current, the fault detection module can determine the direction of the arm current based on a preset current threshold. Here, the fault detection module can sample the current value of the arm current and define the direction of the arm current as positive when the current value is positive and negative when the current value is negative. For ease of description, it can be assumed that a positive direction of the arm current indicates that the arm current flows out of O1, and a negative direction of the arm current indicates that the arm current flows into O1. However, in actual operation, the current value of the arm current is not a stable value, but fluctuates around a certain value. Therefore, when the fault detection module samples an arm current value of 0A, the actual current value of the arm current is fluctuating around 0A. At this time, the direction of the arm current cannot be accurately determined solely from the sign of the current value. To improve the accuracy of the measurement, a preset current threshold can be introduced. For example, the preset current threshold can be ±3A. When the fault detection module collects a bridge arm current value greater than +3A, the direction of the bridge arm current can be determined to be positive; when the bridge arm current value is less than -3A, the direction of the bridge arm current can be determined to be negative. It should be understood that this application does not limit the preset current threshold, which can be determined according to the actual application scenario. Optionally, the three-level inverter may also include a current sampling circuit, which can be external to the fault detection module. In this case, the current sampling circuit can sample the bridge arm current and output the bridge arm current to the fault detection module, or it can sample the bridge arm current and determine the direction of the bridge arm current, and output the direction of the bridge arm current to the fault detection module. Optionally, the three-level inverter may also include two comparators, such as comparator 1 and comparator 2. The positive input terminals of comparator 1 and comparator 2 can receive the bridge arm current output by the current sampling circuit. The negative input terminal of comparator 1 can be configured with a first preset current threshold, and the negative input terminal of comparator 2 can be configured with a second preset current threshold. Comparator 1 compares the current value of the bridge arm current with a first preset current threshold and outputs the comparison result to the fault detection module. Comparator 2 compares the current value of the bridge arm current with a second preset current threshold and outputs the comparison result to the fault detection module. The first preset current threshold is greater than the second preset current threshold. The fault detection module can determine the direction of the bridge arm current using the comparison results output by comparators 1 and 2. Optionally, the fault detection module can also acquire the magnitude of the bridge arm current using a current sensor, such as a Hall current sensor or a power frequency current sensor, depending on the actual application scenario; this application does not impose any limitations on this.

[0043] In some feasible implementations, the fault detection module can be connected to O1 to sample the output voltage of the bridge arm in real time, and then compare the output voltage of the bridge arm with +Vth and -Vth to determine the relationship between the output voltage of the bridge arm and +Vth and -Vth. Optionally, the three-level inverter may also include a voltage sampling circuit, which can be external to the fault detection module and connected to O1 to sample the output voltage of the bridge arm and output the output voltage of the bridge arm to the fault detection module. The voltage sampling circuit can be a hardware circuit composed of multiple interconnected circuit components.

[0044] In other feasible implementations, the +Vbus and -Vbus of the three-level inverter can be high-voltage signals (e.g., hundreds to thousands of volts), in which case the output voltage of the bridge arm is also relatively large. Furthermore, since the fault detection module is a hardware chip (e.g., an FPGA), the voltage of the FPGA during normal operation is only a few volts, and the output voltage of the bridge arm is much higher than that of the FPGA during normal operation. Therefore, when the bus voltage is a high-voltage signal, it is necessary to step down the output voltage of the bridge arm to modulate the high-voltage signal into a low-voltage signal (e.g., a few volts) to meet the requirements of the subsequent circuitry (e.g., the FPGA). For example, if the high-voltage signal is 400V and the low-voltage signal required for normal FPGA operation is 4V, then the step-down ratio K = 0.01 can be determined based on the voltage values ​​of the high-voltage and low-voltage signals.

[0045] In some feasible implementations, +Vth and -Vth can be obtained by voltage division of +Vbus and -Vbus, or by voltage division of other high-voltage signals. Alternatively, they can be dynamically adjusted by the output of the digital-to-analog converter of the control chip or by PWM, etc. This application does not impose any limitations here, and the specific method can be determined according to the actual application scenario. In some feasible implementations, +Vth can be half of +Vbus, i.e., +Vth = Vbus / 2, and -Vth can be half of -Vbus, i.e., -Vth = -Vbus / 2. For example, if +Vbus = 400V and -Vbus = -400V, then +Vth = 200V and -Vth = -200V. Optionally, when the output voltage of the bridge arm is modulated into a low-voltage signal and the step-down ratio is K, +Vth and -Vth should also be multiplied by K. In this case, +Vth = 2V and Vth = -2V.

[0046] The following will combine Figures 4a to 4e Table 2 provides examples of fault detection for each switching transistor. Table 2 is a fault status table for the output voltage and current of the bridge arm.

[0047] Table 2

[0048]

[0049]

[0050] For fault detection methods regarding Q11 when Q11 is off and Q12 is on, please refer to [link / reference needed]. Figure 4a and Figure 4b :

[0051] In one feasible implementation, with Q12 on and both Q11 and Q14 off, specifically with Q12 on and Q14 off, the switching transistors are controlled by Q12 being normally on and Q11 and Q13 generating complementary waveforms. In this case, the combination of operating states of Q11, Q12, Q13, and Q14 can be either 0100 or 0110. Table 1 shows that the corresponding operating state of 0100 or 0110 is Q11 off. As shown in Table 2, when Q11 is off, if the direction of the bridge arm current is positive and the output voltage of the bridge arm is greater than +Vth, a short-circuit fault can be identified in Q11.

[0052] In the specific implementation, see Figure 4a , Figure 4a This is another schematic diagram of the current flow direction of the bridge arm current provided in this application. Among them, in Figures 4a to 4e In this diagram, "1" indicates that the switching transistor is in the ON state, and "0" indicates that the switching transistor is in the OFF state. Further details will not be provided below. With Q11 off and Q11, Q12, Q13, and Q14 operating at states 0100, and assuming the bridge arm current is positive and Q11 is not faulty, the bridge arm current path can be found in [reference needed]. Figure 4aAs shown by the solid line, the bridge arm current flows from the neutral point N through the reverse diodes Q12 and Q13 out of O1, and the bridge arm output voltage is 0V. If a short circuit fault occurs in Q11, the path of the bridge arm current will change. The bridge arm current will change from its original path (from the neutral point N through the reverse diodes Q12 and Q13 out of O1) to flowing from BUS+ through Q11 out of O1. At this time, the bridge arm output voltage will also change from 0V to +Vbus. It should be understood that the direction of the bridge arm current will not change abruptly; that is, the direction of the bridge arm current when the switching transistor is working normally is the same as the direction when the switching transistor has a short circuit fault. However, the direction of the bridge arm current and the bridge arm output voltage may change. For example, when the direction of the bridge arm current is positive and Q11 is not short-circuited, no current flows through Q11. When Q11 is short-circuited, BUS+ is connected to O1 via Q11, causing bridge arm current to flow through Q11 (and the direction of the bridge arm current remains positive), and the output voltage of the bridge arm becomes +Vbus. When the direction of the bridge arm current is negative and Q11 is not short-circuited, the bridge arm current flows from O1 through Q11 to BUS+, and the output voltage of the bridge arm is +Vbus. When Q11 is short-circuited, the path of the bridge arm current remains unchanged, still flowing from O1 through Q11 to BUS+. Bridge arm current flows through Q11 before and after the short circuit, and the output voltage of the bridge arm remains unchanged. Therefore, when the direction of the bridge arm current is negative, it is impossible to determine whether Q11 is short-circuited based on the direction of the bridge arm current and the output voltage of the bridge arm. In summary, when detecting faults in switching transistors, one can determine whether the switching transistor is short-circuited by checking whether there is bridge arm current flowing through it before and after a short circuit, and then by considering the direction of the bridge arm current and the output voltage of the bridge arm.

[0053] Similarly, see Figure 4b , Figure 4b This is another schematic diagram of the current flow direction of the bridge arm current provided in this application. With Q11 off and Q11, Q12, Q13, and Q14 operating in state 0110, and assuming no short-circuit fault occurs in Q11 and the direction of the bridge arm current is positive, the path of the bridge arm current can be seen in [reference needed]. Figure 4b As shown by the solid line, the bridge arm current flows from the neutral point N through the reverse diodes of Q12 and Q13 out of O1. At this time, the output voltage of the bridge arm is 0V. If a short circuit fault occurs in Q11, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from the neutral point N through the reverse diodes of Q12 and Q13 out of O1) to flowing from BUS+ through Q11 out of O1. At this time, the output voltage of the bridge arm will also change from 0V to +Vbus.

[0054] In summary, when Q11, Q12, Q13, and Q14 are operating at states 0100 or 0110, if a short-circuit fault occurs in Q11, the fault detection module can detect that the output voltage of the bridge arm is greater than +Vth and the direction of the bridge arm current is positive. Therefore, during the operation of the three-level inverter, the fault detection module can detect faults in Q11 based on the direction of the bridge arm current and the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is greater than +Vth and the direction of the bridge arm current is positive, the fault detection module can output a fault detection result for Q11 as a short-circuit fault (e.g., output a warning signal to indicate a short-circuit fault in Q11).

[0055] It should be understood that under the control mode of Q12 being normally on (i.e., Q12 is conducting) and Q11 and Q13 generating complementary waveforms, the fault detection module can also detect faults in Q11 when Q11 is off. Specifically, when Q11 is off and the combination of the operating states of Q11, Q12, Q13, and Q14 is 0100 or 0110, if Q11 fails, the fault detection module can detect that the direction of the bridge arm current is positive and the output voltage of the bridge arm is greater than +Vth. Therefore, when the combination of the operating states of Q11, Q12, Q13, and Q14 is 0100 or 0110, the fault detection module can determine whether Q11 has failed based on the direction of the bridge arm current and the output voltage of the bridge arm. The fault detection module can detect faults in the switching transistors when Q11, Q12, Q13, and Q14 are in the operating state of 0100, or during the process of switching the operating state of Q11, Q12, Q13, and Q14 from 0100 to 0110, i.e. before or just when Q13 is turned on. In other words, by using the dead time when both Q11 and Q13 are off to detect faults in the switching transistors, faulty switching transistors can be detected quickly and timely, thereby controlling the bridge arm to stop working, avoiding damage to the devices due to prolonged high current. It has high detection efficiency and high reliability.

[0056] For fault detection methods regarding Q14 when Q14 is off and Q13 is on, please refer to [link / reference needed]. Figure 4c and Figure 4b :

[0057] In one feasible implementation, the fault detection module can determine that Q14 is faulty, i.e., Q14 has a short-circuit fault, when Q13 is on and Q11 and Q14 are all off, and the output voltage of the bridge arm is less than -Vth and the direction of the bridge arm current is negative. Here, when Q13 is on and Q11 and Q14 are all off, it can be considered that the switching transistors are controlled to turn on and off under the condition that Q13 is normally on and Q12 and Q14 are complementary in ripple generation. At this time, it can be determined that the combination of the operating states of Q11, Q12, Q13 and Q14 is 0010 or 0110. In Table 1, the operating state of the switching transistor corresponding to 0010 or 0110 can be determined to be Q14 off. As shown in Table 2, when Q14 is off, and the direction of the bridge arm current is negative and the output voltage of the bridge arm is less than -Vth, it can be determined that Q14 has a short-circuit fault.

[0058] In the specific implementation, see Figure 4c , Figure 4c This is another schematic diagram of the current flow direction of the bridge arm current provided in this application. With Q14 off and Q11, Q12, Q13, and Q14 operating in state 0010, and assuming Q14 is not faulty and the direction of the bridge arm current is negative, the path of the bridge arm current can be seen in [reference needed]. Figure 4c As shown by the dashed line, the bridge arm current flows from O1 through the reverse diodes of Q13 and Q12 to the neutral point N. At this time, the output voltage of the bridge arm is 0V. If Q14 fails, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from O1 through the reverse diodes of Q13 and Q12 to the neutral point N) to flowing from O1 through Q14 to BUS-. At this time, the output voltage of the bridge arm changes from 0V to -Vbus.

[0059] Similarly, with Q14 off and Q11, Q12, Q13, and Q14 operating at state 0110, and assuming Q14 is not faulty and the arm current is negative, the path of the arm current can be found in [reference needed]. Figure 4b As shown by the dashed line, the bridge arm current flows from O1 through the reverse diodes of Q13 and Q12 to the neutral point N. At this time, the output voltage of the bridge arm is 0V. If Q14 fails, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from O1 through the reverse diodes of Q13 and Q12 to the neutral point N) to flowing from O1 through Q14 to BUS-. At this time, the output voltage of the bridge arm will also change from 0V to -Vbus.

[0060] In summary, when Q11, Q12, Q13, and Q14 are operating at state 0010 or 0110 and Q14 does not experience a short-circuit fault, the bridge arm current will not flow through Q14. If a short-circuit fault occurs in Q14, the bridge arm current flows through Q14, and the output voltage of the bridge arm becomes -Vbus. At this time, the fault detection module can detect that the output voltage of the bridge arm is less than -Vth, and the direction of the bridge arm current is negative. Therefore, during the operation of the three-level inverter, the fault detection module can detect faults in Q14 based on the direction of the bridge arm current and the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is less than -Vth, and the direction of the bridge arm current is negative, the fault detection module can output a fault detection result for Q14 as a short-circuit fault (e.g., output a warning signal to indicate a short-circuit fault in Q14).

[0061] As can be seen, under the control mode of Q12 being constantly on (i.e., Q12 is conducting) and Q11 and Q13 generating complementary waveforms, the fault detection module can detect faults in Q14 when Q14 is off. Specifically, when Q14 is off and the combined operating states of Q11, Q12, Q13, and Q14 are 0010 or 0110, if a fault occurs in Q14, the fault detection module can detect that the direction of the bridge arm current is negative and the output voltage of the bridge arm is less than -Vth. Therefore, during the operation of the three-level inverter, the fault detection module can determine whether a short-circuit fault has occurred in Q14 based on the direction of the bridge arm current and the output voltage of the bridge arm. Specifically, the fault detection module can perform fault detection on Q14 when the operating states of Q11, Q12, Q13, and Q14 are 0010, or during the process of switching the operating states of Q11, Q12, Q13, and Q14 from 0100 to 0110, i.e., before or immediately after Q12 is turned on. In other words, by using the dead time when both Q11 and Q13 are off to detect faults in the switching transistors, faulty switching transistors can be detected quickly and promptly, thereby controlling the bridge arm to stop working and avoiding damage to the devices due to prolonged high current. This method has high detection efficiency and high reliability.

[0062] For fault detection methods related to Q12 during Q12 shutdown, please refer to [link / reference needed]. Figure 4c and Figure 4d :

[0063] In some feasible implementations, the fault detection module can determine that Q12 is faulty (i.e., Q12 is short-circuited) when Q13 is on, Q11 and Q12 are both off, the bridge arm output voltage is less than or equal to +Vth and greater than or equal to -Vth, and the bridge arm current is in the positive direction. Here, when Q13 is on and Q11 and Q12 are both off, it can be considered that the switching transistors are controlled to turn on and off when Q13 is normally on and Q12 and Q14 are generating complementary waves. At this time, it can be determined that the combination of the operating states of Q11, Q12, Q13 and Q14 is 0010 or 0011. In Table 1, the operating state of the switching transistor corresponding to 0010 or 0011 is Q12 off. As shown in Table 2, when Q12 is off, when the bridge arm output voltage is less than or equal to +Vth and greater than or equal to -Vth, and the bridge arm current is in the positive direction, it can be determined that Q12 has a short-circuit fault.

[0064] In the specific implementation, see Figure 4c With Q12 off and Q11, Q12, Q13, and Q14 operating at state 0010, and assuming the bridge arm current is in the positive direction and Q12 is not short-circuited, the bridge arm current path can be found in [reference needed]. Figure 4c As shown by the solid line, the bridge arm current flows from BUS- through the reverse diode of Q14 and out of O1, and the output voltage of the bridge arm is -Vbus. If a short circuit fault occurs in Q12, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from BUS- through the reverse diode of Q14 and out of O1) to flowing from the neutral point N through the reverse diodes of Q12 and Q13 and out of O1. The direction of the bridge arm current remains unchanged, and the output voltage of the bridge arm will also change from -Vbus to 0V.

[0065] Similarly, see Figure 4d , Figure 4d This is another schematic diagram of the current flow direction of the bridge arm current provided in this application. With Q12 off and Q11, Q12, Q13, and Q14 operating in state 0011, when the direction of the bridge arm current is positive and Q12 does not experience a short-circuit fault, the path of the bridge arm current can be seen in [reference needed]. Figure 4d As shown by the solid line, the bridge arm current flows from BUS- through the reverse diode of Q14 and out of O1, and the output voltage of the bridge arm is -Vbus. If a short circuit fault occurs in Q12, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from BUS- through the reverse diode of Q14 and out of O1) to flowing from the neutral point N through the reverse diodes of Q12 and Q13 and out of O1. The direction of the bridge arm current remains unchanged, and the output voltage of the bridge arm will also change from -Vbus to 0V.

[0066] In summary, when Q11, Q12, Q13, and Q14 are operating in states 0010 or 0011, if a short-circuit fault occurs in Q12, the fault detection module can detect that the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth, and the direction of the bridge arm current is positive. Therefore, during the operation of the three-level inverter, the fault detection module can detect the fault of Q12 based on the direction of the bridge arm current and the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is between -Vth and +Vth, and the direction of the bridge arm current is positive, the fault detection module can output a fault detection result of Q12 as a short-circuit fault (e.g., output a warning signal to indicate a short-circuit fault in Q12).

[0067] It should be understood that under the control mode of Q13 being normally on (i.e., Q13 is conducting) and Q12 and Q14 generating complementary waveforms, the fault detection module can detect short-circuit faults in Q12 when Q12 is off. Specifically, when Q12 is off and the combination of the operating states of Q11, Q12, Q13, and Q14 is 0010 or 0011, if Q12 fails, the fault detection module can detect that the direction of the bridge arm current is positive, and the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth. Therefore, during the operation of the three-level inverter, the fault detection module can determine whether a short-circuit fault has occurred in Q12 based on the direction of the bridge arm current and the output voltage of the bridge arm when the combination of the operating states of Q11, Q12, Q13, and Q14 is 0010 or 0011. The fault detection module can detect faults in the switching transistors when Q11, Q12, Q13, and Q14 are in the operating state of 0010, or during the process of switching the operating state of Q11, Q12, Q13, and Q14 from 0010 to 0011. In other words, the fault detection module can use the dead time when Q12 and Q14 are both off to detect faults in the switching transistors. It can quickly and timely detect faulty switching transistors before or just when Q14 is turned on, thereby controlling the bridge arm to stop working and avoiding damage to the device due to prolonged high current. It has high detection efficiency and high reliability.

[0068] For fault detection methods regarding Q14 when Q12 is on, please refer to [link / reference]. Figure 4a , Figure 4b and Figure 4e :

[0069] In some feasible implementations, the fault detection module can determine that Q14 is faulty (i.e., Q14 is short-circuited) when Q12 is on and Q14 is off, and the output voltage of the bridge arm is less than -Vth and the direction of the bridge arm current is positive. Here, when Q12 is on and Q14 is off, it can be considered that the switching transistors are controlled to turn on and off when Q12 is normally on and Q11 and Q13 are complementary waveforms. At this time, the combinations of operating states of Q11, Q12, Q13, and Q14 can be determined to be 0100, 0110, and 1100. In Table 1, the operating state of the switching transistors corresponding to 0100, 0110, and 1100 can be determined to be Q12 on. As shown in Table 2, when Q12 is on, and the output voltage of the bridge arm is less than -Vth and the direction of the bridge arm current is positive, a short-circuit fault can be determined for Q14.

[0070] In the specific implementation, see Figure 4a With Q12 on and Q11, Q12, Q13, and Q14 operating at 0100, the path of the bridge arm current when the direction of the bridge arm current is positive and Q14 does not experience a short circuit fault can be found in the following diagram. Figure 4a As shown by the solid line, the bridge arm current flows from the neutral point N through the reverse diodes of Q12 and Q13 out of O1, and the output voltage of the bridge arm is 0V. If a short circuit fault occurs in Q14, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from the neutral point N through the reverse diodes of Q12 and Q13 out of O1) to flowing from BUS- through Q14 to O1. The direction of the bridge arm current remains unchanged, and the output voltage of the bridge arm will also change from 0V to -Vbus.

[0071] Similarly, see Figure 4b With Q12 on and Q11, Q12, Q13, and Q14 operating at state 0110, the path of the bridge arm current when the direction of the bridge arm current is positive and Q14 does not experience a short circuit fault can be found in the following diagram. Figure 4b As shown by the solid line, the bridge arm current flows from the neutral point N through the reverse diodes of Q12 and Q13 out of O1, and the output voltage of the bridge arm is 0V. If a short circuit occurs at Q14, the path of the bridge arm current will change. The current will change from its original path (from the neutral point N through the reverse diodes of Q12 and Q13 out of O1) to flowing from BUS- through Q14 to O1. The direction of the bridge arm current remains unchanged, and the output voltage of the bridge arm will change from 0V to -Vbus.

[0072] Similarly, see Figure 4e , Figure 4e This is another schematic diagram showing the current flow direction of the bridge arm current provided in this application. For example... Figure 4eAs shown, with Q12 on and Q11, Q12, Q13, and Q14 operating at 110°, the path of the bridge arm current is as follows when the direction of the bridge arm current is positive and Q14 does not experience a short circuit fault: Figure 4e As shown by the solid line, the bridge arm current flows from BUS+ through Q11 to O1, and the output voltage of the bridge arm is +Vbus. If a short circuit occurs in Q14, the path of the bridge arm current will change. The current will change from its original path (from BUS+ through Q11 to O1) to flowing from BUS- through Q14 to O1. The direction of the bridge arm current remains unchanged, and the output voltage of the bridge arm will change from +Vbus to -Vbus.

[0073] In summary, when Q12 is on and Q14 is not short-circuited (i.e., when the combined operating states of Q11, Q12, Q13, and Q14 are 0100, 0110, or 1100), no current flows through Q14. If Q14 fails, the fault detection module can detect that the output voltage of the bridge arm is less than -Vth and the direction of the bridge arm current is positive. Therefore, during the operation of the three-level inverter, the fault detection module can detect the fault of Q14 based on the direction of the bridge arm current and the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is less than -Vth and the direction of the bridge arm current is positive, the fault detection module can output a fault detection result for Q14 (e.g., output a warning signal to indicate a Q14 fault).

[0074] It should be understood that under the control mode of Q12 being normally on (i.e., Q12 is on) and Q11 and Q13 generating complementary waveforms, the fault detection module can detect short-circuit faults in Q14 when Q12 is on. Specifically, when Q12 is on and the combined operating states of Q11, Q12, Q13, and Q14 are 0100, 0110, or 1100, Q14 is off, and the bridge arm current will not flow through Q14. If a short-circuit fault occurs in Q14, the bridge arm current will flow through Q14. At this time, the fault detection module can detect that the direction of the bridge arm current is positive, and the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth. Therefore, during the operation of the three-level inverter, the fault detection module can determine whether a short-circuit fault has occurred in Q14 based on the direction of the bridge arm current and the output voltage of the bridge arm when the combined operating states of Q11, Q12, Q13, and Q14 are 0100, 0110, or 1100. The fault detection module can perform fault detection on the switching transistors when Q11, Q12, Q13, and Q14 are in the operating state of 0100, or during the process of switching the operating state of Q11, Q12, Q13, and Q14 from 0100 to 0110, or during the process of switching the operating state of Q11, Q12, Q13, and Q14 from 0100 to 1100. In other words, the fault detection module can use the dead time when Q13 and Q14 are both off to perform fault detection on the switching transistors. It can quickly and timely detect faulty switching transistors before or immediately after the switching transistors are turned on, thereby controlling the bridge arm to stop working and avoiding damage to the devices due to prolonged high current. It has high detection efficiency and high reliability.

[0075] For fault detection methods related to Q13 during Q13 shutdown, please refer to [link / reference]. Figure 4a and Figure 4e :

[0076] In some feasible implementations, the fault detection module can determine that Q12 is faulty (i.e., Q12 is short-circuited) when Q13 is on, Q11 and Q12 are both off, the bridge arm output voltage is less than or equal to +Vth and greater than or equal to -Vth, and the bridge arm current is in the positive direction. Here, when Q13 is on and Q11 and Q12 are both off, it can be considered that the switching transistors are controlled to turn on and off when Q13 is normally on and Q12 and Q14 are generating complementary waves. At this time, it can be determined that the combination of the operating states of Q11, Q12, Q13 and Q14 is 0100 or 1100. In Table 1, the operating state of the switching transistor corresponding to 0100 or 1100 is Q13 off. As shown in Table 2, when Q13 is off, when the bridge arm output voltage is less than or equal to +Vth and greater than or equal to -Vth, and the bridge arm current is in the positive direction, it can be determined that Q13 has a short-circuit fault.

[0077] In the specific implementation, when Q13 is off and the operating states of Q11, Q12, Q13, and Q14 are 0100, and the direction of the bridge arm current is negative and Q13 does not experience a short circuit fault, the path of the bridge arm current can be found in [reference needed]. Figure 4a As shown by the dashed line, the bridge arm current flows from O1 through the reverse diode of Q11 to BUS+, and the output voltage of the bridge arm at this time is +Vbus. If a short circuit fault occurs in Q13, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from O1 through the reverse diode of Q11 to BUS+) to flowing from O1 through the reverse diodes of Q13 and Q12 to the neutral point N. The direction of the bridge arm current remains unchanged, and the output voltage of the bridge arm changes from +Vbus to 0V.

[0078] Similarly, see Figure 4e , Figure 4e This is another schematic diagram of the bridge arm current provided in this application. With Q13 off and Q11, Q12, Q13, and Q14 operating at 1100°C, and the bridge arm current direction being negative and Q13 not faulty, the bridge arm current path can be seen in [reference needed]. Figure 4e As shown by the dashed line, the bridge arm current flows from O1 through the reverse diode of Q11 to BUS+, and the output voltage of the bridge arm at this time is +Vbus. If Q13 fails, the bridge arm current will change from the original current path (i.e., from O1 through the reverse diode of Q11 to BUS+) to flowing from O1 through the reverse diodes of Q13 and Q12 to the neutral point N. The direction of the bridge arm current remains unchanged, but the output voltage of the bridge arm changes from +Vbus to 0V.

[0079] In summary, when Q11, Q12, Q13, and Q14 are operating at 0100 or 1100, if a short-circuit fault occurs in Q13, the fault detection module can detect that the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth, and the direction of the bridge arm current is negative. Therefore, during the operation of the three-level inverter, the fault detection module can detect the fault of Q13 based on the direction of the bridge arm current and the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is between -Vth and +Vth, and the direction of the bridge arm current is positive, the fault detection module can output a fault detection result of short circuit for Q13 (e.g., output a warning signal to indicate a Q13 fault).

[0080] It should be understood that under the control mode of Q12 being normally on (i.e., Q12 is conducting) and Q11 and Q13 generating complementary waveforms, the fault detection module can also detect faults in Q13 when Q13 is off. Specifically, when Q13 is off and the combined operating states of Q11, Q12, Q13, and Q14 are 0100 or 1100, if a short-circuit fault occurs in Q13, the fault detection module can detect that the direction of the bridge arm current is negative, and the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth. Therefore, during the operation of the three-level inverter, the fault detection module can determine whether a fault has occurred in Q13 based on the detected direction of the bridge arm current and the output voltage of the bridge arm when the combined operating states of Q11, Q12, Q13, and Q14 are 0100 or 1100. The fault detection module can detect faults in the switching transistors when Q11, Q12, Q13, and Q14 are in a working state of 0100, or during the process of switching the working state of Q11, Q12, Q13, and Q14 from 0100 to 1100, i.e. before or just after Q11 is turned on. In other words, by using the dead time when both Q11 and Q13 are off to detect faults in the switching transistors, faulty switching transistors can be detected quickly and timely, thereby controlling the bridge arm to stop working, avoiding damage to the devices due to prolonged high current. It has high detection efficiency and high reliability.

[0081] For fault detection methods related to Q11 when Q13 is on, please refer to [link / reference needed]. Figure 4c , Figure 4d and Figure 4b :

[0082] In some feasible implementations, the fault detection module can determine that Q11 is faulty (i.e., Q11 is short-circuited) when Q13 is on and Q11 is off, and the output voltage of the bridge arm is greater than +Vth and the direction of the bridge arm current is negative. Here, when Q13 is on and Q11 is off, it can be considered that the switching transistors are controlled to turn on and off when Q13 is normally on and Q12 and Q14 are complementary waveforms. At this time, the combination of operating states of Q11, Q12, Q13 and Q14 can be determined to be 0010, 0011 and 0110. In Table 1, the operating state of the switching transistors corresponding to 0010, 0011 and 0110 can be determined to be Q13 on. As shown in Table 2, when Q13 is on, and the output voltage of the bridge arm is greater than +Vth and the direction of the bridge arm current is negative, a short-circuit fault in Q11 can be determined.

[0083] In the specific implementation, see Figure 4c With Q13 on and Q11, Q12, Q13, and Q14 operating at state 0010, the path of the bridge arm current when the direction of the bridge arm current is negative and Q11 does not experience a short circuit fault can be found in [reference needed]. Figure 4cAs shown by the dashed line, the bridge arm current flows from O1 through the reverse diodes of Q13 and Q12 to the neutral point N, and the output voltage of the bridge arm is 0V. If a short circuit fault occurs in Q11, the path of the bridge arm current will change. The current will change from the original path (from O1 through the reverse diodes of Q13 and Q12 to the neutral point N) to flowing from O1 through Q11 to BUS+. At this time, the output voltage of the bridge arm will also change from -Vbus to +Vbus.

[0084] Similarly, see Figure 4d With Q13 on and Q11, Q12, Q13, and Q14 operating at state 0011, the path of the bridge arm current when the direction of the bridge arm current is negative and Q11 does not experience a short circuit fault can be found in the following diagram. Figure 4d As shown by the dashed line, the bridge arm current flows from O1 through Q14 to BUS-, and the output voltage of the bridge arm is -Vbus. If a short-circuit fault occurs in Q11, the path of the bridge arm current will change. The current will change from its original path (from O1 through Q14 to BUS-) to flowing from O1 through Q11 to BUS+, while the direction of the current remains unchanged. At this time, the output voltage of the bridge arm will also change from -Vbus to +Vbus.

[0085] Similarly, see Figure 4b With Q13 on and Q11, Q12, Q13, and Q14 operating at state 0110, the path of the bridge arm current when the direction of the bridge arm current is negative and Q11 does not experience a short circuit fault can be found in [reference needed]. Figure 4b As shown by the dashed line, the bridge arm current flows from O1 through the reverse diodes of Q13 and Q12 to the neutral point N, and the output voltage of the bridge arm is 0V. If a short circuit occurs in Q11, the path of the bridge arm current will change. The current will change from its original path (from O1 through the reverse diodes of Q13 and Q12 to the neutral point N) to flowing from O1 through Q11 to BUS+. The direction of the bridge arm current remains unchanged, and the output voltage of the bridge arm will change from 0V to +Vbus.

[0086] In summary, when Q13 is on, i.e., when the combined operating states of Q11, Q12, Q13, and Q14 are 0010, 0011, or 0110, Q11 is off, and the bridge arm current does not flow through Q11. If a short-circuit fault occurs in Q11, the bridge arm current will flow through Q11. In this case, the fault detection module can detect that the output voltage of the bridge arm is greater than +Vth and the direction of the bridge arm current is negative. Therefore, during the operation of the three-level inverter, the fault detection module can detect faults in Q11 based on the direction of the bridge arm current and the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is greater than +Vth and the direction of the bridge arm current is negative, the fault detection module can output a fault detection result for Q11 as a short-circuit fault (e.g., output a warning signal to indicate a short-circuit fault in Q11). The fault detection module can perform fault detection on the switching transistors when Q11, Q12, Q13, and Q14 are in the operating state of 0010, or during the process of switching the operating state of Q11, Q12, Q13, and Q14 from 0010 to 0011, or during the process of switching the operating state of Q11, Q12, Q13, and Q14 from 0100 to 0110. In other words, the fault detection module can use the dead time when Q12 and Q14 are both off to perform fault detection on the switching transistors. It can quickly and timely detect faulty switching transistors before or immediately after the switching transistors are turned on, thereby controlling the bridge arm to stop working and avoiding damage to the devices due to prolonged high current. It has high detection efficiency and high reliability.

[0087] When Q11 is on, the fault detection method for Q13 can be found in [reference needed]. Figure 4e :

[0088] In some feasible implementations, the fault detection module can determine that Q13 is faulty, i.e., Q13 has a short-circuit fault, when Q11 and Q12 are conducting and the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth. Here, when Q11 and Q12 are conducting, it can be considered that the switching transistors are controlled to turn on and off under the condition that Q12 is normally on and Q11 and Q13 are complementary waveforms. At this time, it can be determined that there are 1100 combinations of operating states of Q11, Q12, Q13 and Q14. In Table 1, the operating state of the switching transistor corresponding to 1100 can be determined to be Q11 conducting. As shown in Table 2, when Q11 is conducting, it can be determined that Q13 has a short-circuit fault when the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth.

[0089] In the specific implementation, see Figure 4e , Figure 4eThis is another schematic diagram of the current flow direction of the bridge arm current provided in this application. When Q11 is on, i.e., Q11, Q12, Q13, and Q14 are operating at 1100°, and Q13 does not experience a short circuit fault, regardless of whether the direction of the bridge arm current is positive or negative, BUS+ is connected to O1 via Q11, therefore the output voltage of the bridge arm is +Vbus. At this time, if Q13 experiences a short circuit fault, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from BUS+ through Q11 to O1) to the neutral point N being connected to O1 via Q12 and Q13, therefore the output voltage of the bridge arm will change from +Vbus to 0V.

[0090] In summary, when Q11, Q12, Q13, and Q14 are operating at state 1100, if a short-circuit fault occurs in Q13, the fault detection module can detect that the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth. Therefore, during the operation of the three-level inverter, the fault detection module can detect the fault in Q13 based on the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is between -Vth and +Vth, the fault detection module can output a fault detection result for Q13 as a short-circuit fault (e.g., output a warning signal to indicate a short-circuit fault in Q13).

[0091] When Q11 is on, the fault detection method for Q14 can be found in [reference needed]. Figure 4e :

[0092] In some feasible implementations, the fault detection module can determine that Q14 is faulty, i.e., Q14 has a short-circuit fault, when Q11 and Q12 are conducting and the output voltage of the bridge arm is less than -Vth. Here, when Q11 and Q12 are conducting, it can be considered that the switching transistors are controlled to turn on and off when Q12 is normally on and Q11 and Q13 are complementary waveforms. At this time, it can be determined that there are 1100 combinations of operating states of Q11, Q12, Q13 and Q14. In Table 1, the operating state of the switching transistor corresponding to 1100 can be determined to be Q11 conducting. As shown in Table 2, when Q11 is conducting and the output voltage of the bridge arm is less than -Vth, it can be determined that Q14 has a short-circuit fault.

[0093] In specific implementation, such as Figure 4eAs shown, when Q11 is on (i.e., Q11, Q12, Q13, and Q14 are operating at 1100°), and Q14 is not short-circuited, regardless of the direction of the bridge arm current (positive or negative), BUS+ is connected to O1 via Q11, resulting in an output voltage of +Vbus for the bridge arm. However, if Q14 experiences a short circuit, the path of the bridge arm current changes. The current changes from its original path (from BUS+ through Q11 to O1) to BUS- through Q14 to O1, thus changing the output voltage of the bridge arm from +Vbus to -Vbus.

[0094] In summary, when Q11, Q12, Q13, and Q14 are operating at state 1100, if a short-circuit fault occurs in Q14, the fault detection module can detect that the output voltage of the bridge arm is less than -Vth. Therefore, during the operation of the three-level inverter, the fault detection module can detect the fault in Q14 based on the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is less than -Vth, the fault detection module can output a fault detection result for Q14 as a fault (e.g., output a warning signal to indicate a Q14 fault).

[0095] It should be understood that when Q11, Q12, Q13, and Q14 are operating at 1100°C, the output voltage of the bridge arm when Q13 is not short-circuited can be predetermined. This allows us to determine the output voltage of the bridge arm when Q13 is short-circuited. By comparing the bridge arm's output voltage with +Vth and -Vth, a short-circuit fault in Q13 can be determined when the bridge arm's output voltage is less than or equal to +Vth and greater than or equal to -Vth. Similarly, the output voltage of the bridge arm when Q14 is not short-circuited can be predetermined. This allows us to determine the output voltage of the bridge arm when Q14 is short-circuited. By comparing the bridge arm's output voltage with +Vth and -Vth, a short-circuit fault in Q14 can be determined when the bridge arm's output voltage is less than -Vth. In this way, during the operation of the three-level inverter, the fault detection module can determine whether Q13 or Q14 is faulty based on the output voltage of the bridge arm when Q11, Q12, Q13 and Q14 are operating at 1100. The detection speed is fast and the applicability is strong.

[0096] When Q14 is on, the fault detection method for Q11 can be found in [reference needed]. Figure 4d :

[0097] In some feasible implementations, the fault detection module can determine that Q11 is faulty, i.e., Q11 has a short-circuit fault, when Q13 and Q14 are on and the output voltage of the bridge arm is greater than +Vth. Here, when Q13 is on and both Q11 and Q14 are off, it can be considered that the switching transistors are controlled to turn on and off under the condition that Q13 is normally on and Q12 and Q14 are complementary waveforms. At this time, the combination of the operating states of Q11, Q12, Q13 and Q14 can be determined to be 0011. In Table 1, the operating state of the switching transistor corresponding to 0011 can be determined to be Q14 on. As shown in Table 2, when Q14 is on, a short-circuit fault can be determined for Q11 when the output voltage of the bridge arm is greater than +Vth.

[0098] In the specific implementation, see Figure 4d , Figure 4d This is another schematic diagram of the current flow direction of the bridge arm current provided in this application. When Q14 is on, i.e., when Q11, Q12, Q13, and Q14 are in operating state 0011, and Q11 does not experience a short circuit fault, regardless of whether the direction of the bridge arm current is positive or negative, BUS- is connected to O1 via Q14, therefore the output voltage of the bridge arm is -Vbus. At this time, if Q11 experiences a short circuit fault, the path of the bridge arm current will change. The bridge arm current will change from the original current path (i.e., from BUS- through Q14 to O1) to BUS+ through Q11 to O1, therefore the output voltage of the bridge arm will change from -Vbus to +Vbus.

[0099] In summary, when Q11, Q12, Q13, and Q14 are operating at state 0011, if a short-circuit fault occurs in Q11, the fault detection module can detect that the output voltage of the bridge arm is greater than +Vth. Therefore, during the operation of the three-level inverter, the fault detection module can detect faults in Q11 based on the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is greater than +Vth, the fault detection module can output a fault detection result for Q11 as a short-circuit fault (e.g., output a warning signal to indicate a short-circuit fault in Q11).

[0100] When Q14 is on, the fault detection method for Q12 can be found in [reference needed]. Figure 4d :

[0101] In some feasible implementations, the fault detection module can determine that Q12 is faulty, i.e., Q12 has a short-circuit fault, when Q13 and Q14 are on and the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth. Here, when Q13 is on and Q11 and Q14 are both off, it can be considered that the switching transistors are controlled to turn on and off under the condition that Q13 is normally on and Q12 and Q14 are complementary waveforms. At this time, the combination of the operating states of Q11, Q12, Q13 and Q14 can be determined to be 0011. In Table 1, the operating state of the switching transistor corresponding to 0011 can be determined to be Q14 on. As shown in Table 2, when Q14 is on, when the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth, a short-circuit fault can be determined for Q12.

[0102] In specific implementation, such as Figure 4d As shown, when Q14 is on (i.e., Q11, Q12, Q13, and Q14 are in state 0011), and Q12 does not experience a short circuit, regardless of the direction of the bridge arm current (positive or negative), BUS- is connected to O1 via Q14, therefore the bridge arm output voltage is -Vbus. If Q12 experiences a short circuit, the bridge arm current path changes. The bridge arm current changes from its original path (from BUS- through Q14 to O1) to the neutral point N being connected to O1 via Q12 and Q13, therefore the bridge arm output voltage changes from -Vbus to 0.

[0103] In summary, when Q11, Q12, Q13, and Q14 are operating at state 0011, if a short-circuit fault occurs in Q12, the fault detection module can detect that the output voltage of the bridge arm is less than or equal to +Vth and greater than or equal to -Vth. Therefore, during the operation of the three-level inverter, the fault detection module can detect the fault in Q12 based on the output voltage of the bridge arm. For example, when the output voltage of the bridge arm is greater than +Vth, the fault detection module can output a fault detection result for Q12 as a fault (e.g., output a warning signal to indicate a Q12 fault).

[0104] It should be understood that when Q11, Q12, Q13, and Q14 are operating in state 0011, the output voltage of the bridge arm when Q12 is not short-circuited can be predetermined. This allows us to determine the output voltage of the bridge arm when Q12 is short-circuited. By comparing the bridge arm's output voltage with +Vth and -Vth, a short-circuit fault in Q12 can be determined when the bridge arm's output voltage is less than or equal to +Vth and greater than or equal to -Vth. Similarly, the output voltage of the bridge arm when Q11 is not short-circuited can be predetermined. This allows us to determine the output voltage of the bridge arm when Q11 is short-circuited. By comparing the bridge arm's output voltage with +Vth and -Vth, a short-circuit fault in Q11 can be determined when the bridge arm's output voltage is greater than +Vth. In this way, during the operation of the three-level inverter, the fault detection module can determine whether Q12 or Q11 is faulty based on the output voltage of the bridge arm when the operating status of Q11, Q12, Q13 and Q14 is 0011. It has the advantages of fast detection speed and fast fault judgment.

[0105] In this application, the fault detection module can detect faults in Q11, Q12, Q13, and Q14 based on the bridge arm current and the bridge arm output voltage, or based solely on the bridge arm output voltage, under various operating states of Q11, Q12, Q13, and Q14. It can also utilize dead time for fault detection of the switching transistors. In other words, the fault detection module can perform fault detection on the switching transistors during the dead time when both Q11 and Q13 are off, under a control mode where Q12 is normally on and Q11 and Q13 provide complementary waveforms; or, under a control mode where Q13 is normally on and Q12 and Q14 provide complementary waveforms, it can perform fault detection on the switching transistors during the dead time when both Q12 and Q14 are off. This achieves full coverage of short-circuit conditions, avoids missed detections, and has high accuracy.

[0106] See Figure 5 , Figure 5 This is another structural schematic diagram of the three-level inverter provided in this application. For example... Figure 5 As shown, the three-level inverter may further include a comparator circuit, which includes a first comparator P11 and a second comparator P12. The negative input terminal of the first comparator is configured with +Vth, and the negative input terminal of the second comparator is configured with -Vth. The positive input terminals of the first and second comparators are connected and then connected to O1. The first comparator is used to output a comparison result between +Vth and the output voltage of the bridge arm to the fault detection module, and the second comparator is used to output a comparison result between -Vth and the output voltage of the bridge arm to the fault detection module.

[0107] In some feasible implementations, the positive input terminals of P11 and P12 are connected to O1 via a first resistor R1. P11 can compare the magnitude of +Vth with the output voltage of the bridge arm and output the comparison result of +Vth and the output voltage of the bridge arm to the fault detection module. P12 can compare the magnitude of -Vth with the output voltage of the bridge arm and output the comparison result of -Vth and the output voltage of the bridge arm to the fault detection module. The comparison result of +Vth and the output voltage of the bridge arm output by P11 to the fault detection module can be a first comparison signal (e.g., BIT1), and the comparison result of -Vth and the output voltage of the bridge arm output by P12 to the fault detection module can be a second comparison signal (e.g., BIT2). Both BIT1 and BIT2 include a high level (1) and a low level (0).

[0108] It is understandable that the fault detection module can acquire BIT1 and BIT2 from the outputs of P11 and P12, and then determine the relationship between the bridge arm's output voltage and +Vth and -Vth based on BIT1 and BIT2. It should be understood that P11 can acquire the bridge arm's output voltage and output the comparison result between +Vth and the bridge arm's output voltage in digital form, i.e., BIT1; P12 can acquire the bridge arm's output voltage and output the comparison result between -Vth and the bridge arm's output voltage in digital form, i.e., BIT2. Therefore, P11 and P12 can digitally reflect the voltage range of the bridge arm's output voltage, facilitating the observation and comparison of the relationship between the bridge arm's output voltage and +Vth and -Vth, and offering advantages such as low loss, fast response, simple structure, and ease of implementation.

[0109] In some feasible implementations, such as Figure 5 As shown, the three-level inverter may further include a first filter circuit and a second filter circuit. The first filter circuit can receive BIT1 output from P11, and the second filter circuit can receive BIT2 output from P12. Here, the first and second filter circuits can selectively filter the glitches in BIT1 and BIT2 respectively, so as to output the filtered BIT1 and BIT2 to the fault detection module. For example, the first and second filter circuits can be resistor-capacitor filter units. It should be understood that the specific circuit structure of the first and second filter circuits can be determined according to the actual application scenario, and this application does not impose any limitations on it.

[0110] Optionally, when the fault detection module is a hardware chip with various processing functions, it can also receive the drive signals of each switch in the bridge arm, BIT1 and BIT2 output by P11 and P12 during the self-test phase, and then perform time delay compensation on the drive signals based on BIT1 and BIT2 so that the drive signals of the switch are matched with the waveform of the output voltage of the bridge arm in time.

[0111] In some feasible implementations, during the self-test phase, the fault detection module can receive the drive signal from the switching transistor, delay the rising edge of the drive signal by a first time, and delay the falling edge of the drive signal by a second time, so that the waveform of the drive signal from the switching transistor is time-matched with the output voltage waveform of the bridge arm. Specifically, before the three-level inverter starts working, the fault detection module can perform a self-test on the three-level inverter to determine the first and second times. During the self-test phase, the fault detection module can control the bridge arm to operate in either the mode where Q12 is normally on, Q14 is off, and Q11 and Q13 generate complementary waveforms, or it can control the bridge arm to operate in the mode where Q13 is normally on, Q11 is off, and Q12 and Q14 generate complementary waveforms. For ease of description, the mode where Q12 is normally on, Q14 is off, and Q11 and Q13 generate complementary waveforms will be used as an example for detailed explanation.

[0112] See Figure 6 , Figure 6 This is a timing diagram of the three-level inverter provided in this application. Figure 6 As shown, with Q12 normally on, Q14 off, and Q11 and Q13 providing complementary waveform generation, the drive signal for Q11 can be found in PWM_Q11. The output voltage of the bridge arm is greater than +Vth from t2 to t5, less than -Vth from t8 to t11, and less than or equal to +Vth and greater than or equal to -Vth from t14 to t17. It should be understood that the fault detection module detects the change in the bridge arm's output voltage with a delay between the rising and falling edges of PWM_Q11, and the fault detection module also detects the changes in BIT1 and BIT2 with a delay between the change in the bridge arm's output voltage. Therefore, it is necessary to compensate for the time delay of the drive signal of the switching transistor during the self-test phase to match the waveform of the switching transistor's drive signal with the output voltage of the bridge arm in time. Matching the change in the bridge arm's output voltage with the rising and falling edges of the drive signal improves detection accuracy and avoids false detections.

[0113] For example, during the time intervals t1 to t6, PWM_Q11 has a rising edge at time t1, during which the output voltage of the bridge arm begins to rise and stabilizes at time t2. Until time t4, PWM_Q11 changes from a rising edge to a falling edge, and the output voltage of the bridge arm begins to decrease and stabilizes at time t5. At time t2, the output voltage of the bridge arm stabilizes. At this time, P11 and P12 can compare +Vth and -Vth with the output voltage of the bridge arm, respectively, and output BIT1 = 0 and BIT2 = 1 to the fault detection module, indicating that the output voltage of the bridge arm is greater than +Vth during the time intervals t3 to t5. In this case, the first time interval is t1 to t3, and the second time interval is t4 to t6. The delayed PWM_Q11 has a rising edge at time t3 and a falling edge at time t6.

[0114] Similarly, between times t7 and t12, PWM_Q11 has a rising edge at time t7, during which the bridge arm's output voltage begins to decrease and stabilizes at time t8. Then, at time t10, PWM_Q11 changes from a rising edge to a falling edge, and the bridge arm's output voltage begins to rise and stabilizes at time t11. At time t8, the bridge arm's output voltage stabilizes. At this point, P11 and P12 can compare +Vth and -Vth with the bridge arm's output voltage, respectively, and output BIT1 = 1 and BIT2 = 0 to the fault detection module. This indicates that between times t9 and t11, the bridge arm's output voltage is less than -Vth. The first time interval is t7 to t9, and the second time interval is t10 to t12. The delayed PWM_Q11 has a rising edge at time t9 and a falling edge at time t12.

[0115] Similarly, between times t13 and t18, PWM_Q11 has a rising edge at time t13, and changes from a rising edge to a falling edge at time t10. During these times, the bridge arm's output voltage is always less than or equal to +Vth and greater than or equal to -Vth. At time t14, the bridge arm's output voltage stabilizes. At this time, P11 and P12 can compare +Vth and -Vth with the bridge arm's output voltage, respectively, and output BIT1 = 1 and BIT2 = 1 to the fault detection module. That is, between times t15 and t17, the bridge arm's output voltage is less than or equal to +Vth and greater than or equal to -Vth. The first time interval is t13 to t15, and the second time interval is t16 to t18. The delayed PWM_Q11 has a rising edge at time t15 and a falling edge at time t18. It should be understood that the fault detection module typically receives BIT1 = 1 and BIT2 = 1 at very close times, and the time difference is negligible. It should be understood that by compensating for the time delay of the drive signal during the self-test phase, the waveform of the drive signal of the switching transistor can be matched with the output voltage waveform of the bridge arm in time, avoiding fault detection of the switching transistor before the output voltage of the bridge arm stabilizes, which can effectively reduce the false detection rate and improve the reliability of detection.

[0116] In this embodiment, under the control mode of complementary waveform generation by Q11 and Q13 (and complementary waveform generation by Q12 and Q14), when Q11 and Q13 are simultaneously turned on, the short-circuit current flows from BUS+ through the reverse diodes of Q11, Q13, and Q12 to the neutral point N. When Q12 and Q14 are simultaneously turned on, the short-circuit current flows from the neutral point N through the reverse diodes of Q12 and Q13 and Q14 to BUS-. This short-circuit condition is called a bridge arm shoot-through short circuit. However, under the control mode of complementary waveform generation by Q11 and Q13 (and complementary waveform generation by Q12 and Q14), due to the asymmetry of the turn-on and turn-off times of the switching transistors, it is possible that one switching transistor may not be completely turned off while another switching transistor has already turned on. In this case, a bridge arm shoot-through short circuit may occur, leading to a short-circuit fault in the three-level inverter. Therefore, in order to reduce the probability of bridge arm shoot-through short circuit, the three-level inverter provided in this application is also suitable for realizing fault detection of switching transistors under the control mode of canceling the complementary wave generation of Q11 and Q13 (and canceling the complementary wave generation of Q12 and Q14).

[0117] Specifically, when the complementary waveform generation of Q11 and Q13 is canceled (as is the complementary waveform generation of Q12 and Q14), the operating states of Q11, Q12, Q13, and Q14 have three combinations: 1100, 0110, and 0011. Fault detection of the switching transistors can still be achieved by referring to Table 2. At this time, the structure of the three-level inverter can be found in [reference needed]. Figure 7 , Figure 7 This is another structural schematic diagram of the three-level inverter provided in this application. For example... Figure 7 As shown, the three-level inverter may also include a third filter circuit, which can be connected to O1. This third filter circuit may include a series-connected filter inductor Lr and filter capacitor Cr, and a resistor RLoad connected in parallel with Cr. In this case, the bridge arm current is the inductance current of Lr. Here, the input terminal of Lr is connected to O1, the output terminal of Lr is connected to the input terminal of Cr, and the output terminal of Cr is connected to the series connection terminal of C1 and C2, i.e., the neutral point N.

[0118] In some feasible real-time methods, parasitic capacitances exist between the switching transistors in the bridge arm and the printed circuit board (PCB), such as... Figure 7 The parasitic capacitors Cp1 to Cp4 shown form an inductor-capacitor resonant circuit with Lr. Cp1 to Cp4 resonate with Lr. At the rising and falling edges of the drive signal corresponding to each switch, the output voltage of the bridge arm will generate high-frequency oscillation. That is, at the instant the switch is turned on or off, the output voltage of the bridge arm will not jump immediately, but will oscillate or change gradually. High-frequency oscillation may damage the switch. This high-frequency oscillation may even be output to the subsequent circuit (such as the load), resulting in high-frequency noise in the output voltage of the bridge arm.

[0119] In this application, since the complementary oscillation of Q11 and Q13 is eliminated (as is the complementary oscillation of Q12 and Q14), a bridge arm shoot-through loop will not be formed immediately after a short circuit occurs in a certain switch. Instead, the short circuit occurs through Lr, and the short-circuit current rises at a slower rate, thus providing sufficient time for fault detection. Furthermore, the parallel Cr and resistor RLoad in the filter circuit can form a low-pass filter, allowing low-frequency signals to pass while suppressing high-frequency signals. This effectively filters out high-frequency components and removes noise, resulting in a smooth and clean signal output to the subsequent circuitry.

[0120] In some feasible implementations, high-frequency components can be effectively filtered out by adjusting the resistor-capacitor time constant (i.e., the RC constant). For example, in a control mode where Q11 and Q13 complementarily generate waves (and Q12 and Q14 complementarily generate waves), the resistance of RLoad can be tens of ohms, and the capacitance of Cr can be in the picofarad range. When the control mode where the complementary generation of Q11 and Q13 (and Q12 and Q14) is cancelled is used, high-frequency components generated in the inductor-capacitor oscillation circuit can be filtered out by increasing the RC constant. In this case, the resistance of Load can be tens of ohms, and the capacitance of Cr can be tens to hundreds of nanofarads. It is evident that adjusting the RC constant allows for flexible adaptation to different control modes, ensuring high efficiency under different control conditions, thus demonstrating strong applicability. Optionally, filtering can also be achieved through a resistor-capacitor absorption circuit. Figure 7 The diode connected in parallel across the Cr terminals utilizes the unidirectional conductivity of the diode to control the current value to flow in one direction, diverting noise to ground and thus preferentially suppressing high-frequency noise and interference signals.

[0121] Understandably, the above Figures 2 to 7 The three-level inverter shown is a single-arm inverter, meaning it contains only one arm. However, in practical applications, a three-level inverter can also have multiple arms. In this case, multiple arms can perform fault detection on the switching transistors within that arm. For details, see [link to documentation]. Figure 8 , Figure 8 This is another structural schematic diagram of the three-level inverter provided in this application. For example... Figure 8The three-level inverter shown may include a fault detection module, an A-phase bridge arm, a B-phase bridge arm, and a C-phase bridge arm. In one feasible embodiment, the three-level inverter also includes C1 and C2 connected in series, and BUS+ and BUS-. Here, C1 and C2 are connected in series between BUS+ and BUS-, one end of C1 is connected to BUS+, the other end of C1 is connected to one end of C2, the other end of C2 is connected to BUS-, and the connection point where the other end of C1 connects to one end of C2 is the series connection terminal of C1 and C2. The A-phase bridge arm may include a first switch Q11, a second switch Q12, a third switch Q13, and a fourth switch Q14. The aforementioned B-phase bridge arm may include a first switch Q21, a second switch Q22, a third switch Q23, and a fourth switch Q24, and the aforementioned C-phase bridge arm may include a first switch Q31, a second switch Q32, a third switch Q33, and a fourth switch Q34. The series connection of Q11 and Q14 can be the midpoint O1 of the A-phase bridge arm; the series connection of Q21 and Q24 can be the midpoint O2 of the B-phase bridge arm; and the series connection of Q31 and Q34 can be the midpoint O3 of the C-phase bridge arm. The A-phase, B-phase, and C-phase bridge arms correspond to the A-phase, B-phase, and C-phase outputs of the three-level inverter, respectively. O1, O2, and O3 can be connected together through the second and third switches in reverse series to form a common terminal, which is called the neutral point N. Specifically, O1 is connected to O2 through the reverse series Q12 and Q13, and O2 through the reverse series Q22 and Q23, and O3 through the reverse series Q32 and Q33 to form the neutral point N. It should be understood that the series connection of C1 and C2 is also connected to the neutral point N. The structures of the A-phase, B-phase, and C-phase bridge arms can be referred to the above. Figure 2 The three-level inverter shown.

[0122] Optionally, the above-mentioned three-level inverter can also include a G-phase bridge arm. See [link / reference]. Figure 9 , Figure 9 This is another structural schematic diagram of the three-level inverter provided in this application. For example... Figure 9 The three-level inverter shown may include C1 and C2 connected in series, as well as phase A, phase B, phase C, and phase G bridge arms. The structures of the aforementioned phase A, phase B, phase C, and phase G bridge arms can be referred to the above. Figure 2The three-level inverter shown has its G-phase bridge arm leading to the G-line port. The G-phase bridge arm may include a first switch Q41 and a fourth switch Q44 connected in series. These two switches are connected in parallel across capacitors C1 and C2, and their series connection point is the midpoint O4 of the G-phase bridge arm. O4 can be connected to the series connection point of C1 and C2 via a second switch Q42 and a third switch Q43 connected in reverse series. The series connection point of the first switch Q41 and the fourth switch Q44 can be used to access the G-phase port. It should be understood that the series connection point of C1 and C2 is also connected to the neutral point N.

[0123] In addition, the above Figures 8 to 9 In the three-level inverter shown, the connection terminals of the first and fourth switching transistors of each bridge arm are also connected to the series connection terminals of C1 and C2 through a filter capacitor and a filter inductor. For example, with Figure 10 Taking the three-level inverter shown as an example, see Figure 10 , Figure 10 This is another structural schematic diagram of the three-level inverter provided in this application. (The remaining text appears to be incomplete and requires further context.) Figure 10 In the three-level inverter shown, the connection terminals of Q11 and Q14 in phase A bridge arm are connected to the connection terminals of C1 and C2 through filter inductor L1 and filter capacitor C10. The connection terminals of Q21 and Q24 in phase B bridge arm are connected to the connection terminals of C1 and C2 through filter inductor L2 and filter capacitor C20. The connection terminals of Q31 and Q34 in phase C bridge arm are connected to the connection terminals of C1 and C2 through filter inductor L3 and filter capacitor C30. The connection terminals of Q41 and Q44 in phase G bridge arm are connected to the connection terminals of C1 and C2 through filter inductor L4 and filter capacitor C40.

[0124] In the technical solution provided in this application, the fault detection module in the three-level inverter can perform fault detection on each switch based on the direction of the bridge arm current and the output voltage of the bridge arm under the operating state of each switch. Here, the direction of the bridge arm current can be obtained by sampling the inductor current of the filter inductors (i.e., L1, L2, L3, L4) connected to the midpoint of each phase bridge arm (such as O1, O2, O3, O4), and the output voltage of the bridge arm can be obtained by sampling the voltage at the midpoint of each phase bridge arm. See details... Figures 2 to 7 The corresponding embodiments will not be described in detail here. It should be understood that, Figure 9 In the corresponding embodiment, the comparator circuit, the first filter circuit, the second filter circuit, and the... Figure 7 In the corresponding embodiments, the implementation method corresponding to the third filter circuit is still applicable. Figures 8 to 10 The three-level inverter shown here will not be described in detail here.

[0125] In some feasible implementations, in the case of multiple bridge arms, each bridge arm corresponds to a comparator circuit, which can be used to compare the output voltage of that bridge arm with the magnitudes of +Vth and -Vth, and output BIT1 and BIT2 to the fault detection module. It is evident that when there are multiple bridge arms, the fault detection module will receive multiple BIT1 and BIT2 outputs from the comparator circuits. Therefore, in order to receive the BIT1 and BIT2 outputs from the comparator circuits corresponding to each bridge arm, at least the number of ports needs to be set in the fault detection module, which leads to wasted port resources and high costs. Therefore, by setting a gating module between the fault detection module and the comparator circuits, the fault detection module can receive only one or a few BIT1 and BIT2 outputs from the comparator circuits at the same time, avoiding processing multiple tasks simultaneously, effectively improving response speed and increasing fault detection efficiency.

[0126] In this embodiment, the fault detection module in the three-level inverter can detect faults in each switch based on the direction of the bridge arm current and the output voltage of the bridge arm, under the operating conditions of each switch. In other words, the fault detection module can detect faults in each switch based on the direction of the bridge arm current and the output voltage of the bridge arm, or based solely on the output voltage of the bridge arm, even when the operating states of each switch are different. It can also utilize dead time for fault detection. Specifically, the fault detection module can perform fault detection during the dead time when both the first and third switches are off, under a control mode where the second switch is normally on and the first and third switches generate complementary waveforms; or, under a control mode where the third switch is normally on and the second and fourth switches generate complementary waveforms, during the dead time when both the second and fourth switches are off. This achieves full coverage of short-circuit conditions, avoids missed detections, and has high accuracy.

Claims

1. A three-level inverter, characterized in that, The three-level inverter includes a fault detection module and at least one bridge arm. Each bridge arm includes a first switch and a fourth switch. A second switch and a third switch are connected in series between the midpoint of each bridge arm and the neutral point of the inverter. The fault detection module is used to: determine that the first switch is faulty when the output voltage of the bridge arm is greater than a first voltage threshold and the direction of the bridge arm current is positive, provided that the second switch is turned on and both the first and fourth switches are turned off; the first voltage threshold is greater than zero voltage and less than the positive bus voltage.

2. The three-level inverter according to claim 1, characterized in that, The fault detection module is also used to: determine that the fourth switch is faulty when the output voltage of the bridge arm is less than the second voltage threshold and the direction of the bridge arm current is negative, provided that the third switch is turned on and the first and fourth switches are both turned off; the second reference voltage is greater than the negative bus voltage and less than the zero voltage.

3. The three-level inverter according to claim 1, characterized in that, The fault detection module is further configured to: determine that the second switch is faulty when the third switch is turned on and both the first and second switches are turned off, and the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, and the direction of the bridge arm current is positive; the second reference voltage is greater than the negative bus voltage and less than the zero voltage.

4. The three-level inverter according to claim 1, characterized in that, The fault detection module is further configured to: determine that the third switch is faulty when the second switch is turned on and the third and fourth switches are both turned off, and the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, and the direction of the bridge arm current is negative; the second reference voltage is greater than the negative bus voltage and less than the zero voltage.

5. The three-level inverter according to claim 1, characterized in that, The fault detection module is also used to: determine that the fourth switch is faulty when the output voltage of the bridge arm is less than the second reference voltage and the direction of the bridge arm current is positive, provided that the second reference voltage is greater than the negative bus voltage and less than zero voltage.

6. The three-level inverter according to claim 1, characterized in that, The fault detection module is also used to: determine that the first switch is faulty when the output voltage of the bridge arm is greater than the first reference voltage and the direction of the bridge arm current is negative, provided that the third switch is turned on and the first switch is turned off.

7. The three-level inverter according to claim 1, characterized in that, The fault detection module is further configured to: when the first switch and the second switch are conducting, and when the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, determine that the third switch is faulty; the second reference voltage is greater than the negative bus voltage and less than the zero voltage.

8. The three-level inverter according to claim 1, characterized in that, The fault detection module is further configured to: determine that the fourth switch is faulty when the output voltage of the bridge arm is less than the second reference voltage, provided that the first switch and the second switch are conducting; the second reference voltage is greater than the negative bus voltage and less than the zero voltage.

9. The three-level inverter according to claim 1, characterized in that, The fault detection module is also used to: determine that the first switch is faulty when the output voltage of the bridge arm is greater than the first reference voltage, provided that the third switch and the fourth switch are turned on.

10. The three-level inverter according to claim 1, characterized in that, The fault detection module is also used to: when the third switch and the fourth switch are turned on, and when the output voltage of the bridge arm is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, determine that the second switch is faulty; the second reference voltage is greater than the negative bus voltage and less than zero voltage.

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