A virtual vector modulation method and system for reducing common-mode voltage amplitude

Abstract

The present application relates to midpoint clamping three-level inverter technical field, provide a kind of virtual vector modulation method and system for reducing common-mode voltage amplitude, comprising: constructing space voltage vector diagram and being divided into 12 sectors, according to the relationship of reference voltage vector and α The sector where the reference voltage vector is located is obtained.The high common-mode voltage basic vector is eliminated, the low common-mode voltage virtual vector is reconstructed, and the virtual voltage vector diagram is obtained.The action time of each virtual vector for synthesizing the reference voltage vector is calculated using the volt-second balance principle.The action time of each basic vector for synthesizing the virtual vector is calculated.The pulse sequence is generated in the order of three-phase bridge arm switching state sequential single-phase switching and with the constraint condition that the pulse sequence is half-cycle symmetric.Through this method, the common-mode voltage amplitude of the system is reduced while the number of switching actions is reduced.

Description

Technical Field

[0001] This invention relates to the field of midpoint clamped three-level inverter technology, specifically to a virtual vector modulation method and system for reducing common-mode voltage amplitude. Background Technology

[0002] Neutral-point clamped three-level inverters are widely used in commercial and industrial energy storage, photovoltaic power generation, and motor drives due to their low output voltage harmonic content and ability to effectively reduce the withstand voltage rating of power devices. However, neutral-point clamped three-level inverters using pulse width modulation (PWM) technology generate high-frequency, high-amplitude common-mode voltage between the load neutral point and the ground reference point. These common-mode voltages have a series of adverse effects: for example, in photovoltaic power generation systems, common-mode voltage can generate leakage current to ground, increasing the risk of electric shock. In motor drives, common-mode voltage can induce shaft voltage and current on the motor shaft, which, over time, will accelerate the aging of motor insulation and lead to bearing failure. Therefore, common-mode voltage must be suppressed.

[0003] However, traditional space vector pulse width modulation (SVPWM) strategies utilize a base vector with a large common-mode voltage amplitude, resulting in a large common-mode voltage amplitude in the system when applying SVPWM modulation. Existing virtual vector methods can effectively reduce the system's common-mode voltage amplitude, but they increase the number of switching operations, leading to a sharp increase in system switching losses. Summary of the Invention

[0004] The technical problem to be solved by the present invention is how to make up for the above-mentioned deficiencies and reduce the number of switching actions while reducing the common-mode voltage amplitude of the system.

[0005] The present invention solves the above-mentioned technical problems through the following technical means: This invention provides a virtual vector modulation method for reducing common-mode voltage amplitude, comprising the following steps: S1. Based on the circuit topology of the midpoint clamped three-level inverter, construct a space voltage vector diagram to obtain all basic vectors and their corresponding common-mode voltage amplitudes. S2. Divide the space voltage vector diagram into 12 sectors, and decompose the reference voltage vector into... α-β Coordinate system, based on the reference voltage vector and α By determining the relationship between the included axes angles, the sector where the reference voltage vector is located can be obtained. S3. Remove the high common-mode voltage basic vector and reconstruct the low common-mode voltage virtual vector to obtain the virtual voltage vector map. S4. Based on the sector where the reference voltage vector is located and the virtual voltage vector diagram, calculate the duration of each virtual vector that synthesizes the reference voltage vector using the volt-second balance principle; S5. Based on the duration of action of each virtual vector, calculate the duration of action of each basic vector in the composite virtual vector; S6. Based on the action time of each basic vector, generate a pulse sequence by sequentially switching the three-phase bridge arm switch states one phase at a time and ensuring that the pulse sequence satisfies the half-cycle symmetry constraint.

[0006] Further, the basic vectors mentioned in step S1 are divided into zero vector, small vector, medium vector, and large vector according to their magnitudes, with corresponding magnitudes of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 10 ... V dc , V dc , V dc , V dc This is the DC bus voltage.

[0007] Further, step S2, based on the reference voltage vector and... α The relationship between the shaft angles is used to determine the sector where the reference voltage vector is located, specifically including: reference voltage vector V ref Decomposed into α-β Coordinate system, obtaining the reference vector in α and β The voltage projection on the axis is as follows:

[0008] in, θ For the reference voltage vector and α The included angle of the axis, u α and u β The reference voltage vector is respectively in α and β Voltage projection on the axis; Then sector N The calculation is as follows:

[0009] in, This is the floor function.

[0010] Further, step S3, which involves eliminating high common-mode voltage base vectors and reconstructing low common-mode voltage virtual vectors, specifically involves selecting from all base vectors obtained in step S1 and their corresponding common-mode voltage amplitudes, and using those with common-mode voltage amplitudes no greater than [value missing]. V dcVirtual vectors are synthesized from basic vectors; based on the magnitude of the synthesized virtual vectors, they are defined as virtual medium vector, virtual small vector, and virtual zero vector, respectively.

[0011] Preferably, when the reference voltage vector is located in the first sector, step S4 involves calculating the duration of each virtual vector synthesizing the reference voltage vector using the volt-second balance principle, as shown in the following formula:

[0012] in, T s The time of one PWM cycle, V dc This is the DC bus voltage. t V0 The duration of action of the virtual zero vector. t VS1 The duration of action of the virtual small vector. t VM1 This represents the duration of action of the vector in the virtual space.

[0013] Preferably, when the reference voltage vector is located in the first sector, the action time of each basic vector of the synthesized virtual vector in step S5 is calculated as follows:

[0014] in, t pon The duration of the switch state pon. t poo The duration of the switch state poo t pnn The duration of the switch state pnn. t ooo The duration of action of the zero vector ooo.

[0015] Preferably, when the reference voltage vector is located in the first sector, the pulse sequence in step S6 is: First effective vector V pnn Second effective vector V pon The third effective vector V poo Zero vector V ooo The third effective vector V poo Second effective vector V pon First effective vector V pnn ; The action times of the first effective vector, the second effective vector, and the third effective vector are respectively... t pnn , t pon , tpoo The duration of action of the zero vector is t ooo .

[0016] The present invention also provides a virtual vector modulation system for reducing common-mode voltage amplitude. The system executes the above-described method during operation and includes the following modules: The space voltage vector diagram construction module is used to construct a space voltage vector diagram based on the circuit topology of a midpoint clamped three-level inverter, and obtain all basic vectors and their corresponding common-mode voltage amplitudes. The reference voltage vector positioning module is used to divide the space voltage vector diagram into 12 sectors and decompose the reference voltage vector into... α-β Coordinate system, based on the reference voltage vector and α By determining the relationship between the included axes angles, the sector where the reference voltage vector is located can be obtained. The virtual voltage vector diagram construction module is used to remove the high common-mode voltage base vector, reconstruct the low common-mode voltage virtual vector, and obtain the virtual voltage vector diagram. The virtual vector action time calculation module is used to calculate the action time of each virtual vector that synthesizes the reference voltage vector based on the sector where the reference voltage vector is located and the virtual voltage vector diagram, using the volt-second balance principle. The basic vector action time calculation module is used to calculate the action time of each basic vector in the composite virtual vector based on the action time of each virtual vector. The pulse sequence generation module is used to generate a pulse sequence based on the action time of each basic vector, in the order of successive single-phase switching of the three-phase bridge arm switch states, and with the pulse sequence satisfying the constraint condition of half-cycle symmetry.

[0017] The advantages of this invention are: (1) This invention synthesizes and constructs a virtual vector by selecting a basic vector whose common-mode voltage amplitude is no greater than 1 / 6 of the DC-side voltage, which can stably suppress the common-mode voltage amplitude of the system to 1 / 6 of the DC-side voltage. Compared with the existing SVPWM technology of 1 / 3, it reduces the voltage by half.

[0018] (2) Based on the action time of each basic vector, the present invention generates a pulse sequence by sequentially switching the state of the three-phase bridge arm switch in a single-phase manner and satisfying the constraint condition of half-cycle symmetry. Compared with the traditional virtual vector modulation technology, it reduces the number of switching actions while achieving the reduction of common-mode voltage. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating a virtual vector modulation method for reducing common-mode voltage amplitude according to an embodiment of the present invention; Figure 2This is a schematic diagram of the circuit topology of a point-clamped three-level inverter system in an embodiment of the present invention; Figure 3 This is a space voltage vector diagram of the point-clamped three-level inverter in an embodiment of the present invention; Figure 4 This is a virtual voltage vector diagram and a schematic diagram of virtual vector distribution according to an embodiment of the present invention; Figure 5 The above is a steady-state simulation waveform of the three-phase current output of the modulation method described in this embodiment of the invention. Figure 6 This is a simulation waveform of the common-mode voltage of the conventional SPWM modulation method according to an embodiment of the present invention; Figure 7 This is a simulation waveform of the common-mode voltage of the modulation method described in an embodiment of the present invention; Figure 8 This is a schematic diagram of a pulse sequence for a conventional virtual vector modulation method according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the pulse sequence of the modulation method described in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1 This embodiment provides a virtual vector modulation method for reducing common-mode voltage amplitude. The specific implementation process is as follows: Figure 1 As shown, it includes the following steps: S1, such as Figure 2 As shown, a space voltage vector diagram is constructed based on the circuit topology of a midpoint-clamped three-level inverter, as follows. Figure 3 As shown, all basic vectors and their corresponding common-mode voltage magnitudes are obtained; as shown in the table below:

[0022] The basic vectors are classified into zero vector, small vector, medium vector, and large vector according to their magnitudes, with corresponding magnitudes of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 10, 11, 12, 13, 14, 15, 16 V dc , V dc , V dc ,V dc This is the DC bus voltage.

[0023] S2. Divide the space voltage vector diagram into 12 sectors, and decompose the reference voltage vector into... α-β Coordinate system, based on the reference voltage vector and α The sector containing the reference voltage vector is obtained based on the relationship between the axis and the angle; the step of determining the sector containing the reference voltage vector and the angle between the axis and the reference voltage vector is then performed. α The relationship between the shaft angles is used to determine the sector where the reference voltage vector is located, specifically including: reference voltage vector V ref Decomposed into α-β Coordinate system, obtaining the reference vector in α and β The voltage projection on the axis is as follows:

[0024] in, θ For the reference voltage vector and α The included angle of the axis, u α and u β The reference voltage vector is respectively in α and β Voltage projection on the axis; Then sector N The calculation is as follows:

[0025] in, This is the floor function. In this embodiment, sector 1 corresponds to... θ ∈(0°-30°), sector 2 corresponds to θ ∈[30°, 60°), sector 3 corresponds to θ ∈[60°, 90°), sector 4 corresponds to θ Sector 5 corresponds to [90°, 120°). θ ∈[120°, 150°), sector 6 corresponds to θ ∈[150°, 180°), sector 7 corresponds to θ ∈[180°, 210°), sector 8 corresponds to θ ∈[210°, 240°), sector 9 corresponds to θ ∈[240°, 270°), sector 10 corresponds to θ ∈[270°, 300°), sector 11 corresponds to θ ∈[300°, 330°), sector 12 corresponds to θ ∈[330°, 360°).

[0026] S3. Traditional virtual vector modulation uses a basic vector with a common-mode voltage amplitude of 1 / 3 Vdc when synthesizing virtual vectors, resulting in a still relatively high common-mode voltage in the system. The purpose of the method proposed in this embodiment is to further suppress common-mode voltage and eliminate basic vectors with high common-mode voltages, building upon the traditional advantage of virtual vectors balancing the midpoint potential. Therefore, the specific method for reconstructing low common-mode voltage virtual vectors and obtaining the virtual voltage vector diagram is as follows: From all the basic vectors obtained in step S1 and their corresponding common-mode voltage amplitudes, select and use those with a common-mode voltage amplitude not greater than... V dc Virtual vectors are synthesized from basic vectors; based on the magnitude of the synthesized virtual vectors, they are defined as virtual medium vector, virtual small vector, and virtual zero vector, respectively. The constructed virtual voltage vector diagram and the distribution of virtual vectors in each sector are shown below. Figure 4 As shown, taking sector 1 as an example, the low common-mode virtual vector constructed in this embodiment is as follows:

[0027] in, V V0 For virtual zero vector, V VM1 For virtual vectors, V VS1 This is a virtual small vector. As shown in the table above, the common-mode voltage amplitude of the virtual vectors constructed in this embodiment is no greater than 1 / 6. V dc Therefore, the common-mode voltage amplitude of the midpoint clamped three-level inverter system is suppressed.

[0028] S4. Based on the sector where the reference voltage vector is located and the virtual voltage vector diagram, calculate the duration of each virtual vector synthesizing the reference voltage vector using the volt-second balance principle; when the reference voltage vector is located in the first sector, the duration of each virtual vector synthesizing the reference voltage vector using the volt-second balance principle in step S4 is as follows:

[0029] in, T s The time of one PWM cycle, V dc This is the DC bus voltage. t V0 The duration of action of the virtual zero vector. t VS1 The duration of action of the virtual small vector. t VM1 This represents the duration of action of the vector in the virtual space.

[0030] S5. Based on the duration of each virtual vector, calculate the duration of each basic vector of the synthesized virtual vector; when the reference voltage vector is located in the first sector, the calculation of the duration of each basic vector of the synthesized virtual vector in step S5 is as follows:

[0031] in, t pon The duration of the switch state pon. t poo The duration of the switch state poo t pnn The duration of the switch state pnn. t ooo The duration of action of the zero vector ooo.

[0032] S6. Based on the action time of each basic vector, generate a pulse sequence by sequentially switching the three-phase bridge arm switch states one phase at a time and ensuring that the pulse sequence satisfies the half-cycle symmetry constraint.

[0033] When the reference voltage vector is located in the first sector, the pulse sequence in step S6 is as follows: V pnn — V pon — V poo — V ooo — V poo — V pon — V pnn Specifically: the first effective vector V pnn Second effective vector V pon The third effective vector V poo Zero vector V ooo The third effective vector V poo Second effective vector V pon First effective vector V pnn ; The action times of the first effective vector, the second effective vector, and the third effective vector are respectively... t pnn , t pon , t poo The duration of action of the zero vector is t ooo .

[0034] To address the problem that reducing common-mode voltage in existing technologies often leads to an increase in the number of switching cycles (high switching losses), this invention achieves a reduction in switching losses within one switching cycle through the aforementioned specific basic vector arrangement. T s The specific technical means to ensure that only 6 switching actions occur within a given timeframe are as follows: In the first half of the PWM cycle (0— T s / 2) Inside: (1) By V pnn Switch to V pon At that time, only the state of phase B switch changes from n to 0, and the operation occurs once. (2) By V pon Switch to V poo At that time, only the state of phase C switch changes from n to 0, and the operation occurs once. (3) By V poo Switch to V ooo At that time, only the state of phase A switch changes from p to o, and the operation occurs once. There were a total of 3 switching state changes in the first half of the cycle, and no direct jump between p and n occurred in any phase.

[0035] In the second half of the PWM cycle ( T s / 2— T s ), pulse sequence symmetrical reverse wave generation V ooo — V poo — V pon — V pnn Similarly, only 3 switching actions occurred.

[0036] like Figure 9 As shown, the method proposed in this embodiment, by carefully selecting the basic vector combinations corresponding to the virtual vectors, ensures that only a single-phase bridge arm experiences a change in a single level (such as 0 and n, or p and 0) when adjacent basic vectors switch. Within a complete switching cycle... T s Within this system, the number of main switching actions is strictly limited to 6. This contrasts sharply with traditional virtual vector modulation (where single-phase pole arms may flip multiple times, resulting in 8 or even 10 periodic switching actions). Figure 8 As shown, in one T sIn contrast, the traditional SVPWM modulation method requires a total of 8 switching operations. This method significantly reduces the switching frequency and system switching losses.

[0037] This embodiment also includes experimental simulations of the proposed method, such as... Figure 5 The figure shows the simulated waveform of the three-phase output current of the present invention. As can be seen from the figure, the present invention has good steady-state output capability, which proves the correctness of the method.

[0038] At the same time, such as Figure 6 As shown, the simulated common-mode voltage waveform of the traditional SVPWM modulation method has a common-mode voltage amplitude of 66.7V, which is 1 / 3 of the DC-side voltage; Figure 7 The figure shows the simulated common-mode voltage waveform of the method proposed in this embodiment. The common-mode voltage amplitude is 33.3V, which is 1 / 6 of the DC-side voltage. Compared with the traditional SVPWM modulation method, the common-mode voltage amplitude is reduced by half, achieving a better common-mode voltage amplitude reduction effect.

[0039] Example 2 It should be further explained that, based on the same inventive concept, this embodiment also provides a virtual vector modulation system for reducing the common-mode voltage amplitude. When the system is running, it executes the method described in Embodiment 1, including the following modules: The space voltage vector diagram construction module is used to construct a space voltage vector diagram based on the circuit topology of a midpoint clamped three-level inverter, and obtain all basic vectors and their corresponding common-mode voltage amplitudes. The reference voltage vector positioning module is used to divide the space voltage vector diagram into 12 sectors and decompose the reference voltage vector into... α-β Coordinate system, based on the reference voltage vector and α By determining the relationship between the included axes angles, the sector where the reference voltage vector is located can be obtained. The virtual voltage vector diagram construction module is used to remove the high common-mode voltage base vector, reconstruct the low common-mode voltage virtual vector, and obtain the virtual voltage vector diagram. The virtual vector action time calculation module is used to calculate the action time of each virtual vector that synthesizes the reference voltage vector based on the sector where the reference voltage vector is located and the virtual voltage vector diagram, using the volt-second balance principle. The basic vector action time calculation module is used to calculate the action time of each basic vector in the composite virtual vector based on the action time of each virtual vector. The pulse sequence generation module is used to generate a pulse sequence based on the action time of each basic vector, in the order of successive single-phase switching of the three-phase bridge arm switch states, and with the pulse sequence satisfying the constraint condition of half-cycle symmetry.

[0040] The basic vectors described in the space voltage vector diagram construction module are divided into zero vectors, small vectors, medium vectors, and large vectors according to their magnitudes, with corresponding magnitudes of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 10, 19, 10, 1 V dc , V dc , V dc , V dc This is the DC bus voltage.

[0041] The reference voltage vector positioning module is based on the reference voltage vector and α The relationship between the shaft angles is used to determine the sector where the reference voltage vector is located, specifically including: reference voltage vector V ref Decomposed into α-β Coordinate system, obtaining the reference vector in α and β The voltage projection on the axis is as follows:

[0042] in, θ For the reference voltage vector and α The included angle of the axis, u α and u β The reference voltage vector is respectively in α and β Voltage projection on the axis; Then sector N The calculation is as follows:

[0043] in, This is the floor function.

[0044] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A virtual vector modulation method for reducing common-mode voltage amplitude, characterized in that, Includes the following steps: S1. Based on the circuit topology of the midpoint clamped three-level inverter, construct a space voltage vector diagram to obtain all basic vectors and their corresponding common-mode voltage amplitudes. S2. Divide the space voltage vector diagram into 12 sectors, and decompose the reference voltage vector into... α-β Coordinate system, based on the reference voltage vector and α By determining the relationship between the included axes angles, the sector where the reference voltage vector is located can be obtained. S3. Remove the high common-mode voltage basic vector and reconstruct the low common-mode voltage virtual vector to obtain the virtual voltage vector map. S4. Based on the sector where the reference voltage vector is located and the virtual voltage vector diagram, calculate the duration of each virtual vector that synthesizes the reference voltage vector using the volt-second balance principle; S5. Based on the duration of action of each virtual vector, calculate the duration of action of each basic vector in the composite virtual vector; S6. Based on the action time of each basic vector, generate a pulse sequence by sequentially switching the three-phase bridge arm switch states one phase at a time and ensuring that the pulse sequence satisfies the half-cycle symmetry constraint.

2. The virtual vector modulation method for reducing common-mode voltage amplitude according to claim 1, characterized in that, The basic vectors mentioned in step S1 are divided into zero vector, small vector, medium vector, and large vector according to their magnitudes, with corresponding magnitudes of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 10 ... V dc , V dc , V dc , V dc This is the DC bus voltage.

3. The virtual vector modulation method for reducing common-mode voltage amplitude according to claim 1, characterized in that, Step S2 describes the process based on the reference voltage vector and... α The relationship between the shaft angles is used to determine the sector where the reference voltage vector is located, specifically including: reference voltage vector V ref Decomposed into α-β Coordinate system, obtaining the reference vector in α and β The voltage projection on the axis is as follows: in, θ For the reference voltage vector and α The included angle of the axis, u α and u β The reference voltage vector is respectively in α and β Voltage projection on the axis; Then sector N The calculation is as follows: in, This is the floor function.

4. The virtual vector modulation method for reducing common-mode voltage amplitude according to claim 1, characterized in that, Step S3, which involves removing the high common-mode voltage base vector and reconstructing the low common-mode voltage virtual vector, specifically involves selecting from all the base vectors obtained in step S1 and their corresponding common-mode voltage amplitudes, and using those with a common-mode voltage amplitude not greater than [value missing]. V dc Virtual vectors are synthesized from basic vectors; based on the magnitude of the synthesized virtual vectors, they are defined as virtual medium vector, virtual small vector, and virtual zero vector, respectively.

5. A virtual vector modulation method for reducing common-mode voltage amplitude according to claim 4, characterized in that, When the reference voltage vector is located in the first sector, step S4 involves calculating the duration of each virtual vector synthesizing the reference voltage vector using the volt-second balance principle, as shown in the following formula: in, T s The time of one PWM cycle, V dc This is the DC bus voltage. t V0 The duration of action of the virtual zero vector. t VS1 The duration of action of the virtual small vector. t VM1 This represents the duration of action of the vector in the virtual space.

6. The virtual vector modulation method for reducing common-mode voltage amplitude according to claim 1, characterized in that, When the reference voltage vector is located in the first sector, the action time of each basic vector of the synthesized virtual vector in step S5 is calculated as follows: in, The duration of the switch state pon. The duration of the switch state poo The duration of the switch state pnn. The duration of action of the zero vector ooo.

7. The virtual vector modulation method for reducing common-mode voltage amplitude according to claim 1, characterized in that, When the reference voltage vector is located in the first sector, the pulse sequence in step S6 is as follows: First effective vector Second effective vector Third effective vector Zero vector Third effective vector Second effective vector First effective vector ; The action times of the first effective vector, the second effective vector, and the third effective vector are respectively... , , The duration of action of the zero vector is .

8. A virtual vector modulation system for reducing common-mode voltage amplitude, characterized in that, Includes the following modules: The space voltage vector diagram construction module is used to construct a space voltage vector diagram based on the circuit topology of a midpoint clamped three-level inverter, and obtain all basic vectors and their corresponding common-mode voltage amplitudes. The reference voltage vector positioning module is used to divide the space voltage vector diagram into 12 sectors and decompose the reference voltage vector into... α-β Coordinate system, based on the reference voltage vector and α By determining the relationship between the included axes angles, the sector where the reference voltage vector is located can be obtained. The virtual voltage vector diagram construction module is used to remove the high common-mode voltage base vector, reconstruct the low common-mode voltage virtual vector, and obtain the virtual voltage vector diagram. The virtual vector action time calculation module is used to calculate the action time of each virtual vector that synthesizes the reference voltage vector based on the sector where the reference voltage vector is located and the virtual voltage vector diagram, using the volt-second balance principle. The basic vector action time calculation module is used to calculate the action time of each basic vector in the composite virtual vector based on the action time of each virtual vector. The pulse sequence generation module is used to generate a pulse sequence based on the action time of each basic vector, in the order of successive single-phase switching of the three-phase bridge arm switch states, and with the pulse sequence satisfying the constraint condition of half-cycle symmetry.

9. A virtual vector modulation system for reducing common-mode voltage amplitude according to claim 8, characterized in that, The basic vectors described in the space voltage vector diagram construction module are divided into zero vectors, small vectors, medium vectors, and large vectors according to their magnitudes, with corresponding magnitudes of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 10, 19, 10, 1 V dc , V dc , V dc , V dc This is the DC bus voltage.

10. A virtual vector modulation system for reducing common-mode voltage amplitude according to claim 8, characterized in that, The reference voltage vector positioning module is based on the reference voltage vector and α The relationship between the shaft angles is used to determine the sector where the reference voltage vector is located, specifically including: reference voltage vector V ref Decomposed into α-β Coordinate system, obtaining the reference vector in α and β The voltage projection on the axis is as follows: in, θ For the reference voltage vector and α The included angle of the axis, u α and u β The reference voltage vector is respectively in α and β Voltage projection on the axis; Then sector N The calculation is as follows: in, This is the floor function.

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