LCL type grid-connected inverter's advance sampling control system and method

Abstract

The application discloses a kind of LCL type grid-connected inverter's advance sampling control system, comprising: A / D sampling unit, for collecting DC bus voltage, inverter side inductance current and grid voltage;Signal conditioning unit is used to extract the phase angle of grid voltage and output its sine value and filter ripple component in DC bus voltage;Control operation unit is used to output current amplitude instruction according to the deviation of DC bus voltage and target voltage value and output voltage regulating signal according to the deviation of reference current and inverter side inductance current;Signal synthesis unit is used to generate reference current and modulation wave;PWM modulator is used to generate PWM driving signal according to modulation wave, and output to the control electrode of power switching device;The sampling time of the inverter side inductance current is configured to be ahead of the sampling time K of grid voltage PWM period, wherein K is greater than 0 and less than 1.The application also provides a kind of LCL type grid-connected inverter's advance sampling control method.

Description

Technical Field

[0001] This invention relates to an advanced sampling control system and method for an LCL-type grid-connected inverter. Background Technology

[0002] Photovoltaic power generation is an important direction for the development of new energy sources. Inverters are used to convert the direct current (DC) from photovoltaic modules into alternating current (AC) for transmission to the grid and loads. Inverter PWM signals typically generate high-frequency harmonics, polluting the grid-connected current. Therefore, LCL filters are generally used to reduce the harmonic distortion rate of the grid-connected current.

[0003] LCL filters have an inherent resonant frequency. When the grid impedance changes or system parameters fluctuate, the grid-connected current is prone to oscillation or even resonant divergence near the resonant frequency, severely affecting the stable operation of the inverter and grid quality. Existing technologies for suppressing LCL filter resonance include passive damping and active damping. Passive damping increases the damping at the resonant frequency by connecting resistors in series and parallel in the inverter-side inductor, filter capacitor, and grid-side inductor, thus suppressing oscillation. However, increasing the resistance introduces additional power loss, reduces the overall inverter conversion efficiency, and increases overall cost and heat dissipation design complexity.

[0004] Active damping introduces virtual damping by increasing the feedback of the control system to suppress the resonance spike of the LCL filter. However, it requires additional sampling of the filter capacitor current or inverter side inductor current on the basis of sampling the grid current, which increases the cost of sampling circuits and sensors, makes the control algorithm more complex, and is susceptible to digital delay. It also has poor parameter adaptability when the grid impedance changes. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a control scheme that does not increase hardware costs, does not generate additional losses, and can effectively suppress LCL resonance.

[0006] The present invention provides an advanced sampling control system for an LCL-type grid-connected inverter, applicable to the main circuit of a grid-connected inverter, comprising: The A / D sampling unit is used to collect DC bus voltage, inverter-side inductor current and grid voltage. The signal conditioning unit includes a phase-locked loop, a secondary notch filter, a first subtractor, and a second subtractor. The phase-locked loop is used to extract the phase angle of the grid voltage and output the cosine value. The secondary notch filter is used to filter out the ripple component in the DC bus voltage. The control and operation unit includes a voltage controller and a current controller. The voltage controller is used to output a current amplitude command based on the deviation between the DC bus voltage and the target voltage value. The current controller is used to output a voltage adjustment signal based on the deviation between the reference current and the inverter-side inductor current. The signal synthesis unit includes a multiplier and an adder. The multiplier is used to multiply the current amplitude command by the cosine value to generate a reference current, and the adder is used to superimpose the voltage regulation signal with the grid voltage to generate a modulated wave. A PWM modulator is used to generate a PWM drive signal based on the modulated wave and output it to the control electrode of a power switching device. The sampling time of the inverter-side inductor current is configured to lead the sampling time of the grid voltage by K PWM cycles, where K is greater than 0 and less than 1.

[0007] Both the voltage controller and the current controller are proportional-integral controllers.

[0008] In the signal conditioning unit, the input terminal of the phase-locked loop receives the grid voltage after analog-to-digital conversion; the first input terminal of the first subtractor receives the DC bus voltage after analog-to-digital conversion, the second input terminal of the first subtractor receives the target voltage value, the output terminal of the first subtractor is connected to the input terminal of the secondary notch filter, and the output terminal of the secondary notch filter is connected to the input terminal of the voltage controller; the first input terminal of the second subtractor is connected to the output terminal of the multiplier, the second input terminal of the second subtractor receives the current of the inverter-side inductor, and the output terminal of the second subtractor is connected to the input terminal of the current controller.

[0009] In the control operation unit, the output terminal of the voltage controller is connected to the first input terminal of the multiplier, the second input terminal of the multiplier receives the cosine value output by the phase-locked loop, and the output terminal of the multiplier outputs a reference current to the first input terminal of the second subtractor; the output terminal of the current controller is connected to the first input terminal of the adder, the second input terminal of the adder receives the grid voltage Vg, and the output terminal of the adder is connected to the input terminal of the PWM modulator.

[0010] On the other hand, the present invention also provides a method for advance sampling control of the inverter-side inductor current of an LCL filter in a grid-connected inverter, comprising the following steps: Step S1: Configure the sampling time of the inverter-side inductor current to lead the sampling time of the grid voltage by K PWM cycles, where K is greater than 0 and less than 1; Step S2: Collect the DC bus voltage, inverter side inductor current and grid voltage; extract the phase angle of the grid voltage through a phase-locked loop and output the cosine value; filter the deviation between the DC bus voltage and the target voltage value through a secondary notch filter and send it to the voltage controller; multiply the output of the voltage controller by the cosine value to obtain the reference current. Step S3: The deviation between the reference current and the inverter-side inductor current obtained from the advance sampling is sent to the current controller, and the output of the current controller is superimposed with the grid voltage to generate a PWM modulation signal; and Step S4: Generate a PWM drive signal based on the PWM modulation signal to control the on / off state of the power switching device.

[0011] Both the voltage controller and the current controller are proportional-integral controllers.

[0012] In step S2, the DC bus voltage is converted from analog to digital and then subtracted from the target voltage value in the first subtractor to obtain a voltage deviation signal. After the voltage deviation signal is filtered out by a secondary notch filter to remove the ripple component, it is PI-regulated by the voltage controller to generate a current amplitude command.

[0013] In step S3, the reference current is the product of the current amplitude command and the phase cosine of the grid voltage. The voltage regulation signal output by the current controller and the grid voltage are superimposed in the adder to form a modulation wave, which is used for PWM modulation so that the inverter-side inductor current tracks the reference current and the DC bus voltage tracks the target voltage value.

[0014] This invention advances the sampling time of the inverter-side inductor current by K PWM cycles before the grid voltage, reducing the equivalent delay of the current feedback path from 1.5Ts to (1.5-K)Ts. The phase lag of the LCL filter module near the resonant frequency is compensated, thus preventing the system from losing stability. Furthermore, earlier sampling allows the controller to acquire current information sooner, resulting in faster overcurrent protection response and reducing the risk of damage to power switching devices. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a block diagram illustrating a preferred embodiment of the advanced sampling control system for an LCL-type grid-connected inverter according to the present invention.

[0016] Figure 2 This is a flowchart illustrating a preferred embodiment of the advance sampling control method for an LCL-type grid-connected inverter according to the present invention.

[0017] Figure 3 This is a schematic diagram of PWM modulation and sampling timing. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] The advanced sampling control system and method for an LCL-type grid-connected inverter described in this invention are applicable to the main circuit of a grid-connected inverter. To facilitate the explanation of the working principle of this invention, the structure of the main circuit of the grid-connected inverter will be described first.

[0020] Please refer to Figure 1 As shown, the grid-connected inverter main circuit on which this invention is based consists of a DC-DC module, a full-bridge inverter module, and an LCL filter module.

[0021] The input terminal of the DC-DC module is connected to the output terminal of the photovoltaic module to receive the DC power generated by the photovoltaic module through photoelectric conversion. The output terminal of the DC-DC module is connected to both ends of the DC bus capacitor C1. The anode of the DC bus capacitor C1 is connected to the positive output terminal of the DC-DC module and the positive input terminal of the full-bridge inverter circuit, i.e., node P. The cathode of the DC bus capacitor C1 is connected to the negative output terminal of the DC-DC module and the negative input terminal of the full-bridge inverter circuit, i.e., node N. The DC bus capacitor C1 serves as the DC bus voltage support capacitor, and the voltage across its terminals is the DC bus voltage Vbus.

[0022] The DC-DC module can be any one of a Boost converter, a Buck converter, or a Buck-Boost converter, used to convert the wide-range fluctuating DC voltage output by the photovoltaic module into a stable DC bus voltage Vbus, and control the DC bus voltage Vbus to track a preset target voltage value Vbus_ref.

[0023] The full-bridge inverter module includes power switching devices Q1, Q2, Q3, and Q4. The collector of power switching device Q1 is connected to the positive terminal P of the DC bus, the emitter of power switching device Q1 is connected to the first AC output terminal A, and the control terminal, i.e., the gate, of power switching device Q1 is connected to the first drive signal output terminal of the drive circuit to receive the first drive signal PWM1.

[0024] The collector of power switch Q2 is connected to the first AC output node A, the emitter of power switch Q2 is connected to the negative terminal N of the DC bus, and the control terminal of power switch Q2 is connected to the second drive signal output terminal of the drive circuit to receive the second drive signal PWM2. Power switches Q1 and Q2 form the first bridge arm, i.e., the A-phase bridge arm, and their series connection point is the first AC output node A, which is also the inverter bridge output node A.

[0025] The collector of the power switch Q3 is connected to the positive terminal P of the DC bus, the emitter of the power switch Q3 is connected to the second AC output terminal B, and the control terminal of the power switch Q3 is connected to the third drive signal output terminal of the drive circuit to receive the third drive signal PWM3.

[0026] The collector of power switch Q4 is connected to the second AC output node B, the emitter of power switch Q4 is connected to the negative terminal N of the DC bus, and the gate of power switch Q4 is connected to the fourth drive signal output terminal of the drive circuit to receive the fourth drive signal PWM4. Power switches Q3 and Q4 form the second bridge arm, namely the B-phase bridge arm, and their series connection point is the second AC output node B, which is also the inverter bridge output node B.

[0027] In this embodiment, the power switching devices Q1, Q2, Q3, and Q4 can be individually selected from any one of Si-MOSFET, IGBT, SiCMOSFET, or GaN HEMT. When IGBT is used, each power switching device is also connected in reverse parallel with a freewheeling diode to provide a current freewheeling path for the inductive load.

[0028] The input terminal of the LCL filter module is connected to the output node of the full-bridge inverter module. Specifically, the LCL filter module includes an inverter-side inductor L1, a filter capacitor C2, and a grid-side inductor L2. The first terminal of the inverter-side inductor L1 is connected to the inverter bridge output node A, and the second terminal of the inverter-side inductor L1 is connected to the filter node C, which is the intermediate node of the LCL filter module. The first terminal of the filter capacitor C2 is connected to the filter node C, and the second terminal of the filter capacitor C2 is connected to the grid grid Ug. Figure 1 The resistance Zg represents the equivalent impedance of the grid-side line. In this embodiment, the filter capacitor C2 is used to provide a low-impedance shunt path for the high-frequency switching ripple current.

[0029] The first end of the grid-side inductor L2 is connected to the filter node C, and the second end of the grid-side inductor L2 is connected to the power grid. The inverter-side inductor L1, the filter capacitor C2, and the grid-side inductor L2 together constitute a T-type LCL filter structure. The inverter-side inductor L1 of this LCL filter module is close to the inverter bridge side to suppress high-frequency switching ripple in the inverter bridge output voltage. The grid-side inductor L2 is close to the power grid side to further attenuate current harmonics injected into the power grid. The filter capacitor C2 is connected across the series connection node of L1 and L2 and the power grid to provide a local bypass path for high-frequency harmonics. The LCL filter module converts the DC bus voltage Vbus into a high-frequency PWM pulse voltage based on the switching on and off of power switching devices Q1, Q2, Q3, and Q4. After the high-frequency harmonics are filtered out by the LCL filter module, this high-frequency PWM pulse voltage is converted into a smooth sinusoidal grid-connected current and supplied to the power grid.

[0030] Please continue to refer to this. Figure 1 As shown, the advanced sampling control system for an LCL-type grid-connected inverter according to the present invention includes an A / D sampling unit, a signal conditioning unit, a control operation unit, and a signal synthesis unit. The signal conditioning unit includes a phase-locked loop, a secondary notch filter, a first subtractor, and a second subtractor. The control operation unit includes a voltage controller Gv(s) and a current controller Gi(s). The signal synthesis unit includes a multiplier and an adder.

[0031] The A / D sampling unit is used to acquire the voltage Vbus across the DC bus capacitor C1, the current IL1 of the inverter-side inductor L1, and the grid voltage Vg, and convert them into digital signals via analog-to-digital conversion. The signal conditioning unit is used to preprocess the signals acquired by the A / D sampling unit and the reference signal, including phase extraction, ripple filtering, and deviation calculation. The control operation unit is used to perform PI regulation operations based on the deviation signal, generating current amplitude commands and voltage regulation signals respectively. The signal synthesis unit is used to multiply and add the control operation results with the synchronization reference signal and the feedforward signal to generate a modulated wave.

[0032] Specifically, the first voltage sampling input terminal and the second voltage sampling input terminal of the A / D sampling unit are connected to the two ends of the DC bus capacitor C1 to collect the voltage Vbus across the DC bus capacitor C1; the current sampling input terminal of the A / D sampling unit is connected to the first end of the inverter-side inductor L1 to collect the current IL1 of the inverter-side inductor L1; the grid voltage sampling input terminal of the A / D sampling unit is connected to the end of the grid ug near the grid-side inductor L2 to collect the grid voltage Vg.

[0033] The acquired grid voltage Vg is converted from analog to digital and then fed into a phase-locked loop (PLL). The PLL extracts the phase angle θ of the grid voltage Vg and outputs the cosine value cosθ. The acquired voltage Vbus across the DC bus capacitor C1 is converted from analog to digital and then output along with the target voltage value Vbus_ref to a first subtractor. After processing by the first subtractor, the output is sent to a secondary notch filter. The output of the secondary notch filter is connected to the input of the voltage controller Gv(s). In this embodiment, the secondary notch filter is used to filter out the ripple component in the DC bus voltage Vbus.

[0034] The output of the voltage controller Gv(s) is connected to the first input of the multiplier. The second input of the multiplier is used to receive the cosine value cosθ output by the phase-locked loop. The output of the multiplier is connected to the first output of the second subtractor, which is used to output the reference current I_ref to the first input of the second subtractor. The second input of the second subtractor is used to receive the current IL1 of the inverter-side inductor L1. The output of the second subtractor is connected to the input of the current controller Gi(s). The output of the current controller Gi(s) is connected to the first input of the adder. The second input of the adder is used to receive the grid voltage Vg. The output of the adder is connected to the input of the PWM modulator. The output of the PWM modulator is connected to the gate of the four power switching devices Q1, Q2, Q3, and Q4, which is used to output PWM control signals to the four power switching devices Q1, Q2, Q3, and Q4 to control the on / off state of the four power switching devices Q1, Q2, Q3, and Q4.

[0035] During operation, the DC-DC module converts the wide-range fluctuating DC voltage output from the photovoltaic module into a stable DC bus voltage Vbus, and controls the DC bus voltage Vbus to track a preset target voltage value Vbus_ref. That is, regardless of changes in the input voltage of the photovoltaic module, the DC-DC module ensures that the DC bus voltage Vbus remains near the preset target voltage value Vbus_ref. The DC bus capacitor C1 is used to smooth the DC bus voltage Vbus, and the voltage across its terminals is the DC bus voltage Vbus. The full-bridge inverter circuit inverts the DC bus voltage Vbus into a high-frequency PWM pulse voltage. The LCL filter module is used to filter out high-frequency harmonics in this high-frequency PWM pulse voltage and convert it into a smooth sinusoidal grid-connected current ug injected into the grid.

[0036] The A / D sampling unit collects the voltage Vbus across the DC bus capacitor C1, the current IL1 of the inverter-side inductor L1, and the grid voltage Vg in real time. The sampling time of the inverter-side inductor L1 current IL1 is configured to precede the sampling time of the grid voltage Vg by K PWM cycles, where K is greater than 0 and less than 1. For example, assuming one PWM cycle is Ts, meaning a PWM carrier cycle is generated every Ts, the sampling time of the inverter-side inductor L1 current IL1 is t1, and the sampling time of the grid voltage Vg is t2, then the sampling time of the inverter-side inductor L1 current IL1 is t1 = t2. K*Ts means that the sampling of the inverter-side inductor L1 current IL1 is K*Ts earlier than the grid voltage Vg. Taking K=0.75 as an example, the sampling and analog-to-digital conversion of the inverter-side inductor L1 current IL1 is completed 0.75Ts before the grid voltage Vg is sampled. When the grid voltage Vg is sampled and the control interrupt service routine is started, the current data of the inverter-side inductor L1 current IL1 is ready, and the controller can directly enter the current loop calculation without waiting for the analog-to-digital conversion of the inverter-side inductor L1 current IL1.

[0037] In this invention, the current IL1 of the inverter-side inductor L1 is sampled 0.75 PWM cycles ahead of the grid voltage Vg, which is equivalent to obtaining the current information in advance. When the grid voltage Vg is collected, the controller already has the data of the current IL1 of the inverter-side inductor L1. At this time, there is no need to wait for the sampling and conversion process of the current IL1 of the inverter-side inductor L1, that is, the equivalent delay of the current feedback loop is shortened.

[0038] In digital control systems, the delay from the time all sampled data is ready until the PWM drive waveform is equivalently applied to the power switching device is typically considered to be 1.5Ts. This delay is divided into two parts: First, the calculation and update waiting delay: the new duty cycle instruction calculated within the current sampling period must wait until the start of the next PWM cycle before being written to the PWM comparator register and taking effect; this delay is 1Ts. Second, the modulation equivalent delay: when using symmetrical PWM sampling, the average volt-second point of action of the output voltage pulse within this cycle is located at the midpoint of the cycle, resulting in an inherent half-cycle lag of 0.5Ts.

[0039] Specifically Figure 3 Timing example, Figure 3 In the diagram, the vertical axis IL1 represents the current in the inverter-side inductor L1, Vg represents the grid voltage, Vtri1 and Vtri2 represent a pair of anti-phase triangular carrier waves, and Q1, Q2, Q3, and Q4 represent the PWM control signals output from the PWM modulator to the four power switching devices Q1, Q2, Q3, and Q4, respectively. The horizontal axes t0, t1, and t2 represent three different sampling times. Specifically, the triangular carrier wave Vtri1 is compared with the input modulation wave Vm to generate PWM control signals Q1 and Q2, and the triangular carrier wave Vtri2 is compared with the input modulation wave Vm to generate PWM control signals Q3 and Q4. Vm0 is the 0th modulation signal, Vm1 is the 1st modulation signal, Vm0* is the 0th preloaded modulation signal, Vm1* is the 1st preloaded modulation signal, and Vm2* is the 2nd preloaded modulation signal. Figure 3 When the value of K is less than 0.5, the sampling of the current IL1 of the inverter-side inductor L1 is located in the downlink segment after the peak value of the triangular carrier wave.

[0040] The triangular carriers Vtri1 and Vtri2 both employ an up-and-down counting method, with each triangular carrier having a counter period of 0.5Ts. This means that a complete PWM cycle Ts contains two counter cycles. The PWM timer starts counting upwards from 0. When it reaches time (1-K)*Ts, it triggers the A / D sampling unit to sample the current IL1 of the inverter-side inductor L1. The counter continues running, and at time Ts (when the count value decreases to 0), it triggers the A / D sampling unit to sample the grid voltage Vg. Therefore, the sampling times of the current IL1 of the inverter-side inductor L1 and the grid voltage Vg differ by K*Ts.

[0041] The grid voltage Vg is converted from analog to digital and then fed into a phase-locked loop (PLL). The PLL extracts the phase angle θ of the grid voltage Vg and outputs the cosine value cosθ. The DC bus voltage Vbus is converted from analog to digital and then output to the first subtractor along with the target voltage value Vbus_ref. The first subtractor subtracts the two and outputs the deviation signal to the secondary notch filter. The secondary notch filter filters out the ripple component in the deviation signal and then outputs it to the voltage controller Gv(s).

[0042] The output of the voltage controller Gv(s) is multiplied by the cosine value cosθ of the phase-locked loop output in a multiplier to generate a reference current I_ref, which is then fed into the first input of the second subtractor. The second input of the second subtractor receives the current IL1 from the inverter-side inductor L1, and simultaneously subtracts the reference current I_ref from the current IL1 of the inverter-side inductor L1, outputting a deviation signal to the current controller Gi(s). The output of the current controller Gi(s) is superimposed on the grid voltage Vg in an adder to generate a modulated wave, which is then fed into the PWM modulator.

[0043] The PWM modulator generates four drive signals (PWM1-PWM4) based on the modulation wave, which control the on / off states of power switching devices Q1, Q2, Q3, and Q4 respectively. The DC bus voltage Vbus tracks the target voltage value Vbus_ref after loop regulation, and the inverter-side inductor current IL1 tracks the reference current I_ref after the same loop regulation. This constitutes a complete control loop, enabling stable grid-connected operation of the inverter.

[0044] In the above control process, the sampling time of the inverter-side inductor current IL1 always leads the sampling time of the grid voltage Vg by K PWM cycles. This advanced sampling timing reduces the equivalent digital delay in the current feedback path from the original 1.5Ts to (1.5-K)Ts, thereby compensating for the phase delay caused by the LCL filter module near the resonant frequency. This ensures that the inverter can operate stably under any operating conditions, including light load, heavy load, and grid impedance changes, with a smooth, sinusoidal grid current waveform and no oscillations.

[0045] Please continue to refer to this. Figure 2As shown, based on the system described above, a preferred embodiment of the advance sampling control method for an LCL-type grid-connected inverter provided by the present invention specifically includes the following steps: Step S1: Real-time acquisition of the voltage Vbus across the DC bus capacitor C1, the current IL1 of the inverter-side inductor L1, and the grid voltage Vg.

[0046] Specifically, the sampling time of the current IL1 of the inverter-side inductor L1 is configured to lead the sampling time of the grid voltage Vg by K PWM cycles, where K is greater than 0 and less than 1. Assuming one PWM cycle is Ts, the sampling time of the current IL1 of the inverter-side inductor L1 is t1, and the sampling time of the grid voltage Vg is t2. Then t2 minus t1 equals K multiplied by Ts, meaning the sampling time of the grid voltage Vg lags behind the sampling time of the current IL1 of the inverter-side inductor L1 by K PWM cycles. When K = 0.75, it means the sampling time of the current IL1 of the inverter-side inductor L1 is 0.75 PWM cycles ahead of the sampling time of the grid voltage Vg.

[0047] Step S2 involves preprocessing the acquired signal. Specifically, this includes: converting the grid voltage Vg to digital and then feeding it into a phase-locked loop (PLL); extracting the phase angle θ of the grid voltage Vg from the PLL and outputting the cosine value cosθ; converting the DC bus voltage Vbus to digital and then outputting it along with the target voltage value Vbus_ref to a first subtractor; subtracting the two values ​​by the first subtractor and outputting the deviation signal to a secondary notch filter; filtering out the ripple component in the deviation signal by the secondary notch filter and then outputting it to the voltage controller Gv(s).

[0048] Step S3 involves performing an adjustment operation. Specifically, this includes: the voltage controller Gv(s) performs a PI adjustment operation based on the received deviation signal, outputting a current amplitude command to the first input terminal of the multiplier; the second input terminal of the multiplier receives the cosine value cosθ output by the phase-locked loop, multiplies the current amplitude command by the cosine value cosθ to generate a reference current I_ref, and outputs it to the first input terminal of the second subtractor; the second input terminal of the second subtractor receives the current IL1 of the inverter-side inductor L1, subtracts the reference current I_ref from the current IL1 of the inverter-side inductor L1, and outputs a deviation signal to the current controller Gi(s); the current controller Gi(s) performs a PI adjustment operation based on the received deviation signal, outputting a voltage adjustment signal to the first input terminal of the adder.

[0049] Step S4 involves generating a modulated wave through a signal synthesis unit. Specifically, this includes: receiving the grid voltage Vg at the second input terminal of the adder, superimposing the voltage regulation signal output by the current controller Gi(s) with the grid voltage Vg to generate a modulated wave, which is then output to the PWM modulator.

[0050] Step S5: The PWM modulator generates four drive signals, PWM1-PWM4, based on the modulation wave, and outputs them to the control electrodes (gates) of the power switching devices Q1, Q2, Q3, and Q4 respectively, so as to control the on / off state of the four power switching devices Q1, Q2, Q3, and Q4.

[0051] This invention configures the sampling time of the inverter-side inductor current to lead the grid voltage sampling time by K PWM cycles, thereby shortening the equivalent delay in the current feedback path from 1.5Ts to (1.5-K)Ts. This effectively compensates for the phase lag caused by the LCL filter module near the resonant frequency, preventing the system from losing stability due to large phase deviations. When K is 0.75, the equivalent delay is 0.75Ts, which is lower than the upper limit of the delay allowed by the system stability boundary. The phase deviation at the resonant frequency can be effectively compensated, and the grid-connected current does not oscillate. Furthermore, this invention only requires adjusting the timing configuration of the sampling time, without adding a control algorithm module. Even under complex operating conditions such as fluctuations in grid impedance, the system can still maintain stable operation.

[0052] In addition, since the sampling time of the inverter-side inductor current is earlier than that of the grid voltage, the controller can obtain current feedback information earlier. When an overcurrent occurs, the protection action responds faster, which helps to reduce the risk of power switching devices being damaged by overcurrent.

[0053] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A lead sampling control system for an LCL-type grid-connected inverter, applicable to the main circuit of a grid-connected inverter, characterized in that, The advanced sampling control system of the LCL grid-connected inverter includes: The A / D sampling unit is used to collect DC bus voltage, inverter-side inductor current and grid voltage. The signal conditioning unit includes a phase-locked loop, a secondary notch filter, a first subtractor, and a second subtractor. The phase-locked loop is used to extract the phase angle of the grid voltage and output the cosine value. The secondary notch filter is used to filter out the ripple component in the DC bus voltage. The control and operation unit includes a voltage controller and a current controller. The voltage controller is used to output a current amplitude command based on the deviation between the DC bus voltage and the target voltage value. The current controller is used to output a voltage adjustment signal based on the deviation between the reference current and the inverter-side inductor current. The signal synthesis unit includes a multiplier and an adder. The multiplier is used to multiply the current amplitude command by the cosine value to generate a reference current, and the adder is used to superimpose the voltage regulation signal with the grid voltage to generate a modulated wave. A PWM modulator is used to generate a PWM drive signal based on the modulated wave and output it to the control electrode of a power switching device. The sampling time of the inverter-side inductor current is configured to lead the sampling time of the grid voltage by K PWM cycles, where K is greater than 0 and less than 1.

2. The advanced sampling control system for the LCL-type grid-connected inverter according to claim 1, characterized in that, Both the voltage controller and the current controller are proportional-integral controllers.

3. The advanced sampling control system for the LCL-type grid-connected inverter according to claim 1, characterized in that, In the signal conditioning unit, the input terminal of the phase-locked loop receives the grid voltage after analog-to-digital conversion; the first input terminal of the first subtractor receives the DC bus voltage after analog-to-digital conversion, the second input terminal of the first subtractor receives the target voltage value, the output terminal of the first subtractor is connected to the input terminal of the secondary notch filter, and the output terminal of the secondary notch filter is connected to the input terminal of the voltage controller. The first input terminal of the second subtractor is connected to the output terminal of the multiplier, the second input terminal of the second subtractor receives the current of the inverter-side inductor, and the output terminal of the second subtractor is connected to the input terminal of the current controller.

4. The advanced sampling control system for the LCL-type grid-connected inverter according to claim 3, characterized in that, In the control and operation unit, the output terminal of the voltage controller is connected to the first input terminal of the multiplier, the second input terminal of the multiplier receives the cosine value output by the phase-locked loop, and the output terminal of the multiplier outputs a reference current to the first input terminal of the second subtractor; the output terminal of the current controller is connected to the first input terminal of the adder, the second input terminal of the adder receives the grid voltage Vg, and the output terminal of the adder is connected to the input terminal of the PWM modulator.

5. A method for advance sampling control of an LCL-type grid-connected inverter, employing the system described in any one of claims 1 to 4, characterized in that, Includes the following steps: Step S1: Configure the sampling time of the inverter-side inductor current to lead the sampling time of the grid voltage by K PWM cycles, where K is greater than 0 and less than 1; Step S2: Collect the DC bus voltage, inverter side inductor current and grid voltage; extract the phase angle of the grid voltage through a phase-locked loop and output the cosine value; filter the deviation between the DC bus voltage and the target voltage value through a secondary notch filter and send it to the voltage controller; multiply the output of the voltage controller by the cosine value to obtain the reference current. Step S3: The deviation between the reference current and the inverter-side inductor current obtained by advance sampling is sent to the current controller, and the output of the current controller is superimposed with the grid voltage to generate a PWM modulation signal; as well as Step S4: Generate a PWM drive signal based on the PWM modulation signal to control the on / off state of the power switching device.

6. The advance sampling control method for an LCL-type grid-connected inverter according to claim 5, characterized in that, Both the voltage controller and the current controller are proportional-integral controllers.

7. The advanced sampling control of the LCL-type grid-connected inverter according to claim 5, characterized in that, In step S2, the DC bus voltage is converted from analog to digital and then subtracted from the target voltage value in the first subtractor to obtain a voltage deviation signal. After the voltage deviation signal is filtered out by a secondary notch filter to remove the ripple component, it is PI-regulated by the voltage controller to generate a current amplitude command.

8. The advanced sampling control of the LCL-type grid-connected inverter according to claim 5, characterized in that, In step S3, the reference current is the product of the current amplitude command and the phase cosine of the grid voltage. The voltage regulation signal output by the current controller and the grid voltage are superimposed in the adder to form a modulation wave, which is used for PWM modulation so that the inverter-side inductor current tracks the reference current and the DC bus voltage tracks the target voltage value.

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