Switchable capacitor cell

Abstract

A capacitor cell includes two capacitor circuits and two cell nodes, with each capacitor circuit located in a path between a circuit node of the cell and a respective cell node. The capacitor cell includes enable transistors, with the enable transistors being caused to conduct to enable a capacitance of the cell to be utilized by a circuit, such as an oscillator, for frequency control by an enable signal having a voltage range between a low supply voltage and a high supply voltage. One of the enable transistors is coupled between the cell nodes. Each of the two enable transistors includes a first current terminal coupled in the path to the respective cell node. Second current terminals of the two enable transistors are biased at a bias voltage less than the high supply voltage when the enable signal is not asserted.

Description

Technical Field

[0001] This invention relates to a switchable capacitor unit. Background Technology

[0002] Circuits such as oscillators, tuning circuits, filters, amplifiers, or integrators may use capacitors to perform their functions. For at least some of these circuits, the effective capacitance can be adjusted to affect circuit operation. For example, some programmable oscillators utilize capacitor cells that can be selectively enabled or disabled to adjust the effective capacitance of the oscillator, thereby adjusting the oscillator frequency. Summary of the Invention

[0003] Features specifically shown or described relative to one embodiment set forth herein may be implemented in other embodiments set forth herein.

[0004] In one embodiment, a circuit includes a capacitor cell. The capacitor cell includes: a first capacitor circuit coupled between a first circuit node and a first cell node of the capacitor cell; a second capacitor circuit coupled between a second circuit node and a second cell node of the capacitor cell; a first transistor including a first current terminal coupled in a path leading to the first cell node; a second transistor including a first current terminal coupled in a path leading to the second cell node; and a third transistor including a first current terminal coupled in a path leading to the first cell node and a second current terminal coupled in a path leading to the second cell node. Each of the first, second, and third transistors includes a control terminal for receiving an enable signal, wherein the first, second, and third transistors are placed in a predetermined conduction state to enable the capacitor cell in the circuit in response to the enable signal being placed in an assertion state, and wherein the first, second, and third transistors are placed in a predetermined non-conduction state to deactivate the capacitor cell in the circuit by the enable signal being placed in a non-assertion state. The circuit includes a first bias circuit system coupled to a second current terminal of the first transistor and a second current terminal of the second transistor. The first bias circuit system is configured to bias the second current terminals of the first transistor and the second current terminal of the second transistor at a bias voltage when the enable signal is in a non-assertional state. The enable signal ranges between a low supply voltage at the low supply terminal and a high supply voltage at the high supply voltage terminal, wherein the bias voltage is a voltage less than the high supply voltage but greater than the low supply voltage.

[0005] In another embodiment, the capacitor unit further includes a second bias circuit system configured to bias the second current terminal of the first transistor and the second current terminal of the second transistor to one of the low supply voltage or the high supply voltage when the enable signal is in an assertion state.

[0006] In another embodiment, the second bias circuit system includes a fourth transistor having a first current terminal coupled in a path to the second current terminal of the first transistor, the fourth transistor being in a predetermined conduction state when the enable signal is in an assertion state to bias the second current terminal of the first transistor to one of the low supply voltage or the high supply voltage.

[0007] In another embodiment, when the enable signal is in an assertion state, the second current terminal of the fourth transistor is biased to one of the low power supply voltage or the high power supply voltage; when the enable signal is in a non-assertion state, the second current terminal of the fourth transistor is biased to the other of the low power supply voltage or the high power supply voltage.

[0008] In another embodiment, the second current terminal of the fourth transistor is coupled via the fifth transistor of the inverter of the capacitor cell in a path leading to the low power supply voltage terminal, for biasing the second current terminal of the fourth transistor at the low power supply voltage when the fifth transistor is in a predetermined conduction state, and the second current terminal of the fourth transistor is coupled via the sixth transistor of the inverter in a path leading to the high power supply voltage terminal, for biasing the second current terminal at the high power supply voltage when the sixth transistor is in a predetermined conduction state.

[0009] In another embodiment, the output of the inverter is coupled to the input of the second inverter, wherein the enable signal is provided by the output of the second inverter.

[0010] In another embodiment, the second bias circuit system includes a fifth transistor having a first current terminal coupled in a path to the second current terminal of the second transistor, wherein the fifth transistor is in a predetermined conduction state when the enable signal is in an assertion state to bias the second current terminal of the second transistor to one of the low supply voltage or the high supply voltage.

[0011] In another embodiment, the first current terminal of the fourth transistor is coupled in a path leading to the second current terminal of the second transistor.

[0012] In another embodiment, the circuit includes an oscillator. The first circuit node is characterized as a first output node providing a first oscillator signal. The second circuit node is characterized as a second output node providing a second oscillator signal. The second oscillator signal is complementary to the first oscillator signal. The oscillator further includes: a positive feedback circuit including a first input coupled to the first output node and a second input coupled to the second output node; an inductor circuit coupled in a path between the first and second output nodes; a plurality of capacitor cells including the capacitor cells, wherein each of the plurality of capacitor cells includes a configuration of three enable transistors similar to the configuration of the first, second, and third transistors, wherein each capacitor cell includes a first capacitor circuit coupled in a path leading to the first output node and a second capacitor circuit coupled in a path leading to the second output node; and a controller including a plurality of controller outputs, wherein each controller output controls a corresponding enable signal of a corresponding capacitor cell among the plurality of capacitor cells to selectively enable the corresponding capacitor cell during operation of the oscillator by placing the corresponding enable signal in an assertion state to place the three enable transistors of the corresponding capacitor cell in a predetermined conduction state.

[0013] In another embodiment, during operation, the controller asserts selective capacitor cells among the plurality of capacitor cells to control the effective capacitance of the oscillator, thereby controlling the frequencies of the first oscillator signal and the second oscillator signal.

[0014] In another embodiment, the bias voltage is greater than or equal to half the difference between the high supply voltage and the low supply voltage.

[0015] In another embodiment, the first bias circuit system includes a switch coupled in a path between a bias voltage source and a second current terminal of the first transistor, wherein the switch closes when the enable signal is not asserted to bias the second current terminal of the first transistor at the bias voltage.

[0016] In another embodiment, the switch is coupled in the path between the bias voltage source and the second current terminal of the second transistor, wherein when the enable signal is not asserted, the switch closes to bias the second current terminal of the second transistor to the bias voltage.

[0017] In another embodiment, the capacitor cell includes a second switch coupled in a path between a reference bias source and the second current terminal of the second transistor, wherein the second switch closes when the enable signal is not asserted to bias the second current terminal of the second transistor at the bias voltage.

[0018] In another embodiment, the enable signal is at the high power supply voltage in the assertion state and at the low power supply voltage in the non-assertion state.

[0019] In another embodiment, the second current terminal of the second transistor is connected to the second current terminal of the first transistor.

[0020] In another embodiment, the first transistor, the second transistor, and the third transistor are characterized as N-type transistors.

[0021] In another embodiment, a method for operating a circuit including a first circuit node and a second circuit node, wherein the circuit includes a capacitor cell, the capacitor cell including a first capacitor circuit, a second capacitor circuit, a first cell node, a second cell node, a first transistor, a second transistor, and a third transistor, the first capacitor circuit being located in a path between the first circuit node and the first cell node, the second capacitor circuit being located in a path between the second circuit node and the second cell node, the third transistor including a first current terminal coupled in a path leading to the first cell node and a second current terminal coupled in a path leading to the second cell node, the first transistor including a first current terminal coupled in a path leading to the first cell node, and the second transistor including a first current terminal coupled in a path leading to the second cell node. The method includes operating the capacitor cell in an enabled state, wherein operating the capacitor cell in the enabled state includes asserting an enable signal at a first voltage to place the first transistor, the second transistor, and the third transistor in a predetermined conduction state. The method includes operating the capacitor cell in a deactivated state, wherein operating the capacitor cell in the deactivated state includes placing the enable signal in a non-assertive state at a second voltage to place the first transistor, the second transistor, and the third transistor in a predetermined non-conductive state; and includes biasing the second current terminal of the first transistor and the second current terminal of the second transistor at a bias voltage, wherein the bias voltage is between the first voltage and the second voltage.

[0022] In another embodiment, operating the capacitor cell in the enabled state includes biasing the second current terminal of the first transistor and the second current terminal at the second transistor to the second voltage, wherein the second voltage is lower than the first voltage and lower than the bias voltage.

[0023] In another embodiment, the circuit includes an oscillator, and the method further includes: generating a first oscillator signal at a first circuit node at a first frequency and generating a second oscillator signal at a second circuit node, wherein generating at the first frequency includes operating the capacitor cell in the enabled state; and generating the first oscillator signal at the first circuit node and generating the second oscillator signal at the second oscillator node at a second frequency different from the first frequency, wherein generating at the second frequency includes operating the capacitor cell in the disabled state. Attached Figure Description

[0024] The invention can be better understood by referring to the accompanying drawings, which will make the many objectives, features and advantages of the invention clear to those skilled in the art.

[0025] Figure 1 This is a circuit diagram of a programmable oscillator according to some embodiments of the present invention.

[0026] Figure 2 This is a circuit diagram of a capacitor cell according to some embodiments of the present invention.

[0027] Figure 3 This is a circuit diagram of a capacitor cell according to some embodiments of the present invention.

[0028] Unless otherwise specified, the same reference numerals are used in different diagrams to indicate the same items. The diagrams are not necessarily drawn to scale. Detailed Implementation

[0029] The following is a detailed description of the modes of carrying out the invention. This description is intended to illustrate the invention and should not be considered limiting.

[0030] As disclosed herein, a capacitor cell includes two capacitor circuits and two cell nodes, wherein each capacitor circuit is located in a path between the cell's circuit node and the corresponding cell node. The capacitor cell includes an enable transistor that conducts to enable the cell's capacitance to be utilized by a circuit, such as an oscillator, for frequency control via an enable signal having a voltage range between a low supply voltage and a high supply voltage. One of the enable transistors is coupled between the cell nodes. Each of the two enable transistors includes a first current terminal coupled in the path to the corresponding cell node. When the enable signal is not asserted, second current terminals of the two enable transistors are biased at a bias voltage less than the high supply voltage.

[0031] In some embodiments, biasing the current terminal of the enable transistor at a bias voltage lower than the high supply voltage when the capacitor cell is deactivated can reduce the stress across the enable transistor when the capacitive cell is deactivated. Therefore, enable transistors with thin gate oxide can be implemented faster and provide a better enable / deactivation capacitance ratio for the cell compared to thick gate oxide transistors.

[0032] Figure 1 This is a circuit diagram of a programmable oscillator 101 according to some embodiments of the present invention. The oscillator 101 includes two oscillator output nodes (OSC+ and OSC-) that provide complementary oscillation signals at a certain frequency, determined by the inductance of inductor 105, the effective capacitance provided by capacitor units 107, 109, and 111, and the positive feedback circuit 103 of the oscillator 101. Inductor 105 and capacitor units 107, 109, and 111 form a resonant circuit.

[0033] In the illustrated embodiment, the positive feedback circuit 103 includes a pair of cross-coupled NFETs 117 and 119 and a pair of cross-coupled PFETs 114 and 115 connected to the oscillator output nodes (OSC+ and OSC-). The cross-coupling configuration of circuit 103 causes the complementary oscillator signal to alternate between a high-voltage signal state and a low-voltage signal state at a frequency determined by the inductance of inductor 105, the programmable effective capacitance provided by capacitor units 107, 109, and 111, and the positive feedback circuit 103.

[0034] Oscillator 101 includes a controller 113 that provides enable signals (EN1-ENN) to capacitor cells 107, 109, and 111 to selectively enable the capacitor cells to adjust the capacitance provided by cells 107, 109, and 111, thereby changing the frequency of the oscillation signal. Each of the signals (EN1-ENN) can be set to an assertion state to "enable" its corresponding capacitor cell (107, 109, 111) in the resonant circuit. Each of the signals (EN1-ENN) can be set to a non-assertion state to deactivate its corresponding capacitive cell.

[0035] When enabled, the capacitor cells provide their designed "enable capacitance" to the resonant circuit to set the frequency of the oscillator signal. In some embodiments, each capacitor cell 107, 109, and 111 can be configured to provide a different amount of enable capacitance to the resonant circuit depending on the size and configuration of its capacitor circuit. Accordingly, different combinations of enable signals can be asserted to provide the desired effective capacitance, thereby providing the desired frequency.

[0036] When in a deactivated state, the capacitor cell can contribute some capacitance to the effective capacitance of the resonant circuit due to parasitic capacitance. However, it may be desirable for the cell to provide the lowest possible amount of "deactivated capacitance" in order to provide the oscillator's maximum tuning range.

[0037] In other embodiments, the oscillator may have other configurations, including different arrangements of capacitor cells and inductors and / or different types of positive feedback circuitry. For example, in some embodiments, the positive feedback circuitry will not include PFETs 114 and 115, or it will not include NFETs 117 and 119.

[0038] Figure 2 This is a circuit diagram of capacitor cell 111 according to some embodiments of the present invention. Cell 111 includes two capacitors 201 and 203 for providing capacitance to the resonant circuit of oscillator 101 when enabled. In one embodiment, capacitors 201 and 203 have capacitance in the range of a few nanofarads, but in other embodiments, they may have another capacitance. One end of capacitor 201 is connected to node OSC+, and the other end is connected to cell node CN+. One end of capacitor 203 is connected to node OSC-, and the other end is connected to cell node CN-. Capacitors 201 and 203 may be implemented by one or more edge capacitors, MIM capacitors, trench capacitors, MOS capacitors, other types of capacitors, or combinations thereof.

[0039] One current terminal of NFET 205 is connected to node CN+, and the other current terminal is connected to CN-. The drain of NFET 207 is connected to node CN+. The source of NFET 207 is connected to switch 213, which is connected to the source of pull-down NFET 209 and the drain of NFET 211. The drain of NFET 209 is connected to node CN-. The source of NFET 211 is connected to the drains of PFET 217 and NFET 219 of inverter 215. The gates of NFETs 205, 207, 209, and 211 are connected to the output of inverter 221 to receive an enable signal EN1BUF, which is logically connected to the signal from controller 113 (see [link to controller 113]). Figure 1 The enable signal EN1 is the same as and controlled by the enable signal EN1. The enable signal EN1 is received at the gates of NFET 219 and PFET 217 of inverter 215. The output of inverter 215 generates an enable signal EN1B, which is input to inverter 221. The body bias terminals of NFETs 205, 207, 209 and 211 are connected to the VSS terminal, but in other embodiments they may be connected to other voltages. Inverter 215 and NFET 211 are used as a bias circuit system to bias the sources of NFETs 207 and 209 at VSS when cell 111 is enabled.

[0040] Switch 213 is connected to receive voltage VBIAS from voltage source 214 at one end. Switch 213 is controlled by an enable signal EN1B, which closes when EN1B is high (VDD). Switch 213 and voltage source 214 serve as a bias circuit system to bias the sources of NFETs 207 and 209 at voltage VBIAS when cell 111 is deactivated. Switch 213 can be implemented using an NFET, PFET, another type of transistor, transmission gate, or other type of switch. If switch 213 is implemented using a PFET (not shown), the gate of the PFET will receive a signal inverted from EN1B. The source of PFET 217 and the high-voltage supply terminal of inverter 221 are connected to the VDD supply terminal. The source of NFET 219 and the low-voltage supply terminal of inverter 221 are connected to the VSS terminal. In one embodiment, VDD is 0.8 volts and VSS is ground, but in other embodiments, these voltages can be other values, including VSS being negative. VBIAS is less than VDD but greater than VSS.

[0041] During operation, to enable unit 111, controller 113 asserts the EN1 signal by placing it in a high-voltage state (at VDD). In this state, EN1B is at VSS, and EN1BUF is at a high voltage, i.e., the assertion state of VDD. With the enable signal EN1BUF in the assertion state, NFETs 205, 207, 209, and 211 are placed in an intentionally conducted state, such that nodes CN+ and CN- are biased at VSS (via the paths of conducting NFETs 207, 211, and 219, and via the conduction paths of NFETs 209, 211, and 219, respectively) and connected together via conducting NFET 205. Therefore, when enabled during operation, the capacitance seen between nodes OSC+ and OSC- is a series combination of the capacitance values ​​of capacitors 201 and 203. This effective capacitance of unit 111 is added in parallel with the effective capacitance of oscillator 101.

[0042] In some cases, in response to a change in the desired frequency, controller 113 disables unit 111 by setting the enable signal EN1 to a non-assertive voltage state in VSS. This causes signal EN1B to go to a high voltage state in VDD, and enable signal EN1BUF to go to a non-assertive voltage state in VSS, thereby placing NFETs 205, 207, 209, and 211 in an intentionally non-conducting state. Switch 213 is closed because EN1B is in VDD (e.g., if switch 213 is implemented with an NFET). Under this condition, the sources of NFETs 207 and 209 are biased at VBIAS. The source of NFET 211 is biased at VDD via conducting PFET 217.

[0043] Because there is no direct bias at nodes CN+ and CN- in the off-state, the voltages at nodes CN+ and CN- are affected by the leakage currents through NFETs 207 and 209, respectively, and by the oscillation voltages at nodes OSC+ and OSC-, respectively. Even when NFETs 207 and 209 are in their intended non-conductive state, the leakage currents through NFETs 207 and 209 will still contribute to raising the voltages at nodes CN+ and CN- to VBIAS. Nodes OSC+ and OSC-, having reached their positive peak voltages, can raise the voltages at nodes CN+ and CN-, respectively, and even higher during portions of the oscillation clock cycle. For example, as the voltage at node OSC+ moves toward its positive peak voltage, the voltage at node CN+ will also follow and move toward a voltage higher than VBIAS, such as VBIAS plus the peak voltage of OSC+ (e.g., 0.4 V in some embodiments). Similarly, because oscillator 101 is symmetrical, when the voltage at node OSC- moves toward its positive peak voltage, the voltage at node CN- will also follow and increase.

[0044] The voltage of VBIAS is set below that of VDD in order to limit the voltage of nodes CN+ and CN- so that they do not exceed the levels that could damage NFETs 205, 207 and 209 when cell 111 is deactivated.

[0045] If the source biases of NFETs 207 and 209 are at VDD, the voltages at nodes CN+ and CN- will be higher (VDD plus the peak voltage of node OSC+ or node OSC-) when nodes OSC+ and OSC- reach their positive peak voltages, respectively. During such peak times, nodes CN+ and CN- may exceed voltages that could cause the reliability limits of the gate-to-drain (VGD) voltages of NFETs 207 and 209, as well as the gate-to-drain (VGD) and gate-to-source (VGS) voltages of NFET 205, to be exceeded when the source biases of NFETs 207 and 209 are at VDD.

[0046] Therefore, in the embodiments described herein, when cell 111 is deactivated, the sources of enabled pull-down NFETs 207 and 209 are biased at voltages below VDD, such that during the positive peaks of nodes OSC+ and OSC-, the voltages at nodes CN+ and CN- do not exceed the reliability limits of the gate-to-drain voltages of NFETs 207 and 209, and the gate-to-drain and gate-to-source voltages of NFET 205, respectively.

[0047] In some embodiments, the value of VBIAS must be high enough that NFETs 205, 207, and 209 do not enter an intentionally conductive state. For example, VBIAS - VSS must be higher than the voltage threshold of NFETs 205, 207, and 209 (e.g., 0.35 volts in some embodiments). Furthermore, VBIAS must be high enough that NFET 205 does not become intentionally conductive when nodes OSC+ and OSC- reach their minimum voltages. In some embodiments, VBIAS is set to a voltage less than VDD but greater than or equal to ½(VDD - VSS), where VSS equals 0 volts, corresponding to VDD > VBIAS. > VDD / 2.

[0048] In some embodiments, the other units 107 and 109 of the oscillator 101 have the same Figure 2 The configuration is similar to that of unit 111. In some of these embodiments, other units may have different capacitance values ​​for their capacitors, which are similar to capacitors 201 and 203. However, in other embodiments, the units may all have the same capacitance value.

[0049] Figure 3This is a circuit diagram of capacitor cell 300 according to some embodiments. Capacitor cell 300 is similar to... Figure 2 Unit 111, wherein capacitors 301 and 303, NFETs 305, 307 and 309, and inverters 315 and 321 are respectively similar to capacitors 202 and 203, NFETs 205, 207 and 209, and inverters 215 and 221. Unit 300 and Figure 2 The difference between cell 111 and cell 111 is that its bias circuitry includes two NFETs 311 and 312 (instead of...). Figure 2 NFET 312 is used to bias the source of NFET 307, and NFET 311 is used to bias the source of NFET 309 at VSS when cell 300 is enabled. The sources of NFETs 312 and 311 are connected to the output of inverter 315. The gates of NFETs 312 and 311 are connected to the output of inverter 321. NFETs 312 and 311 are intentionally conducted when the EN1BUF enable signal goes to a high voltage state.

[0050] Additionally, unit 300 includes two switches 313 and 310 connected to voltage source 314, used to bias the sources of NFETs 307 and 309, respectively, when the EN1B enable signal is at a high voltage value indicating that unit 300 will be deactivated. Switches 313 and 310 can be implemented using NFETs, PFETs, other types of transistors, transmission gates, or other types of switches.

[0051] In other embodiments, the oscillator and capacitor units described herein may include other circuit systems, have other configurations, and / or operate in different ways. For example, in Figure 2 In this configuration, the gates of NFETs 205, 207, 209, and 211 can be configured to receive an EN1 signal from controller 113, or a logically equivalent signal. As another example, the switchable capacitor cell can be implemented using PFET enable transistors (not shown) comprising two enable PFETs in a pull-up configuration to bias nodes CN+ and CN- at VDD when enabled and at a VBIAS voltage when disabled, wherein VBIAS is greater than VSS and less than VDD.

[0052] Besides oscillators, the switchable capacitor units (e.g., 111) described herein can also be used in other circuits such as tuning circuits, filters, amplifiers, or integrators (not shown) to provide variable effective capacitance. For example, in amplifiers, they can be used for frequency tuning, impedance tuning, or gain control. Such capacitor units can be used in various types of systems, such as computers, mobile phones, automotive electronics, wearable devices, IoT systems, industrial systems, embedded systems, or communication systems. Switchable capacitor units can be particularly advantageous when used in programmable capacitor banks subjected to high voltage signals.

[0053] As used herein, one item is "coupled" to another item by connecting to it, or by being coupled in a current or signal path via at least one other item. For example, in Figure 2 In this circuit, the output of inverter 215 is coupled to the input of inverter 221 via a connection to the input of inverter 221. The output of inverter 215 is coupled to the source of NFETs 207 and 209 via NFET 211. The drain and source are the current terminals of the FETs. As used herein, a “node” of a circuit is a conductive region between two or more circuit devices and is designed to have substantially the same potential along said region (with at most only a negligible voltage drop). A “deliberately conductive state” of a transistor is: in response to a voltage or current at the control terminal of the transistor having a value that predetermines the transistor to be conductive (e.g., when the gate-to-source voltage of the NFET exceeds its threshold voltage), the transistor is in a conductive state. Leakage current through the transistor does not mean that the transistor is in a deliberately conductive state, in which case the voltage or current at the control terminal is not at a value that would put the transistor in a conductive state. Similarly, when the voltage or current at the control terminal of the transistor has a value that predetermines the transistor to be non-conductive, the transistor is in a deliberately non-conductive state.

[0054] As disclosed herein, providing a capacitor cell that includes a pull-down enable transistor (or, in some embodiments, a pull-up transistor) biased at a voltage less than VDD when the cell is deactivated can enable a cell such that the voltage of the enable transistor does not exceed safe operating region limits when the oscillator node is at a positive peak voltage. This may be particularly important when the internal nodes of the cell connected to the capacitor are not directly biased during deactivation to provide lower capacitance during deactivation to improve the enable / deactivation capacitance ratio.

[0055] While specific embodiments of the invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, other changes and modifications may be made without departing from the invention and its broader aspects, and therefore the appended claims are intended to cover all such changes and modifications within the true spirit and scope of the invention.

Claims

1. A circuit, characterized in that, include: A capacitor unit, comprising: A first capacitor circuit is coupled between the first circuit node and the first unit node of the capacitor unit. A second capacitor circuit is coupled between the second circuit node and the second unit node of the capacitor unit. A first transistor includes a first current terminal coupled in a path leading to the first cell node; The second transistor includes a first current terminal coupled in the path leading to the second cell node; The third transistor includes a first current terminal coupled in a path leading to the first cell node and a second current terminal coupled in a path leading to the second cell node. The first transistor, the second transistor, and the third transistor each include a control terminal for receiving an enable signal, wherein the first transistor, the second transistor, and the third transistor are placed in a predetermined conduction state in response to the enable signal being placed in an assertion state to enable the capacitor cell in the circuit, wherein the first transistor, the second transistor, and the third transistor are placed in a predetermined nonconducting state by the enable signal being placed in a non-assertion state to disable the capacitor cell in the circuit. A first bias circuit system coupled to a second current terminal of the first transistor and a second current terminal of the second transistor is configured to bias the second current terminal of the first transistor and the second current terminal of the second transistor at a bias voltage when the enable signal is in a non-assertional state. The enable signal range is between the low power supply voltage at the low power supply terminal and the high power supply voltage at the high power supply terminal, wherein the bias voltage is a voltage less than the high power supply voltage but greater than the low power supply voltage.

2. The circuit according to claim 1, characterized in that, The capacitor unit further includes a second bias circuit system configured to bias the second current terminal of the first transistor and the second current terminal of the second transistor to one of the low supply voltage or the high supply voltage when the enable signal is in an assertion state.

3. The circuit according to claim 2, characterized in that, The second bias circuit system includes a fourth transistor, the fourth transistor including a first current terminal coupled in a path to the second current terminal of the first transistor, the fourth transistor being in a predetermined conduction state when the enable signal is in an assertion state to bias the second current terminal of the first transistor to one of the low supply voltage or the high supply voltage.

4. The circuit according to claim 3, characterized in that, When the enable signal is in an assertion state, the second current terminal of the fourth transistor is biased to one of the low power supply voltage or the high power supply voltage; when the enable signal is in a non-assertion state, the second current terminal of the fourth transistor is biased to the other of the low power supply voltage or the high power supply voltage.

5. The circuit according to claim 4, characterized in that: The second current terminal of the fourth transistor is coupled to the path leading to the low power supply voltage terminal via the fifth transistor of the inverter of the capacitor unit, for biasing the second current terminal of the fourth transistor at the low power supply voltage when the fifth transistor is in a predetermined conduction state. The second current terminal of the fourth transistor is coupled via the sixth transistor of the inverter in a path leading to the high power supply voltage terminal, for biasing the second current terminal at the high power supply voltage when the sixth transistor is in a predetermined conduction state.

6. The circuit according to claim 3, characterized in that, The second bias circuit system includes a fifth transistor, the fifth transistor including a first current terminal coupled in a path to the second current terminal of the second transistor, the fifth transistor being in a predetermined conduction state when the enable signal is in an assertion state to bias the second current terminal of the second transistor to one of the low supply voltage or the high supply voltage.

7. The circuit according to claim 1, characterized in that, Additionally, it includes an oscillator, in which: The first circuit node is characterized as a first output node that provides a first oscillator signal; The second circuit node is characterized as a second output node that provides a second oscillator signal, which is complementary to the first oscillator signal; The oscillator further includes: A positive feedback circuit, comprising a first input coupled to the first output node and a second input coupled to the second output node; An inductor circuit coupled in the path between the first output node and the second output node; A plurality of capacitor units, comprising the capacitor units, wherein each of the plurality of capacitor units includes a configuration of three enable transistors similar to the configuration of the first transistor, the second transistor, and the third transistor, wherein each capacitor unit includes a first capacitor circuit coupled in a path leading to the first output node and a second capacitor circuit coupled in a path leading to the second output node. The controller includes multiple controller outputs, each controller output controlling a corresponding enable signal of a corresponding capacitor cell among the multiple capacitor cells to selectively enable the corresponding capacitor cell during operation of the oscillator by placing the corresponding enable signal in an assertion state to place the three enable transistors of the corresponding capacitor cell in a predetermined conduction state.

8. The circuit according to claim 1, characterized in that, The first bias circuit system includes a switch coupled in a path between a bias voltage source and a second current terminal of the first transistor, wherein when the enable signal is not asserted, the switch closes to bias the second current terminal of the first transistor at the bias voltage.

9. A method for operating a circuit including a first circuit node and a second circuit node, characterized in that, The circuit includes a capacitor unit, which includes a first capacitor circuit, a second capacitor circuit, a first unit node, a second unit node, a first transistor, a second transistor, and a third transistor. The first capacitor circuit is located in a path between the first circuit node and the first unit node, and the second capacitor circuit is located in a path between the second circuit node and the second unit node. The third transistor includes a first current terminal coupled to the path leading to the first unit node and a second current terminal coupled to the path leading to the second unit node. The first transistor includes a first current terminal coupled to the path leading to the first unit node, and the second transistor includes a first current terminal coupled to the path leading to the second unit node. The method includes: Operating the capacitor unit in the enabled state, wherein operating the capacitor unit in the enabled state includes: An assertion signal is made at a first voltage to place the first transistor, the second transistor, and the third transistor into a predetermined conduction state; Operating the capacitor unit in a deactivated state, wherein operating the capacitor unit in the deactivated state includes: At the second voltage, the enable signal is placed in a non-assertive state to place the first transistor, the second transistor, and the third transistor in a predetermined non-conductive state; The second current terminal of the first transistor and the second current terminal of the second transistor are biased at a bias voltage, wherein the bias voltage is between the first voltage and the second voltage.

10. The method according to claim 9, characterized in that, The circuit includes an oscillator, and the method further includes: A first oscillator signal is generated at the first circuit node at a first frequency and a second oscillator signal is generated at the second circuit node, wherein generating at the first frequency includes operating the capacitor cell in the enabled state; The first oscillator signal is generated at the first circuit node at a second frequency different from the first frequency, and the second oscillator signal is generated at the second oscillator node, wherein generating at the second frequency includes operating the capacitor cell in the deactivated state.

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