Periodically tunable voltage-controlled oscillator based on JEFT varactor region with large duty cycle

Abstract

The application discloses a JEFT variable resistance area-based large-duty-cycle period-adjustable voltage-controlled oscillator, a power supply Vcc circuit sequentially charges a capacitor C3 through a resistor R1, a capacitor C1, a field effect transistor VT1, a capacitor C2, a negative electrode of the capacitor C3 is connected with a working ground, a positive electrode of a direct current control voltage Ui is connected with an S pole of the VT1, a negative electrode of the direct current Ui voltage is connected with a G pole of the VT1, a NE555 time base circuit is composed of an integrated circuit IC1 and peripheral circuits, the resistor R2 constitutes an oscillation capacitor discharge circuit, the positive electrode of the capacitor C3 is connected with a 7 pin of the IC1 through the resistor R2, and the positive electrode of the capacitor C3 is connected with a 2 pin and a 6 pin of the IC1 simultaneously; a transistor VT2 and a resistor R3 constitute a voltage follower, the direct current power supply Vcc circuit sequentially connects the working ground through a C-E pole of the transistor VT2 and the resistor R3, a base pole of the VT2 is connected with a 3 pin of the IC1, and an emitter pole of the VT2 outputs a voltage-controlled oscillation signal Uo.

Description

Technical Field

[0001] This invention relates to a voltage-controlled oscillator with a large duty cycle and adjustable period. This is a novel design for implementing PWM based on a 555 timer circuit, which has a simple structure and a novel approach. Background Technology

[0002] PWM generally refers to pulse width modulation, also known as duty cycle modulation. A commonly used PWM circuit is essentially a square wave circuit with a fixed period and an adjustable duty cycle. Its basic working principle is to compare a sawtooth wave signal with a DC control voltage. When the DC control voltage changes, the duty cycle of the output pulse changes accordingly.

[0003] Since the oscillation frequency of the multivibrator composed of the NE555 timer is less affected by changes in power supply voltage and external temperature, in the absence of a dedicated PWM circuit, based on the different threshold voltages (1 / 3Vcc and 2 / 3Vcc) of the 555 timer circuit and the different charging and discharging paths of the timer circuit, the duty cycle of the output pulse signal can be adjusted by directly changing the RC time constant τ=RC of the charging and discharging circuit, such as by changing the resistance or capacitance value.

[0004] Strictly speaking, this is not the requirement we need for a DC voltage to control the duty cycle of the pulse output. However, based on the 555 timer circuit, some DC voltage control pulse duty cycle circuits can also be designed. The common method used in the industry is: the 555 timer circuit is first combined with external resistor and capacitor components to form an astable multivibrator. A DC control voltage is compared with the sawtooth wave signal generated during charging and discharging. The duty cycle of the pulse waveform output by the comparator can be adjusted within a large range.

[0005] However, the common DC voltage control pulse duty cycle circuit structure based on NE555 is relatively complex, with a large number of components, resulting in high cost and low cost-effectiveness.

[0006] A field-effect transistor (FET) has three operating regions: the variable resistance region, the constant current region, and the pinch-off region. When the FET is operating in the variable resistance region, the curve in this region is approximately a curve with different slopes.

[0007] When U G-S When the slope of the line is determined, it is also uniquely determined. The reciprocal of the slope of the line is the equivalent resistance between D and S. Therefore, in this region, the slope can be changed by altering U. GS The magnitude of the voltage, i.e. the voltage control method, is used to change the value of the drain-source equivalent resistance, hence it is called the variable resistance region.

[0008] If the drain and source terminals of a field-effect transistor (FET) are connected in series in the charging circuit of a 555 multivibrator, and a DC control voltage Ui is applied between the gate (G) and source (S) of the FET, i.e., U... GS If the voltage Ui changes, the equivalent resistance between D and S will change accordingly, and the time parameter τ of the charging circuit will also change at the same time. Ultimately, the duty cycle of the output pulse of the 555 multivibrator will change accordingly.

[0009] This is another novel design for implementing PWM based on a 555 timer circuit, with a simple structure and innovative approach. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a voltage-controlled oscillator that is simple in structure, low in cost, reliable in use, and can output a large duty cycle with an adjustable period.

[0011] To achieve the above objectives, this invention provides a voltage-controlled oscillator with a large duty cycle and adjustable period based on the JEFT variable resistance region. It includes a DC control voltage Ui circuit, an oscillation capacitor circuit, an oscillation capacitor charging circuit, an oscillation capacitor discharging circuit, a coupling capacitor circuit, an NE555 timer circuit, a voltage follower circuit, and a DC power supply Vcc circuit. The coupling capacitor circuit consists of electrolytic capacitors C1 and C2. A resistor R1, electrolytic capacitor C1, a field-effect transistor VT1, and electrolytic capacitor C2 constitute the oscillation capacitor charging circuit. The DC power supply Vcc circuit charges the oscillation capacitor circuit, i.e., electrolytic capacitor C3, sequentially through resistor R1, forward electrolytic capacitor C1, the drain and source terminals of field-effect transistor VT1, and forward electrolytic capacitor C2. The negative terminal of capacitor C3 is connected to the working ground; the positive terminal of the DC control voltage Ui circuit is connected to the source (S) terminal of the field-effect transistor VT1, and the negative terminal of the DC Ui voltage is connected to the gate (G) terminal of VT1; the NE555 timer circuit consists of integrated circuit IC1 and peripheral circuits, resistor R2 constitutes the oscillation capacitor discharge circuit, the positive terminal of electrolytic capacitor C3 is connected to pin 7 of IC1 through resistor R2, and the positive terminal of electrolytic capacitor C3 is also connected to pins 2 and 6 of IC1; transistor VT2 and resistor R3 constitute the voltage follower circuit, the DC power supply Vcc circuit is connected to the working ground sequentially through the collector (CE) terminal of transistor VT2 and resistor R3, the base of transistor VT2 is connected to pin 3 of IC1, and the emitter of transistor VT2 outputs the voltage-controlled oscillation signal Uo.

[0012] The field-effect transistor in the oscillating capacitor charging circuit can only be an N-channel junction field-effect transistor.

[0013] In the NE555 timer circuit, pin 4 of integrated circuit IC1 is connected to the DC power supply Vcc circuit, and pin 5 of IC1 is connected to the working ground through capacitor C4.

[0014] In the aforementioned oscillation capacitor circuit, when the frequency of the voltage-controlled oscillator is low, the oscillation capacitor C3 can be an electrolytic capacitor. When the frequency of the voltage-controlled oscillator is high, the oscillation capacitor C3 must be a non-polar ceramic or film capacitor, preferably a ceramic capacitor. Furthermore, the smaller the capacitance of C3, the higher the oscillation frequency; the larger the capacitance of C3, the lower the oscillation frequency.

[0015] In the coupling capacitor circuit, the capacitance of electrolytic capacitors C1 and C2 should preferably be 10 times that of capacitor C3. Attached Figure Description

[0016] Appendix Figure 1 Appendix Figure 2 Appendix Figure 3 Appendix Figure 4 Appendix Figure 5 This document is provided to provide a further understanding of the invention and forms part of this application. Figure 1 It is a traditional voltage-controlled pulse duty cycle circuit based on a constant current source; (Attached) Figure 2 This is the output characteristic curve of a field-effect transistor; attached. Figure 3 This is a schematic diagram of a voltage-controlled oscillator with a large duty cycle and adjustable period based on JEFT; (Attached) Figure 4 This is a schematic diagram of a voltage-controlled oscillator with a large duty cycle and adjustable period; (Attached) Figure 5 This is the transfer characteristic curve of a channel junction field-effect transistor (JFET). Detailed Implementation

[0017] The embodiments of the present invention are further described below with reference to the accompanying drawings.

[0018] Traditional voltage control pulse duty cycle circuit based on 555 timer circuit First, we will briefly introduce a traditional voltage-controlled pulse duty cycle circuit to understand its working principle, explain its advantages, and demonstrate its shortcomings, thereby highlighting the advantages of our design: novel working principle, simple structure, low cost, and high cost-effectiveness.

[0019] In automatic control systems, there are situations where voltage variations are needed to control the duty cycle of pulse waves, such as... Figure 1 As shown.

[0020] Figure 1 The circuit mainly consists of a timer chip (IC1, model NE555) and an astable multivibrator composed of resistor R1, timing capacitor C1, and transistor T1. The charging circuit is powered by power supply V. CC → Resistor R1 → Transistor T1 (saturated and conducting) → Capacitor C1. The discharge circuit consists of capacitor C1 → discharge transistor T inside the 555 timer → working ground.

[0021] Transistor T1, diodes D1 and D2 form a constant current source circuit. T1 serves as the constant current source for charging timing capacitor C1, ensuring good linearity in the sawtooth waveform of C1's charging process. Operational amplifier IC2 is used as a comparator. Since the voltages (low and high threshold voltages) at the inverting input of IC2, i.e., pins 2 and 6 of IC1, vary between 1 / 3Vcc and 2 / 3Vcc respectively, and the control voltage Ui is connected to the non-inverting input of op-amp IC2, when the control voltage Ui also varies between 1 / 3Vcc and 2 / 3Vcc, the duty cycle of the pulse waveform output by IC2 can be adjusted within a range of approximately 0% to 100%.

[0022] For example, when the voltage Ui equals 2 / 3U cc At this time, the duty cycle of the IC2 output pulse is up to 100%; when the Ui voltage is equal to 1 / 3U cc At that time, the duty cycle of the IC2 output pulse is at its lowest point of 0, that is, closer to 2 / 3U. cc The higher the duty cycle, the closer it is to 1 / 3U. cc The lower the duty cycle.

[0023] The advantage of this duty cycle adjustment circuit is that the pulse frequency can remain unchanged while the output pulse duty cycle changes. The disadvantage is that the circuit uses two integrated circuits, which makes it slightly complex, but the working principle is easy to understand and it is a relatively mature solution.

[0024] A voltage-controlled oscillator with a large duty cycle and adjustable period based on JEFT. Figure 1 The innovation of the voltage-controlled pulse width circuit is mainly to compare the charging and discharging sawtooth wave signal controlled by the constant current source with the external DC control voltage to achieve voltage-controlled pulse width control. The external DC voltage does not directly control the charging and discharging current. If the external DC voltage is applied to the charging and discharging circuit, it is also a pulse width control design idea.

[0025] A field-effect transistor (FET) has three operating regions: the variable resistance region, the constant current region, and the pinch-off region. When the FET operates in the variable resistance region, its curve approximates curves with different slopes, such as... Figure 2 As shown.

[0026] When U G-S When the slope of the line is determined, it is also uniquely determined. The reciprocal of the slope of the line is the equivalent resistance between D and S. Therefore, in this region, the slope can be changed by altering U. GS The magnitude of the voltage, i.e. the voltage control method, is used to change the value of the drain-source equivalent resistance, hence it is called the variable resistance region.

[0027] If the drain and source terminals of a field-effect transistor (FET) are connected in series in the charging circuit of a 555 multivibrator, and a DC control voltage Ui is applied between the gate (G) and source (S) of the FET, i.e., U...GS If the voltage Ui changes, the equivalent resistance between D and S will change accordingly, and the time parameter τ of the charging circuit will also change at the same time. Ultimately, the duty cycle of the output pulse of the 555 multivibrator will change accordingly.

[0028] This is another novel design for implementing PWM based on a 555 timer circuit. The specific circuit is as follows: Figure 3 As shown. It includes a DC control voltage Ui circuit, an oscillating capacitor charging circuit, an oscillating capacitor discharging circuit, a coupling capacitor circuit, an NE555 timer circuit, a voltage follower circuit, and a DC power supply Vcc circuit.

[0029] The working principle can be described as follows: a 555 timer circuit, resistors R1 and R2, capacitors C1 to C3, and a field-effect transistor VT1 form a voltage-controlled multivibrator. The field-effect transistor (JFET, junction type) VT1 here acts as a voltage-controlled resistor, and its gate-source voltage V is adjusted by changing... GS It can change the equivalent impedance between the drain (D) and source (S) of VT1.

[0030] The coupling electrolytic capacitors C1 and C2 connected to the drain (D) and source (S) terminals of VT1 are used to prevent the DC voltage from other circuits from affecting VT1. To prevent the coupling capacitors C1 and C2 from affecting the charging and discharging time of the timer circuit, the values ​​of C1 and C2 should preferably be 10 times the value of the timing capacitor C3.

[0031] The advantage of this circuit is that it overcomes the gate-source voltage V of the field-effect transistor. GS The change in VT1 creates a variable resistor Rx with a very wide adjustable range (up to several hundred kΩ), thus achieving a large duty cycle and period variation. In other words, since the discharge path remains unchanged, for... Figure 3 In terms of circuits, as the pulse duty cycle changes, the pulse oscillation frequency also changes accordingly, meaning the period is adjustable.

[0032] The oscillation process is similar to that of a typical multivibrator circuit based on a 555 timer, and can be briefly described as follows: Upon power-up, the voltage across capacitor C1 is "0", lower than 1 / 3 Vcc. Pin 3 outputs "out" at a high level, and emitter follower VT2 outputs "Uo" at a high level. Pin 7 is in a high-impedance state. The power supply Vcc charges the oscillation capacitor C3 through resistors R1, C1, VT1, and C2, gradually increasing the voltage across C3. When the voltage of C3 exceeds 2 / 3 Vcc, the output of pin 3 (out) reverses to "0", and the output of "Uo" becomes "0". Pin 7 is short-circuited to ground through the internal transistor T, and the voltage across C3 discharges to ground through resistor R2 until the voltage of C3 falls below 1 / 3 Vcc. At this point, the output of pin 3 (out) reverses again to "1", and "Uo" becomes "1". This cycle repeats continuously. Figure 3 The circuit achieves self-excited oscillation, and the waveform of the oscillation process is shown in the figure below. Figure 4 As shown.

[0033] As can be seen, the charging channel of the oscillating capacitor C3 is controlled by the input DC control voltage Ugs, which controls the charging current. The larger Ugs is, the larger the charging current and the shorter the time Uo is at the high level. The smaller Ugs is, the smaller the charging current and the longer the time Uo is at the high level. The discharging channel of C3 is fixed by the resistor R2, so the time Uo is at the low level is constant. As mentioned above, as the pulse duty cycle changes, the pulse oscillation frequency will also change, and of course, the period will also change.

[0034] Production and Precautions The choice of MOSFET VT1 is crucial; only an N-channel junction field-effect transistor (JFET) can be selected. When the JFET is in amplification mode, the source-drain resistance (R0) is... DS The resistance value of the drain is relatively small, and the width of the reverse charge region is also small. At this time, the operating point (Q point) of the JFET is in the constant current region, and the signal in the circuit can be amplified. When a voltage is applied between the drain and the source, the reverse charge region widens, and the drain-source resistance (R) increases. DS As the reverse charge region decreases, the signal amplification effect also weakens. When the reverse charge region becomes wide enough, the resistance between the drain and source becomes very large, resulting in a weakening of the amplification effect in the circuit, forming a variable resistance region.

[0035] Therefore, the condition for the variable resistance region of a junction field-effect transistor is the external U. GS Under the influence of voltage, the change in the width of the reverse charge region causes R DS Changes in resistance value.

[0036] Within this area, it is possible to change U GS The size of the drain-source conductive channel resistance is changed by adjusting the value of U. GS The more negative the value, the greater the channel resistance, the more sloping the output characteristic curve (i.e., the smaller the slope), and the greater the equivalent resistance of DS. GS The voltage range is U GS（off） <U GS <0, therefore pay attention to U GS The voltage direction must be correct. If the direction is reversed, the voltage-controlled oscillator will not oscillate. That is, the positive terminal of the DC voltage Ui is connected to the source (S) terminal of VT1, and the negative terminal of the Ui voltage is connected to the gate (G) terminal of VT1. The reason is explained in [link to documentation]. Figure 5 As shown, only U GS An N-channel junction field-effect transistor can only be in the variable resistance region when the DC negative voltage is applied.

[0037] The coupling electrolytic capacitors C1 and C2 connected to the drain (D) and source (S) terminals of VT1 are used to prevent the DC voltage from other circuits from affecting VT1. To prevent the coupling capacitors C1 and C2 from affecting the charging and discharging time of the oscillation circuit, the values ​​of C1 and C2 should be selected to be 10 times the value of the timing capacitor C3.

[0038] The novelty of this design lies in utilizing the variable resistance region characteristic of the field-effect transistor to connect JEFT in series with the charging circuit, so that VT1 forms a variable resistor Rx with a very large adjustable range (up to several hundred kΩ). The charging current varies greatly, thus providing a large duty cycle adjustment range. Since the discharge channel is a fixed resistor (R2, 1kΩ), the discharge current is fixed, and the period of this voltage-controlled oscillator is adjustable.

[0039] The selection of the oscillation capacitor C3 requires special attention. Electrolytic capacitors can be used as oscillation capacitors, but only in low-frequency applications (usually <100Hz). Furthermore, caution must be exercised regarding poor frequency stability, high losses, and the risk of reverse polarity connection. High-frequency oscillations require ceramic or film capacitors. Therefore, if the oscillation frequency of the voltage-controlled oscillator in this design is relatively low, an electrolytic capacitor with a larger capacitance can be used for C3. Figure 3 The parameters shown are as follows: If a higher frequency voltage-controlled oscillator is required, C3 must be a non-polar ceramic or film capacitor, preferably ceramic, and the capacitance is generally small, in the pF or nF range. The smaller the capacitance of C3, the higher the oscillation frequency; the larger the capacitance of C3, the lower the oscillation frequency.

[0040] The above embodiments are only used to illustrate and not limit the technical solutions of the present invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention without departing from the spirit and scope of the present invention. Any modifications or partial substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A voltage-controlled oscillator with a large duty cycle and adjustable period based on the JEFT variable resistance region, characterized in that, The voltage-controlled oscillator includes a DC control voltage Ui circuit, an oscillation capacitor circuit, an oscillation capacitor charging circuit, an oscillation capacitor discharging circuit, a coupling capacitor circuit, an NE555 timer circuit, a voltage follower circuit, and a DC power supply Vcc circuit. The coupling capacitor circuit consists of electrolytic capacitors C1 and C2. Resistor R1, electrolytic capacitor C1, MOSFET VT1, and electrolytic capacitor C2 constitute the oscillation capacitor charging circuit. The DC power supply Vcc circuit charges the oscillation capacitor circuit, i.e., electrolytic capacitor C3, sequentially through resistor R1, forward electrolytic capacitor C1, the drain and source terminals of MOSFET VT1, and forward electrolytic capacitor C2. The negative terminal of electrolytic capacitor C3 is connected to ground. The DC control voltage... The positive terminal of the DC voltage Ui in the Ui circuit is connected to the source (S) terminal of the field-effect transistor VT1, and the negative terminal of the DC voltage Ui is connected to the gate (G) terminal of VT1. The NE555 timer circuit consists of integrated circuit IC1 and peripheral circuits. Resistor R2 constitutes the oscillation capacitor discharge circuit. The positive terminal of electrolytic capacitor C3 is connected to pin 7 of IC1 through resistor R2. The positive terminal of electrolytic capacitor C3 is also connected to pins 2 and 6 of IC1. Transistor VT2 and resistor R3 constitute the voltage follower circuit. The DC power supply Vcc circuit is connected to the working ground through the collector (CE) terminal of transistor VT2 and resistor R3. The base of transistor VT2 is connected to pin 3 of IC1. The emitter of transistor VT2 outputs the voltage-controlled oscillation signal Uo.

2. In the voltage-controlled oscillator with adjustable large duty cycle based on the JEFT variable resistance region according to claim 1, the field-effect transistor in the oscillation capacitor charging circuit can only be an N-channel junction field-effect transistor.

3. In the voltage-controlled oscillator with large duty cycle adjustable based on the JEFT variable resistance region according to claim 1, in the NE555 timer circuit, pin 4 of integrated circuit IC1 is connected to the DC power supply Vcc circuit, and pin 5 of IC1 is connected to the working ground through capacitor C4.

4. The voltage-controlled oscillator with large duty cycle and adjustable period based on the JEFT variable resistance region according to claim 1, wherein the oscillation capacitor circuit, when the frequency of the voltage-controlled oscillator is low, the oscillation capacitor C3 can be an electrolytic capacitor; when the frequency of the voltage-controlled oscillator is high, the oscillation capacitor C3 must be a non-polar ceramic or film capacitor, preferably a ceramic capacitor; furthermore, the smaller the capacitance of C3, the higher the oscillation frequency, and the larger the capacitance of C3, the lower the oscillation frequency.

5. In the voltage-controlled oscillator with large duty cycle and adjustable period based on the JEFT variable resistance region according to claim 1, the capacitance of electrolytic capacitor C1 and electrolytic capacitor C2 in the coupling capacitor circuit should preferably be 10 times the capacitance of capacitor C3.

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