Load impedance circuit for an amplifier

Abstract

The present disclosure relates to a load impedance circuit for an amplifier. The impedance circuit comprises: a center axis; a stage comprising: a pair of components connected to a first node on one side of the center axis, comprising a capacitor and a resistor connected in series; another pair of components connected to a second node on the other side, comprising a capacitor and a resistor connected in series, the pair of components connected via a first central node on the center axis; a first inductor and a second inductor, the first inductor connected to the first node and coupled to a third node, the second inductor connected to the second node and coupled to a fourth node; a third inductor and a fourth inductor, the third inductor between the first node and a voltage rail, the fourth inductor between the second node and the voltage rail.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French patent application number FR2503478, filed on April 3, 2025, entitled “Circuit électronique d'impédance de charge pour un amplificateur”, the entire text of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to electronic amplifiers, and more particularly to electronic load impedance circuits for amplifiers. Background Technology

[0004] An amplifier corresponds to an electronic circuit configured to generate an output signal with an amplitude greater than that of the input signal. An amplifier is known to be designed for a fixed frequency or a fixed frequency range of the input signal. Amplifier components are then defined for that fixed frequency or frequency range.

[0005] A broadband amplifier is configured to amplify the input signal over a relatively wide frequency range.

[0006] Electronic load impedance circuits for amplifiers are typically formed by one or more components, such as resistors or units containing one or more inductors or capacitors, which may be connected in series and / or parallel. However, these electronic circuits for achieving load impedance require components with high values ​​and / or large volumes, for example, for broadband amplifiers, and typically only allow narrowband operation.

[0007] There is a need for electronic load impedance circuits for broadband amplifiers. There is also a need for amplifiers with relatively constant or frequency-increasing output impedance over a relatively wide frequency range. Furthermore, there is a need for electronic load impedance circuits for amplifiers that have small surface area and are easier to manage common-mode. Summary of the Invention

[0008] An embodiment provides an electronic load impedance circuit for an amplifier, comprising: 1) a central axis; 2) a first stage comprising: a first component pair including a capacitor and a resistor connected in series, the first component pair being connected to a first node; a second component pair including a capacitor and a resistor connected in series, the second component pair being connected to a second node, the first component pair being located on a first side of the central axis, the second component pair being located on a second side of the central axis opposite to the first side, the first component pair and the second component pair being connected to each other via a first central connection node belonging to the central axis; a first inductor connected to the first node and a second inductor connected to the second node, the first inductor being further coupled to a third node, the second inductor being further coupled to a fourth node; and 3) a third inductor and a fourth inductor, the third inductor being between the first node and a voltage rail to which a first reference voltage is applied, the fourth inductor being between the second node and a voltage rail to which the first reference voltage is applied.

[0009] According to an embodiment, the first central connection node is connected to a voltage rail to which a first reference voltage is applied.

[0010] According to an embodiment, the first central connection node is connected to a voltage rail that applies a second reference voltage different from the first reference voltage.

[0011] According to an embodiment, the first central connecting node is floating.

[0012] According to the embodiment, the third node and the fourth node form a differential output.

[0013] According to an embodiment, the inductor loop is configured to implement at least two of the first, second, third, and fourth inductors.

[0014] According to an embodiment, one or more of the first, second, third, and fourth inductors are implemented by a figure-eight inductor, an inductor comprising two concentric loops, or an inductor comprising three concentric loops.

[0015] According to an embodiment, the circuit further includes a second stage comprising: a first component pair including a capacitor and a resistor connected in series, the first component pair being connected to a third node; a second component pair including a capacitor and a resistor connected in series, the second component pair being connected to a fourth node, the first component pair being located on a first side of the central axis, the second component pair being located on a second side of the central axis opposite to the first side, the first component pair and the second component pair being connected to each other via a second central connection node belonging to the central axis; and a fifth inductor connected to the third node and a sixth inductor connected to the fourth node, the fifth inductor being further coupled to the fifth node, and the sixth inductor being further coupled to the sixth node.

[0016] According to an embodiment, the second central connection node is connected to the voltage rail to which the first reference voltage is applied.

[0017] According to an embodiment, the second central connection node is connected to a voltage rail to which a second reference voltage is applied.

[0018] According to the embodiment, the second central connecting node is floating.

[0019] According to the embodiment, the fifth node and the sixth node form a differential output.

[0020] According to an embodiment, the first component pair and the second component pair of each stage are arranged symmetrically with respect to the central axis.

[0021] An example provides an amplifier that includes the impedance circuit described above.

[0022] According to an embodiment, the amplifier is configured to receive radio waves having frequencies in the range of 1 GHz to 200 GHz. Attached Figure Description

[0023] Referring to the accompanying drawings, the foregoing features and advantages, as well as other features and advantages, will be described in detail in the remaining disclosure of specific embodiments given by way of illustration and not limitation, wherein:

[0024] Figure 1 A system including an electronic load impedance circuit and an amplifier according to an embodiment of the present disclosure is illustrated schematically;

[0025] Figure 2A An electronic load impedance circuit including a first stage is schematically illustrated according to an embodiment of the present disclosure;

[0026] Figure 2B A two-stage electronic load impedance circuit according to an embodiment of the present disclosure is schematically illustrated.

[0027] Figure 3A An electronic load impedance circuit including a first stage is schematically illustrated according to another embodiment of the present disclosure;

[0028] Figure 3B A two-stage electronic load impedance circuit according to another embodiment of the present disclosure is schematically illustrated;

[0029] Figure 4A An electronic load impedance circuit including a first stage is schematically illustrated according to another embodiment of the present disclosure;

[0030] Figure 4B A two-stage electronic load impedance circuit according to another embodiment of the present disclosure is schematically illustrated;

[0031] Figure 5 It is shown Figure 2A and Figure 3A A graph of the S-parameters ("scattering parameters") of the input adaptation, output adaptation and transmission adaptation of the circuit.

[0032] Figure 6A yes Figure 2A A top view of the circuit is shown, and embodiments according to this disclosure are illustrated. Figure 2A Examples of circuit wiring; and

[0033] Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F yes Figure 4A A top view of the circuit is shown, and embodiments according to this disclosure are illustrated. Figure 4A An example of circuit wiring. Detailed Implementation

[0034] In the various figures, the same elements have been designated with the same reference numerals. In particular, structural and / or functional elements common to different embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0035] For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, amplifiers are known to those skilled in the art, and the wiring between the amplifier and the load impedance circuit is known to those skilled in the art.

[0036] Unless otherwise specified, when referring to two elements being connected to each other, it means a direct connection without any intermediate elements other than conductors, and when referring to two elements being coupled to each other, it means that the two elements can be connected or can be connected by one or more other elements.

[0037] In the following description, references to absolute positional qualifiers, such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative positional qualifiers, such as the terms “top,” “bottom,” “up,” “down,” etc., or directional qualifiers, such as “horizontal,” “vertical,” etc., refer to the orientation of the accompanying drawings, unless otherwise specified.

[0038] Unless otherwise stated, expressions such as “approximately,” “roughly,” “basically,” and “on the order of” indicate plus or minus 10%, preferably plus or minus 5%.

[0039] Figure 1 A system 100 according to an embodiment of the present disclosure is schematically shown, which includes an electronic load impedance circuit 110 (“LOAD”) and an amplifier 120 (“AMPL”).

[0040] Amplifier 120 is configured, for example, to receive an input signal at an input (“IN”) of system 100 and to transmit an output signal from an output (“OUT”) of system 100. The amplitude of the output signal is, for example, greater than the amplitude of the input signal. The amplitude of the input signal is, for example, multiplied by a gain of a circuit defined by amplifier 120.

[0041] According to the embodiment, amplifier 120 is a differential amplifier, that is, an amplifier capable of receiving and amplifying differential signals.

[0042] Amplifier 120 is coupled, for example, to a first reference voltage 122, for example, to ground, and for example, to the output OUT of system 100. Figure 1 In the example, the output OUT is a differential output coupled to one connection node 124 and another connection node 124'. Amplifier 120 is coupled to connection nodes 124 and 124'.

[0043] Amplifier 120 is, for example, a low-noise amplifier, a power amplifier, etc. For example, amplifier 120 includes two transistors, such as two MOS transistors, which are connected in a common-source, common-gate configuration.

[0044] Amplifier 120 is, for example, a radio frequency amplifier, configured to receive radio waves as input.

[0045] According to an embodiment, amplifier 120 is a broadband amplifier, for example configured to amplify the input signal over a frequency range with amplitude greater than or equal to 10 GHz, and for an operating frequency range, for example, from 1 GHz to 200 GHz.

[0046] The load impedance circuit 110 is coupled, for example, to a voltage rail on which a second reference voltage 126 is applied, which is different from the first reference voltage 122, and is, for example, higher than the first reference voltage 122. The load impedance circuit 110 is coupled, for example, to the output OUT of the system 100, for example, via connection nodes 124 and 124'.

[0047] Load impedance circuit 110 is configured, for example, to generate and set output impedance Z11 at connection node 124 and output impedance Z11' at connection node 124'. Output impedances Z11 and Z11' are, for example, substantially similar or considered similar. Output impedances Z11 and Z11' correspond to, for example, the output impedance of amplifier 120.

[0048] According to the embodiment, the output impedances Z11 and Z11' remain constant or substantially unchanged with respect to the frequency of the input signal over at least a portion of the frequency range of the amplifier's input signal.

[0049] Figure 2AAn electronic load impedance circuit 200 including a first stage is schematically shown according to an embodiment of the present disclosure.

[0050] Circuit 200 includes a central axis 202. The central axis 202 is, for example, the axis of symmetry of circuit 200, meaning that circuit 200 includes identical sub-circuits on each side of the central axis 202, and these sub-circuits include identical components arranged symmetrically with respect to the central axis 202. Furthermore, although... Figure 2A This is a simplified diagram, but circuit 200 is, for example, part of an integrated circuit or a printed circuit board (PCB), and the symmetry between the sub-circuits of circuit 200 involves, for example, the physical layout of components.

[0051] Circuit 200 includes a first inductor 204 in a first sub-circuit on a first side of the central axis 202. The first inductor 204 is coupled (preferably connected) to a voltage rail on which a second reference voltage 126 is applied (see reference 126). Figure 1 (Described) and connected to node N1.

[0052] Circuit 200 includes a second inductor 204' in a second sub-circuit on the second side (opposite to the first side) of the central axis 202. The second inductor 204' is coupled (preferably connected) to a voltage rail on which a second reference voltage 126 is applied (see reference). Figure 1 (Described) and connected to node N1'.

[0053] According to an embodiment, the first inductor 204 and the second inductor 204' are arranged symmetrically with respect to the central axis 202. The first inductor 204 and the second inductor 204' have similar inductance values, for example, in the range of 10 picohens (pH) to 1,000 pH.

[0054] exist Figure 2A In the example, circuit 200 includes stage 210. Stage 210 includes: an inductor 212 in a first sub-circuit coupled (preferably connected) between connection node N1 and connection node N2; an inductor 212' in a second sub-circuit coupled (preferably connected) between connection node N1' and connection node N2'; a first component pair in the first sub-circuit, including a resistor 214 and a capacitor 216, connected in series between connection node N1 and a first central connection node C1; and a second component pair in the second sub-circuit, including a resistor 214' and a capacitor 216', connected in series between connection node N1' and the first central connection node C1.

[0055] Connection node N2 corresponds to, for example, reference Figure 1 The described connection node 124, and connection node N2' corresponds to, for example, reference... Figure 1 The described connection node is 124'.

[0056] According to the embodiment, the first central connecting node C1 belongs to the central axis 202.

[0057] According to an embodiment, a single capacitor is configured to realize capacitors 216 and 216' such that the capacitance of the single capacitor is equal to the equivalent capacitance of capacitors 216 and 216' connected in series. Then, a first central connection node C1 is located in the single capacitor, for example, at the center of the single capacitor.

[0058] According to an embodiment, the first component pair and the second component pair are arranged symmetrically with respect to the central axis 202. Resistors 214 and 214' have, for example, similar resistance values, in the range of 10Ω to 500Ω. Capacitors 216 and 216' have, for example, similar capacitance values, in the range of 100 femtofarads (fF) to 5,000 fF.

[0059] According to an embodiment, inductors 212 and 212' are arranged symmetrically with respect to the central axis 202. Inductors 212 and 212' have, for example, similar inductance values, in the range of 10 pH to 2,000 pH. According to an embodiment, inductor 212 has a lower inductance value than inductor 204, and inductor 212' has a lower inductance value than inductor 204'.

[0060] The values ​​of the components of circuit 200 are selected, for example, to produce an output impedance Z11 that increases or decreases with the frequency of the input signal over at least a portion of the frequency range of the amplifier's input signal, and a relatively constant output impedance Z11'. Specifically, the values ​​of the components of circuit 200 are selected, for example, to control resonance phenomena over the entire frequency range of the amplifier's input signal. Each component, including the series-connected resistors and capacitors, is configured, for example, to control the resonance phenomenon of the inductor closest to the voltage rail to which the second reference voltage 126 is applied in the inductor directly connected to it.

[0061] For example, at relatively low frequencies, capacitors 216 and 216' behave similarly to open switches, and the output impedances Z11 and Z11' are approximately equal to the sum of the values ​​of inductors 204 and 212, and 204' and 212', respectively. For example, for an input signal frequency close to the resonant frequency of inductor 204, resistor 214 is configured, for example, to attenuate or compensate for the resonance phenomenon, and the inductance of the output impedance Z11 is approximately equal to the value of inductor 212. Similarly, for an input signal frequency close to the resonant frequency of inductor 204', resistor 214' is configured to attenuate or compensate for the resonance phenomenon, and the inductance of the output impedance Z11' is, for example, approximately equal to the value of inductor 212'. Inductor 212 has, for example, a lower inductance value than inductor 204, so that inductor 212 begins to resonate at frequencies higher than the resonant frequency of inductor 204, and for example, at frequencies higher than the frequency of the amplifier's input signal. Similarly, inductor 212' has, for example, a lower inductance value than inductor 204', so that inductor 212' begins to resonate at a frequency higher than the resonant frequency of inductor 204', and for example, at a frequency higher than the frequency of the amplifier's input signal.

[0062] According to another embodiment, inductor 212 has an inductance value similar to or greater than that of inductor 204, and inductor 212' has an inductance value similar to or greater than that of inductor 204'.

[0063] The advantage of circuit 200 is that its physical implementation allows for optimization of the occupied surface area. Specifically, the central connection node C1 is floating. There are no wires to apply voltage, for example, to the central connection node C1. Therefore, the central connection node C1 is a virtual ground node. The advantage of making the central connection node C1 floating is that it has a variable physical implementation that does not require specific connections.

[0064] Figure 2B A two-stage electronic load impedance circuit 200 according to an embodiment of the present disclosure is schematically shown.

[0065] Figure 2B Some components are similar to Figure 2A The components, which are denoted by the same reference numerals, will not be discussed in detail hereafter.

[0066] and Figure 2A Like circuit 200, the central axis 202 is, for example, the axis of symmetry of circuit 200'.

[0067] Circuit 200' and Figure 2A The difference between circuits 200 and 200' is that circuit 200' includes a second stage 220.

[0068] Stage 220 includes: an inductor 222 in the first sub-circuit, coupled (preferably connected) to connection node N2 (see reference). Figure 2A The inductor 222' in the second sub-circuit is coupled (preferably connected) to the connection node N2' (see description) between the connection node N3 and the connection node N3; the inductor 222' in the second sub-circuit is coupled (preferably connected) to the connection node N2' (see description). Figure 2A The first component pair in the first sub-circuit, including resistor 224 and capacitor 226, is connected in series between connection node N2 and the second central connection node C2; ​​and the second component pair in the second sub-circuit, including resistor 224' and capacitor 226', is connected in series between connection node N2' and the second central connection node C2.

[0069] For example, the connection node N3 corresponds to the reference. Figure 1 The described connection node 124, and the connection node N3', for example, corresponds to the reference. Figure 1 The described connection node is 124'.

[0070] According to an embodiment, the second central connecting node C2 belongs to the central axis 202. The first central connecting node C1 and the second central connecting node C2 are aligned, for example, along the central axis 202.

[0071] According to an embodiment, a single capacitor is configured to realize capacitors 226 and 226' such that the capacitance of the single capacitor is equal to the equivalent capacitance of capacitors 226 and 226' connected in series. Then, a second central connection node C2 is located within the single capacitor, for example, at the center of the single capacitor.

[0072] According to an embodiment, the first and second component pairs of stage 220 are arranged symmetrically with respect to the central axis 202. Resistors 224 and 224' have, for example, similar resistance values. Capacitors 226 and 226' have, for example, similar capacitance values.

[0073] According to an embodiment, inductors 222 and 212' are arranged symmetrically with respect to the central axis 202. Inductors 222 and 222' have, for example, similar inductance values. According to an embodiment, the inductance value of inductor 222 is lower than that of inductor 212, and the inductance value of inductor 222' is lower than that of inductor 212'.

[0074] For example, the values ​​of the components of circuit 200' are selected to generate an output impedance Z11 that increases or decreases with the frequency of the input signal over at least a portion of the frequency range of the amplifier's input signal, and a relatively constant output impedance Z11'. Specifically, the values ​​of the components of circuit 200' are selected, for example, to control resonance phenomena over the entire frequency range of the amplifier's input signal.

[0075] For example, at relatively low frequencies, capacitors 216, 216', 226, and 226' exhibit behavior similar to that of an open switch. The output impedance Z11 is approximately equal to, for example, the sum of the values ​​of inductors 204, 212, and 222, and the output impedance Z11' is approximately equal to, for example, the sum of the values ​​of inductors 204', 212', and 222'.

[0076] For input signal frequencies close to the resonant frequency of inductor 204, resistor 214 is configured to, for example, attenuate or compensate for the resonance phenomenon, and the output impedance Z11 is approximately equal to the sum of the values ​​of inductors 212 and 222. Similarly, for input signal frequencies close to the resonant frequency of inductor 204', resistor 214' is configured to attenuate or compensate for the resonance phenomenon, and the output impedance Z11' is approximately equal to the sum of the values ​​of inductors 212' and 222'.

[0077] For input signal frequencies close to the resonant frequency of inductor 212, resistor 224 is configured to attenuate or compensate for the resonance phenomenon, and the output impedance Z11 is approximately equal to the value of inductor 222. Similarly, for input signal frequencies close to the resonant frequency of inductor 212', resistor 224' is configured to attenuate or compensate for the resonance phenomenon, and the output impedance Z11' is approximately equal to the value of inductor 222'. For example, inductor 222 has a lower inductance value than inductor 212, so that inductor 222 begins to resonate at frequencies higher than the resonant frequency of inductor 212, and for example, at frequencies higher than the frequency of the amplifier's input signal. Similarly, inductor 222' has, for example, a lower inductance value than inductor 212', so that inductor 222' begins to resonate at frequencies higher than the resonant frequency of inductor 212', and for example, at frequencies higher than the frequency of the amplifier's input signal.

[0078] According to another embodiment, inductor 222 has an inductance value similar to or greater than that of each of inductors 212 and 204, and inductor 222' has an inductance value similar to or greater than that of each of inductors 212' and 204'.

[0079] The advantage of adding a second stage 220 to circuit 200' is the control over the output impedances Z11 and Z11', as well as compensation for resonance phenomena over a potentially wider frequency range of input signals and / or additional degrees of freedom in defining the impedance.

[0080] Figure 3A An electronic load impedance circuit 300 including stages is schematically shown according to another embodiment of the present disclosure.

[0081] Figure 3A Some components are similar to Figure 2AThe components, which are denoted by the same reference numerals, will not be discussed in detail hereafter.

[0082] Circuit 300 and Figure 2A The difference between circuits 200 and 300 is that in circuit 200, the first central connection node C1 is floating, while in circuit 300, the first central connection node C1 is coupled to the first reference voltage 122.

[0083] Figure 3B A two-stage electronic load impedance circuit 300' according to another embodiment of the present disclosure is schematically shown.

[0084] Figure 3B Some components are similar to Figure 2B The components, which are denoted by the same reference numerals, will not be discussed in detail hereafter.

[0085] Circuit 300' and Figure 2B The difference between circuits 200' and 300' is that in circuit 200', the first central connection node C1 is floating, while in circuit 300', the first central connection node C1 and the second central connection node C2 are coupled to the first reference voltage 122.

[0086] Figure 4A An electronic load impedance circuit 400 including stages is schematically shown according to another embodiment of the present disclosure.

[0087] Figure 4A Some components are similar to Figure 2A The components, which are denoted by the same reference numerals, will not be discussed in detail hereafter.

[0088] Circuit 400 and Figure 2A The difference between circuits 200 and circuit 400 is that, in circuit 400, the first central connection node C1 is coupled to the voltage rail to which the second reference voltage 126 is applied via wire 305.

[0089] Figure 4B A two-stage electronic load impedance circuit 400' according to another embodiment of the present disclosure is schematically shown.

[0090] Figure 4B Some components and Figure 2B The components are similar, and these components are designated with the same reference numerals and will not be discussed in detail hereafter.

[0091] Circuit 400' and Figure 2B The difference between the circuits 200' shown is that, in circuit 400', the first central connection node C1 and the second central connection node C2 are coupled to the voltage rail to which the second reference voltage 126 is applied via wire 305'.

[0092] Figure 5 It is shown Figure 2A and Figure 3A The graph shows the amplitude ("A [dB]") of the S-parameters ("scattering parameters") of the input, output, and transmission adaptations of the circuit as a function of frequency ("F [GHz]").

[0093] This graph includes six curves: 500, 505, 510, 515, 520, and 525. Curves 500 and 505 represent circuits 200 and 300, respectively. Figure 1 The input reflection coefficient S11 of system 100. Curves 510 and 515 represent the circuits 200 and 300 respectively. Figure 1 The power gain S21 of system 100. Curves 520 and 525 represent circuits 200 and 300 respectively. Figure 1 The system output reflection coefficient S22 is 100.

[0094] Between 50 GHz and 160 GHz, curves 500 and 505 are approximately the same.

[0095] Between 50 GHz and 160 GHz, curves 510 and 515, as well as curves 520 and 525, exhibit similar amplitude variations.

[0096] The graph shows that circuits 200 and 300 exhibit similar behavior between 50 GHz and 160 GHz.

[0097] Reference Figures 2A to 4B All the circuits described are suitable for broadband amplifiers. Specifically, refer to... Figures 2A to 4B The circuit described has S-parameters that vary similarly.

[0098] Figure 5 The curves show that circuits 200 and 200', in which the central connection nodes C1 and C2 are floating, are adapted to provide the output load impedance for the differential amplifier.

[0099] Figure 6A yes Figure 2A A top view of circuit 200 is shown, and an example of the wiring of circuit 200 according to an embodiment of the present disclosure is illustrated.

[0100] exist Figure 6A In the example, resistors 214 and 214' correspond to the resistance of the wire and are not labeled in the diagram.

[0101] exist Figure 6A In the example, each of inductors 204, 212, 204', and 212' corresponds to all or part of an inductor.

[0102] exist Figure 6A In the example, the central axis 202 is the axis of symmetry of the circuit 200. The first sub-circuit and the second sub-circuit are identical on each side of the central axis 202, for example, and the sub-circuit includes identical components that are physically symmetrically arranged with respect to the central axis 202.

[0103] Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F yes Figure 4A A top view of circuit 400 is shown, and an example of the wiring of circuit 400 according to an embodiment of the present disclosure is illustrated.

[0104] Each of inductors 204, 212, 204', and 212' corresponds, for example, to all or part of an inductor. Figures 6B to 6F In the example, the inductor loop is configured to implement at least two of inductors 204, 212, 204', and 212'. The central connection node C1 is coupled to a voltage rail to which a second reference voltage 126 is applied, and the wiring is symmetrical with respect to axis 202.

[0105] exist Figures 6B to 6F In the example shown, the central axis 202 is the axis of symmetry of the circuit 400. The first and second sub-circuits are identical, for example, on each side of the central axis 202, and the sub-circuits include identical components arranged physically symmetrically with respect to the central axis 202.

[0106] Figures 6B to 6F Each of these shows an example of the wiring for circuit 400. Figure 6B In the example, circuit 400 includes two inductor loops arranged symmetrically with respect to the central axis 202, one configured to implement inductors 204 and 212, and the other configured to implement inductors 204' and 212'. Figure 6C In the example, circuit 400 includes two inductor loops forming a figure-eight inductor, each of inductors 204, 212, 204', and 212' being formed by a half-loop. Figure 6D In the example, circuit 400 includes two concentric inductor loops, each of inductors 204, 212, 204', and 212' being formed by a half-loop. Figure 6E In the example, circuit 400 includes three inductor loops. Each of inductors 212 and 212' is formed by half-loops, and each of inductors 204 and 204' is formed by two half-loops. Figure 6FIn the example, circuit 400 includes three concentric inductor loops. Each of inductors 212 and 212' is formed by one half-loop, and each of inductors 204 and 204' is formed by two half-loops. The choice of wiring is performed, for example, based on the available surface area, the size of each circuit component, and the possible coupling between the inductors and capacitors.

[0107] Reference Figures 2A to 4B Each circuit described has a relatively low volume. Specifically, circuit 200 in which the first central connection node C1 is floating and circuit 200' in which the first central connection node C1 and the second central connection node C2 are floating have low volumes.

[0108] Reference Figures 2A to 4B Each circuit described advantageously has an inductive output impedance Z11, Z11' over the entire frequency range of the amplifier’s use (e.g., over a frequency range with amplitude greater than or equal to 10 GHz, such as greater than or equal to 100 GHz). That is, it has a positive imaginary part.

[0109] Reference Figures 2A to 4B Another advantage of each circuit described is that the output impedance of the differential amplifier can be controlled using a single circuit.

[0110] The embodiment provides an electronic load impedance circuit for an amplifier, comprising: 1) a central axis; 2) a first stage including: a first resistor connected to a first node; a second resistor connected to a second node, the first resistor being located on a first side of the central axis and the second resistor being located on a second side of the central axis opposite to the first side, the first resistor and the second resistor being connected together via a capacitor located on the central axis; a first inductor connected to the first node and a second inductor connected to the second node, the first inductor also being coupled to a third node and the second inductor also being coupled to a fourth node; and 3) a third inductor and a fourth inductor, the third inductor being connected between the first node and a voltage rail to which a first reference voltage is applied, and the fourth inductor being connected between the second node and the voltage rail to which the first reference voltage is applied.

[0111] The embodiment provides an electronic load impedance circuit for an amplifier, comprising: 1) a central axis; 2) a first stage including: a first capacitor connected to a first node; a second capacitor connected to a second node, the first capacitor being located on a first side of the central axis and the second capacitor being located on a second side of the central axis opposite to the first side, the first capacitor and the second capacitor being connected together via a resistor located on the central axis; a first inductor connected to the first node and a second inductor connected to the second node, the first inductor also being coupled to a third node and the second inductor also being coupled to a fourth node; and 3) a third inductor and a fourth inductor, the third inductor being connected between the first node and a voltage rail to which a first reference voltage is applied, and the fourth inductor being connected between the second node and the voltage rail to which the first reference voltage is applied.

[0112] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, although... Figures 2A to 4B Each circuit has one or two stages, but more than two stages are possible.

[0113] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. An electronic load impedance circuit for an amplifier, comprising: 1) Central axis; 2) Level 1, including: The first component pair includes a capacitor and a resistor connected in series with each other, and the first component pair is connected to a first node; The second component pair includes a capacitor and a resistor connected in series, the second component pair is connected to a second node, the first component pair is positioned on a first side of the central axis and the second component pair is positioned on a second side of the central axis opposite to the first side, and the first component pair and the second component pair are connected to each other via a first central connection node belonging to the central axis; and A first inductor connected to the first node and a second inductor connected to the second node, the first inductor being further coupled to a third node and the second inductor being further coupled to a fourth node; and 3) A third inductor and a fourth inductor, the third inductor being located between the first node and the voltage rail to which the first reference voltage is applied, and the fourth inductor being located between the second node and the voltage rail to which the first reference voltage is applied.

2. The circuit of claim 1, wherein the first central connection node is connected to the voltage rail to which the first reference voltage is applied.

3. The circuit of claim 1, wherein the first central connection node is connected to a voltage rail to which a second reference voltage different from the first reference voltage is applied.

4. The circuit according to claim 1, wherein the first central connection node is floating.

5. The circuit according to claim 1, wherein the third node and the fourth node form a differential output.

6. The circuit of claim 1, wherein the inductor loop is configured to implement at least two of the first inductor, the second inductor, the third inductor, and the fourth inductor.

7. The circuit of claim 1, wherein one or more of the first inductor, the second inductor, the third inductor, and the fourth inductor are implemented by a figure-eight inductor, an inductor comprising two concentric loops, or an inductor comprising three concentric loops.

8. The circuit according to claim 1, further comprising a second stage, the second stage comprising: The first component pair includes a capacitor and a resistor connected in series with each other, and the first component pair is connected to the third node; The second component pair includes a capacitor and a resistor connected in series with each other. The second component pair is connected to the fourth node. The first component pair is positioned on a first side of the central axis, and the second component pair is positioned on a second side of the central axis opposite to the first side. The first component pair and the second component pair are connected to each other via a second central connection node belonging to the central axis. A fifth inductor is connected to the third node and a sixth inductor is connected to the fourth node, the fifth inductor being further coupled to the fifth node and the sixth inductor being further coupled to the sixth node.

9. The circuit of claim 8, wherein the second central connection node is connected to the voltage rail to which the first reference voltage is applied.

10. The circuit of claim 8, wherein the first central connection node is connected to a voltage rail to which a second reference voltage different from the first reference voltage is applied, and the second central connection node is connected to the voltage rail to which the second reference voltage is applied.

11. The circuit of claim 8, wherein the second central connection node is floating.

12. The circuit of claim 1, wherein the amplifier is a broadband amplifier configured to amplify the input signal over a frequency range having a bandwidth of 10 GHz or greater.

13. The circuit of claim 1, wherein the first component pair and the second component pair of each stage are arranged symmetrically with respect to the central axis.

14. An amplifier, comprising: Load impedance circuit, including: 1) Central axis; 2) Level 1, including: The first component pair includes a capacitor and a resistor connected in series with each other, and the first component pair is connected to a first node; The second component pair includes a capacitor and a resistor connected in series, the second component pair is connected to a second node, the first component pair is positioned on a first side of the central axis and the second component pair is positioned on a second side of the central axis opposite to the first side, and the first component pair and the second component pair are connected to each other via a first central connection node belonging to the central axis; and A first inductor connected to the first node and a second inductor connected to the second node, the first inductor being further coupled to a third node and the second inductor being further coupled to a fourth node; and 3) A third inductor and a fourth inductor, the third inductor being located between the first node and the voltage rail to which the first reference voltage is applied, and the fourth inductor being located between the second node and the voltage rail to which the first reference voltage is applied.

15. The amplifier of claim 14, configured to receive radio waves having frequencies in the range of 1 GHz to 200 GHz.

16. The amplifier of claim 14, wherein the first central connection node is connected to the voltage rail to which the first reference voltage is applied.

17. The amplifier of claim 14, wherein the first central connection node is connected to a voltage rail to which a second reference voltage, different from the first reference voltage, is applied.

18. The amplifier of claim 14, wherein the first central connection node is floating.

19. The amplifier of claim 14, wherein the amplifier is a broadband amplifier configured to amplify the input signal over a frequency range having a bandwidth of 10 GHz or greater.

20. The amplifier of claim 14, wherein the inductor loop is configured to implement at least two of the first inductor, the second inductor, the third inductor, and the fourth inductor.

Images