Differential amplifier circuit

Abstract

A differential amplifier circuit is provided. A first bias circuit includes first and second transistors connected in an emitter or source follower connection. The collectors or drains of the first and second transistors are connected to a bias power supply voltage, the emitter or source of the first transistor is connected to a first amplifier via a first bias wiring, and the emitter or source of the second transistor is connected to a second amplifier via a second bias wiring. The first and second amplifiers are arranged in a first direction parallel to a surface of a substrate, and the first and second transistors are arranged in a range on a side opposite the first amplifier in the first direction as viewed from the second amplifier. The first bias wiring includes a first intermediate portion arranged in the second bias wiring between a second amplifier connection portion connected to the second amplifier and a primary coil and extending in the first direction. The first intermediate portion connects a first amplifier connection portion connected to the first amplifier in the first bias wiring and the first transistor.

Description

Technical Field

[0001] This invention relates to a differential amplifier circuit. Background Technology

[0002] An amplifier circuit is known to convert a differential signal output from a differential amplifier into a single-ended signal using a balun (Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2023-147645 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] The primary and secondary coils of the balun that converts a differential signal to a single-ended signal are inductively coupled, but parasitic capacitance exists between them. The output node of the differential amplifier is connected to the load via the balun. When viewed from the differential amplifier, the output node of the differential amplifier is also connected to the load via the parasitic capacitance of the balun. The transmission line for transmitting a single-ended signal is an unbalanced transmission line, therefore a difference in load impedance occurs when viewing the load side from the amplifiers that form the differential pair (one for the non-inverted signal and one for the inverted signal). When the load impedances of the two amplifiers differ, the gain and output power of the two amplifiers differ. In particular, the symmetry of the output signal collapses at high output, thereby reducing the overall output power of the amplifier circuit.

[0008] The purpose of this invention is to provide a differential amplifier circuit that can suppress the drop in output even when the load impedances of the two amplifiers forming a differential pair differ.

[0009] Solution for solving the problem

[0010] According to one aspect of the present invention, a differential amplifier circuit is provided, the differential amplifier circuit comprising:

[0011] A first amplifier and a second amplifier for amplifying differential signals;

[0012] An input matching circuit includes a primary coil and a secondary coil that are inductively coupled to each other. The two ends of the secondary coil are respectively connected to the input node of the first amplifier and the input node of the second amplifier. The input matching circuit outputs the high-frequency signal input to the primary coil from the secondary coil.

[0013] A first bias circuit provides bias to the first amplifier and the second amplifier, respectively;

[0014] The first bias wiring connects the first bias circuit to the first amplifier, forming a bias-providing path;

[0015] The second bias wiring connects the first bias circuit to the second amplifier, forming a bias provision path;

[0016] A substrate is formed on the substrate, comprising the first amplifier, the second amplifier, the input matching circuit, the first bias circuit, the first bias wiring, and the second bias wiring.

[0017] The first bias circuit includes a first transistor and a second transistor that are either emitter-follower or source-follower connected. The collector or drain of the first transistor and the second transistor is connected to a bias power supply voltage. The emitter or source of the first transistor is connected to the first amplifier via the first bias wiring, and the emitter or source of the second transistor is connected to the second amplifier via the second bias wiring.

[0018] The first amplifier and the second amplifier are arranged along a first direction parallel to the surface of the substrate, and the first transistor and the second transistor are arranged in a region on the side opposite to the first amplifier in the first direction when viewed from the second amplifier.

[0019] The first bias wiring includes a first intermediate portion disposed in the second bias wiring between a second amplifier connection portion connected to the second amplifier and the primary coil and extending along the first direction, the first intermediate portion connecting the first amplifier connection portion in the first bias wiring to the first transistor.

[0020] According to another aspect of the present invention, a differential amplifier circuit is provided, the differential amplifier circuit comprising:

[0021] A first amplifier and a second amplifier for amplifying differential signals;

[0022] An input matching circuit includes a primary coil and a secondary coil that are inductively coupled to each other. The two ends of the secondary coil are respectively connected to the input node of the first amplifier and the input node of the second amplifier. The input matching circuit outputs the high-frequency signal input to the primary coil from the secondary coil.

[0023] A first bias circuit provides bias to the first amplifier; and

[0024] The second bias circuit provides bias to the second amplifier.

[0025] The first bias circuit is configured such that when the power of the differential signal input to the first amplifier and the second amplifier increases, the bias is adjusted in the direction that increases the gain of the first amplifier.

[0026] The second bias circuit is configured such that when the power of the differential signal input to the first amplifier and the second amplifier increases, the bias is adjusted in the direction that increases the gain of the second amplifier, provided that the increase in gain is less than the increase in gain of the first amplifier, or the gain of the second amplifier is not increased.

[0027] The effects of the invention

[0028] The first intermediate portion of the first bias wiring is electromagnetically coupled to the primary coil. Therefore, a high-frequency signal is generated in the first bias wiring due to the high-frequency signal transmitted in the primary coil. When this high-frequency signal is superimposed on the bias of the first amplifier and exhibits a self-biasing effect, the gain of the first amplifier increases. Even when the gain of the first amplifier is lower than that of the second amplifier due to the difference in load impedance between the first and second amplifiers, the gain difference decreases due to the increase in the gain of the first amplifier. As a result, the drop in output can be suppressed.

[0029] Furthermore, even when the first bias circuit is configured to adjust the bias in the direction that increases the gain of the first amplifier, the gain difference between the first amplifier and the second amplifier decreases. As a result, the drop in output can be suppressed. Attached Figure Description

[0030] Figure 1 This is the equivalent circuit diagram of the differential amplifier circuit in the first embodiment.

[0031] Figure 2 This is a diagram showing the layout of multiple structural elements of the differential amplifier circuit of the first embodiment.

[0032] Figure 3 This is an equivalent circuit diagram of the first amplifier 21, the second amplifier 22, the input matching circuit 30, the first bias circuit 40, the first bias wiring 51, and the second bias wiring 52 of the differential amplifier circuit in the first embodiment.

[0033] Figure 4A This is a graph showing the simulation results of the time waveform of the emitter voltage of the first transistor 41. Figure 4B This is a graph showing the simulation results of the time waveform of the emitter voltage of the second transistor 42. Figure 4C This is a graph illustrating an example of the relationship between the DC component of the emitter voltage of the first transistor 41 and the second transistor 42 and the output power. Figure 4DThis is a graph illustrating an example of the relationship between the gain and output power of the first amplifier 21 and the second amplifier 22.

[0034] Figure 5 This is an equivalent circuit diagram of the first amplifier 21, the second amplifier 22, the input matching circuit 30, the first bias circuit 40, the first bias wiring 51, and the second bias wiring 52 of the differential amplifier circuit in the first embodiment.

[0035] Figure 6 This is a diagram showing the layout of multiple structural elements of a differential amplifier circuit in a modified example of the first embodiment.

[0036] Figure 7 This is the equivalent circuit diagram of the differential amplifier circuit in the second embodiment.

[0037] Figure 8 This is a diagram showing the layout of multiple structural elements of the differential amplifier circuit of the second embodiment.

[0038] Figure 9A This is an equivalent circuit diagram used to illustrate the operation of the differential amplifier circuit in the second embodiment. Figure 9B This is a graph illustrating an example of the relationship between the gains G1 and G2 of the first amplifier 21 and the second amplifier 22 and their output power.

[0039] Figure 10A This is an equivalent circuit diagram used to illustrate the operation of the differential amplifier circuit in the second embodiment. Figure 10B This is a graph illustrating an example of the relationship between the gains G1 and G2 of the first amplifier 21 and the second amplifier 22 and their output power.

[0040] Figure 11A This is an equivalent circuit diagram used to illustrate the operation of the differential amplifier circuit in the second embodiment. Figure 11B This is a graph illustrating an example of the relationship between the gains G1 and G2 of the first amplifier 21 and the second amplifier 22 and their output power.

[0041] Figure 12 This is a schematic top view showing the layout of the primary coil 31, the first bias wiring 51, and the second bias wiring 52 of the input matching circuit 30 of the differential amplifier circuit of the third embodiment.

[0042] Figure 13 This is the equivalent circuit diagram of the first bias circuit 40 of the differential amplifier circuit in the fourth embodiment.

[0043] Figure 14 This is the equivalent circuit diagram of the differential amplifier circuit in the fifth embodiment.

[0044] Figure 15 This is a block diagram of the differential amplifier circuit in the sixth embodiment.

[0045] Figure 16 This is a block diagram of the differential amplifier circuit of a modified example of the sixth embodiment.

[0046] Figure 17 This is a block diagram of a differential amplifier circuit in another variation of the sixth embodiment.

[0047] Figure 18 This is a block diagram of a differential amplifier circuit, which is another variation of the sixth embodiment.

[0048] Figure 19 This is a block diagram of a differential amplifier circuit, which is another variation of the sixth embodiment. Detailed Implementation

[0049] [First Embodiment]

[0050] Reference Figures 1 to 4D The accompanying drawings illustrate the differential amplifier circuit of the first embodiment.

[0051] Figure 1 This is an equivalent circuit diagram of the differential amplifier circuit of the first embodiment. The differential amplifier circuit of the first embodiment includes a first amplifier 21 and a second amplifier 22 for amplifying differential signals, an input matching circuit 30, an output matching circuit 60, and a first bias circuit 40. Furthermore, in this specification, a differential amplifier circuit refers to a circuit that amplifies signals by inputting signals with opposite phases to each active element as a group; it can also be called a push-pull amplifier circuit.

[0052] The input matching circuit 30 includes a primary coil 31 and a secondary coil 32 that are inductively coupled to each other. The two ends of the secondary coil 32 are connected to the input node 21I of the first amplifier 21 and the input node 22I of the second amplifier 22, respectively. One end of the primary coil 31 is input with a high-frequency signal RF. IN The other end is connected to a reference potential (ground potential). The input matching circuit 30 receives the high-frequency signal RF input to the primary coil 31. IN The signal is converted into a differential signal and output from the secondary coil 32. That is, the input matching circuit 30 is a balun that converts a single-ended signal into a differential signal.

[0053] The input matching circuit 30 has the following polarity: in the high-frequency signal RF IN During the period when the voltage is positive, this polarity causes a voltage to be induced in the direction that the potential of the end of the second amplifier 22 side is higher than the potential of the end of the first amplifier 21 side of the secondary coil 32.

[0054] The first amplifier 21 includes an amplifying transistor 21Q, a ballast resistor element 21R, and an input capacitor 21C. For example, the first amplifier 21 can be constructed by connecting multiple units in parallel, using the amplifying transistor 21Q, the ballast resistor element 21R, and the input capacitor 21C as a single unit. Similarly, the second amplifier 22 includes an amplifying transistor 22Q, a ballast resistor element 22R, and an input capacitor 22C. For example, a heterojunction bipolar transistor (HBT) can be used as the amplifying transistors 21Q and 22Q.

[0055] The two ends of the secondary coil 32 of the input matching circuit 30 are connected to the bases of the amplifying transistors 21Q and 22Q via input capacitors 21C and 22C, respectively.

[0056] The first bias circuit 40 provides bias current to the first amplifier 21 and the second amplifier 22, respectively. For example, the first bias circuit 40 provides bias current to the base of the amplifying transistor 21Q via the ballast resistor element 21R of the first amplifier 21, and provides bias current to the base of the amplifying transistor 22Q via the ballast resistor element 22R of the second amplifier 22.

[0057] The first bias wiring 51 connects the first bias circuit 40 to the first amplifier 21, forming a bias supply path that provides bias to the first amplifier 21. The second bias wiring 52 connects the first bias circuit 40 to the second amplifier 22, forming a bias supply path that provides bias to the second amplifier 22.

[0058] The first bias circuit 40 includes a first transistor 41, a second transistor 42, a capacitor 43, and a diode circuit 44. HBTs are used as the first transistor 41 and the second transistor 42. The first transistor 41 and the second transistor 42 are emitter-follower connected. That is, the collectors of the first transistor 41 and the second transistor 42 are connected to the bias power supply voltage V. BAT The emitter of the first transistor 41 is connected to the first amplifier via the first bias wiring 51, and the emitter of the second transistor 42 is connected to the second amplifier 22 via the second bias wiring 52.

[0059] The bases of the first transistor 41 and the second transistor 42 are provided with a bias control current I. CONT1 The bases of the first transistor 41 and the second transistor 42 are connected to a reference potential via a capacitor 43 and also via a diode circuit 44. The diode circuit 44 includes, for example, a two-stage diode connected in a forward direction from the bases of the first transistor 41 and the second transistor 42 toward the reference potential. The base voltages of the first transistor 41 and the second transistor 42 are fixed to the forward voltage of the diode circuit 44.

[0060] The output matching circuit 60 includes a primary coil 61 and a secondary coil 62 that are inductively coupled to each other. The two ends of the primary coil 61 are connected to the output node 21O of the first amplifier 21 and the output node 22O of the second amplifier 22, respectively. The midpoint of the primary coil 61 is connected to the power supply voltage V. CC Connection. The collectors of the amplifying transistor 21Q of the first amplifier 21 and the amplifying transistor 22Q of the second amplifier 22 are each supplied with a power supply voltage V via the primary coil 61. CC .

[0061] One end of the secondary coil 62 of the output matching circuit 60 is connected to the reference potential, and the amplified high-frequency signal RF is output from the other end. OUT High-frequency signal RF OUT It is a single-ended signal.

[0062] A parasitic capacitance 30C is generated between the primary coil 31 and the secondary coil 32 of the input matching circuit 30, and also between the primary coil 61 and the secondary coil 62 of the output matching circuit 60. The input nodes of the first amplifier 21 and the second amplifier 22 are connected to the signal source via the input matching circuit 30, and also via this parasitic capacitance 30C. As a result, the signal source impedances observed from the first amplifier 21 and the second amplifier 22 are different in the first amplifier 21 and the second amplifier 22. Similarly, the output nodes of the first amplifier 21 and the second amplifier 22 are connected to the load via the parasitic capacitance 60C, therefore the load impedances observed from the first amplifier 21 and the second amplifier 22 are different in the first amplifier 21 and the second amplifier 22.

[0063] When the signal source impedance and load impedance are different in the first amplifier 21 and the second amplifier 22, a difference in gain occurs between them. Particularly at high output, the symmetry of the output signal collapses, resulting in a decrease in the overall output power of the differential amplifier circuit and a deterioration in its amplification characteristics. In the first embodiment, the deterioration of amplification characteristics caused by the asymmetry of the output signals of the first amplifier 21 and the second amplifier 22 is suppressed. The structure capable of suppressing the deterioration of amplification characteristics will be described below.

[0064] Figure 2This diagram illustrates the layout of multiple structural elements of the differential amplifier circuit according to the first embodiment. A first amplifier 21, a second amplifier 22, an input matching circuit 30, a first bias circuit 40, a first bias wiring 51, and a second bias wiring 52 are formed on the semiconductor substrate 10. The first amplifier 21 is composed of multiple units including an amplifying transistor 21Q, an input capacitor 21C, and a ballast resistor element 21R. The second amplifier 22 is composed of multiple units including an amplifying transistor 22Q, an input capacitor 22C, and a ballast resistor element 22R.

[0065] Multiple amplifying transistors 21Q and 22Q are arranged in a direction parallel to the surface of the semiconductor substrate 10. The direction in which the multiple amplifying transistors 21Q and 22Q are arranged is called the first direction D1. Figure 2 (The middle is the horizontal direction). The direction orthogonal to the first direction D1 within the surface of the semiconductor substrate 10 is called the second direction D2 (in the middle). Figure 2 (The middle is vertical). The multiple input capacitors 21C and multiple ballast resistors 21R of the first amplifier 21, and the multiple input capacitors 22C and multiple ballast resistors 22R of the second amplifier 22 are also arranged along the first direction D1.

[0066] The first amplifier 21 and the second amplifier 22 are arranged along a first direction D1. The first transistor 41 and the second transistor 42 of the first bias circuit 40 are located on the side opposite to the first amplifier 21 in the first direction D1 when viewed from the second amplifier 22. The capacitor 43 and the diode circuit 44 of the first bias circuit 40 are also located on the side opposite to the first amplifier 21 in the first direction D1 when viewed from the second amplifier 22. Furthermore, the relationship between the positions of the first amplifier 21 and the second amplifier 22 in the second direction and the position of the first bias circuit 40 in the second direction is not particularly limited. Figure 2 In the example shown, the first transistor 41 and the second transistor 42 of the first bias circuit 40 are positioned at a position offset relative to the first amplifier 21 and the second amplifier 22 along the second direction D2.

[0067] The input matching circuit 30 is positioned offset relative to the first amplifier 21 and the second amplifier 22 along a second direction. The first amplifier 21 and the second amplifier 22 are respectively positioned on either side of a straight line parallel to the second direction D2 passing through the geometric center of the input matching circuit 30. The primary coil 31 has, for example, approximately 3 turns, and its ends 31T1 and 31T2 are positioned at their furthest points along the second direction D2 when viewed from the first amplifier 21 and the second amplifier 22. That is, the winding portion of the primary coil 31 is positioned along the second direction D2 between the ends 31T1 and 31T2 of the primary coil 31 and the first amplifier 21 and the second amplifier 22.

[0068] The secondary coil 32 has, for example, slightly fewer than one turn. One end of the secondary coil 32 is connected to a plurality of input capacitors 21C of the first amplifier 21, and the other end is connected to a plurality of input capacitors 22C of the second amplifier 22.

[0069] The first bias wiring 51 is connected to a plurality of ballast resistor elements 21R of the first amplifier 21. The plurality of ballast resistor elements 21R are arranged along a first direction D1, therefore the first bias wiring 51 is connected to the first amplifier 21 for a certain length along the first direction D1. The portion of the first bias wiring 51 connected to the first amplifier 21 is referred to as the first amplifier connection portion 51A. Similarly, the second bias wiring 52 is connected to the second amplifier 22 at the second amplifier connection portion 52A, which is also long along the first direction D1.

[0070] A high-frequency signal RF is input to one end 31T1 of the primary coil 31. IN The other end, 31T2, is connected to a reference potential. In the high-frequency signal RF... IN During the period when the voltage of the secondary coil 32 deflects negatively relative to the reference potential, a negative voltage is generated at the end of the secondary coil 32 connected to the second amplifier 22 relative to the end connected to the first amplifier 21. When the midpoint of the secondary coil 32 is assumed to be a virtual reference potential, the second amplifier 22 is applied a negative voltage, and the first amplifier 21 is applied a positive voltage. Figure 2 In this diagram, the polarity relationship is represented by a negative circle and a positive circle. Furthermore, the terminal 31T2, which is connected to the reference potential, generates a relatively positive potential relative to the other terminal 31T1, and is therefore marked with a positive sign.

[0071] A first bias wiring 51 is disposed between the second amplifier connection portion 52A of the second bias wiring 52 and the primary coil 31, including a first intermediate portion 51B extending along a first direction D1. The first intermediate portion 51B connects the first amplifier connection portion 51A of the first bias wiring 51 to the first transistor 41. The shortest distance between the first intermediate portion 51B of the first bias wiring 51 and the primary coil 31 is closer than the shortest distance between the second amplifier connection portion 52A of the second bias wiring and the primary coil 31. Therefore, the first intermediate portion 51B of the first bias wiring 51 is strongly electromagnetically coupled (capacitive and inductive coupling) to the primary coil 31. The electromagnetic coupling between the first intermediate portion 51B and the primary coil 31 is greater than the electromagnetic coupling between the second amplifier connection portion 52A of the second bias wiring 52 and the primary coil 31.

[0072] The primary coil 31 includes a first coupling portion 31A, which is spaced apart from the first intermediate portion 51B of the first bias wiring 51 in the second direction D2 and extends along the first direction D1. No other portion of the primary coil 31 is disposed between the first coupling portion 31A and the first intermediate portion 51B. The first coupling portion 31A is located from the end 31T2 of the primary coil 31 that presents the same polarity as the end of the secondary coil 32 connected to the first amplifier 21, to the midpoint 31M of the primary coil 31.

[0073] Next, refer to Figures 3 to 4D The accompanying drawings illustrate the capacitive coupling operation between the first coupling portion 31A of the primary coil 31 and the first intermediate portion 51B of the first bias wiring 51. Figure 3 This is an equivalent circuit diagram of the first amplifier 21, the second amplifier 22, the input matching circuit 30, the first bias circuit 40, the first bias wiring 51, and the second bias wiring 52 of the differential amplifier circuit in the first embodiment.

[0074] The first coupling portion 31A of the primary coil 31 is capacitively coupled to the first intermediate portion 51B of the first bias wiring 51. When one end 31T2 of the primary coil 31 is deflected in a relatively positive direction, the first amplifier 21 is input with a relatively positive voltage, and the second amplifier 22 is input with a relatively negative voltage. A relatively positive voltage is generated in the first intermediate portion 51B of the first bias wiring 51 through capacitive coupling with the first coupling portion 31A of the primary coil 31. Conversely, when one end 31T2 of the primary coil 31 is deflected in a relatively negative direction, a relatively negative voltage is generated in the first intermediate portion 51B of the first bias wiring 51.

[0075] The voltage of the first intermediate portion 51B is deflected in both positive and negative directions, thus generating a high-frequency signal at the emitter of the first transistor 41 in the first bias circuit 40. This high-frequency signal is in phase with the high-frequency signal input from the secondary coil 32 to the first amplifier 21, therefore, a voltage is generated at the emitter of the first transistor 41 that is the high-frequency signal input to the first amplifier 21 superimposed on the high-frequency signal generated by the first intermediate portion 51B of the first bias wiring 51. As a result, the amplitude of the high-frequency signal generated at the emitter of the first transistor 41 increases.

[0076] In contrast, the second bias wiring 52 hardly couples with the primary coil 31, so the amplitude of the high-frequency signal generated at the emitter of the second transistor 42 is smaller than the amplitude of the high-frequency signal generated at the emitter of the first transistor 41.

[0077] Figure 4A This is a graph showing the simulation results of the time waveform of the emitter voltage of the first transistor 41. The solid line represents the emitter voltage V when the output power is high. E1L The dashed line represents the emitter voltage V when the output power is low. E1S The output power is related to the high-frequency signal RF input to the input-to-input matching circuit 30. IN The magnitude of the amplitude corresponds to this. Figure 4A The graph shown in the image represents time on the horizontal axis and the normalized voltage on the vertical axis. The normalized voltage is the emitter voltage V of the first transistor 41. E1L It is obtained by standardizing based on the maximum value.

[0078] When the output power is low, that is, when the amplitude of the high-frequency signal input to the first amplifier 21 is low, the emitter voltage V of the first transistor 41 is low. E1S It is determined by the base voltage of the first transistor 41, and is approximately a certain value.

[0079] When the output power increases, the emitter voltage V of the first transistor 41... E1L The first transistor 41 is affected by the high-frequency signal input to the first amplifier 21, and by the capacitive coupling between the first coupling portion 31A of the primary coil 31 and the first intermediate portion 51B of the first bias wiring 51. Due to these effects, the emitter voltage V of the first transistor 41... E1L The amplitude increases. At this time, the emitter voltage V of the first transistor 41 increases. E1L It will not be lower than the value obtained by subtracting the forward voltage between the base and emitter from the base voltage of the first transistor 41. Therefore, the emitter voltage V during the period when the high-frequency signal input to the first amplifier 21 is deflected in the negative direction. E1L The decrease in voltage is limited by the base voltage of the first transistor 41.

[0080] For the reasons mentioned above, the emitter voltage V when the input power is high E1L The time waveform changes to the following shape: when the input power is low, the emitter voltage V E1S As a reference, the deflection amplitude in the positive direction is greater than the deflection amplitude in the negative direction. Therefore, the emitter voltage V E1L The average value becomes lower than the emitter voltage V when the input power is low. E1S The average value is high.

[0081] At the emitter voltage V E1L During the period of deflection in the positive direction, the first transistor 41 ( Figure 3 The emitter current decreases. At emitter voltage V E1L During the negative deflection period, the emitter current of the first transistor 41 increases. When time averaging is performed, the average emitter current of the first transistor 41 when the output power is high becomes larger than the average emitter current of the first transistor 41 when the output power is low. This is equivalent to increasing the emitter current of the first amplifier 21 ( Figure 1 The bias current supplied by the amplifying transistor 21Q increases. The effect of the amplifying transistor 21Q increasing the bias current when the power of the high-frequency signal input to the first amplifier 21 increases is called the self-biasing effect.

[0082] Figure 4B This shows the second transistor 42 ( Figure 3 The graph shows the simulation results of the emitter voltage time waveform. The solid line represents the emitter voltage V when the output power is high. E2L The dashed line represents the emitter voltage V when the output power is low. E2S The horizontal axis represents time, and the vertical axis represents the standardized value of voltage. The standardized value of voltage is calculated by... Figure 4A The emitter voltage V of the first transistor 41 shown in the figure E1L It is obtained by standardizing based on the maximum value.

[0083] When the output power is low, the emitter voltage V of the second transistor 42 is... E2S With the emitter voltage V of the first transistor 41 E1S Approximately equal. When the output power increases, the emitter voltage V of the second transistor 42... E2L The second bias wiring 52, which varies according to the waveform of the high-frequency signal, is connected to the emitter of the second transistor 42. Figure 3 The primary coil 31 has almost no electromagnetic coupling with the transistor, so its amplitude is relatively small compared to the emitter voltage V of the first transistor 41. E1L Therefore, it is small. Thus, it does not exhibit a self-biasing effect.

[0084] Figure 4CThis is a graph illustrating an example of the relationship between the DC component of the emitter voltages of the first transistor 41 and the second transistor 42 and the output power. The horizontal axis represents the output power of the differential amplifier circuit, and the vertical axis represents the DC component of the emitter voltages of the first transistor 41 and the second transistor 42 using a normalized value obtained with the emitter voltage at a sufficiently low output power as a reference. Figure 4C The solid and dashed lines represent the emitter voltage V of the first transistor 41, respectively. E1 The DC component and the emitter voltage V of the second transistor 42 E2 DC component.

[0085] Within the low output power range, the DC components of the emitter voltages of the first transistor 41 and the second transistor 42 are approximately equal. When the output power increases, as referenced... Figure 4A As explained, the emitter current of the first transistor 41 increases. As a result, the emitter current of the second transistor 42 relatively decreases. Consequently, the emitter voltage V of the second transistor 42... E2 decline.

[0086] Figure 4D This is a graph illustrating an example of the relationship between the gain and output power of the first amplifier 21 and the second amplifier 22. The horizontal axis represents the output power of the differential amplifier circuit, and the vertical axis represents the gain. Figure 4D The solid and dashed lines represent the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22, respectively. Figure 4D The diagram illustrates an example where, at low output power, the gain G2 of the second amplifier 22 is higher than the gain G1 of the first amplifier 21. This gain difference arises because... Figure 1 The parasitic capacitances 30C and 60C of the input matching circuit 30 and the output matching circuit 60 shown in the figure cause a difference in the signal source impedance and load impedance between the first amplifier 21 and the second amplifier 22.

[0087] When the output power increases, the emitter voltage V of the first transistor 41... E1 The DC component increases, thus increasing the gain G1 of the first amplifier 21. This characteristic of increasing gain with increasing output power is called gain expansion. Accompanying the increase in output power, the emitter voltage V of the second transistor 42... E2 The DC component decreases, thus the gain G2 of the second amplifier 22 also decreases. With the gain G1 of the first amplifier 21 increasing and the gain G2 of the second amplifier 22 decreasing, at a specific output power, the two become approximately equal. This mitigates the gain asymmetry as the output power increases.

[0088] Next, refer to Figure 5This describes the operation of inductive coupling between the first coupling portion 31A of the primary coil 31 and the first intermediate portion 51B of the first bias wiring 51. Figure 5 This is an equivalent circuit diagram of the first amplifier 21, the second amplifier 22, the input matching circuit 30, the first bias circuit 40, the first bias wiring 51, and the second bias wiring 52 of the differential amplifier circuit in the first embodiment.

[0089] The first coupling portion 31A of the primary coil 31 of the input matching circuit 30 is inductively coupled to the first intermediate portion 51B of the first bias wiring 51. When a voltage is generated from one end 31T1 of the primary coil 31 to the other end 31T2, an induced voltage is generated in the secondary coil 32 from the end connected to the second amplifier 22 to the end connected to the first amplifier 21. Additionally, an induced voltage is generated in the first intermediate portion 51B of the first bias wiring 51 from the first amplifier 21 to the emitter of the first transistor 41.

[0090] When the high-frequency signal input to the first amplifier 21 deflects in the positive direction, the voltage generated at the emitter of the first transistor 41 is superimposed on the induced voltage generated in the first intermediate portion 51B, thereby increasing the deflection amplitude. Therefore, a voltage similar to... Figure 4A The emitter voltage V shown in the figure E1L The same voltage waveform. As a result, the asymmetry of gain can be mitigated when the output power increases.

[0091] As described above, the asymmetry of gain during output power rise can be mitigated in either case where the primary coil 31 of the input matching circuit 30 is considered to be capacitively coupled to the first intermediate portion 51B of the first bias wiring 51, or where inductive coupling is considered to be present.

[0092] Furthermore, assuming that the primary coil 31 of the input matching circuit 30 is capacitively coupled to the first intermediate portion 51B of the first bias wiring 51, the first coupling portion 31A of the primary coil 31 ( Figure 2 It needs to be located at the midpoint 31M from the primary coil 31. Figure 2 The portion extending from one end 31T2.

[0093] In contrast, when it is assumed that the primary coil 31 of the input matching circuit 30 is inductively coupled to the first intermediate portion 51B of the first bias wiring 51, there is no restriction on the portion of the primary coil 31 inductively coupled to the first intermediate portion 51B of the first bias wiring 51. Preferably, the first coupling portion 31A of the primary coil 31 ( Figure 5 The direction of inductive coupling with the first intermediate part 51B changes Figure 5The primary coil 31, the first bias wiring 51, the first amplifier 21, and the second amplifier 22 are configured in the direction shown in the diagram. For example, preferably, the polarity of the end of the first amplifier 21 side of the first intermediate portion 51B is opposite to the polarity of the end of the secondary coil 32 connected to the first amplifier 21.

[0094] Next, the superior effects of the first embodiment will be explained.

[0095] In the first embodiment, the following excellent effects can be obtained: Figure 4D As shown, the asymmetry between the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22 is mitigated when the output power increases. As a result, the degradation of the amplification characteristics of the differential amplifier circuit is suppressed.

[0096] Next, refer to Figure 6 The differential amplifier circuit of a modified example of the first embodiment will be described. Figure 6 This is a diagram showing the layout of multiple structural elements of a differential amplifier circuit in a modified example of the first embodiment. In the first embodiment ( Figure 2 In this configuration, the second bias wiring 52 used by the second amplifier 22 does not extend in the first direction D1 into the region where the first amplifier 21 is located. In contrast, in... Figure 6 In the modified example shown, the second bias wiring 52 extends along the first direction D1 to the region where the first amplifier 21 is disposed. The portion extending along the first direction D1 is referred to as the front end portion 52T of the second bias wiring 52.

[0097] The front end portion 52T of the second bias wiring 52 is disposed in the second direction D2 between the first amplifier connection portion 51A of the first bias wiring 51 and the primary coil 31 of the input matching circuit 30. Therefore, the first bias wiring 51 and the second bias wiring 52 cross between the first amplifier 21 and the second amplifier 22 in the first direction D1.

[0098] The front end portion 52T of the second bias wiring 52 is electromagnetically coupled to the primary coil 31 of the input matching circuit 30. Therefore, a voltage waveform corresponding to the high-frequency signal propagating in the primary coil 31 is generated at the front end portion 52T. Since the front end portion 52T is connected to the emitter of the second transistor 42 via the second amplifier connection portion 52A of the second bias wiring 52, its impact on the emitter voltage of the second transistor 42 is minimal. Therefore, even if the second bias wiring 52 extends along the first direction D1 and the front end portion 52T is provided, similar to the first embodiment, the excellent effect of mitigating the asymmetry between the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22 when the output power increases can be obtained.

[0099] like Figure 6As shown in the modified example, when the front end portion 52T is provided on the second bias wiring 52, the symmetry of the shape and configuration of the first bias wiring 51 and the second bias wiring 52 can be improved.

[0100] Next, a differential amplifier circuit of another variation of the first embodiment will be described. In the first embodiment, HBTs are used as the amplifying transistor 21Q of the first amplifier 21, the amplifying transistor 22Q of the second amplifier 22, and the first transistor 41 and second transistor 42 of the first bias circuit 40. However, MOSFETs can also be used as these transistors. When using MOSFETs, the emitter, collector, and base described above can be renamed as the source, drain, and gate, respectively. The emitter follower connection can be renamed as the source follower connection.

[0101] Furthermore, when using MOSFETs, the bias current supplied to the first amplifier 21 and the second amplifier 22 can be replaced with a bias voltage. Additionally, the bias control current I supplied to the first bias circuit 40... CONT1 It can be renamed bias control voltage.

[0102] [Second Embodiment]

[0103] Next, refer to Figures 7 to 11B The differential amplifier circuit of the second embodiment will be described with reference to the accompanying drawings. Hereinafter, references to the drawings will be omitted. Figures 1 to 5 The accompanying drawings illustrate the common structure of the differential amplifier circuit of the first embodiment.

[0104] Figure 7 This is an equivalent circuit diagram of the differential amplifier circuit of the second embodiment. In the second embodiment, in addition to the first bias circuit 40 included in the differential amplifier circuit of the first embodiment, a second bias circuit 70 is also included. The circuit structure of the second bias circuit 70 is the same as that of the first bias circuit 40. The second bias circuit 70 includes a third transistor 71, a fourth transistor 72, a capacitor 73, and a diode circuit 74. The third transistor 71 and the fourth transistor 72 are connected in emitter follower configuration.

[0105] The second bias circuit 70 provides bias current to the first amplifier 21 and the second amplifier 22, respectively. Specifically, the collectors of the third transistor 71 and the fourth transistor 72 are connected to the bias power supply voltage V. BAT Connections. The emitter of the third transistor 71 is connected to the first amplifier 21 via the first bias wiring 51, and the emitter of the fourth transistor 72 is connected to the second amplifier 22 via the second bias wiring 52.

[0106] The bias control circuit 77 provides bias control current I to the first bias circuit 40 and the second bias circuit 70 respectively. CONT1I CONT2 When a bias control current I is supplied to the first bias circuit 40 CONT1 When the first bias circuit 40 operates, the bias control current I stops. CONT1 When the bias current I is supplied, the first bias circuit 40 becomes inactive. Similarly, when the bias control current I is supplied to the second bias circuit 70... CONT2 When the second bias circuit 70 operates, the bias control current I stops. CONT2 When the supply is provided, the second bias circuit 70 becomes inactive.

[0107] Figure 8 This diagram illustrates the layout of various structural elements of the differential amplifier circuit according to the second embodiment. In the second embodiment, in addition to the first bias circuit 40, a second bias circuit 70 is formed on the semiconductor substrate 10. The second bias circuit 70 and the first bias circuit 40 are disposed together at a position that sandwiches the first amplifier 21 and the second amplifier 22 in the first direction D1. That is, the second bias circuit 70 is disposed in a region on the side opposite to the second amplifier 22 in the first direction D1 when viewed from the first amplifier 21.

[0108] The second intermediate portion 52B of the second bias wiring 52 is disposed between the first amplifier connection portion 51A of the first bias wiring 51 and the primary coil 31 of the input matching circuit 30, and extends along the first direction D1. The emitter of the fourth transistor 72 is connected to the second amplifier 22 via the second intermediate portion 52B. The first bias wiring 51 and the second bias wiring 52 intersect each other between the first amplifier connection portion 51A and the first intermediate portion 51B, and between the second amplifier connection portion 52A and the second intermediate portion 52B.

[0109] The second intermediate portion 52B of the second bias wiring 52 is electromagnetically coupled to the primary coil 31 of the input matching circuit 30. Therefore, when the second bias circuit 70 is activated, the gain G2 of the second amplifier 22 increases as the output power of the differential amplifier circuit increases. When the first bias circuit 40 is activated, the gain G2 of the second amplifier 22 increases as the output power of the differential amplifier circuit increases. Figure 4D Similarly, as the output power of the differential amplifier circuit increases, the gain G1 of the first amplifier 21 increases.

[0110] The signal source impedance and load impedance of the first amplifier 21 and the second amplifier 22 vary according to the frequency. Therefore, in a structure that increases the gain of one of the first amplifier 21 and the second amplifier 22, a situation arises where the gain asymmetry can be mitigated in a specific frequency band but not in other frequency bands.

[0111] Reference Figure 9A and Figure 9B This explains the operation of the differential amplifier circuit when it operates within a frequency range where the gain G1 of the first amplifier 21 is less than the gain G2 of the second amplifier 22, and the output power is sufficiently small.

[0112] Figure 9A This is an equivalent circuit diagram illustrating the operation of the differential amplifier circuit in the second embodiment. The bias control circuit 77 provides a bias control current I to the first bias circuit 40. CONT1 No bias control current I is provided to the second bias circuit 70. CONT2 Therefore, the first bias circuit 40 operates, and the second bias circuit 70 becomes inactive. Figure 9A In the diagram, thick lines represent the portions of the first bias wiring 51 and the second bias wiring 52 through which the bias current flows, and dashed lines represent the portions through which the bias current does not flow. This will be explained later. Figure 10A , Figure 11A The same applies to China.

[0113] Electromagnetic field coupling occurs between the first intermediate portion 51B of the first bias wiring 51 and the primary coil 31, resulting in a significant deflection of the emitter voltage of the first transistor 41 in the first bias circuit 40. Consequently, the first amplifier 21 exhibits a large self-biasing effect. In contrast, regarding the second bias wiring 52, the electromagnetic field coupling between the second intermediate portion 52B and the primary coil 31 does not significantly affect the emitter voltage of the second transistor 42. Therefore, the second amplifier 22 is less likely to exhibit a self-biasing effect.

[0114] Figure 9B This is a graph illustrating an example of the relationship between the gains G1 and G2 of the first amplifier 21 and the second amplifier 22 and their output power. The horizontal axis represents the output power, and the vertical axis represents the gain. Figure 9B The solid and dashed lines in the graph represent the gains G1 of the first amplifier 21 and G2 of the second amplifier 22, respectively. Within a sufficiently small output power range, the gain G1 of the first amplifier 21 is less than the gain G2 of the second amplifier 22. As the output power increases, the gain G1 of the first amplifier 21 increases due to the self-biasing effect. Therefore, the gain asymmetry can be mitigated when the output power increases.

[0115] Next, refer to Figure 10A and Figure 10B This explains the operation of the differential amplifier circuit when it operates within a frequency range where the gain G1 of the first amplifier 21 is greater than the gain G2 of the second amplifier 22, and the output power is sufficiently small.

[0116] Figure 10AThis is an equivalent circuit diagram illustrating the operation of the differential amplifier circuit in the second embodiment. The bias control circuit 77 provides a bias control current I to the second bias circuit 70. CONT2 No bias control current I is provided to the first bias circuit 40. CONT1 Therefore, the second bias circuit 70 operates, and the first bias circuit 40 becomes inactive.

[0117] Electromagnetic field coupling occurs between the second intermediate portion 52B of the second bias wiring 52 and the primary coil 31, resulting in a significant deflection of the emitter voltage of the fourth transistor 72 in the second bias circuit 70. Consequently, the second amplifier 22 exhibits a large self-biasing effect. In contrast, regarding the first bias wiring 51, the electromagnetic field coupling between the first intermediate portion 51B and the primary coil 31 does not significantly affect the emitter voltage of the third transistor 71. Therefore, the first amplifier 21 is less likely to exhibit a self-biasing effect.

[0118] Figure 10B This is a graph illustrating an example of the relationship between the gains G1 and G2 of the first amplifier 21 and the second amplifier 22 and their output power. The horizontal axis represents the output power, and the vertical axis represents the gain. Figure 10B The solid and dashed lines in the graph represent the gains G1 of the first amplifier 21 and G2 of the second amplifier 22, respectively. Within a sufficiently low output power range, the gain G1 of the first amplifier 21 is greater than the gain G2 of the second amplifier 22. As the output power increases, the gain G2 of the second amplifier 22 increases due to the self-biasing effect. Therefore, the gain asymmetry as the output power increases can be mitigated.

[0119] Next, refer to Figure 11A and Figure 11B This explains the operation of the differential amplifier circuit when it operates within a frequency range where the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22 are approximately equal, within a range where the output power is sufficiently small.

[0120] Figure 11A This is an equivalent circuit diagram illustrating the operation of the differential amplifier circuit in the second embodiment. The bias control circuit 77 provides bias control current I to the first bias circuit 40 and the second bias circuit 70, respectively. CONT1 I CONT2 Therefore, both the first bias circuit 40 and the second bias circuit 70 operate. When the output power increases, a large self-biasing effect is observed in both the first amplifier 21 and the second amplifier 22.

[0121] Figure 11B This is a graph illustrating an example of the relationship between the gains G1 and G2 of the first amplifier 21 and the second amplifier 22 and their output power. The horizontal axis represents the output power, and the vertical axis represents the gain. Figure 11BThe solid and dashed lines in the graph represent the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22, respectively. Within a sufficiently small output power range, the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22 are approximately equal. As the output power increases, both the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22 increase. Therefore, it is possible to maintain the symmetry of the gain as the output power increases while simultaneously increasing the upper limit of the output power.

[0122] Next, the superior effects of the second embodiment will be explained.

[0123] In the second embodiment, even in an asymmetric differential amplifier circuit where the relationship between the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22 varies depending on the operating frequency, the asymmetry can be mitigated when the output power increases. Therefore, operation over a wider frequency band is possible.

[0124] [Third Embodiment]

[0125] Next, refer to Figure 12 The differential amplifier circuit of the third embodiment will be described below. References will be omitted hereafter. Figures 7 to 11B The accompanying drawings illustrate the common structure of the differential amplifier circuit in the second embodiment.

[0126] Figure 12 This is a schematic top view showing the layout of the primary coil 31, first bias wiring 51, and second bias wiring 52 of the input matching circuit 30 of the differential amplifier circuit in the third embodiment. The first bias wiring 51 and the second bias wiring 52 are the same as in the second embodiment. Figure 8 The situations are similarly intersecting in a three-dimensional manner. The intersection 55 is located between the first amplifier connection portion 51A and the first intermediate portion 51B of the first bias wiring 51 and between the second amplifier connection portion 52A and the second intermediate portion 52B of the second bias wiring 52.

[0127] A power supply voltage V is applied to the midpoint 31M of the primary coil 31. CC Power supply voltage V CC The primary coil 31 is supplied to the preamplifier. The midpoint 31M and the crossover portion 55 of the primary coil 31 are arranged at approximately the same position in the first direction D1 and spaced apart in the second direction D2.

[0128] The intersection 55 of the first bias wiring 51 and the second bias wiring 52 is positioned, when viewed from the primary coil 31, in the second direction D2, at a position farther than either the first amplifier connection portion 51A of the first bias wiring 51 or the second amplifier connection portion 52A of the second bias wiring 52 than either of them.

[0129] exist Figure 12 Conductor patterns represented by relatively thick solid lines are arranged in the same first wiring layer, while conductor patterns represented by relatively thin solid lines are arranged in a second wiring layer different from the first wiring layer. For example, portions of the first bias wiring 51 and the second bias wiring 52, excluding the intersection 55, are arranged in a wiring layer different from the primary coil 31. Therefore, portions of the first bias wiring 51 and the second bias wiring 52, excluding the intersection 55, are arranged at a position far from the primary coil 31 in the thickness direction.

[0130] The second bias wiring 52 includes a conductor pattern at the intersection 55, disposed on the same first wiring layer as the primary coil 31. The conductor pattern at the intersection 55 does not move away from the primary coil 31 in the thickness direction, and is therefore close to the midpoint 31M of the primary coil 31. A power supply voltage V is applied to the midpoint 31M of the primary coil 31. CC Therefore, a high voltage is generated between the midpoint 31M of the primary coil 31 and the conductor pattern of the intersection 55.

[0131] Next, the superior effects of the third embodiment will be explained.

[0132] In the third embodiment, when viewed from the midpoint 31M of the primary coil 31, the crossover portion 55 is positioned in the second direction D2 further than either the first amplifier connection portion 51A of the first bias wiring 51 or the second amplifier connection portion 52A of the second bias wiring 52. This positional relationship acts in a direction that weakens the electric field strength generated between the conductor pattern of the midpoint 31M and the crossover portion 55. By weakening the electric field strength, the decrease in reliability caused by the generation of a strong electric field is suppressed.

[0133] [Fourth Embodiment]

[0134] Next, refer to Figure 13 The differential amplifier circuit of the fourth embodiment will be described below. References will be omitted hereafter. Figures 1 to 5 The accompanying drawings illustrate the common structure of the differential amplifier circuit of the first embodiment.

[0135] Figure 13 This is an equivalent circuit diagram of the first bias circuit 40 of the differential amplifier circuit in the fourth embodiment. In the fourth embodiment, a β-assisted bias circuit is used as the first bias circuit 40. In the first embodiment ( Figure 1 In the first embodiment, a diode circuit 44 is used to generate the base potential of the first bias circuit 40. In contrast, in the fourth embodiment, a decimation transistor 45 is used instead of the diode circuit 44. An HBT is used as the decimation transistor 45, and its collector is connected to the base of the first transistor 41 and the second transistor 42.

[0136] The emitter of the detached transistor 45 is connected to a reference potential. The base of the detached transistor 45 is connected to the emitter of the first transistor 41 via a resistor 46, and to the emitter of the second transistor 42 via a resistor 47. A capacitor 48 is connected between the base and emitter of the detached transistor 45.

[0137] The bias control current I supplied to the first bias circuit 40 CONT1 A portion of the current is pulled down to the reference potential via the pull-out transistor 45, and the remaining current is supplied to the bases of the first transistor 41 and the second transistor 42. The bias control current I is determined based on the emitter voltages of the first transistor 41 and the second transistor 42. CONT1 The pull-down current changes. As a result, negative feedback takes effect, stabilizing the emitter voltages of the first transistor 41 and the second transistor 42.

[0138] Next, the superior effects of the fourth embodiment will be explained.

[0139] In the fourth embodiment, the emitter voltages of the first transistor 41 and the second transistor 42 are stabilized. Therefore, the amplifying transistor 21Q of the first amplifier 21... Figure 1 ) and the amplifying transistor 22Q of the second amplifier 22 Figure 1 The base voltage of the amplifier is stabilized. As a result, the excessive drop in gain and output of the amplifier that does not exhibit self-biasing effect can be suppressed.

[0140] [Fifth Embodiment]

[0141] Next, refer to Figure 14 The differential amplifier circuit of the fifth embodiment will be described below. References will be omitted hereafter. Figures 1 to 5 The accompanying drawings illustrate the common structure of the differential amplifier circuit of the first embodiment.

[0142] Figure 14 This is the equivalent circuit diagram of the differential amplifier circuit in the fifth embodiment. In the first embodiment ( Figure 1 In the first embodiment, the input matching circuit 30 uses a balun that converts a single-ended signal into a differential signal. In contrast, in the fifth embodiment, the input signal to the input matching circuit 30 is also a differential signal. The two ends of the primary coil 31 of the input matching circuit 30 are respectively connected by the non-inverting signal RF of the input differential signal. INP and inverted signal RF INN That is, an impedance transformation transformer is used as the input matching circuit 30. The first intermediate portion 51B of the first bias wiring 51 is electromagnetically coupled to the primary coil 31 of the transformer.

[0143] Next, the superior effects of the fifth embodiment will be explained.

[0144] In the fifth embodiment, similar to the first embodiment, the following excellent effect can be obtained: when the output power increases, the asymmetry between the gain G1 of the first amplifier 21 and the gain G2 of the second amplifier 22 is mitigated.

[0145] Next, the differential amplifier circuit of a modified example of the fifth embodiment will be described.

[0146] In the fifth embodiment, a balun that converts the differential signal into a single-ended signal is used as the output matching circuit 60. As a variation of the fifth embodiment, a transformer that outputs the differential signal can also be used as the output matching circuit 60. When the operating output node of the output matching circuit 60 is connected to a subsequent differential amplifier circuit, sometimes the load impedance of the first amplifier 21 and the load impedance of the second amplifier 22 exhibit asymmetry due to the asymmetry of the subsequent differential amplifier circuit. In the variation of the fifth embodiment, this load impedance asymmetry can be mitigated.

[0147] [Sixth Embodiment]

[0148] Next, refer to Figure 15 The differential amplifier circuit of the sixth embodiment will be explained.

[0149] Figure 15 This is a block diagram of the differential amplifier circuit in the sixth embodiment. The input matching circuit 30 receives the high-frequency signal RF as a single-ended signal. IN The differential signal is converted into a differential signal. The differential signal output from the input matching circuit 30 is input to the first amplifier 21 and the second amplifier 22 that constitute the differential pair. The first amplifier 21 and the second amplifier 22 amplify the differential signal. The differential signal output from the first amplifier 21 and the second amplifier 22 is converted into a single-ended signal, a high-frequency signal RF, by the output matching circuit 60. OUT Output. To illustrate, consider the following example: When the input power is low, due to the asymmetry of the signal source impedance and load impedance between the first amplifier 21 and the second amplifier, the gain of the first amplifier 21 is less than the gain of the second amplifier 22.

[0150] The first bias circuit 83 and the second bias circuit 84 provide biases to the first amplifier 21 and the second amplifier 22, respectively. The first bias circuit 83 is configured to adjust the bias in the direction that increases the gain of the first amplifier 21 when the power of the differential signal input to the first amplifier 21 and the second amplifier 22 increases. The second bias circuit 84 is configured to adjust the bias in the direction that increases the gain of the second amplifier 22 when the power of the differential signal input to the first amplifier 21 and the second amplifier 22 increases, provided that the increase in the gain of the second amplifier 22 becomes less than the increase in the gain of the first amplifier 21. For example, the first bias circuit 83 and the second bias circuit 84 adjust the bias based on bias adjustment signals obtained from various circuit elements constituting the differential amplifier circuit.

[0151] In addition, the second bias circuit 84 can also be structured such that even if the power of the differential signal input to the first amplifier 21 and the second amplifier 22 increases, the gain of the second amplifier 22 will not increase.

[0152] As an example, the function of the first bias circuit 83 is as described in the first embodiment ( Figure 1 The first transistor 41 and the first bias wiring 51 coupled to the electromagnetic field of the primary coil 31 are used to implement the second bias circuit 84. The function of the second bias circuit 84 is, for example, achieved through the first embodiment (…). Figure 1 This is achieved through a second transistor 42 and a second bias wiring 52 that is not coupled to the electromagnetic field of the primary coil 31.

[0153] Next, the superior effects of the sixth embodiment will be explained.

[0154] In the sixth embodiment, similar to the first embodiment, the following excellent effect can be obtained: when the input power and output power of the differential amplifier circuit increase, the asymmetry of the gain of the first amplifier 21 and the second amplifier 22 is mitigated.

[0155] Next, refer to Figures 16 to 19 The accompanying drawings illustrate the differential amplifier circuits of various modifications of the sixth embodiment. Figures 16 to 19 The accompanying drawings are block diagrams of differential amplifier circuits for various modifications of the sixth embodiment. In the modifications described below, the sixth embodiment is shown (…). Figure 15 Example of the structure of the first bias circuit 83 and the second bias circuit 84.

[0156] exist Figure 16 In the modified example shown, the first bias circuit 83 includes a first bias generating section 83A and a first branch section 83B, and the second bias circuit 84 includes a second bias generating section 84A and a second branch section 84B. The first bias generating section 83A and the second bias generating section 84A respectively output bias current.

[0157] The first branch 83B and the second branch 84B are respectively inserted into one transmission line and the other transmission line of the primary coil side of the input matching circuit 30. The first branch 83B and the second branch 84B generate a bias adjustment signal based on the input signal of the input matching circuit 30. The bias current output from the first bias generation unit 83A is supplemented with the bias adjustment signal generated by the first branch 83B, and the total current is input to the first amplifier 21 as a bias current. Similarly, the bias current output from the second bias generation unit 84A is supplemented with the bias adjustment signal generated by the second branch 84B, and the total current is input to the second amplifier 22 as a bias current.

[0158] Thus, in Figure 16 In the modified example shown, the bias adjustment signal used to adjust the bias is obtained from a high-frequency signal transmitted in the transmission line on the primary coil side of the input matching circuit 30. If the second bias circuit 84 does not have the function of adjusting the bias in the direction that increases the gain of the second amplifier 22, the second branch 84B may not be inserted.

[0159] exist Figure 17 In the modified example shown, the first branch 83B and the second branch 84B are... Figure 16 The inductive coupling circuits 83C and 84C are used. The induced current generated by the high-frequency signal transmitted in the transmission line on the primary coil side of the input matching circuit 30 is used as the bias adjustment signal.

[0160] By adjusting the coupling coefficients of the inductive coupling circuits 83C and 84C, the gain increase of the first amplifier 21 and the second amplifier 22 can be adjusted.

[0161] exist Figure 18 In the modified example shown, the first branch 83D and the second branch 84D are respectively inserted into one transmission line and the other transmission line of the secondary coil side of the input matching circuit 30. Thus, it can also be configured such that the bias adjustment signal is obtained from the high-frequency signal transmitted in the transmission line on the secondary coil side of the input matching circuit 30.

[0162] exist Figure 19 In the modified example shown, the first branch 83D ( Figure 18 The capacitor 83E is composed of a capacitor. The capacitor 83E is capacitively coupled to the bias current path from the first bias generator 83A to the first amplifier 21 via the transmission line on the secondary coil side of the input matching circuit 30. Similarly, the second branch 84D ( Figure 18It is composed of capacitor 84E. Capacitor 84E is capacitively coupled to the bias current path from the second bias generator 84A to the second amplifier 22 through the transmission line on the secondary coil side of the input matching circuit 30.

[0163] Thus, it can also be configured as follows: the bias adjustment signal is obtained from the transmission line on the secondary coil side of the input matching circuit 30 via a capacitive coupling circuit. Furthermore, as... Figure 18 The first branch 83D and the second branch 84D can also be as follows: Figure 17 The inductive coupling circuit is used as shown in the modified example. Additionally, as... Figure 16 The first branch 83B and the second branch 84B of the modified example shown can also use capacitive coupling circuits.

[0164] The above embodiments are illustrative, and it is self-evident that the structures shown in different embodiments can be partially replaced or combined. The same effects resulting from the same structures in multiple embodiments are not mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, various changes, improvements, and combinations are possible, which will be apparent to those skilled in the art.

[0165] Explanation of reference numerals in the attached figures

[0166] 10: Semiconductor substrate; 21: First amplifier; 21C: Input capacitor; 21I: Input node; 21O: Output node; 21Q: Amplifying transistor; 21R: Ballast resistor; 22: Second amplifier; 22C: Input capacitor; 22I: Input node; 22O: Output node; 22Q: Amplifying transistor; 22R: Ballast resistor; 30: Input matching circuit; 30C: Parasitic capacitance; 31: Primary coil; 31A: First coupling portion; 31M: Midpoint of primary coil; 31T1, 31T2: Ends of primary coil; 32: Secondary coil; 40: First bias circuit; 41: First transistor; 42: Second transistor; 43: Capacitor; 44: Diode circuit; 45: Extracted transistor; 46, 47: Resistor; 48: Capacitor; 51: First bias wiring; 51A: First amplifier connection portion of the first bias wiring. 51B: First intermediate portion of the first bias wiring; 52: Second bias wiring; 52A: Second amplifier connection portion of the second bias wiring; 52B: Second intermediate portion of the second bias wiring; 52T: Front end portion of the second bias wiring; 55: Crossover portion; 60: Output matching circuit; 60C: Parasitic capacitance; 61: Primary coil; 62: Secondary coil; 70: Second bias circuit; 71: Third transistor; 72: Fourth transistor; 73: Capacitor; 74: Diode circuit; 77: Bias control circuit; 83: First bias circuit; 83A: First bias generation section; 83B: First branch section; 83C: Inductive coupling circuit; 83D: First branch section; 83E: Capacitor; 84: Second bias circuit; 84A: Second bias generation section; 84B: Second branch section; 84C: Inductive coupling circuit; 84D: Second branch section; 84E: Capacitor.

Claims

1. A differential amplifier circuit, comprising: A first amplifier and a second amplifier for amplifying differential signals; An input matching circuit includes a primary coil and a secondary coil that are inductively coupled to each other. The two ends of the secondary coil are respectively connected to the input node of the first amplifier and the input node of the second amplifier. The input matching circuit outputs the high-frequency signal input to the primary coil from the secondary coil. A first bias circuit provides bias to the first amplifier and the second amplifier, respectively; The first bias wiring connects the first bias circuit to the first amplifier, forming a bias-providing path; The second bias wiring connects the first bias circuit to the second amplifier, forming a bias supply path; as well as A substrate is formed on the substrate, comprising the first amplifier, the second amplifier, the input matching circuit, the first bias circuit, the first bias wiring, and the second bias wiring. The first bias circuit includes a first transistor and a second transistor that are either emitter-follower or source-follower connected. The collector or drain of the first transistor and the second transistor is connected to a bias power supply voltage. The emitter or source of the first transistor is connected to the first amplifier via the first bias wiring, and the emitter or source of the second transistor is connected to the second amplifier via the second bias wiring. The first amplifier and the second amplifier are arranged along a first direction parallel to the surface of the substrate, and the first transistor and the second transistor are arranged in a region on the side opposite to the first amplifier in the first direction when viewed from the second amplifier. The first bias wiring includes a first intermediate portion disposed in the second bias wiring between a second amplifier connection portion connected to the second amplifier and the primary coil and extending along the first direction, the first intermediate portion connecting the first amplifier connection portion in the first bias wiring to the first transistor.

2. The differential amplifier circuit according to claim 1, wherein, The primary coil includes a first coupling portion that is spaced apart from the first intermediate portion and extends along the first direction. No other portion of the primary coil is disposed between the first coupling portion and the first intermediate portion. The first coupling portion is located from the end of the primary coil that exhibits the same polarity as the end of the secondary coil connected to the first amplifier, to the midpoint of the primary coil.

3. The differential amplifier circuit according to claim 1 or 2, wherein, It also includes a second bias circuit, which is formed on the substrate and provides bias to the first amplifier and the second amplifier, respectively. The second bias circuit includes a third transistor and a fourth transistor with emitter-follower or source-follower connections. The collector or drain of the third transistor and the fourth transistor is connected to a bias power supply voltage. The emitter or source of the third transistor is connected to the first amplifier via the first bias wiring, and the emitter or source of the fourth transistor is connected to the second amplifier via the second bias wiring. The second bias wiring includes a second intermediate portion disposed between the first amplifier connection portion of the first bias wiring and the primary coil and extending along the first direction, the second intermediate portion connecting the second amplifier connection portion to the fourth transistor.

4. The differential amplifier circuit according to claim 3, wherein, Between the first amplifier connection portion and the first intermediate portion of the first bias wiring, and between the second amplifier connection portion and the second intermediate portion of the second bias wiring, the first bias wiring and the second bias wiring intersect each other three-dimensionally. The portion where the first bias wiring and the second bias wiring intersect each other is positioned at a location that, when viewed from the primary coil, is farther than either the first amplifier connection portion of the first bias wiring or the second amplifier connection portion of the second bias wiring in a direction orthogonal to the first direction.

5. The differential amplifier circuit according to any one of claims 1 to 4, wherein, The first bias circuit includes: A de-emitter transistor, wherein the collector of the de-emitter transistor is connected to the base or gate of the first transistor and the second transistor, and the emitter of the de-emitter transistor is connected to a reference potential. A first resistive element is connected between the emitter or source of the first transistor and the base of the withdrawing transistor; and A second resistive element is connected between the emitter or source of the second transistor and the base of the extraction transistor.

6. A differential amplifier circuit, comprising: A first amplifier and a second amplifier for amplifying differential signals; An input matching circuit includes a primary coil and a secondary coil that are inductively coupled to each other. The two ends of the secondary coil are respectively connected to the input node of the first amplifier and the input node of the second amplifier. The input matching circuit outputs the high-frequency signal input to the primary coil from the secondary coil. A first bias circuit provides bias to the first amplifier; as well as The second bias circuit provides bias to the second amplifier. The first bias circuit is configured such that when the power of the differential signal input to the first amplifier and the second amplifier increases, the bias is adjusted in the direction that increases the gain of the first amplifier. The second bias circuit is configured such that when the power of the differential signal input to the first amplifier and the second amplifier increases, the bias is adjusted in the direction that increases the gain of the second amplifier, provided that the increase in gain is less than the increase in gain of the first amplifier, or the gain of the second amplifier is not increased.

7. The differential amplifier circuit according to claim 6, wherein, The first bias circuit changes the bias based on a bias adjustment signal obtained from a high-frequency signal transmitted in the transmission line of one of the primary coil side and the secondary coil side.

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