High speed high bandwidth rail-to-rail operational amplifier

Abstract

The application discloses a high-speed high-bandwidth rail-to-rail operational amplifier, and relates to the technical field of analog integrated circuits. The operational amplifier comprises a rail-to-rail input stage, a gain stage, an output stage, an AB bias stage, a compensation circuit, a common-mode state detection circuit and an adaptive feedforward circuit. The common source of a PMOS differential input pair in the rail-to-rail input stage forms a common-mode state sensing node, and the common-mode state detection circuit forms a control voltage at a control node according to the potential change of the node. The adaptive feedforward circuit comprises a first feedforward branch, a second feedforward branch and a control voltage conversion branch. The first feedforward adjusting PMOS tube in the first feedforward branch is controlled by the control voltage. The control voltage conversion branch forms a second control voltage according to the control voltage to control the second feedforward adjusting NMOS tube in the second feedforward branch. The equivalent impedance of the two feedforward branches can be adjusted according to the common-mode working state of the rail-to-rail input stage, and the consistency of transient response under different input common-mode working states can be improved.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a high-speed, high-bandwidth rail-to-rail operational amplifier. Background Technology

[0002] Operational amplifiers are fundamental functional units in analog integrated circuits, widely used in circuits for signal conditioning, data acquisition, sensor interfaces, analog-to-digital conversion, and feedback control. With the increasing demands for low-voltage power supplies and high-speed signal processing, operational amplifiers typically need to achieve a wide input common-mode range within a limited power supply voltage range, while also maintaining high bandwidth and fast transient response.

[0003] Existing rail-to-rail operational amplifiers typically employ complementary PMOS differential input pairs and NMOS differential input pairs to extend the input common-mode range. During changes in the input common-mode voltage, the operating states of the PMOS and NMOS differential input pairs change, potentially causing variations in the input stage's equivalent transconductance, branch currents, and the operating states of subsequent internal nodes. This results in differences in the operational amplifier's frequency and transient responses under different input common-mode voltage conditions.

[0004] To improve the transient response speed of operational amplifiers, existing technologies may incorporate feedforward paths to couple transient changes at the output or internal nodes to the preceding or gain stage nodes, thereby shortening the signal propagation process and improving transient response. However, such feedforward structures typically employ capacitors, resistors, or other impedance devices with fixed parameters, and their propagation characteristics are essentially determined after the circuit design is completed.

[0005] When the input common-mode voltage of a rail-to-rail operational amplifier changes, the operating state of the input stage and the electrical characteristics of the internal nodes of the subsequent stages may change accordingly. However, the feedforward structure with fixed parameters maintains relatively fixed transfer characteristics. Therefore, insufficient transient response consistency may occur under different operating states within a wide input common-mode range. Furthermore, if the feedforward effect is too weak, its improvement on transient response is limited; if the feedforward effect is too strong, it may affect the dynamic response of the main amplification path. Summary of the Invention

[0006] To address the issue that in existing rail-to-rail operational amplifiers, the operating state of the complementary differential input pair varies with the input common-mode voltage, while the fixed-parameter feedforward structure maintains relatively fixed transfer characteristics under different input common-mode operating states, potentially leading to insufficient transient response consistency, this invention provides a high-speed, high-bandwidth rail-to-rail operational amplifier. This amplifier obtains common-mode state information from the common source of the PMOS differential input pair and generates a control voltage based on this information. The control voltage directly adjusts the first feedforward regulating PMOS transistor in the first feedforward branch, and a second control voltage is generated through a control voltage conversion branch to adjust the second feedforward regulating NMOS transistor in the second feedforward branch. This allows the equivalent impedance of the first and second feedforward branches to be adjusted accordingly based on the common-mode operating state of the rail-to-rail input stage. The invention employs the following technical solution: A high-speed, high-bandwidth rail-to-rail operational amplifier includes a rail-to-rail input stage, a gain stage, an output stage, an AB bias stage, a compensation circuit, a common-mode state detection circuit, and an adaptive feedforward circuit.

[0007] The rail-to-rail input stage includes complementary PMOS differential input pairs and NMOS differential input pairs. The common source of the PMOS differential input pairs forms a common-mode state sensing node. The rail-to-rail input stage is configured to receive differential input signals and convert the differential input signals into differential currents.

[0008] The gain stage is connected to the rail-to-rail input stage. The gain stage has a first gain control node, a second gain control node, a first output drive node, and a second output drive node. It is configured to form a first control potential at the first gain control node and a second control potential at the second gain control node based on the differential current. It also forms a first drive potential at the first output drive node and a second drive potential at the second output drive node based on the first control potential and the second control potential, respectively.

[0009] The output stage is connected to the first output driver node and the second output driver node, and generates an output voltage at the output node according to the first drive potential and the second drive potential.

[0010] The AB bias stage is connected between the first output driver node and the second output driver node, and establishes a static potential relationship between the first output driver node and the second output driver node to statically bias the output stage.

[0011] The compensation circuit includes a first compensation branch connected between the first output driving node and the output node, and a second compensation branch connected between the second output driving node and the output node. The first compensation branch and the second compensation branch respectively perform frequency compensation on the signal transmission from the first output driving node and the second output driving node to the output node.

[0012] The common-mode state detection circuit is connected to the common-mode state sensing node and has a control node. The common-mode state detection circuit generates a control voltage in the control node that characterizes the common-mode operating state of the rail-to-rail input stage based on the potential change of the common-mode state sensing node.

[0013] The adaptive feedforward circuit includes a first feedforward branch, a second feedforward branch, and a control voltage conversion branch. The first feedforward branch is connected between the output node and the first gain control node, and the second feedforward branch is connected between the output node and the second gain control node. The first feedforward branch includes a first feedforward capacitor and a first feedforward regulating PMOS transistor connected in series, with the gate of the first feedforward regulating PMOS transistor connected to the control node. The control voltage conversion branch connects to the control node and forms a conversion control node, generating a second control voltage at the conversion control node based on the control voltage. The second feedforward branch includes a second feedforward capacitor and a second feedforward regulating NMOS transistor connected in series, with the gate of the second feedforward regulating NMOS transistor connected to the conversion control node. Thus, the conduction levels of the first feedforward regulating PMOS transistor and the second feedforward regulating NMOS transistor are changed according to the control voltage and the second control voltage, respectively, thereby adjusting the equivalent impedance of the first and second feedforward branches.

[0014] The above scheme combines the common-mode state sensing of the rail-to-rail input stage with two transient feedforward branches, enabling the common-mode state detection circuit to generate a control voltage based on the potential change at the common source of the PMOS differential input. This control voltage directly acts on the first feedforward regulating PMOS transistor and, through a control voltage conversion branch, forms a second control voltage for controlling the second feedforward regulating NMOS transistor. This allows the equivalent impedance of the first and second feedforward branches to be adjusted according to the common-mode operating state of the rail-to-rail input stage, which helps improve the consistency of feedforward action and transient response under different input common-mode operating states.

[0015] Preferably, the rail-to-rail input stage further includes a first bias PMOS transistor and a first bias NMOS transistor; the source of the first bias PMOS transistor is connected to the power supply terminal, the gate is connected to the first bias voltage terminal, and the drain is connected to the common-mode state sensing node; the PMOS differential input pair includes a first input PMOS transistor and a second input PMOS transistor, the sources of the first input PMOS transistor and the second input PMOS transistor are jointly connected to the common-mode state sensing node, and the gates are respectively connected to the non-inverting input terminal and the inverting input terminal; the NMOS differential input pair includes a first input NMOS transistor and a second input NMOS transistor, the sources of the first input NMOS transistor and the second input NMOS transistor are jointly connected to the drain of the first bias NMOS transistor, and the gates are respectively connected to the non-inverting input terminal and the inverting input terminal; the gate of the first bias NMOS transistor is connected to the second bias voltage terminal, and the source is grounded.

[0016] The first bias PMOS transistor and the first bias NMOS transistor provide bias current to the PMOS differential input pair and the NMOS differential input pair, respectively, so that the PMOS differential input pair and the NMOS differential input pair can form differential current according to the differential input signal between the non-inverting input terminal and the inverting input terminal during the input common-mode voltage change, thereby expanding the input common-mode range of the operational amplifier.

[0017] Preferably, the gain stage includes a first gain PMOS transistor, a second gain PMOS transistor, a first gain NMOS transistor, and a second gain NMOS transistor. The sources of the first gain PMOS transistor and the second gain PMOS transistor are connected to the power supply terminal, and their gates are both connected to the first gain control node. The gate and drain of the first gain PMOS transistor are interconnected. The drain of the second input NMOS transistor is connected to the first gain control node. The drain of the second gain PMOS transistor and the drain of the first input NMOS transistor are both connected to form the first output drive node. Alternatively, the sources of the first gain NMOS transistor and the second gain NMOS transistor are grounded, and their gates are both connected to the second gain control node. The gate and drain of the first gain NMOS transistor are interconnected. The drain of the second input PMOS transistor is connected to the second gain control node. The drain of the second gain NMOS transistor and the drain of the first input PMOS transistor are both connected to form the second output drive node.

[0018] The above scheme uses gain transistors on the PMOS and NMOS sides to further convert the differential current generated by the rail-to-rail input stage into corresponding control potentials and output drive potentials, so that the first output drive node and the second output drive node can drive the subsequent output transistors respectively.

[0019] Preferably, the AB bias stage includes an AB bias PMOS transistor and an AB bias NMOS transistor; the source of the AB bias PMOS transistor is connected to the first output driving node, the drain is connected to the second output driving node, and the gate is connected to the first AB bias voltage terminal; the drain of the AB bias NMOS transistor is connected to the first output driving node, the source is connected to the second output driving node, and the gate is connected to the second AB bias voltage terminal.

[0020] The above scheme establishes a static potential relationship between the AB bias PMOS transistor and the AB bias NMOS transistor between the first output drive node and the second output drive node, thereby providing static bias conditions for the output stage.

[0021] Preferably, the output stage includes a PMOS output transistor and an NMOS output transistor; the source of the PMOS output transistor is connected to the power supply terminal, the gate is connected to the first output driving node, and the drain is connected to the output node; the source of the NMOS output transistor is grounded, the gate is connected to the second output driving node, and the drain is connected to the output node.

[0022] The first compensation branch includes a first compensation capacitor connected between the first output driver node and the output node; the second compensation branch includes a second compensation capacitor connected between the second output driver node and the output node. The first and second compensation capacitors respectively form corresponding frequency compensation paths to improve the frequency response stability of the operational amplifier.

[0023] Preferably, the common-mode state detection circuit includes a detection NMOS transistor, a protection PMOS transistor, and a state transition PMOS transistor. The gates of the detection NMOS transistor and the protection PMOS transistor are jointly connected to the common-mode state sensing node, and the source of the state transition PMOS transistor is connected to the common-mode state sensing node; the drain of the detection NMOS transistor is connected to the switching reference voltage terminal, and the sources of the detection NMOS transistor, the protection PMOS transistor, and the gate of the state transition PMOS transistor are jointly connected; the drain of the protection PMOS transistor is grounded, and the drain of the state transition PMOS transistor forms a state current node.

[0024] The detection NMOS transistor, the protection PMOS transistor, and the state transition PMOS transistor together constitute a common-mode state transition branch. Based on the potential change of the common-mode state sensing node, a corresponding state current is generated at the state current node, thereby converting the common-mode operating state of the rail-to-rail input stage into a current signal that can be further processed.

[0025] More preferably, the common-mode state detection circuit further includes a first mirror NMOS transistor and a second mirror NMOS transistor; the gate and drain of the first mirror NMOS transistor are connected to each other and are jointly connected to the state current node, and the gate of the second mirror NMOS transistor is connected to the state current node; the sources of both the first mirror NMOS transistor and the second mirror NMOS transistor are grounded, and the drain of the second mirror NMOS transistor is connected to the control node to form a mirror current flowing from the control node to ground and corresponding to the state current.

[0026] Through the aforementioned current mirror structure, the state current is correspondingly introduced into the control node, enabling the common-mode operating state to further affect the current balance relationship of the control node.

[0027] More preferably, the common-mode state detection circuit further includes a control PMOS transistor and a bias current source; the source of the control PMOS transistor is connected to the power supply terminal, and the gate and drain are connected to each other and jointly connected to the control node; the drain of the second mirror NMOS transistor is connected to the control node, and the bias current source is connected between the control node and ground, with the current direction of the bias current source pointing from the control node to ground.

[0028] The control PMOS transistor, the bias current source, and the second mirror NMOS transistor together form the current balance relationship of the control node, so that the mirror current change corresponding to the common-mode operating state can be converted into the control voltage change at the control node, providing control quantity for the adaptive adjustment of the subsequent feedforward branch.

[0029] Preferably, the first feedforward branch includes a first feedforward capacitor and a first feedforward regulating PMOS transistor, the second feedforward branch includes a second feedforward capacitor and a second feedforward regulating NMOS transistor, and the control voltage conversion branch includes a mirror PMOS transistor and a voltage conversion NMOS transistor; One end of the first feedforward capacitor is connected to the output node, and the other end is connected to the source of the first feedforward adjustment PMOS transistor. The drain of the first feedforward adjustment PMOS transistor is connected to the first gain control node, and the gate is connected to the control node. One end of the second feedforward capacitor is connected to the output node, and the other end is connected to the drain of the second feedforward adjustment NMOS transistor. The source of the second feedforward adjustment NMOS transistor is connected to the second gain control node, and the gate is connected to the switching control node. The source of the mirrored PMOS transistor is connected to the power supply terminal, the gate is connected to the control node, and the drain is connected to the switching control node; the source of the voltage-converting NMOS transistor is grounded, and the gate and drain are connected to each other and together to the switching control node. The mirror PMOS transistor and the control PMOS transistor form a current mirror relationship, and the voltage conversion NMOS transistor forms the second control voltage at the conversion control node, so that the conduction degree of the first feedforward adjustment PMOS transistor and the second feedforward adjustment NMOS transistor is adjusted accordingly with the common mode operating state of the rail-to-rail input stage.

[0030] In the above scheme, when the control voltage changes with the common-mode operating state of the rail-to-rail input stage, the conduction degree of the first feedforward adjustment PMOS transistor changes accordingly. At the same time, the control voltage conversion branch generates a correspondingly changing second control voltage based on the control voltage, causing the conduction degree of the second feedforward adjustment NMOS transistor to change accordingly. This adjusts the equivalent impedance of the first feedforward branch and the second feedforward branch, so that the transient voltage change generated by the output node can be coupled to the first gain control node and the second gain control node with the propagation conditions corresponding to the current common-mode operating state.

[0031] More preferably, the system further includes a control holding capacitor, one end of which is connected to the control node and the other end is grounded. The control holding capacitor filters the control voltage to reduce the impact of control node voltage fluctuations on the conduction level of the first feedforward regulation PMOS transistor and the second control voltage formed by the control voltage conversion branch.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) This invention utilizes the common source of the PMOS differential input pair to form a common-mode state sensing node, and forms a control voltage characterizing the common-mode operating state of the rail-to-rail input stage through a common-mode state detection circuit, thereby obtaining potential information related to the common-mode operating state of the rail-to-rail input stage, and providing a control basis for the adaptive adjustment of the feedforward branch.

[0033] (2) The present invention utilizes the control voltage to directly regulate the first feedforward regulating PMOS transistor in the first feedforward branch, and forms a second control voltage through the control voltage conversion branch to regulate the second feedforward regulating NMOS transistor in the second feedforward branch. This enables the two feedforward branches corresponding to the PMOS side gain branch and the NMOS side gain branch to adopt the corresponding type of regulating device, and makes the equivalent impedance of the two feedforward branches adjusted accordingly with the common-mode operating state of the rail-to-rail input stage. Compared with the feedforward structure with fixed parameters, it is beneficial to improve the consistency of feedforward effect and transient response under different input common-mode operating states.

[0034] (3) The present invention establishes a static potential relationship between the first output driving node and the second output driving node through the AB bias stage, provides static bias for the output stage, and forms a frequency compensation path through the first compensation branch and the second compensation branch, which is beneficial to maintain the static operating conditions of the output stage and the frequency response stability of the operational amplifier while introducing an adaptive feedforward structure. Attached Figure Description

[0035] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Elements in the drawings are not necessarily to scale. The same reference numerals refer to corresponding similar parts.

[0036] Figure 1 This is a schematic diagram of the overall architecture of a high-speed, high-bandwidth rail-to-rail operational amplifier according to a specific embodiment of the present invention; Figure 2 This is a circuit diagram of a high-speed, high-bandwidth rail-to-rail operational amplifier according to a specific embodiment of the present invention.

[0037] The meanings of the numbers in the diagram are as follows: 01-Rail-to-rail input stage; 02-Gain stage; 03-Output stage; 04-AB bias stage; 051-First compensation branch; 052-Second compensation branch; 06-Common mode state detection circuit; 071-First feedforward branch; 072-Second feedforward branch; 073-Control voltage conversion branch.

[0038] P1 - First bias PMOS transistor; P2 - First input PMOS transistor; P3 - Second input PMOS transistor; N1 - First input NMOS transistor; N2 - Second input NMOS transistor; N3 - First bias NMOS transistor; P4 - First gain PMOS transistor; P5 - Second gain PMOS transistor; N4 - First gain NMOS transistor; N5 - Second gain NMOS transistor; P6 - AB bias PMOS transistor; N6 - AB bias NMOS transistor; P7 - PMOS output transistor; N7 - NMOS output transistor; N8 - Detection NMOS transistor; P8 - Protection PMOS transistor; P9 - State transition PMOS transistor; N9 - First mirror NMOS transistor; N10 - Second mirror NMOS transistor; P10 - Control PMOS transistor; P11 - First feedforward adjustment PMOS transistor; N11 - Second feedforward adjustment NMOS transistor P12 - Mirror PMOS transistor; N12 - Voltage conversion NMOS transistor; C1 - First compensation capacitor; C2 - Second compensation capacitor; C3 - First feedforward capacitor; C4 - Second feedforward capacitor; C5 - Control holding capacitor; IB - Bias current source; VIN+ - Non-inverting input; VIN - Inverting input; VCMX - Common-mode state sensing node; XP - First gain control node; XN - Second gain control node; GP - First output drive node; GN - Second output drive node; VCTRL - Control node; VCTRLLB - Conversion control node; VOUT - Output node; VCC - Power supply; GND - Ground; VB1 - First bias voltage terminal; VB2 - Second bias voltage terminal; VBP - First AB bias voltage terminal; VBN - Second AB bias voltage terminal; VREF - Switching reference voltage terminal. Detailed Implementation

[0039] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present invention are shown in the accompanying drawings.

[0040] In the description of this invention, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a circuit or device comprising a list of elements includes not only those elements but also other elements not expressly listed. The terms "first," "second," etc., are used only to distinguish identical or similar technical features and should not be construed as indicating or implying relative importance.

[0041] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly, for example, it can refer to a direct electrical connection or an indirect electrical connection through other circuit elements; "grounding" refers to the reference ground potential of the corresponding circuit. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0042] See Figure 1 This is a schematic diagram of the overall architecture of a high-speed, high-bandwidth rail-to-rail operational amplifier provided by an embodiment of the present invention. The high-speed, high-bandwidth rail-to-rail operational amplifier includes a rail-to-rail input stage 01, a gain stage 02, an output stage 03, an AB bias stage 04, a compensation circuit, a common-mode state detection circuit 06, and an adaptive feedforward circuit. The compensation circuit includes a first compensation branch 051 and a second compensation branch 052; the adaptive feedforward circuit includes a first feedforward branch 071, a second feedforward branch 072, and a control voltage conversion branch 073.

[0043] The rail-to-rail input stage 01 is connected to the non-inverting input terminal VIN+ and the inverting input terminal VIN-, respectively, to receive the differential input signal formed by the non-inverting input terminal VIN+ and the inverting input terminal VIN-, and convert the differential input signal into a differential current. The rail-to-rail input stage 01 is connected to the gain stage 02. The gain stage 02 generates a first control potential and a second control potential based on the differential current at the first gain control node XP and the second gain control node XN, and further generates a first drive potential and a second drive potential at the first output drive node GP and the second output drive node GN.

[0044] Output stage 03 is connected to the first output drive node GP and the second output drive node GN, and generates an output voltage at output node VOUT according to the first drive potential and the second drive potential. AB bias stage 04 is connected between the first output drive node GP and the second output drive node GN, and establishes a static potential relationship between the two output drive nodes, thereby statically biasing output stage 03.

[0045] The first compensation branch 051 is connected between the first output driver node GP and the output node VOUT, and the second compensation branch 052 is connected between the second output driver node GN and the output node VOUT to form a corresponding frequency compensation path.

[0046] The rail-to-rail input stage 01 also forms a common-mode state sensing node VCMX, which is connected to the common-mode state detection circuit 06. Based on the potential change of the common-mode state sensing node VCMX, the common-mode state detection circuit 06 generates a control voltage at the control node VCTRL that characterizes the common-mode operating state of the rail-to-rail input stage 01.

[0047] The first feedforward branch 071 is connected between the output node VOUT and the first gain control node XP, and its control terminal is connected to the control node VCTRL; the control voltage conversion branch 073 is connected to the control node VCTRL and forms the conversion control node VCTRLLB, and a second control voltage is formed in the conversion control node VCTRLLB according to the control voltage at the control node VCTRL; the second feedforward branch 072 is connected between the output node VOUT and the second gain control node XN, and its control terminal is connected to the conversion control node VCTRLLB.

[0048] Therefore, the control voltage generated by the common-mode state detection circuit 06 can directly adjust the feedforward propagation condition of the first feedforward branch 071. Simultaneously, a second control voltage is formed through the control voltage conversion branch 073 to adjust the second feedforward branch 072, allowing the equivalent impedance of the first and second feedforward branches 071 and 072 to be adjusted accordingly based on the common-mode operating state of the rail-to-rail input stage 01. The transient voltage change of the output node VOUT can be coupled to the first gain control node XP and the second gain control node XN via the first and second feedforward branches 071 and 072, respectively.

[0049] Depend on Figure 1 As shown in the overall architecture, this embodiment forms a main amplification path and a common-mode state adaptive feedforward path that cooperate with each other. The main amplification path is formed by sequentially connecting the rail-to-rail input stage 01, the gain stage 02, and the output stage 03, which is used to complete the conversion, amplification, and output of the differential input signal. The common-mode state adaptive feedforward path uses the common-mode state sensing node VCMX to obtain the common-mode operating state of the rail-to-rail input stage 01, generates a control voltage through the common-mode state detection circuit 06, and uses the first feedforward branch 071, the second feedforward branch 072, and the control voltage conversion branch 073 to adjust the transient propagation conditions between the output node VOUT and the first gain control node XP and the second gain control node XN.

[0050] See Figure 2 ,for Figure 1 The diagram shows a specific transistor-level circuit structure for a high-speed, high-bandwidth rail-to-rail operational amplifier. Figure 2 The track-to-track input stage 01, gain stage 02, output stage 03, AB bias stage 04, first compensation branch 051, second compensation branch 052, common-mode state detection circuit 06, first feedforward branch 071, second feedforward branch 072, and control voltage conversion branch 073 are shown in dashed boxes.

[0051] In this embodiment, the power supply terminal VCC provides the power supply potential for the operational amplifier, and ground GND serves as the reference ground potential for the circuit. The first bias voltage terminal VB1 and the second bias voltage terminal VB2 provide bias voltages to the first bias PMOS transistor P1 and the first bias NMOS transistor N3, respectively, to establish the corresponding bias operating conditions for the PMOS differential input pair and the NMOS differential input pair. The first AB bias voltage terminal VBP and the second AB bias voltage terminal VBN provide bias voltages to the AB bias PMOS transistor P6 and the AB bias NMOS transistor N6, respectively, to establish a static potential relationship between the first output drive node GP and the second output drive node GN. The switching reference voltage terminal VREF provides the reference potential corresponding to the common-mode state transition to the detection NMOS transistor N8. The bias voltage terminals and switching reference voltage terminals in this application represent electrical connection nodes used to receive corresponding preset voltages and are not limited to external pins of the operational amplifier chip.

[0052] In a specific embodiment, the rail-to-rail input stage 01 includes a first bias PMOS transistor P1, a first input PMOS transistor P2, a second input PMOS transistor P3, a first input NMOS transistor N1, a second input NMOS transistor N2, and a first bias NMOS transistor N3.

[0053] The source of the first bias PMOS transistor P1 is connected to the power supply terminal VCC, the gate is connected to the first bias voltage terminal VB1, and the drain is connected to the common-mode state sensing node VCMX.

[0054] The first input PMOS transistor P2 and the second input PMOS transistor P3 form a PMOS differential input pair. The sources of the first input PMOS transistor P2 and the second input PMOS transistor P3 are connected to the common-mode state sensing node VCMX; the gate of the first input PMOS transistor P2 is connected to the non-inverting input terminal VIN+, and the gate of the second input PMOS transistor P3 is connected to the inverting input terminal VIN-.

[0055] The first input NMOS transistor N1 and the second input NMOS transistor N2 form an NMOS differential input pair. The sources of the first input NMOS transistor N1 and the second input NMOS transistor N2 are connected to the drain of the first bias NMOS transistor N3; the gate of the first input NMOS transistor N1 is connected to the non-inverting input terminal VIN+, and the gate of the second input NMOS transistor N2 is connected to the inverting input terminal VIN-. The gate of the first bias NMOS transistor N3 is connected to the second bias voltage terminal VB2, and the source is connected to ground GND.

[0056] The first bias PMOS transistor P1 and the first bias NMOS transistor N3 provide bias current to the PMOS differential input pair and the NMOS differential input pair, respectively. When there is a voltage difference between the non-inverting input terminal VIN+ and the inverting input terminal VIN-, the PMOS differential input pair P2 and P3 and the NMOS differential input pair N1 and N2 change the current distribution of their corresponding branches according to the voltage difference, thereby converting the differential input signal into differential current. As the input common-mode voltage changes, the operating state of the two sets of complementary differential input pairs changes accordingly, enabling the rail-to-rail input stage 01 to complete differential signal conversion over a wide range of input common-mode voltages.

[0057] Meanwhile, the common source of the first input PMOS transistor P2 and the second input PMOS transistor P3 forms a common-mode state sensing node VCMX. Since the common-mode state sensing node VCMX serves as both the common source node of the PMOS differential input pair and the detection input node of the common-mode state detection circuit 06, it can utilize the existing nodes of the rail-to-rail input stage 01 to obtain potential information related to its common-mode operating state, providing a detection basis for subsequent common-mode state detection and feedforward adjustment.

[0058] In a specific embodiment, the gain stage 02 includes a first gain PMOS transistor P4, a second gain PMOS transistor P5, a first gain NMOS transistor N4, and a second gain NMOS transistor N5.

[0059] The sources of the first-gain PMOS transistor P4 and the second-gain PMOS transistor P5 are connected to the power supply terminal VCC. The gates of the first-gain PMOS transistor P4 and the second-gain PMOS transistor P5 are connected to the first-gain control node XP. The gate and drain of the first-gain PMOS transistor P4 are interconnected and connected to the first-gain control node XP. The drain of the second-input NMOS transistor N2 is connected to the first-gain control node XP. The drain of the second-gain PMOS transistor P5 and the drain of the first-input NMOS transistor N1 are connected to form the first output drive node GP.

[0060] The sources of the first-gain NMOS transistor N4 and the second-gain NMOS transistor N5 are connected to ground GND. The gates of the first-gain NMOS transistor N4 and the second-gain NMOS transistor N5 are connected to the second gain control node XN. The gate and drain of the first-gain NMOS transistor N4 are interconnected and connected to the second gain control node XN. The drain of the second-input PMOS transistor P3 is connected to the second gain control node XN. The drain of the second-gain NMOS transistor N5 and the drain of the first-input PMOS transistor P2 are connected to form the second output drive node GN.

[0061] Through the above connections, the first-gain PMOS transistor P4 and the second-gain PMOS transistor P5 form the PMOS-side gain branch corresponding to the first gain control node XP, and the first-gain NMOS transistor N4 and the second-gain NMOS transistor N5 form the NMOS-side gain branch corresponding to the second gain control node XN. The differential current generated by the rail-to-rail input stage 01 can form the first control potential and the second control potential at the first gain control node XP and the second gain control node XN, respectively, and further form the first drive potential and the second drive potential at the first output drive node GP and the second output drive node GN, thereby realizing the conversion from the input stage differential current to the output stage 03 drive potential.

[0062] In a specific embodiment, the AB bias stage 04 includes an AB bias PMOS transistor P6 and an AB bias NMOS transistor N6.

[0063] The source of the AB-biased PMOS transistor P6 is connected to the first output drive node GP, the drain is connected to the second output drive node GN, and the gate is connected to the first AB bias voltage terminal VBP; the drain of the AB-biased NMOS transistor N6 is connected to the first output drive node GP, the source is connected to the second output drive node GN, and the gate is connected to the second AB bias voltage terminal VBN.

[0064] The first AB bias voltage terminal VBP and the second AB bias voltage terminal VBN provide bias conditions to the AB bias PMOS transistor P6 and the AB bias NMOS transistor N6, respectively, so that the first output drive node GP and the second output drive node GN establish a corresponding static potential relationship, and the output stage 03 is statically biased by the static potential relationship, so that the output stage 03 forms the corresponding working conditions in the static state, and performs complementary driving when the output voltage changes.

[0065] In a specific embodiment, output stage 03 includes a PMOS output transistor P7 and an NMOS output transistor N7.

[0066] The source of PMOS output transistor P7 is connected to the power supply terminal VCC, the gate is connected to the first output drive node GP, and the drain is connected to the output node VOUT; the source of NMOS output transistor N7 is connected to ground GND, the gate is connected to the second output drive node GN, and the drain is connected to the output node VOUT.

[0067] When the potential of the first output drive node GP decreases, the conduction level of PMOS output transistor P7 increases, resulting in a stronger pull-up effect on output node VOUT. When the potential of the second output drive node GN increases, the conduction level of NMOS output transistor N7 increases, resulting in a stronger pull-down effect on output node VOUT. Therefore, output stage 03 can change the conduction levels of PMOS output transistor P7 and NMOS output transistor N7 according to the first and second drive potentials, and generate a corresponding output voltage at output node VOUT, achieving mutually complementary discharge drive for output node VOUT.

[0068] In a specific embodiment, the first compensation branch 051 includes a first compensation capacitor C1, and the second compensation branch 052 includes a second compensation capacitor C2.

[0069] One end of the first compensation capacitor C1 is connected to the first output drive node GP, and the other end is connected to the output node VOUT; one end of the second compensation capacitor C2 is connected to the second output drive node GN, and the other end is connected to the output node VOUT. The first compensation capacitor C1 and the second compensation capacitor C2 form frequency compensation paths between the first output drive node GP and the output node VOUT, and between the second output drive node GN and the output node VOUT, respectively. By performing frequency compensation on the corresponding signal transmission paths, it is beneficial to improve the frequency response stability of the main amplification path of the operational amplifier.

[0070] In a specific embodiment, the common-mode state detection circuit 06 includes a detection NMOS transistor N8, a protection PMOS transistor P8, a state transition PMOS transistor P9, a first mirror NMOS transistor N9, a second mirror NMOS transistor N10, a control PMOS transistor P10, and a bias current source IB.

[0071] The gate of the detection NMOS transistor N8 is connected to the common-mode state sensing node VCMX, and its drain is connected to the switching reference voltage terminal VREF. The gate of the protection PMOS transistor P8 is connected to the common-mode state sensing node VCMX. The source of the detection NMOS transistor N8, the source of the protection PMOS transistor P8, and the gate of the state transition PMOS transistor P9 are connected together to form the first state control node.

[0072] The drain of the protection PMOS transistor P8 is connected to ground GND; the source of the state transition PMOS transistor P9 is connected to the common-mode state sensing node VCMX, and the drain of the state transition PMOS transistor P9 forms a state current node.

[0073] The detection NMOS transistor N8, the protection PMOS transistor P8, and the state transition PMOS transistor P9 together constitute the common-mode state transition branch. When the potential of the common-mode state sensing node VCMX changes with the input common-mode voltage, the operating state of the detection NMOS transistor N8 changes accordingly, thereby changing the potential of the first state control node and the gate of the state transition PMOS transistor P9. This causes a change in the conduction level of the state transition PMOS transistor P9, and a state current corresponding to the current common-mode operating state is formed at the state current node.

[0074] It should be noted that the protection PMOS transistor P8 is not used to continuously generate a pull-down current from the first state control node to ground (GND) during the conduction of the detection NMOS transistor N8. When the common-mode state sensing node VCMX is within the potential range that turns on the detection NMOS transistor N8, the first state control node can establish a corresponding node potential under the action of the detection NMOS transistor N8. When the common-mode state sensing node VCMX changes from a higher potential to a lower potential and causes the detection NMOS transistor N8 to tend to turn off, due to the charge in the gate capacitance of the state transition PMOS transistor P9 and the parasitic capacitance of the first state control node, the potential of the first state control node cannot instantaneously decrease synchronously with the common-mode state sensing node VCMX. When the first state control node forms a source-gate voltage relative to the common-mode state sensing node VCMX that turns on the protection PMOS transistor P8, the protection PMOS transistor P8 turns on, forming a charge release path from the first state control node through the protection PMOS transistor P8 to ground (GND), thereby releasing the residual charge on the first state control node, allowing the gate potential of the state transition PMOS transistor P9 to complete the corresponding transition with the common-mode operating state. Therefore, the protection PMOS transistor P8 is mainly used for node charge release during common-mode state changes, rather than as a constant DC pull-down load for detecting NMOS transistor N8.

[0075] The gate and drain of the first mirror NMOS transistor N9 are interconnected and share a common state current node; the gate of the second mirror NMOS transistor N10 is also connected to the state current node. The sources of both the first mirror NMOS transistor N9 and the second mirror NMOS transistor N10 are connected to ground GND, and the drain of the second mirror NMOS transistor N10 is connected to the control node VCTRL.

[0076] The first mirror NMOS transistor N9 converts the state current into the gate-source control condition corresponding to the current mirror. The second mirror NMOS transistor N10 forms a mirror current corresponding to the state current, which flows from the control node VCTRL to ground GND based on the gate-source control condition. This further converts the common-mode operating state of the rail-to-rail input stage 01 into a current change acting on the control node VCTRL.

[0077] The source of the control PMOS transistor P10 is connected to the power supply terminal VCC. The gate and drain of the control PMOS transistor P10 are interconnected and connected to the control node VCTRL. The bias current source IB is connected between the control node VCTRL and ground GND, and its current direction is from the control node VCTRL to ground GND.

[0078] Therefore, the control PMOS transistor P10 forms a current path from the power supply terminal VCC to the control node VCTRL, and the second mirror NMOS transistor N10 and the bias current source IB form current paths from the control node VCTRL to ground GND. The control PMOS transistor P10, the second mirror NMOS transistor N10, and the bias current source IB together form the current balance relationship of the control node VCTRL, and generate the control voltage at the control node VCTRL corresponding to the current common-mode operating state.

[0079] When a change in the state current causes a change in the mirror current formed by the second mirror NMOS transistor N10, the original current balance state of the control node VCTRL changes accordingly, causing a corresponding change in the control voltage at the control node VCTRL. The current balance is then re-established by controlling the change in the conduction level of the PMOS transistor P10. Therefore, the common-mode state detection circuit 06 can convert the common-mode operating state reflected by the common-mode state sensing node VCMX into the control voltage at the control node VCTRL, providing control input for subsequent adaptive feedforward regulation.

[0080] Furthermore, in this embodiment, one end of the control holding capacitor C5 is connected to the control node VCTRL, and the other end is connected to ground GND. The control holding capacitor C5 is used to filter the control voltage on the control node VCTRL to reduce the impact of voltage fluctuations superimposed on the control node VCTRL on the conduction degree of subsequent feedforward regulation devices.

[0081] In a specific embodiment, the first feedforward branch 071 includes a first feedforward capacitor C3 and a first feedforward regulating PMOS transistor P11; the second feedforward branch 072 includes a second feedforward capacitor C4 and a second feedforward regulating NMOS transistor N11; and the control voltage conversion branch 073 includes a mirror PMOS transistor P12 and a voltage conversion NMOS transistor N12.

[0082] One end of the first feedforward capacitor C3 is connected to the output node VOUT, and the other end is connected to the source of the first feedforward adjustment PMOS transistor P11; the drain of the first feedforward adjustment PMOS transistor P11 is connected to the first gain control node XP, and the gate is connected to the control node VCTRL.

[0083] One end of the second feedforward capacitor C4 is connected to the output node VOUT, and the other end is connected to the drain of the second feedforward adjustment NMOS transistor N11; the source of the second feedforward adjustment NMOS transistor N11 is connected to the second gain control node XN, and the gate is connected to the switching control node VCTRLB.

[0084] The source of the mirrored PMOS transistor P12 is connected to the power supply terminal VCC, the gate is connected to the control node VCTRL, and the drain is connected to the switching control node VCTRLLB. The source of the voltage-converting NMOS transistor N12 is connected to ground GND, and its gate and drain are interconnected and jointly connected to the switching control node VCTRLLB, thus forming a diode connection structure for the voltage-converting NMOS transistor N12. The switching control node VCTRLLB is the node formed by connecting the drain of the mirrored PMOS transistor P12, the gate and drain of the voltage-converting NMOS transistor N12, and the gate of the second feedforward regulating NMOS transistor N11.

[0085] Both the source of the control PMOS transistor P10 and the mirror PMOS transistor P12 are connected to the power supply terminal VCC, and their gates are both connected to the control node VCTRL. The control PMOS transistor P10 uses a diode configuration with its gate and drain connected, thus forming a current mirror branch with the mirror PMOS transistor P12. The mirror PMOS transistor P12 generates a corresponding output current based on the gate-source control voltage formed at the control node VCTRL. The correspondence between the output current and the current in the control PMOS transistor P10 can be set by the ratio of their device dimensions.

[0086] Therefore, the control voltage at the control node VCTRL directly acts on the gate of the first feedforward regulation PMOS transistor P11, and is converted into the second control voltage at the conversion control node VCTRLLB through the mirror PMOS transistor P12 and the voltage conversion NMOS transistor N12. The second control voltage further acts on the gate of the second feedforward regulation NMOS transistor N11.

[0087] In this embodiment, the first gain control node XP corresponds to the PMOS-side gain branch, and the second gain control node XN corresponds to the NMOS-side gain branch. The first feedforward branch 071 uses a first feedforward adjustment PMOS transistor P11 to adjust the feedforward propagation condition between the output node VOUT and the first gain control node XP, and the second feedforward branch 072 uses a second feedforward adjustment NMOS transistor N11 to adjust the feedforward propagation condition between the output node VOUT and the second gain control node XN, so that the two feedforward branches can respectively use MOS transistors adapted to the operating potential of the corresponding gain control nodes for feedforward impedance adjustment.

[0088] In specific implementation, the device size ratio of the control PMOS transistor P10 to the mirror PMOS transistor P12, the width-to-length ratio of the voltage conversion NMOS transistor N12, and the device parameters of the first feedforward regulation PMOS transistor P11 and the second feedforward regulation NMOS transistor N11 can be set according to the semiconductor process adopted and the static operating potential of the first gain control node XP, the second gain control node XN, the control node VCTRL and the conversion control node VCTRLLB. This allows the conversion control node VCTRLLB to form a gate-source control voltage relative to the second gain control node XN for adjusting the conduction level of the second feedforward regulation NMOS transistor N11.

[0089] Within the predetermined operating range, when the control voltage at control node VCTRL decreases, the gate-source control voltage of the first feedforward regulating PMOS transistor P11 increases accordingly, increasing the conduction level of the first feedforward regulating PMOS transistor P11. Simultaneously, the gate-source control voltage of the mirror PMOS transistor P12 increases, causing the current supplied by the mirror PMOS transistor P12 to the switching control node VCTRLLB to increase accordingly. The diode-connected voltage-converting NMOS transistor N12 generates a correspondingly increased second control voltage at the switching control node VCTRLLB based on the current, thus increasing the conduction level of the second feedforward regulating NMOS transistor N11. When the control voltage at control node VCTRL increases, the above process reverses accordingly, decreasing the conduction levels of the first feedforward regulating PMOS transistor P11 and the second feedforward regulating NMOS transistor N11. Therefore, the equivalent impedance of the first feedforward branch 071 and the second feedforward branch 072 can be adjusted accordingly based on the common-mode operating state.

[0090] It should be noted that the specific correspondence between the above-mentioned control voltage, the second control voltage, and the conduction degree of each MOSFET is related to the semiconductor process, the threshold voltage of the MOSFET, the device size ratio, and the static operating potential of each node. The corresponding device parameters can be set according to the target common-mode input range and the feedforward adjustment range. This embodiment does not limit the specific device size ratio and control voltage value.

[0091] The first feedforward capacitor C3 and the second feedforward capacitor C4 are used to couple the transient voltage change of the output node VOUT to the first gain control node XP and the second gain control node XN, respectively. When the first feedforward regulating PMOS transistor P11 and the second feedforward regulating NMOS transistor N11 are in their respective on states, the transient voltage change of the output node VOUT can be transmitted to the first gain control node XP and the second gain control node XN through the first feedforward branch 071 and the second feedforward branch 072, respectively.

[0092] It should be further explained that, in this embodiment, the first feedforward branch 071 and the second feedforward branch 072 are capacitively coupled branches for transient enhancement. The transient voltage change of the output node VOUT is coupled to the first gain control node XP and the second gain control node XN via the first feedforward capacitor C3 and the second feedforward capacitor C4, which can form a transient positive feedback effect to assist the original output change direction, thereby assisting the output node VOUT in voltage conversion.

[0093] For example, when the output node VOUT changes to a higher potential, the first feedforward capacitor C3 and the second feedforward capacitor C4 couple the positive transient change to the first gain control node XP and the second gain control node XN, respectively. The transient rise of the first gain control node XP reduces the conduction level of the second gain PMOS transistor P5, making it easier for the first output drive node GP to change to a lower potential, thereby enhancing the pull-up effect of the PMOS output transistor P7 on the output node VOUT; the transient rise of the second gain control node XN increases the conduction level of the second gain NMOS transistor N5, making it easier for the second output drive node GN to change to a lower potential, thereby weakening the pull-down effect of the NMOS output transistor N7. These effects together assist the output node VOUT in transitioning to a higher potential.

[0094] When the output node VOUT changes to a low potential, its operation is reversed. The negative transient change of the output node VOUT is coupled to the first gain control node XP and the second gain control node XN through the first feedforward capacitor C3 and the second feedforward capacitor C4, respectively. This increases the conduction level of the second gain PMOS transistor P5 and decreases the conduction level of the second gain NMOS transistor N5. Consequently, the first output drive node GP changes to a higher potential and the second output drive node GN changes to a higher potential. This weakens the pull-up effect of the PMOS output transistor P7 and strengthens the pull-down effect of the NMOS output transistor N7, thereby assisting the output node VOUT to switch to a low potential.

[0095] Therefore, the first feedforward branch 071 and the second feedforward branch 072 can bypass part of the signal transmission process in the main amplification path and couple the transient change of the output node VOUT to the first gain control node XP and the second gain control node XN respectively, thereby assisting the charging and discharging process of the output stage 03.

[0096] It should be further explained that in the rail-to-rail input stage 01, as the input common-mode voltage changes, the operating states of the PMOS differential input pairs P2 and P3 and the NMOS differential input pairs N1 and N2, as well as their respective differential signal conversion functions, change accordingly. This causes the operating state of the rail-to-rail input stage 01 in providing differential current to the gain stage 02, as well as the operating conditions of the first gain control node XP and the second gain control node XN, to change accordingly. If a feedforward branch with fixed parameters is used between the output node VOUT and the first gain control node XP and the second gain control node XN, the corresponding feedforward action cannot be adjusted according to the changes in the aforementioned common-mode operating state.

[0097] Therefore, in this embodiment, the common source of the first input PMOS transistor P2 and the second input PMOS transistor P3 is used to form a common-mode state sensing node VCMX, and the potential change of the common-mode state sensing node VCMX is converted into a control voltage at the control node VCTRL through the aforementioned common-mode state detection circuit 06, so that the control voltage can characterize the current common-mode operating state of the rail-to-rail input stage 01.

[0098] The control voltage directly regulates the first feedforward regulating PMOS transistor P11 in the first feedforward branch 071, and forms a second control voltage for controlling the second feedforward regulating NMOS transistor N11 via the control voltage conversion branch 073, thereby regulating the equivalent impedance of the first feedforward branch 071 and the second feedforward branch 072 respectively. Therefore, this embodiment does not change the capacitance values ​​of the first feedforward capacitor C3 and the second feedforward capacitor C4 themselves, but rather changes the transient propagation conditions between the output node VOUT and the first gain control node XP and the second gain control node XN by adjusting the conduction degree of the MOS transistors in the two feedforward branches.

[0099] The parameters of the first feedforward capacitor C3, the second feedforward capacitor C4, the first feedforward regulating PMOS transistor P11, and the second feedforward regulating NMOS transistor N11 can be set according to the transient response and frequency stability requirements of the operational amplifier. The first compensation capacitor C1 and the second compensation capacitor C2 respectively compensate for the frequency transmission of the signal from the first output drive node GP and the second output drive node GN to the output node VOUT. Thus, by combining transient feedforward and frequency compensation, while using the first feedforward branch 071 and the second feedforward branch 072 to assist the output node VOUT in transient transition, the impact of excessive feedforward on the dynamic response of the main amplification path is reduced. The specific device parameters of the first feedforward capacitor C3, the second feedforward capacitor C4, the first compensation capacitor C1, the second compensation capacitor C2, and the related MOS transistors can be determined through circuit simulation and testing based on semiconductor process, load conditions, target bandwidth, and stability requirements.

[0100] Among them, the control holding capacitor C5 plays a different role from the first feedforward capacitor C3 and the second feedforward capacitor C4. The first feedforward capacitor C3 and the second feedforward capacitor C4 are located in the first feedforward branch 071 and the second feedforward branch 072, respectively, and are used to transmit the transient voltage changes of the output node VOUT; the control holding capacitor C5 is connected between the control node VCTRL and ground GND, and is not located in the above-mentioned transient feedforward signal path, but is used to filter the control voltage at the control node VCTRL, so as to reduce the influence of voltage fluctuations at the control node VCTRL on the first feedforward regulating PMOS transistor P11 and the second control voltage formed through the control voltage conversion branch 073.

[0101] Therefore, the common-mode state detection circuit 06 and the control node VCTRL mainly undertake the detection of the common-mode operating state and the formation of the first control quantity. The control voltage conversion branch 073 undertakes the conversion from the control voltage to the second control voltage. The first feedforward branch 071 and the second feedforward branch 072 mainly undertake the capacitive coupling and feedforward transmission of the transient changes of the output node VOUT. The control holding capacitor C5 is used to filter the control voltage. By distinguishing the common-mode state adjustment path from the output transient transmission path, it is possible to adjust the equivalent impedance of the two feedforward branches using the common-mode operating state while allowing the first feedforward capacitor C3 and the second feedforward capacitor C4 to continue to bear the role of transmitting the output transient changes.

[0102] The following is combined Figure 1 and Figure 2 The overall working process of this embodiment will be described.

[0103] When the non-inverting input terminal VIN+ and the inverting input terminal VIN- receive a differential input signal, the PMOS differential input pairs P2 and P3 and the NMOS differential input pairs N1 and N2 in the rail-to-rail input stage 01 change the current distribution in their respective branches according to the input voltage difference, thus forming a differential current. After being processed by the gain stage 02, the differential current forms a first control potential and a second control potential at the first gain control node XP and the second gain control node XN, and further forms a first drive potential and a second drive potential at the first output drive node GP and the second output drive node GN.

[0104] The first driving potential is applied to the gate of PMOS output transistor P7 in output stage 03, and the second driving potential is applied to the gate of NMOS output transistor N7, causing the output node VOUT to form the corresponding output voltage. In AB bias stage 04, AB bias PMOS transistor P6 and AB bias NMOS transistor N6 establish a static potential relationship between the first output drive node GP and the second output drive node GN; the first compensation branch 051 and the second compensation branch 052 respectively form corresponding frequency compensation paths between the first output drive node GP, the second output drive node GN, and the output node VOUT.

[0105] Meanwhile, the potential of the common-mode state sensing node VCMX changes with the common-mode operating state of the rail-to-rail input stage 01. The common-mode state detection circuit 06 converts this potential change sequentially into a state current, a mirror current, and a control voltage at the control node VCTRL.

[0106] The control voltage acts directly on the first feedforward regulating PMOS transistor P11 and simultaneously on the mirror PMOS transistor P12 in the control voltage conversion branch 073. The mirror PMOS transistor P12 and the diode-connected voltage conversion NMOS transistor N12 form a second control voltage at the conversion control node VCTRLLB based on the control voltage. This second control voltage acts on the second feedforward regulating NMOS transistor N11. Therefore, the conduction levels of the first feedforward regulating PMOS transistor P11 and the second feedforward regulating NMOS transistor N11 can be adjusted according to the common-mode operating state of the rail-to-rail input stage 01, thereby changing the equivalent impedance of the first feedforward branch 071 and the second feedforward branch 072.

[0107] When the output node VOUT undergoes a transient change, the first feedforward capacitor C3 couples the transient change to the first gain control node XP through the first feedforward adjustment PMOS transistor P11, and the second feedforward capacitor C4 couples the transient change to the second gain control node XN through the second feedforward adjustment NMOS transistor N11, thereby assisting the potential transition of the first output drive node GP and the second output drive node GN, and further assisting the output stage O3 in charging or discharging the output node VOUT.

[0108] Therefore, in this embodiment, the main amplification path is constructed using the rail-to-rail input stage 01, gain stage 02, and output stage 03; a common-mode state adaptive feedforward path is constructed using the common-mode state sensing node VCMX, common-mode state detection circuit 06, control node VCTRL, control voltage conversion branch 073, first feedforward branch 071, and second feedforward branch 072; and the AB bias stage 04, first compensation branch 051, and second compensation branch 052 are used to provide static bias and frequency compensation for the output stage, respectively. This allows the transmission conditions of the feedforward branch to be adjusted according to the common-mode operating state of the rail-to-rail input stage 01, which helps improve the consistency of feedforward action and transient response under different input common-mode operating states, while also ensuring the frequency response stability of the main amplification path.

[0109] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the specific embodiments described above. Without departing from the concept of this invention, the aspect ratio or other device size parameters, bias voltage, current source current, capacitor parameters, and current mirror ratio of each MOSFET can be adaptively set according to specific semiconductor processes, power supply voltages, load conditions, and application requirements.

Claims

1. A high-speed, high-bandwidth rail-to-rail operational amplifier, characterized in that, include: The rail-to-rail input stage includes complementary PMOS differential input pairs and NMOS differential input pairs, wherein the common source of the PMOS differential input pairs forms a common-mode state sensing node, and the rail-to-rail input stage is configured to receive differential input signals and convert the differential input signals into differential currents. A gain stage, connected to the rail-to-rail input stage, has a first gain control node, a second gain control node, a first output drive node, and a second output drive node, and is configured to form a first control potential at the first gain control node and a second control potential at the second gain control node based on the differential current, and to form a first drive potential at the first output drive node and a second drive potential at the second output drive node based on the first control potential and the second control potential, respectively. An output stage, connected to the first output driver node and the second output driver node, is configured to generate an output voltage at the output node based on the first drive potential and the second drive potential. An AB bias stage, connected between the first output driver node and the second output driver node, is configured to establish a static potential relationship between the first output driver node and the second output driver node to statically bias the output stage. The compensation circuit includes a first compensation branch connected between the first output driving node and the output node, and a second compensation branch connected between the second output driving node and the output node. The first compensation branch and the second compensation branch are configured to perform frequency compensation on the signal transmission from the first output driving node and the second output driving node to the output node, respectively. A common-mode state detection circuit, connected to the common-mode state sensing node, and having a control node, is configured to generate a control voltage characterizing the common-mode operating state of the rail-to-rail input stage at the control node based on the potential change of the common-mode state sensing node. as well as An adaptive feedforward circuit includes a first feedforward branch, a second feedforward branch, and a control voltage conversion branch. The first feedforward branch is connected between the output node and the first gain control node, and the second feedforward branch is connected between the output node and the second gain control node. The first feedforward branch includes a first feedforward capacitor and a first feedforward regulating PMOS transistor connected in series, with the gate of the first feedforward regulating PMOS transistor connected to the control node. The control voltage conversion branch is connected to the control node and forms a conversion control node, configured to generate a second control voltage at the conversion control node based on the control voltage. The second feedforward branch includes a second feedforward capacitor and a second feedforward regulating NMOS transistor connected in series, with the gate of the second feedforward regulating NMOS transistor connected to the conversion control node, to adjust the conduction levels of the first feedforward regulating PMOS transistor and the second feedforward regulating NMOS transistor according to the control voltage and the second control voltage, respectively, and to adjust the equivalent impedance of the first feedforward branch and the second feedforward branch.

2. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 1, characterized in that, The rail-to-rail input stage also includes a first bias PMOS transistor and a first bias NMOS transistor; The source of the first bias PMOS transistor is connected to the power supply terminal, the gate is connected to the first bias voltage terminal, and the drain is connected to the common-mode state sensing node. The PMOS differential input pair includes a first input PMOS transistor and a second input PMOS transistor. The sources of the first input PMOS transistor and the second input PMOS transistor are connected to the common-mode state sensing node, and their gates are connected to the non-inverting input terminal and the inverting input terminal, respectively. The NMOS differential input pair includes a first input NMOS transistor and a second input NMOS transistor. The sources of the first input NMOS transistor and the second input NMOS transistor are connected to the drain of the first bias NMOS transistor, and their gates are respectively connected to the non-inverting input terminal and the inverting input terminal. The gate of the first bias NMOS transistor is connected to the second bias voltage terminal, and the source is grounded; the first bias PMOS transistor and the first bias NMOS transistor provide bias currents for the PMOS differential input pair and the NMOS differential input pair, respectively. The PMOS differential input pair and the NMOS differential input pair are configured to form the differential current based on the differential input signal between the non-inverting input terminal and the inverting input terminal during the input common-mode voltage change.

3. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 2, characterized in that, The gain stage includes a first gain PMOS transistor, a second gain PMOS transistor, a first gain NMOS transistor, and a second gain NMOS transistor; The sources of the first gain PMOS transistor and the second gain PMOS transistor are connected to the power supply terminal, and their gates are connected to the first gain control node. The gate and drain of the first gain PMOS transistor are connected to each other. The drain of the second input NMOS transistor is connected to the first gain control node. The drain of the second gain PMOS transistor and the drain of the first input NMOS transistor are connected together to form the first output drive node. The sources of the first gain NMOS transistor and the second gain NMOS transistor are grounded, and their gates are connected to the second gain control node. The gate and drain of the first gain NMOS transistor are connected to each other. The drain of the second input PMOS transistor is connected to the second gain control node. The drain of the second gain NMOS transistor and the drain of the first input PMOS transistor are connected to form the second output drive node. The first gain PMOS transistor, the second gain PMOS transistor, the first gain NMOS transistor, and the second gain NMOS transistor are configured to form the first control potential and the second control potential at the first gain control node and the second gain control node, respectively, according to the differential current, and to form the first drive potential and the second drive potential at the first output drive node and the second output drive node, respectively.

4. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 3, characterized in that, The AB bias stage includes an AB bias PMOS transistor and an AB bias NMOS transistor; The source of the AB bias PMOS transistor is connected to the first output drive node, the drain is connected to the second output drive node, and the gate is connected to the first AB bias voltage terminal. The drain of the AB-biased NMOS transistor is connected to the first output drive node, the source is connected to the second output drive node, and the gate is connected to the second AB bias voltage terminal. The AB-biased PMOS transistor and the AB-biased NMOS transistor together establish the static potential relationship between the first output driving node and the second output driving node to statically bias the output stage.

5. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 3, characterized in that, The output stage includes PMOS output transistors and NMOS output transistors; The source of the PMOS output transistor is connected to the power supply terminal, the gate is connected to the first output drive node, and the drain is connected to the output node. The source of the NMOS output transistor is grounded, the gate is connected to the second output drive node, and the drain is connected to the output node. The first compensation branch includes a first compensation capacitor, which is connected between the first output driving node and the output node; The second compensation branch includes a second compensation capacitor, which is connected between the second output driving node and the output node. The first compensation capacitor and the second compensation capacitor form frequency compensation paths between the first output driving node and the output node and between the second output driving node and the output node, respectively.

6. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 2, characterized in that, The common-mode state detection circuit includes a detection NMOS transistor, a protection PMOS transistor, and a state transition PMOS transistor; The gate of the detection NMOS transistor and the gate of the protection PMOS transistor are both connected to the common-mode state sensing node, and the source of the state transition PMOS transistor is connected to the common-mode state sensing node. The drain of the detection NMOS transistor is connected to the switching reference voltage terminal, and the source of the detection NMOS transistor, the source of the protection PMOS transistor, and the gate of the state transition PMOS transistor are all connected together. The drain of the protection PMOS transistor is grounded, and the drain of the state transition PMOS transistor forms a state current node. The detection NMOS transistor, the protection PMOS transistor, and the state transition PMOS transistor together constitute a common-mode state transition branch. The common-mode state transition branch is configured to generate a corresponding state current at the state current node based on the potential change of the common-mode state sensing node.

7. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 6, characterized in that, The common-mode state detection circuit further includes a first mirror NMOS transistor and a second mirror NMOS transistor; The gate and drain of the first mirror NMOS transistor are connected to each other and are connected to the state current node. The gate of the second mirror NMOS transistor is connected to the state current node. The sources of both the first and second mirror NMOS transistors are grounded, and the drain of the second mirror NMOS transistor is connected to the control node to form a mirror current flowing from the control node to ground and corresponding to the state current.

8. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 7, characterized in that, The common-mode state detection circuit also includes a control PMOS transistor and a bias current source; The source of the control PMOS transistor is connected to the power supply terminal, and the gate and drain are connected to each other and together connected to the control node. The drain of the second mirror NMOS transistor is connected to the control node, and the bias current source is connected between the control node and ground. The current direction of the bias current source is from the control node to ground. The control PMOS transistor, the bias current source, and the second mirror NMOS transistor together form the current balance relationship of the control node, and generate the control voltage at the control node.

9. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 8, characterized in that, The first feedforward branch includes a first feedforward capacitor and a first feedforward regulating PMOS transistor; the second feedforward branch includes a second feedforward capacitor and a second feedforward regulating NMOS transistor; and the control voltage conversion branch includes a mirror PMOS transistor and a voltage conversion NMOS transistor. One end of the first feedforward capacitor is connected to the output node, and the other end is connected to the source of the first feedforward adjustment PMOS transistor. The drain of the first feedforward adjustment PMOS transistor is connected to the first gain control node, and the gate is connected to the control node. One end of the second feedforward capacitor is connected to the output node, and the other end is connected to the drain of the second feedforward adjustment NMOS transistor. The source of the second feedforward adjustment NMOS transistor is connected to the second gain control node, and the gate is connected to the switching control node. The source of the mirrored PMOS transistor is connected to the power supply terminal, the gate is connected to the control node, and the drain is connected to the switching control node; the source of the voltage-converting NMOS transistor is grounded, and the gate and drain are connected to each other and together to the switching control node. The mirror PMOS transistor and the control PMOS transistor form a current mirror relationship, and the voltage conversion NMOS transistor forms the second control voltage at the conversion control node, so that the conduction degree of the first feedforward adjustment PMOS transistor and the second feedforward adjustment NMOS transistor is adjusted accordingly with the common mode operating state of the rail-to-rail input stage.

10. The high-speed, high-bandwidth rail-to-rail operational amplifier according to claim 9, characterized in that, It also includes a control holding capacitor, one end of which is connected to the control node and the other end is grounded, and the control holding capacitor is configured to filter the control voltage.

Images