Method of manufacturing bulk acoustic resonator, filter

Abstract

The application relates to the technical field of acoustic devices, and discloses a manufacturing method of a bulk acoustic wave resonator and a filter, wherein the manufacturing method comprises the following steps: obtaining a substrate, sequentially forming a second electrode layer, a piezoelectric layer and a first electrode structure layer on the substrate, and then removing the substrate to obtain a resonant main structure; depositing a carrier structure on the side of the first electrode structure layer away from the piezoelectric material; grinding and etching a cover wafer to form a substrate layer with a recess; sequentially arranging a stress adjusting layer and a barrier layer on the side of the substrate layer with the recess to form a cover substrate; bonding the side of the cover substrate close to the barrier layer with the side of the resonant main structure close to the second electrode layer through a cover bonding layer to form a second cavity, and enabling part of the second electrode layer to be located in the second cavity. The application can realize stress adjustment and electrical isolation of the cover substrate and the resonant main structure, and improve the reliability and electrical performance of the device.

Description

[0001] This application claims priority to international patent application No. PCT / CN2026 / 106616, filed on June 26, 2026, entitled "Bulk Acoustic Resonator and Method for Fabrication Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of acoustic device technology, such as a method for manufacturing a bulk acoustic resonator and a filter. Background Technology

[0003] With the rapid development of mobile communication technology, filters based on resonators are increasingly widely used in communication devices such as smartphones. Thin-film bulk acoustic resonators typically include an upper electrode, a piezoelectric layer, and a lower electrode. Conductive pads and a cover structure are provided on the side of the piezoelectric layer and the upper electrode away from the lower electrode, and the cover structure and the piezoelectric layer enclose an upper cavity.

[0004] In related technologies, the cover wafer of a thin-film bulk acoustic resonator is usually bonded directly to resonant components such as piezoelectric layers using a bonding layer.

[0005] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: Direct bonding between different materials can generate stress due to the mismatch in thermal expansion coefficients, leading to cracks or bonding voids at the bonding interface. At the same time, charge carriers in the substrate may leak into the resonant region, increasing energy loss and affecting device performance.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a method for manufacturing a bulk acoustic wave resonator and a filter to achieve stress adjustment and electrical isolation between the cover substrate and the resonant main body structure, thereby improving device reliability and electrical performance.

[0009] In some embodiments, a method for manufacturing a bulk acoustic wave resonator includes: obtaining a substrate and sequentially depositing a second electrode material, a piezoelectric material, and a first electrode material on the substrate; performing a patterning process on the first electrode material to form a first electrode structure, obtaining a first electrode structure layer; depositing a carrier structure on the side of the first electrode structure layer away from the piezoelectric material; removing the substrate and performing a patterning process on the second electrode material to form a second electrode, obtaining a second electrode layer; performing a patterning process on the piezoelectric material to form a piezoelectric layer, obtaining a resonant main body structure; etching the interior of the carrier structure to form a first cavity, with a portion of the first electrode structure located in the first cavity; grinding and etching a cover wafer to form a substrate layer with a depression; sequentially covering the side of the substrate layer with the depression with a stress adjustment layer and a barrier layer to form a cover substrate; bonding the side of the cover substrate near the barrier layer to the side of the resonant main body structure near the second electrode layer through a cover bonding layer to form a second cavity, with a portion of the second electrode layer located in the second cavity.

[0010] Optionally, after patterning the piezoelectric material, multiple piezoelectric vias extending through the piezoelectric layer are formed; the piezoelectric vias include piezoelectric vias located in the dicing region and piezoelectric vias located in the internal region of the device; the dicing region is located on two opposite sides of the resonant main structure in the second direction; a conductive material layer is deposited on the piezoelectric layer and the second electrode layer, and the conductive material layer fills each piezoelectric via; the conductive material layer is patterned to form dicing pads in the dicing region and first conductive pads in the internal region of the device; both the dicing pads and the first conductive pads have recesses that are recessed toward the first electrode structure layer.

[0011] Optionally, the side of the cover substrate near the barrier layer is bonded to the side of the resonant main structure near the second electrode layer via a cover bonding layer, including: depositing a bonding material layer on the side of the cover substrate near the barrier layer; performing a patterning process on the bonding material layer to remove a portion of the bonding material layer to form a cover bonding layer and obtain a cover structure; and bonding the side of the cover structure with the cover bonding layer to the piezoelectric layer and the dicing pad.

[0012] Optionally, after forming the carrier structure, an etching process is performed on the carrier structure in the cutting channel area to form a recessed structure on the side of the carrier structure away from the resonant main structure; the orthogonal projection of the recessed structure on the resonant main structure is located in the cutting channel area.

[0013] Optionally, before forming the carrier structure, a first passivation layer is deposited on the side of the first electrode structure layer away from the piezoelectric material.

[0014] Optionally, forming a carrier structure includes: forming a dielectric material layer on the side of the first passivation layer away from the piezoelectric layer; performing a patterning process on the dielectric material layer to remove a portion of the dielectric material layer and form a support dielectric layer and a sacrificial dielectric layer separated from each other; forming a cavity boundary layer on the side of the piezoelectric layer away from the second electrode layer; the cavity boundary layer covering the sidewalls of the sacrificial dielectric layer and the surface away from the piezoelectric layer, the sidewalls of the support dielectric layer and the surface away from the piezoelectric layer, and a portion of the surface of the first passivation layer; forming a carrier bonding layer on the side of the cavity boundary layer away from the piezoelectric layer; providing a carrier substrate and bonding the carrier substrate to the carrier bonding layer.

[0015] Optionally, etching is performed inside the carrier structure to form a first cavity, including: etching the piezoelectric layer to form one or more release holes in the piezoelectric layer; the release holes extend through the piezoelectric layer and expose a portion of the surface of the sacrificial dielectric layer away from the carrier substrate; applying an etchant to the region where the sacrificial dielectric layer is located through the release holes to remove the sacrificial dielectric layer and the first passivation layer covered by the sacrificial dielectric layer, thereby forming the first cavity.

[0016] Optionally, forming a cavity boundary layer on the side of the piezoelectric layer away from the second electrode layer includes: depositing a cavity boundary material layer on the side of the piezoelectric layer away from the second electrode layer; etching away a portion of the cavity boundary material layer to form a cavity boundary layer having a first boundary layer opening and a second boundary layer opening.

[0017] Optionally, after forming the carrier structure, an etching process is performed on the carrier structure and the first passivation layer to form a first carrier via and a second carrier via in the carrier structure, and to form a first passivation opening and a second passivation opening in the first passivation layer; wherein, the portion of the first carrier via near the first passivation opening and the orthographic projection of the first passivation opening on the main surface of the piezoelectric layer are located within the orthographic projection of the first boundary layer opening of the cavity boundary layer on the main surface of the piezoelectric layer; the portion of the second carrier via near the second passivation opening and the orthographic projection of the second passivation opening on the main surface of the piezoelectric layer are located within the orthographic projection of the second boundary layer opening of the cavity boundary layer on the main surface of the piezoelectric layer. A first conductive connector and a second conductive connector are formed on the carrier structure; the first conductive connector is filled into a first carrier through-hole and a first passivation opening, and the second conductive connector is filled into a second carrier through-hole and a second passivation opening; wherein, the first conductive connector extends through the carrier structure to be electrically connected to the first electrode structure, and the second conductive connector extends through the carrier structure and is electrically connected to the second electrode through an intermediate connecting member.

[0018] In some embodiments, the filter includes a bulk acoustic resonator manufactured using the method described above for manufacturing a bulk acoustic resonator.

[0019] The manufacturing method for the bulk acoustic resonator and the filter provided in this disclosure can achieve the following technical effects: In this embodiment, the cover substrate comprises a substrate layer, a stress-regulating layer, and a barrier layer, enabling coordinated management of mechanical stress and electrical isolation between the cover substrate and the resonant main structure. The stress-regulating layer compensates for stress caused by the difference in thermal expansion coefficients between the cover substrate and the underlying device layer, preventing interface cracking or void formation due to stress concentration during bonding and subsequent temperature cycling, thus improving the mechanical integrity, hermeticity, and long-term reliability of the bonding interface. The barrier layer prevents carrier leakage or injection from the cover substrate into the operating region of the resonator. Such carrier leakage introduces additional energy loss and parasitic conductance, severely degrading the resonator's quality factor (Q) and frequency stability. Adding a barrier layer prevents carrier leakage into the operating region, increases the Q value, and improves the device's electrical purity and high-frequency performance.

[0020] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic cross-sectional view of a bulk acoustic resonator provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a method for manufacturing a bulk acoustic resonator according to an embodiment of this disclosure; Figure 3 This is a schematic cross-sectional view of a substrate provided in a method for manufacturing a bulk acoustic resonator according to an embodiment of this disclosure; Figure 4 This is a method provided in the embodiments of this disclosure. Figure 3 A schematic cross-sectional view of the dielectric layer formed on the basis of this. Figure 5 This is a method provided in the embodiments of this disclosure. Figure 4 A schematic cross-sectional view showing the formation of a second passivation layer, a second electrode layer, a piezoelectric layer, and a first electrode layer in sequence. Figure 6 This is a method provided in the embodiments of this disclosure. Figure 5 A schematic cross-sectional view of the metal layer formed on the basis of this. Figure 7 This is a method provided in the embodiments of this disclosure. Figure 6 A schematic cross-sectional view of the edge protrusion layer formed on the basis of this. Figure 8This is a method provided in the embodiments of this disclosure. Figure 7 A schematic cross-sectional diagram illustrating the patterning process based on this. Figure 9 This is a method provided in the embodiments of this disclosure. Figure 8 A schematic cross-sectional view showing the formation of the first passivation layer based on this. Figure 10 This is a method provided in the embodiments of this disclosure. Figure 9 A schematic cross-sectional view of the supporting dielectric layer and the sacrificial dielectric layer is formed based on this. Figure 11 This is a method provided in the embodiments of this disclosure. Figure 10 A schematic cross-sectional view of the cavity boundary layer formed on the basis of this. Figure 12 This is a method provided in the embodiments of this disclosure. Figure 11 A schematic cross-sectional view of the carrier bonding layer formed on the basis of this. Figure 13 This is a method provided in the embodiments of this disclosure. Figure 12 A schematic cross-sectional view of the carrier substrate is formed based on this. Figure 14 This is a method provided in the embodiments of this disclosure. Figure 13 A schematic cross-sectional view showing the substrate removed; Figure 15 This is a method provided in the embodiments of this disclosure. Figure 14 A schematic cross-sectional view showing the removal of the dielectric layer. Figure 16 This is a method provided in the embodiments of this disclosure. Figure 15 A schematic cross-sectional diagram illustrating the patterning process based on this. Figure 17 This is a method provided in the embodiments of this disclosure. Figure 16 A schematic cross-sectional view of the etching process performed on the basis of the above. Figure 18 This is a method provided in the embodiments of this disclosure. Figure 17 A schematic cross-sectional view of the etching process performed on the basis of the above. Figure 19 This is a method provided in the embodiments of this disclosure. Figure 18 A schematic cross-sectional view of the pad layer is formed based on this. Figure 20 This is a method provided in the embodiments of this disclosure. Figure 19 A schematic cross-sectional view of the first cavity formed based on this; Figure 21 This is a schematic cross-sectional view of a substrate layer formed according to an embodiment of this disclosure; Figure 22 This is a method provided in the embodiments of this disclosure. Figure 21A schematic cross-sectional view of the cover substrate formed on the basis of this. Figure 23 This is a method provided in the embodiments of this disclosure. Figure 20 and Figure 22 A schematic cross-sectional view of the bonding process based on the above. Figure 24 This is a method provided in the embodiments of this disclosure. Figure 23 A schematic cross-sectional diagram of the grinding process based on the above. Figure 25 This is a method provided in the embodiments of this disclosure. Figure 24 A schematic cross-sectional view of the etching process performed on the basis of the above. Figure 26 This is a method provided in the embodiments of this disclosure. Figure 25 Based on this, a schematic cross-sectional view of the first and second routing layers is formed; Figure 27 This is a method provided in the embodiments of this disclosure. Figure 26 A schematic cross-sectional view of the formation of the third passivation layer based on this; Figure 28 This is a method provided in the embodiments of this disclosure. Figure 27 A schematic cross-sectional view of the formation of the first and second conductive bumps based on this. Figure 29 This is a method provided in the embodiments of this disclosure. Figure 28 A schematic cross-sectional view of the reflow soldering process based on the above. Figure 30 This is a schematic cross-sectional view of another bulk acoustic resonator provided in an embodiment of this disclosure; Figure 31 This is a schematic cross-sectional view of another bulk acoustic resonator provided in an embodiment of this disclosure; Figure 32 This is a schematic cross-sectional view of another bulk acoustic resonator provided in an embodiment of this disclosure; Figure 33 This is a schematic cross-sectional view of another bulk acoustic resonator provided in an embodiment of this disclosure; Figure 34 This is a schematic cross-sectional view of another bulk acoustic resonator provided in an embodiment of this disclosure.

[0022] Reference numerals: 100, substrate; 101, dielectric layer; 102, second passivation layer; 103, second electrode layer; 104, piezoelectric layer; 105, first electrode layer; 106, metal layer; 107, edge bump layer; 400, first electrode structure layer; P1, first electrode edge bump portion; AP1, additional electrode bump portion; 401, dicing region; E1, first electrode; AE1, additional electrode; 402, first electrode structure; 403, additional electrode structure; 108, first passivation layer; 109, supporting dielectric layer; 109b, sacrificial dielectric layer; 110, cavity boundary layer; 110a, first boundary layer opening; 110b, second boundary layer opening; 111, carrier bonding layer; 200, carrier substrate; E2, second electrode; 500, release hole; 104a 104b, Piezoelectric via; 404, Pad layer; 210, Cut track pad; 220, First conductive pad; 230, Second conductive pad; 240, Interconnect pad; 10, Resonant body structure; 20, Carrier structure; 30, Cover structure; 300, Substrate layer; 310, Stress adjustment layer; 311, Barrier layer; 405, Cover substrate; 301, Cover bonding layer; 20a, First carrier via; 20b, Second carrier via; 406, Recessed structure; 302a, First redistribution layer; 302b, Second redistribution layer; 303, Third passivation layer; 304a, First conductive bump; 304b, Second conductive bump; 305a, First conductive connector; 305b, Second conductive connector; D1, First direction; D2, Second direction. Detailed Implementation

[0023] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0024] The terms "first," "second," etc., used in the technical solutions described in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0025] Unless otherwise stated, the term "multiple" means two or more.

[0026] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0027] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0028] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0029] Combination Figure 1 As shown, this embodiment of the present disclosure provides a bulk acoustic resonator, including a resonant main body structure 10, a carrier structure 20, and a cover structure 30.

[0030] The resonant main structure 10 includes a piezoelectric layer 104, a first electrode structure layer 400, and a second electrode layer 103. The first electrode structure layer 400 is disposed on a first side of the piezoelectric layer 104 and includes a first electrode structure 402. The second electrode layer 103 is disposed on a second side of the piezoelectric layer 104 and includes a second electrode E2. The first and second sides of the piezoelectric layer 104 are two opposite sides in a first direction D1. A carrier structure 20 is disposed on the first side of the resonant main structure 10. A first cavity is formed between the carrier structure 20 and the resonant main structure 10, and a portion of the first electrode structure 402 is located in the first cavity. A cover structure 30 is disposed on the second side of the resonant main structure 10 and includes a cover bonding layer 301 and a cover substrate 405. The cover bonding layer 301 is disposed between the cover substrate 405 and the resonant main structure 10, and a second cavity is formed between the cover structure 30 and the resonant main structure 10. A portion of the second electrode layer 103 is located in the second cavity. The first side and the second side of the resonant main structure 10 are two opposite sides in the first direction D1. The cover substrate 405 has a recess that is recessed away from the resonant main structure 10 to form the second cavity. The cover substrate 405 includes: a substrate layer 300 disposed on the side of the cover substrate 405 away from the resonant main structure 10, and the substrate layer 300 has a recess that is recessed away from the resonant main structure 10; a stress adjustment layer 310 disposed on the side of the substrate layer 300 close to the resonant main structure 10; and a barrier layer 311 disposed on the side of the stress adjustment layer 310 close to the resonant main structure 10.

[0031] In this embodiment, the cover substrate 405 comprises a substrate layer 300, a stress-adjusting layer 310, and a barrier layer 311, enabling coordinated management of mechanical stress and electrical isolation between the cover substrate 405 and the resonant main structure 10. The stress-adjusting layer 310 compensates for stress caused by the difference in thermal expansion coefficients between the cover substrate 405 and the underlying device layer, preventing interface cracking or void formation due to stress concentration during bonding and subsequent temperature cycling, thus improving the mechanical integrity, hermeticity, and long-term reliability of the bonding interface. The barrier layer 311 prevents carrier leakage or injection from the cover substrate 405 into the operating region of the resonator. Such carrier leakage introduces additional energy loss and parasitic conductance, severely degrading the resonator's quality factor (Q) and frequency stability. Adding the barrier layer 311 prevents carrier leakage into the operating region, increases the Q value, and improves the device's electrical purity and high-frequency performance.

[0032] Optionally, the bulk acoustic wave resonator further includes: a pad layer 404 located on the second side of the resonant main body structure 10, and including two cleaved pads 210; the orthographic projections of the two cleaved pads 210 on the resonant main body structure 10 are respectively located within two cleaved regions 401; the cleaved regions 401 are located on two opposite sides of the resonant main body structure 10 in the second direction D2; at least a portion of the cleaved pads 210 is bonded to the cap bonding layer 301 and has a recess that is recessed toward the first electrode structure layer 400. A recessed structure 406 is also provided on the side of the carrier structure 20 away from the resonant main body structure 10, the recessed structure 406 having a recess that is recessed toward the resonant main body structure 10; the orthographic projection of the recessed structure 406 on the resonant main body structure 10 is located within the cleaved region 401.

[0033] In this embodiment, the dicing pads 210 and recessed structures 406 provided in the dicing area 401 can open the dicing channel and carrier structure 20 in advance to release stress, providing buffer and stress release space for thermal expansion and contraction of the device during process and subsequent packaging. This can effectively reduce the risk of chip edge peeling or cracking caused by stress concentration during reflow soldering and chip dicing, thereby improving overall yield and long-term reliability. In addition, at least a portion of the dicing pads 210 are bonded to the cover bonding layer 301, and the dicing pads 210 have recesses facing the first electrode structure layer 400, which can also include the dicing area 401 in the bonding interface, increasing the total bonding area and mechanical anchor points between the cover structure 30 and the resonant main body structure 10, thereby enhancing bonding strength and hermeticity, preventing bonding interface failure under mechanical or thermal stress, and enhancing structural stability.

[0034] In this paper, the first direction D1 and the second direction D2 intersect each other, for example, they are perpendicular to each other; for example, in the example shown, the first direction D1 is the vertical direction and the second direction D2 is the horizontal direction.

[0035] Optionally, the piezoelectric layer 104, the first electrode structure 402, the second electrode E2, the first cavity, and the second cavity at least partially overlap in a direction perpendicular to the main surface of the piezoelectric layer 104 (e.g., the first direction D1).

[0036] Optionally, the cap bonding layer 301 includes a protrusion that fills the recess of the dicing pad 210, the protrusion being surrounded by the dicing pad 210.

[0037] In some embodiments, the cap bonding layer 301 may also not include the protrusions that fill the recesses of the diced pads 210.

[0038] In some embodiments, the cut track pad 210 may also not have a recess that is recessed toward the first electrode structure layer 400.

[0039] Optionally, the orthographic projection of the recess of the dicing pad 210 on the main surface of the piezoelectric layer 104 lies within the orthographic projection of the cap bonding layer 301 on the main surface of the piezoelectric layer 104. For example, the piezoelectric layer 104 includes a piezoelectric via 104a, and the dicing pad 210 includes a horizontal extension and a recess. The horizontal extension is located on the side of the piezoelectric layer 104 away from the first electrode structure layer 400, and the recess fills the piezoelectric via 104a, extending through the piezoelectric layer 104 to be electrically connected to the first electrode structure layer 400.

[0040] For example, the recess of the cut track pad 210 has a first surface and a second surface that are opposite to each other in a direction perpendicular to the main surface of the piezoelectric layer 104 (e.g., the first direction D1), and the second surface is in contact with the first electrode structure layer 400; the recess has a first sidewall (or inner sidewall) and a second sidewall (or outer sidewall) that are opposite to each other in a direction parallel to the main surface of the piezoelectric layer 104 (e.g., the horizontal direction including the second direction D2), and the second sidewall is in contact with the piezoelectric layer 104.

[0041] For example, the recess of the dicing pad 210 is defined by a first surface and a first sidewall of the recess; the capping bonding layer 301 may cover and contact a portion of the horizontal extension of the dicing pad 210, and fill the recess, covering and contacting the first surface and the first sidewall of the recess of the dicing pad 210. In some embodiments, the first surface and the first sidewall of the dicing pad 210 are completely covered by the capping bonding layer 301. The contact area between the capping bonding layer 301 and the dicing pad 210 may be greater than or equal to the sum of the area of ​​the first surface of the recess of the dicing pad 210 and the surface area of ​​the first sidewall.

[0042] In some embodiments, the second cavity is formed by the cover bonding layer 301 and the cover substrate 405 of the cover structure 30 surrounding the resonant main structure 10, and the sidewalls of the cover bonding layer 301 and the surface of the cover substrate 405 facing the resonant main structure 10 define a portion of the boundary of the second cavity.

[0043] In some embodiments, since the recesses of the scribe line pads 210 are completely covered by the cap bonding layer 301, the recesses may not be exposed in the second cavity. For example, the orthographic projection of the recesses of the scribe line pads 210 on the main surface of the piezoelectric layer 104 is offset from the orthographic projection of the second cavity on the main surface of the piezoelectric layer 104. In this document, offset orthographic projections of multiple components on a reference plane indicate that the orthographic projections of the multiple components do not overlap, including cases where the orthographic projections of the multiple components are spaced apart from each other without overlapping, and cases where the orthographic projections of the multiple components are adjacent to each other without overlapping.

[0044] Optionally, the pads included in the pad layer 404 are made of conductive materials such as metal.

[0045] Optionally, the bulk acoustic resonator further includes: a first conductive connector 305a and a second conductive connector 305b, disposed on the side of the carrier structure 20 away from the resonant main structure 10. The first conductive connector 305a extends through the carrier structure 20 to be electrically connected to the first electrode structure 402, and the second conductive connector 305b extends through the carrier structure 20 and is electrically connected to the second electrode E2 through an intermediate connecting member. The intermediate connecting member is spaced apart from the first cavity.

[0046] In this embodiment, by placing the first conductive connector 305a and the second conductive connector 305b on the side of the carrier structure 20 away from the resonant main structure 10, and by setting an intermediate connecting member to achieve the electrical connection between the second conductive connector 305b and the second electrode E2 located on the second side of the piezoelectric layer 104, the adverse effects on the conductive connector caused by possible deformation, delamination and other problems of the cover bonding layer 301 can be minimized, ensuring the effective electrical connection between the conductive connector and the electrode and improving the reliability of the device.

[0047] Optionally, the pad layer 404 further includes an interconnect pad 240, which is electrically connected to the second electrode E2 and extends through the piezoelectric layer 104 to be electrically connected to the additional electrode structure 403 of the first electrode structure layer 400.

[0048] Optionally, the interconnect pad 240 includes a first portion located in a via of the piezoelectric layer 104 and a second portion in contact with the second electrode E2. The first portion is electrically connected to the additional electrode structure 403, and the second portion at least covers and contacts the sidewall of the second electrode E2 and is connected to the first portion, thereby enabling the second electrode E2 to be electrically connected to the additional electrode structure 403 through the interconnect pad 240.

[0049] Optionally, the second electrode E2 has an electrode via, and the piezoelectric layer 104 has an additional piezoelectric via 104b, with the electrode via and the additional piezoelectric via 104b spatially connected to each other to expose a portion of the surface of the additional electrode structure 403 near the piezoelectric layer 104. The interconnect pad 240 contacts and is electrically connected to the second electrode E2, and is electrically connected to the additional electrode structure 403 through the electrode via in the second electrode E2 and the additional piezoelectric via 104b in the piezoelectric layer 104.

[0050] Optionally, a second passivation layer 102 is further provided on the side of the second electrode layer 103 away from the piezoelectric layer 104, and the second passivation layer 102 has a passivation opening that can spatially communicate with the electrode via in the second electrode E2 and the aforementioned additional piezoelectric via 104b. Interconnect pads 240 may also be provided on the side of the second electrode E2 and / or the passivation layer away from the piezoelectric layer 104, and pass through the passivation opening, the electrode via, and the additional piezoelectric via 104b to be electrically connected to the additional electrode structure 403.

[0051] Optionally, the sidewall of the portion defining the electrode via of the second electrode E2 may be covered by and in contact with the interconnect pad 240. In some embodiments, the surface of the second electrode E2 on the side away from the piezoelectric layer 104 may be covered by the second passivation layer 102 and may not be in contact with the interconnect pad 240. In other embodiments, a portion of the surface of the second electrode E2 on the side away from the piezoelectric layer 104 may not be covered by the second passivation layer 102 and may be covered by and in contact with the interconnect pad 240. In some examples, the portion of the interconnect pad 240 located on the side of the second electrode E2 away from the piezoelectric layer 104 may be located within a passivation opening and may protrude from the surface of the second passivation layer 102 on the side away from the piezoelectric layer 104, and may extend to cover the portion of the surface of the second passivation layer 102 on the side away from the piezoelectric layer 104. In other examples, the surface of the interconnect pad 240 on the side away from the piezoelectric layer 104 may also be substantially flush with the surface of the second passivation layer 102 on the side away from the piezoelectric layer 104 in a direction parallel to the main surface of the piezoelectric layer 104 (e.g., the second direction D2).

[0052] Optionally, the pad layer 404 further includes: a first conductive pad 220 disposed on the surface of the second side of the piezoelectric layer 104, having a recess that is recessed toward the first electrode structure layer 400, and extending through the piezoelectric layer 104 to be electrically connected to the first electrode structure layer 400.

[0053] Optionally, the pad layer 404 further includes a second conductive pad 230 disposed on the side of the second electrode E2 and the second passivation layer 102 away from the piezoelectric layer 104, having a recess that is recessed toward the second electrode E2, and extending through the second passivation layer 102 to be electrically connected to the second electrode E2.

[0054] In some embodiments, the piezoelectric layer 104 may further have a piezoelectric via 104a exposing a portion of the surface of the first electrode E1. A first conductive pad 220 is disposed on a second side of the piezoelectric layer 104 and can be filled into the piezoelectric via 104a to electrically connect with the first electrode structure 402 through the piezoelectric via 104a. A second conductive pad 230 is disposed on the side of the second electrode E2 away from the piezoelectric layer 104 and is electrically connected to the second electrode E2. The first conductive pad 220 and the second conductive pad 230 can serve as test pads, for example, for testing the relevant performance of the resonator during the manufacturing process of the resonator.

[0055] Optionally, the intermediate connection member includes interconnect pads 240 and an additional electrode structure 403 electrically connected to each other. For example, the additional electrode structure 403 is located between the interconnect pads 240 and the second conductive connector 305b in the first direction D1, and is electrically connected to the interconnect pads 240 and the second conductive connector 305b, such that the second conductive connector 305b can be electrically connected to the second electrode E2 through the additional electrode structure 403 and the interconnect pads 240.

[0056] Optionally, the first electrode structure 402 and the additional electrode structure 403 are disposed in the same layer of the first electrode structure layer 400, and are spaced apart from each other and electrically isolated. That is, the first electrode structure layer 400 includes the first electrode structure 402 and the additional electrode structure 403 that are isolated from each other.

[0057] In some embodiments, the first electrode structure layer 400 includes at least a first electrode layer 105; for example, the first electrode layer 105 includes a first electrode E1 and an additional electrode AE1 that are spaced apart from each other and electrically isolated, the first electrode E1 constituting at least a portion of the first electrode structure 402, and the additional electrode AE1 constituting at least a portion of the additional electrode structure 403.

[0058] In some embodiments, the first electrode structure layer 400 further includes an edge bump layer 107 located on the side of the first electrode layer 105 away from the piezoelectric layer 104 and / or close to the piezoelectric layer 104, wherein the edge bump layer 107 may include a first electrode edge bump portion P1, the first electrode edge bump portion P1 and the first electrode E1 are stacked and electrically connected to each other in the first direction D1; the edge bump layer 107 may also include an additional electrode bump portion AP1, the additional electrode bump portion AP1 and the additional electrode AE1 are stacked and electrically connected to each other in the first direction D1.

[0059] For example, the first electrode structure layer 400 further includes an edge bump layer 107; the edge bump layer 107 comprises a conductive material and is electrically connected to the first electrode layer 105. For example, the edge bump layer 107 is located on the side of the first electrode layer 105 away from the piezoelectric layer 104, and includes a first electrode edge bump portion P1 and an additional electrode bump portion AP1 that are separated from each other and electrically isolated. For example, the first electrode edge bump portion P1 may be disposed on the side of the first electrode E1 away from the piezoelectric layer 104, and may cover the surface of the edge region of the portion of the first electrode E1 located in the first cavity on the side away from the piezoelectric layer 104 and the surface of the portion of the first electrode E1 located outside the first cavity on the side away from the piezoelectric layer 104. The surface of the central region of the portion of the first electrode E1 located in the first cavity on the side away from the piezoelectric layer 104 is not covered by the first electrode edge bump portion P1.

[0060] The additional electrode bump AP1 may be stacked on the side of the additional electrode AE1 away from the piezoelectric layer 104. In some embodiments, the additional electrode bump AP1 and the additional electrode AE1 may have approximately the same size in a direction parallel to the main surface of the piezoelectric layer 104. For example, the orthographic projection of the additional electrode bump AP1 onto the main surface of the piezoelectric layer 104 may lie within the orthographic projection of the additional electrode AE1 onto the main surface of the piezoelectric layer 104.

[0061] In this embodiment, the first electrode E1 and the first electrode edge protrusion P1 together constitute the first electrode structure 402; the auxiliary electrode AE1 and the auxiliary electrode protrusion AP1 together constitute the auxiliary electrode structure 403.

[0062] Optionally, the bulk acoustic resonator further includes a first passivation layer 108 located between the resonant main body structure 10 and the carrier structure 20, and the first passivation layer 108 is not provided at the first cavity.

[0063] Optionally, a metal layer 106 is further provided on the contact surface between the first electrode layer 105 and the first cavity.

[0064] In some embodiments, a first passivation layer 108 may be provided at the resonant main structure 10 and the first cavity.

[0065] In this embodiment, a first passivation layer 108 is provided between the resonant main structure 10 and the underlying carrier structure 20, which can provide mechanical protection and electrical isolation for the first electrode structure 402 and its interface. The absence of the first passivation layer 108 in the first cavity avoids the additional acoustic losses that the passivation layer material might introduce in the effective vibration area of ​​the resonator (i.e., the area corresponding to the lower cavity). Because the first passivation layer 108 has poor in-plane oxidation uniformity and a large surface roughness after corrosion, it increases acoustic straying and affects the Q value. Therefore, in the cavity region where high-quality resonance is required, the first passivation layer 108, which may degrade acoustic performance, is avoided, thereby ensuring purer sound wave reflection at the cavity interface and reducing energy scattering and loss.

[0066] Optionally, the first passivation layer 108 includes a first passivation opening and a second passivation opening; the first conductive connector 305a extends through the carrier structure 20 and through the first passivation opening to be electrically connected to the first electrode structure 402; the second conductive connector 305b extends through the carrier structure 20 and through the second passivation opening to be electrically connected to the intermediate connecting member.

[0067] Optionally, the carrier structure 20 includes: a supporting dielectric layer 109 disposed on the side of the first electrode structure layer 400 away from the piezoelectric layer 104; a cavity boundary layer 110 located on the side of the supporting dielectric layer 109 and the resonant main structure 10 away from the cover structure 30, and defining a portion of the boundary of the first cavity; a carrier bonding layer 111 located on the side of the cavity boundary layer 110 away from the resonant main structure 10; and a carrier substrate 200 located on the side of the carrier bonding layer 111 away from the resonant main structure 10.

[0068] Optionally, the recessed structure 406 of the carrier structure 20 has a recess that reaches the cavity boundary layer 110, or the recessed structure 406 of the carrier structure 20 has a recess that reaches the first passivation layer 108. That is, the filling material in the recessed structure 406 is in contact with the cavity boundary layer 110, the carrier bonding layer 111 and the carrier substrate 200, or in contact with the first passivation layer 108, the supporting dielectric layer 109, the cavity boundary layer 110, the carrier bonding layer 111 and the carrier substrate 200.

[0069] In some embodiments, the first conductive connector 305a and the second conductive connector 305b are in contact with the carrier substrate 200 and the carrier bonding layer 111, and are separated from the supporting dielectric layer 109. For example, the first conductive connector 305a and the second conductive connector 305b are also separated from the cavity boundary layer 110. Alternatively, the first conductive connector 305a and the second conductive connector 305b may also be in contact with the cavity boundary layer 110.

[0070] For example, the carrier structure 20 has a first carrier via 20a and a second carrier via 20b, each of which is located in the carrier substrate 200 and the carrier bonding layer 111, and includes a substrate via and a bonding layer via that are interconnected; the first carrier via 20a of the carrier structure 20 is connected to a first passivation opening space of the first passivation layer 108 to expose a portion of the surface of the first electrode structure 402 on the side away from the piezoelectric layer 104; the second carrier via 20b of the carrier structure 20 is connected to a second passivation opening space of the passivation layer to expose a portion of the surface of the additional electrode structure 403 on the side away from the piezoelectric layer 104.

[0071] For example, the first conductive connector 305a includes a first conductive via located in the first carrier via 20a and the first passivation opening, and a second conductive via located in the second carrier via 20b and the second passivation opening. The first conductive via may at least cover the surface of the first carrier via 20a, fill the first passivation opening, and be electrically connected to the first electrode structure 402; the second conductive via may at least cover the surface of the second carrier via 20b, fill the second passivation opening, and be electrically connected to the additional electrode structure 403.

[0072] In some embodiments, the supporting dielectric layer 109 is located on the side of the edge portion of the resonant main body structure 10 away from the cover structure 30; a portion of the supporting dielectric layer 109 is located between the first electrode structure layer 400 and the cavity boundary layer 110 in the first direction D1, and overlaps with the cavity boundary layer 110, the carrier bonding layer 111 and the first cavity in a direction parallel to the main surface of the piezoelectric layer 104 (e.g., the second direction D2), and a portion of the supporting dielectric layer 109 may be located on the side of the cavity boundary layer 110 away from the conductive connector in a direction parallel to the main surface of the piezoelectric layer 104.

[0073] For example, the supporting dielectric layer 109 includes a first dielectric portion and a second dielectric portion; the first dielectric portion is located between the first electrode structure 402 and the cavity boundary layer 110 in a first direction D1 perpendicular to the main surface of the piezoelectric layer 104, and the second dielectric portion is located between the additional electrode structure 403 and the cavity boundary layer 110 in the first direction D1. Moreover, the first dielectric portion is located on the side of the cavity boundary layer 110 away from the carrier bonding layer 111 and the first conductive via in a direction parallel to the main surface of the piezoelectric layer 104 (e.g., the second direction D2); the second dielectric portion is located on the side of the cavity boundary layer 110 away from the carrier bonding layer 111 and the second conductive via in a direction parallel to the main surface of the piezoelectric layer 104.

[0074] In some embodiments, the first electrode structure layer 400 has a gap between the first electrode structure 402 and the additional electrode structure 403, and the orthographic projection of the gap on the main surface of the piezoelectric layer 104 is offset from the orthographic projection of the supporting dielectric layer 109 on the main surface of the piezoelectric layer 104. For example, the orthographic projection of the space between the first conductive via and the second conductive via on the main surface of the piezoelectric layer 104 in a direction parallel to the main surface of the piezoelectric layer 104 (e.g., the second direction D2) is offset from the orthographic projection of the supporting dielectric layer 109 on the main surface of the piezoelectric layer 104.

[0075] For example, the supporting dielectric layer 109 is located on the edge portion of the first electrode structure layer 400 and has an opening region, at least a portion of which is located between the first dielectric portion and the second dielectric portion of the supporting dielectric layer 109; portions of the cavity boundary layer 110 and the carrier bonding layer 111 are located in the opening region, and at least portions of the first carrier via 20a and the second carrier via 20b of the carrier structure 20 near the first electrode structure layer 400 are located within the opening region. For example, the orthographic projection of at least the portion of the first carrier via 20a and the second carrier via 20b near the first electrode structure layer 400 on the main surface of the piezoelectric layer 104 lies within the orthographic projection of the opening region on the main surface of the piezoelectric layer 104; or, the orthographic projections of the first carrier via 20a and the second carrier via 20b on the main surface of the piezoelectric layer 104 may all lie within the orthographic projection of the opening region on the main surface of the piezoelectric layer 104. For example, the orthographic projection of the portion of the first and second conductive vias contacting the first electrode structure layer 400 on the main surface of the piezoelectric layer 104 lies within the orthographic projection of the opening region on the main surface of the piezoelectric layer 104, i.e., it is offset from the orthographic projection of the supporting dielectric layer 109 on the main surface of the piezoelectric layer 104; or, the orthographic projections of the first and second conductive vias on the main surface of the piezoelectric layer 104 may all lie within the orthographic projection of the opening region on the main surface of the piezoelectric layer 104. The supporting dielectric layer 109 may not include the portion located near the first cavity side of the first and second conductive vias. In some embodiments, the orthographic projection of the supporting dielectric layer 109 on the main surface of the piezoelectric layer 104 may be offset from the orthographic projection of the second cavity on the main surface of the piezoelectric layer 104.

[0076] In some embodiments, the first conductive via and the second conductive via are embedded in the carrier substrate 200 and the carrier bonding layer 111, and are separated from the cavity boundary layer 110 and the support dielectric layer 109. For example, portions of the cavity boundary layer 110 and the carrier bonding layer 111 are located between the first conductive connector 305a (e.g., its first conductive via) and the support dielectric layer 109, and between the second conductive connector 305b (e.g., its second conductive via) and the support dielectric layer 109, in a direction parallel to the main surface of the piezoelectric layer 104 (e.g., the second direction D2).

[0077] In some embodiments, the cavity boundary layer 110 has a first boundary layer opening 110a and a second boundary layer opening 110b, and the carrier bonding layer 111 has a first bonding layer via (i.e., a portion of the first carrier via 20a) and a second bonding layer via (i.e., a portion of the second carrier via 20b); the portion of the first bonding layer via is located in the first boundary layer opening 110a, and the portion of the second bonding layer via is located in the second boundary layer opening 110b. For example, the orthographic projection of the portion of the first bonding layer via closest to the resonant host structure 10 (i.e., the top portion shown in the figure) onto the piezoelectric layer 104 is within the orthographic projection of the first boundary layer opening 110a (e.g., the portion closest to the resonant host structure 10) onto the piezoelectric layer 104; similarly, the orthographic projection of the portion of the second bonding layer via closest to the resonant host structure 10 onto the piezoelectric layer 104 is within the orthographic projection of the second boundary layer opening 110b (e.g., the portion closest to the resonant host structure 10) onto the piezoelectric layer 104.

[0078] For example, the carrier bonding layer 111 includes a first filling portion that fills the first boundary layer opening 110a and a second filling portion that fills the second boundary layer opening 110b, and the portion of the first bonding layer via is located in the first filling portion, and the portion of the second bonding layer via is located in the second filling portion.

[0079] For example, at least a portion of the first filling portion may be located between the first conductive connector 305a (e.g., its first conductive via) and the cavity boundary layer 110, and separate the first conductive connector 305a and the cavity boundary layer 110; at least a portion of the second filling portion may be located between the second conductive connector 305b (e.g., its second conductive via) and the cavity boundary layer 110, and separate the second conductive connector 305b and the cavity boundary layer 110.

[0080] In some embodiments, the above-described arrangement of the material layers in the carrier structure 20 reduces the number of material layers through which the carrier vias pass, thereby simplifying the formation process of the carrier vias and reducing the difficulty of forming the carrier vias; that is, it reduces the number of material layers that the conductive connectors need to pass through and reduces the types of contact interfaces between the conductive connectors and different material layers in the carrier structure 20; such an arrangement can improve the structural strength of the carrier structure 20 and the resonator device, thereby improving the reliability of the resonator and the device performance.

[0081] In some embodiments, the first conductive connector 305a includes a first rewiring layer 302a and a first conductive bump 304a, and the first conductive bump 304a is electrically connected to the first electrode structure 402 through the first rewiring layer 302a; the second conductive connector 305b includes a second rewiring layer 302b and a second conductive bump 304b, and the second conductive bump 304b is electrically connected to the additional electrode structure 403 through the second rewiring layer 302b.

[0082] For example, a redistribution layer may include via portions (i.e., conductive vias) located in carrier vias of carrier structure 20 and conductive portions located on the side of carrier structure 20 away from piezoelectric layer 104; the via portions and the conductive portions are connected to each other. For example, a first redistribution layer 302a includes a first conductive via and a first conductive wire connected to each other; a second redistribution layer 302b includes a second conductive via and a second conductive wire connected to each other. The first conductive via and the second conductive via are respectively filled in the first carrier via 20a and the second carrier via 20b of carrier structure 20, and the first conductive wire and the second conductive wire are located on the side of carrier structure 20 (e.g., carrier substrate 200) away from piezoelectric layer 104. A first conductive bump 304a is disposed on the first redistribution layer 302a, for example, on the side of the first conductive wire away from piezoelectric layer 104, and is electrically connected to the first electrode structure 402 through the first redistribution layer 302a. The second conductive bump 304b is disposed on the second redistribution layer 302b, for example, on the side of the second conductor away from the piezoelectric layer 104, and is electrically connected to the additional electrode structure 403 through the second redistribution layer 302b.

[0083] In some embodiments, the first redistribution layer 302a may fill the first carrier via 20a and the first passivation opening.

[0084] In some embodiments, a third passivation layer 303 is further provided on the side of the redistribution layer away from the piezoelectric layer 104. The third passivation layer 303 may have a first opening and a second opening. The first opening exposes a portion of the surface of the first redistribution layer 302a, and the second opening exposes a portion of the surface of the second redistribution layer 302b. The first conductive bump 304a and the second conductive bump 304b are electrically connected to the first redistribution layer 302a and the second redistribution layer 302b respectively through the first opening and the second opening. That is, the first conductive bump 304a and the second conductive bump 304b extend through the third passivation layer 303 to be electrically connected to the first redistribution layer 302a and the second redistribution layer 302b respectively. In some embodiments, the first conductive via may not fill the first carrier via 20a of the carrier structure 20, the second conductive via may not fill the second carrier via 20b of the carrier structure 20, and a portion of the third passivation layer 303 may be filled into the first carrier via 20a and the second carrier via 20b. For example, the first conductive via and the second conductive via can extend along the surfaces of the first carrier via 20a and the second carrier via 20b of the carrier structure 20, respectively, and the third passivation layer 303 has a first portion and a second portion that are filled into the first carrier via 20a and the second carrier via 20b, respectively. The first portion of the third passivation layer 303 can be surrounded by the first conductive via in a direction parallel to the main surface of the carrier structure 20, and the second portion of the third passivation layer 303 can be surrounded by the second conductive via in a direction parallel to the main surface of the carrier structure 20.

[0085] Optionally, the third passivation layer 303 fills the recessed structure 406 of the carrier structure 20.

[0086] Combination Figure 2 As shown in the embodiments of this disclosure, a method for manufacturing a bulk acoustic resonator is also provided, comprising: S201, Obtain a substrate, and sequentially deposit a second electrode material, a piezoelectric material, and a first electrode material on the substrate.

[0087] S202, patterning process is performed on the first electrode material to form the first electrode structure and obtain the first electrode structure layer.

[0088] S203 is deposited on the side of the first electrode structure layer away from the piezoelectric material to form a carrier structure.

[0089] S204, remove the substrate and perform a patterning process on the second electrode material to form the second electrode and obtain the second electrode layer.

[0090] S205 involves patterning piezoelectric materials to form a piezoelectric layer, thereby obtaining the resonant main structure.

[0091] S206, etching is performed inside the carrier structure to form a first cavity, and a portion of the first electrode structure is located in the first cavity.

[0092] S207 involves grinding and etching the cover wafer to form a substrate layer with depressions.

[0093] S208, a stress-adjusting layer and a barrier layer are sequentially covered on the side of the substrate layer with a depression to form a cover substrate.

[0094] S209, the side of the cover substrate near the barrier layer is bonded to the side of the resonant main body structure near the second electrode layer through the cover bonding layer to form a second cavity, and a portion of the second electrode layer is located in the second cavity.

[0095] Optionally, after patterning the piezoelectric material, a plurality of piezoelectric vias 104a extending through the piezoelectric layer 104 are formed; the piezoelectric vias 104a include piezoelectric vias 104a located in the cut-through region 401 and piezoelectric vias 104a located in the internal region of the device; the cut-through region 401 is located on two opposite sides of the resonant main body structure 10 in the second direction; a conductive material layer is deposited on the piezoelectric layer 104 and the second electrode layer 103, and the conductive material layer fills each piezoelectric via 104a; the conductive material layer is patterned to form a cut-through pad 210 in the cut-through region 401 and a first conductive pad 220 in the internal region of the device; both the cut-through pad 210 and the first conductive pad 220 have recesses that are recessed toward the first electrode structure layer 400.

[0096] Optionally, the side of the cover substrate 405 near the barrier layer 321 is bonded to the side of the resonant main structure 10 near the second electrode layer 103 via the cover bonding layer 301, including: depositing a bonding material layer on the side of the cover substrate 405 near the barrier layer 321; performing a patterning process on the bonding material layer to remove a portion of the bonding material layer to form the cover bonding layer 301, thereby obtaining the cover structure 30; and bonding the side of the cover structure 30 with the cover bonding layer 301 to the piezoelectric layer 104 and the diced pad 210.

[0097] Optionally, after forming the carrier structure 20, an etching process is performed on the carrier structure 20 in the cutting channel region 401 to form a recessed structure 406 on the side of the carrier structure 20 away from the resonant main body structure 10; the orthogonal projection of the recessed structure 406 on the resonant main body structure 10 is located within the cutting channel region 401.

[0098] Optionally, before forming the carrier structure 20, a first passivation layer 108 is deposited on the side of the first electrode structure layer 400 away from the piezoelectric material.

[0099] Optionally, forming the carrier structure 20 includes: forming a dielectric material layer on the side of the first passivation layer 108 away from the piezoelectric layer 104; performing a patterning process on the dielectric material layer to remove a portion of the dielectric material layer and form a support dielectric layer 109 and a sacrificial dielectric layer 109b separated from each other; forming a cavity boundary layer 110 on the side of the piezoelectric layer 104 away from the second electrode layer 103; the cavity boundary layer 110 covers the sidewalls of the sacrificial dielectric layer 109b and the surface away from the piezoelectric layer 104, the sidewalls of the support dielectric layer 109 and the surface away from the piezoelectric layer 104, and a portion of the surface of the first passivation layer 108; forming a carrier bonding layer 111 on the side of the cavity boundary layer 110 away from the piezoelectric layer 104; providing a carrier substrate 200 and bonding the carrier substrate 200 to the carrier bonding layer 111.

[0100] Optionally, etching is performed inside the carrier structure 20 to form a first cavity, including: etching the piezoelectric layer 104 to form one or more release holes 500 in the piezoelectric layer 104; the release holes 500 extend through the piezoelectric layer 104 and expose a portion of the surface of the sacrificial dielectric layer 109b away from the carrier substrate 200; applying an etchant to the area where the sacrificial dielectric layer 109b is located through the release holes 500 to remove the sacrificial dielectric layer 109b and the first passivation layer 108 covered by the sacrificial dielectric layer 109b, thereby forming the first cavity.

[0101] Optionally, a cavity boundary layer 110 is formed on the side of the piezoelectric layer 104 away from the second electrode layer 103, including: depositing a cavity boundary material layer on the side of the piezoelectric layer 104 away from the second electrode layer 103; etching away a portion of the cavity boundary material layer to form a cavity boundary layer 110 having a first boundary layer opening 110a and a second boundary layer opening 110b.

[0102] Optionally, after forming the carrier structure 20, an etching process is performed on the carrier structure 20 and the first passivation layer 108 to form a first carrier via 20a and a second carrier via 20b in the carrier structure 20, and a first passivation opening and a second passivation opening in the first passivation layer 108; wherein, the portion of the first carrier via 20a near the first passivation opening and the orthographic projection of the first passivation opening on the main surface of the piezoelectric layer 104 are located within the orthographic projection of the first boundary layer opening 110a of the cavity boundary layer 110 on the main surface of the piezoelectric layer 104; the portion of the second carrier via 20b near the second passivation opening and the second passivation opening are located within the orthographic projection of the first boundary layer opening 110a of the cavity boundary layer 110 on the main surface of the piezoelectric layer 104. The orthographic projection on the surface is located within the orthographic projection of the second boundary layer opening 110b of the cavity boundary layer 110 onto the main surface of the piezoelectric layer 104; a first conductive connector 305a and a second conductive connector 305b are formed on the carrier structure 20; the first conductive connector 305a fills the first carrier through-hole 20a and the first passivation opening, and the second conductive connector 305b fills the second carrier through-hole 20b and the second passivation opening; wherein, the first conductive connector 305a extends through the carrier structure 20 to be electrically connected to the first electrode structure 402, and the second conductive connector 305b extends through the carrier structure 20 and is electrically connected to the second electrode E2 through an intermediate connecting member.

[0103] Figures 3 to 24 A schematic cross-sectional view showing a method for manufacturing a bulk acoustic resonator according to some embodiments of the present disclosure.

[0104] Combination Figure 3 As shown, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, but this disclosure is not limited thereto. The substrate 100 may also be made of other suitable materials, such as a glass substrate, as long as it can provide structural support for the subsequently formed overlay layer. The substrate 100 will be removed in a subsequent process and may also be referred to as a sacrificial substrate. In some embodiments, the substrate 100 is a wafer-level substrate.

[0105] Combination Figure 4 As shown, a dielectric layer 101 is formed on the substrate 100. The dielectric layer 101 may be an oxide layer, such as silicon oxide (SiO2). The dielectric layer 101 may be formed by a deposition process such as chemical vapor deposition or a thermal oxidation process.

[0106] Combination Figure 5As shown, a second passivation layer 102, a second electrode layer 103, a piezoelectric layer 104, and a first electrode layer 105 are sequentially formed on the dielectric layer 101. The second passivation layer 102 may include insulating materials such as aluminum nitride, silicon nitride, or similar materials or combinations thereof. For example, the material layer may be formed by a suitable deposition process such as chemical vapor deposition or physical vapor deposition. For example, the first electrode layer 105 and the second electrode layer 103 may each include suitable electrode materials, such as metallic materials including molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), similar materials, alloys thereof, or combinations thereof. The piezoelectric layer 104 may include suitable piezoelectric materials, such as aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), zinc oxide, lithium niobate, lithium tantalate, and other materials with piezoelectric properties. It should be understood that the above materials are only illustrative examples, and this disclosure is not limited thereto.

[0107] Combination Figure 6 As shown, a metal layer 106 is formed on the first electrode layer 105. The metal layer 106 only covers a portion of the surface of the first electrode layer 105 to protect the first electrode layer 105.

[0108] Combination Figure 7 As shown, an edge bump layer 107 is formed on the surfaces of the first electrode layer 105 and the metal layer 106. The edge bump layer 107 covers a portion of the surface of the first electrode layer 105 and the metal layer 106, and exposes a portion of the surface of the metal layer 106. The first electrode layer 105, the metal layer 106, and the edge bump layer 107 constitute the first electrode structure layer 400. The edge bump layer 107 comprises a conductive material, such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), and similar materials, alloys thereof, or combinations thereof. The edge bump layer 107 is electrically connected to the corresponding electrode layer and may have the same or different material as the corresponding electrode layer.

[0109] Combination Figure 8As shown, a patterning process is performed on the first electrode layer 105, metal layer 106, and edge bump layer 107 to remove portions of the first electrode layer 105, metal layer 106, and edge bump layer 107, forming a first electrode edge bump portion P1 and an additional electrode bump portion AP1 that are separated from each other and electrically isolated. The formed first electrode edge bump portion P1 has an opening to expose a portion of the surface of the metal layer 106, while defining two opposite sides of the device in the second direction D2 as scribe line regions 401. The patterning process may include photolithography and etching processes. For example, the patterning process forms gaps between the first electrode edge bump portion P1 and the additional electrode bump portion AP1, between the scribe line region 401 and the additional electrode bump portion AP1, and between the scribe line region 401 and the first electrode edge bump portion P1. These gaps separate the scribe line region 401, the first electrode edge bump portion P1, and the additional electrode bump portion AP1 from each other and expose a portion of the surface of the piezoelectric layer 104. In some embodiments, from a plan view, the first electrode edge protrusion P1 may be continuous, and the opening is located in the first electrode edge protrusion P1, without dividing the first electrode edge protrusion P1 into multiple portions spaced apart from each other.

[0110] Simultaneously, the patterning process of the first electrode layer 105 forms a first electrode E1 and an additional electrode AE1 that are spaced apart from each other and electrically isolated. For example, the patterning process removes a portion of the first electrode layer 105 exposed by the gaps in the edge bump layer 107, and forms a gap between the first electrode E1 and the additional electrode AE1, which separates the first electrode E1 and the additional electrode AE1 and exposes a portion of the surface of the piezoelectric layer 104. For example, the gap in the first electrode layer 105 communicates with the gap space in the edge bump layer 107, and their orthographic projections on the main surface of the piezoelectric layer 104 overlap. In the patterning process, the portion of the metal layer 106 exposed by the opening of the first electrode edge bump portion P1 of the edge bump layer 107 is not removed; for example, it can be covered by a mask in the patterning process without being removed. For example, after the first electrode layer 105 is patterned, the first electrode E1 and the first electrode edge protrusion P1 are stacked together; the first electrode E1 and the first electrode edge protrusion P1 together constitute the first electrode structure 402; the additional electrode AE1 and the additional electrode protrusion AP1 are stacked together and together constitute the additional electrode structure 403.

[0111] Combination Figure 9As shown, a first passivation layer 108 is formed on the side of the piezoelectric layer 104 and the first electrode structure layer 400 away from the second electrode layer 103. The first passivation layer 108 extends along the surface of the first electrode structure layer 400 and the piezoelectric layer 104 and fills the gap. For example, the first passivation layer 108 covers the surface of the first electrode edge protrusion P1 of the first electrode structure 402 on the side away from the piezoelectric layer 104, the sidewall of the defining gap between the first electrode edge protrusion P1 and the first electrode E1, and fills the opening of the first electrode edge protrusion P1, covering the sidewall of the defining opening of the first electrode edge protrusion P1 and the surface of the first electrode E1 exposed by the opening; the first passivation layer 108 also covers the surface of the additional electrode protrusion AP1 of the additional electrode structure 403 on the side away from the piezoelectric layer 104 and the sidewall of the defining gap between the additional electrode protrusion AP1 and the additional electrode AE1; and the first passivation layer 108 also covers the surface of the piezoelectric layer 104 on the side away from the second electrode layer 103 and not covered by the first electrode structure layer 400; and the first passivation layer 108 also covers the cutting channel region 401. For example, the first electrode structure layer 400 may be completely covered by the first passivation layer 108, and the orthographic projection of the first electrode structure layer 400 on the main surface of the piezoelectric layer 104 lies within the orthographic projection of the first passivation layer 108 on the main surface of the piezoelectric layer 104. The material of the first passivation layer 108 may include insulating materials such as aluminum nitride, silicon nitride, the like, or combinations thereof.

[0112] Combination Figure 10 As shown, a dielectric material layer is formed on the side of the first passivation layer 108 away from the piezoelectric layer 104; the material of the dielectric material layer is different from the material of the passivation layer, and the two have an etching selectivity ratio in the etching process. For example, the dielectric material layer may include a dielectric material such as silicon oxide. Subsequently, a patterning process is performed on the dielectric material layer to remove a portion of the dielectric material layer and form a support dielectric layer 109 and a sacrificial dielectric layer 109b that are separated from each other. For example, the support dielectric layer 109 may be located above the edge portion of the piezoelectric layer 104 and may cover the edge portions of the first electrode structure 402 and the additional electrode structure 403 of the first electrode structure layer 400. For example, portions of the first electrode structure 402 and the additional electrode structure 403 and the portion of the first passivation layer 108 above them may not be covered by the support dielectric layer 109.

[0113] The sacrificial dielectric layer 109b covers a portion of the first electrode structure 402 and the first passivation layer 108. For example, the orthographic projection of the opening of the first electrode edge bump P1 and the portion defining the opening, as well as the portion of the first electrode E1 corresponding to the edge bump layer 107 and the portion of the first passivation layer 108, onto the piezoelectric layer 104 may lie within the orthographic projection range of the sacrificial dielectric layer 109b onto the piezoelectric layer 104. In this embodiment, the first electrode structure 402 is covered by the first passivation layer 108, and the first electrode structure 402 and the sacrificial dielectric layer 109b are separated by the passivation layer and do not contact each other.

[0114] Combination Figure 11 As shown, a cavity boundary layer 110 is formed on the side of the piezoelectric layer 104 away from the second electrode layer 103. For example, the cavity boundary layer 110 covers the sidewalls of the sacrificial dielectric layer 109b and the surface away from the piezoelectric layer 104, the sidewalls of the supporting dielectric layer 109 and its surface away from the piezoelectric layer 104, and a portion of the surface of the first passivation layer 108. The material of the cavity boundary layer 110 is different from the material of the dielectric material layer, that is, different from the materials of the supporting dielectric layer 109 and the sacrificial dielectric layer 109b. In some embodiments, the material of the cavity boundary layer 110 may include a semiconductor material, a dielectric material, the like thereof, or a combination thereof. For example, the cavity boundary layer 110 may include amorphous silicon, polycrystalline silicon, silicon nitride, aluminum nitride, the like thereof, or a combination thereof, and may be formed by a suitable deposition process such as CVD or atomic layer deposition (ALD).

[0115] In some embodiments, forming the cavity boundary layer 110 further includes forming a first boundary layer opening 110a and a second boundary layer opening 110b in the cavity boundary layer 110. For example, forming the cavity boundary layer 110 may include depositing a cavity boundary material layer over the piezoelectric layer 104 and then etching away a portion of the cavity boundary material layer to form the cavity boundary layer 110 having the aforementioned boundary layer openings.

[0116] In some embodiments, a first boundary layer opening 110a exposes a portion of the first passivation layer 108 directly above the first electrode structure 402, and a second boundary layer opening 110b exposes a portion of the first passivation layer 108 directly above the additional electrode structure 403. That is, the first boundary layer opening 110a and the second boundary layer opening 110b overlap with the first electrode structure 402 and the additional electrode structure 403 respectively in a direction perpendicular to the main surface of the piezoelectric layer 104. For example, the orthographic projection of the first boundary layer opening 110a onto the main surface of the piezoelectric layer 104 lies within the orthographic projection of the first electrode structure 402 onto the main surface of the piezoelectric layer 104; the orthographic projection of the second boundary layer opening 110b onto the main surface of the piezoelectric layer 104 lies within the orthographic projection of the additional electrode structure 403 onto the main surface of the piezoelectric layer 104.

[0117] Combination Figure 12 As shown, a carrier bonding layer 111 is formed on the side of the cavity boundary layer 110 away from the piezoelectric layer 104, and the carrier bonding layer 111 fills the first boundary layer opening 110a and the second boundary layer opening 110b. For example, the carrier bonding layer 111 has a first filling portion located in the first boundary layer opening 110a and a second filling portion located in the second boundary layer opening 110b.

[0118] In some embodiments, the cavity boundary layer 110 may be a conformal layer, i.e., having a morphology conforming to the underlying material layer, while the carrier bonding layer 111 covers the cavity boundary layer 110 and has a generally flat surface on the side away from the piezoelectric layer 104 to facilitate subsequent bonding processes. The material of the carrier bonding layer 111 may be different from the material of the cavity boundary layer 110; for example, the carrier bonding layer 111 may include a dielectric material such as silicon oxide (SiO2). The method of forming the carrier bonding layer 111 may include forming it by depositing a bonding material layer and then performing a planarization process (e.g., CMP) on the bonding material layer, thereby giving the carrier bonding layer 111 a flat surface.

[0119] Combination Figure 13 As shown, a carrier substrate 200 is provided, and a bonding process is performed to bond the carrier substrate 200 to a carrier bonding layer 111. In some embodiments, the carrier substrate 200 may include a semiconductor material, a dielectric material, the like, or a combination thereof. For example, the carrier substrate 200 includes a stack of silicon (Si), silicon oxide (SiO2), polycrystalline silicon, silicon carbide, the like, or combinations thereof. In some embodiments, the carrier substrate 200 includes a semiconductor substrate (e.g., a silicon-containing substrate) and a dielectric material layer (e.g., silicon oxide) located on the semiconductor substrate, and can be bonded to the carrier bonding layer 111 through the dielectric material layer. In some embodiments, the carrier substrate 200 may be a semiconductor wafer, such as a silicon wafer.

[0120] Combination Figure 14 and Figure 15 As shown, substrate 100 and dielectric layer 101 are removed to expose the surface of second passivation layer 102 on the side away from piezoelectric layer 104. Figure 16 As shown, a patterning process (e.g., including photolithography and etching processes) is performed on the second passivation layer 102 and the second electrode layer 103 to remove portions of the second passivation layer 102 and the second electrode layer 103 and form the second electrode E2, and the surface of the second passivation layer 102 corresponding to the second electrode E2 on the side away from the piezoelectric layer 104 is covered.

[0121] In some embodiments, the patterning process includes forming a passivation opening in the second passivation layer 102 and forming an electrode via in the second electrode layer 103. The passivation opening and the electrode via are spatially connected to each other. The electrode via extends through the second electrode E2 and exposes the sidewall of the second electrode E2 and a portion of the surface of the piezoelectric layer 104 away from the first electrode layer 105. At least a portion of the electrode via and the passivation opening is located directly above the additional electrode structure 403, that is, at least a portion of the orthographic projection of the electrode via and the passivation opening onto the main surface of the piezoelectric layer 104 overlaps with the orthographic projection of the additional electrode structure 403 onto the main surface of the piezoelectric layer 104.

[0122] Combination Figure 17 and Figure 18 As shown, an etching process is performed on the piezoelectric layer 104 to remove portions of the piezoelectric layer 104 exposed by the second electrode layer 103 and the second passivation layer 102, and to form piezoelectric vias 104a and additional piezoelectric vias 104b extending through the piezoelectric layer 104. The piezoelectric vias 104a include those located in the cut-through region 401 and those located in the internal region of the device. For example, the piezoelectric via 104a exposes a portion of the surface of the first electrode structure 402 away from the carrier substrate 200; the additional piezoelectric via 104b communicates with the electrode vias and the passivation opening space, and exposes a portion of the surface of the additional electrode structure 403 away from the carrier substrate 200. In some embodiments, the etching process also forms one or more release holes 500 in the piezoelectric layer 104, the release holes 500 extending through the piezoelectric layer 104 and exposing a portion of the surface of the sacrificial dielectric layer 109b away from the carrier substrate 200. For example, the etching process removes a portion of the piezoelectric layer 104 and the first passivation layer 108 directly above the sacrificial dielectric layer 109b to form the release holes 500. The release holes 500 expose a portion of the surface of the sacrificial dielectric layer 109b without exposing the second electrode structure layer, the cavity boundary layer 110, and the supporting dielectric layer 109, etc.

[0123] In some embodiments, during the etching process of the piezoelectric layer 104, a small portion of the second passivation layer 102 and the second electrode layer 103 may also be removed by the etching process, and for example, the size of the electrode vias and passivation openings may be increased or the shape may be changed. For example, the portion of the surface of the piezoelectric layer 104 away from the first electrode structure layer 400 may also be exposed by the electrode vias and passivation openings.

[0124] In some embodiments, the second passivation layer 102 is further etched to remove the portion of the second passivation layer 102 covering the second electrode E2 and to form a passivation opening in the second passivation layer 102. The location of the passivation opening is offset from the location of the electrode via in a direction parallel to the main surface of the piezoelectric layer 104, that is, the orthogonal projection of the passivation opening on the piezoelectric layer 104 is offset from the orthogonal projection of the electrode via on the piezoelectric layer 104. The passivation opening extends through the second passivation layer 102 and exposes a portion of the surface of the second electrode E2 away from the piezoelectric layer 104. In some embodiments, the etching process may not remove the passivation layer around the passivation opening; in other embodiments, the etching process may also remove a portion of the passivation layer around the passivation opening, thereby allowing the size of the passivation opening to be further increased and exposing a portion of the surface of the second electrode E2 away from the piezoelectric layer 104.

[0125] Combination Figure 19 As shown, a pad layer 404 is formed on the side of the piezoelectric layer 104 away from the carrier substrate 200. The pad layer 404 includes one or more conductive pads, such as cut track pads 210, first conductive pads 220, second conductive pads 230, and interconnect pads 240. For example, a conductive material layer can be deposited on the piezoelectric layer 104, the second electrode layer 103, and the passivation layer, and this conductive material layer fills each piezoelectric via 104a, electrode via, and passivation opening; subsequently, a patterning process including etching is performed on the conductive material layer to form the pad layer 404 including the one or more conductive pads. That is, the cut track pads 210, first conductive pads 220, second conductive pads 230, and interconnect pads 240 are disposed in the same layer of the pad layer 404. In this document, "disposed in the same layer" means that the multiple components are formed from the same material layer using the same patterning process.

[0126] For example, the cut track pad 210 and the first conductive pad 220 are filled into the piezoelectric via 104a to be electrically connected to the first electrode structure 402; the second conductive pad 230 is filled into the passivation opening to be electrically connected to the second electrode E2; and the interconnect pad 240 is filled into the passivation opening, the electrode via, and the additional piezoelectric via 104b to be electrically connected to the second electrode E2 and the additional electrode structure 403. The interconnect pad 240 and the additional electrode structure 403 together constitute an intermediate connection member.

[0127] In some embodiments, the cut track pad 210 and the first conductive pad 220 partially fill the piezoelectric via 104a, for example, lining the surface of the piezoelectric via 104a, and have recesses. The recesses, for example, include portions of the piezoelectric via 104a that are not filled by the pad layer 404. Interconnect pads 240 fill additional piezoelectric vias 104b and form recesses; for example, the interconnect pads 240 partially fill the passivation openings, electrode vias, and additional piezoelectric vias 104b, for example, lining the surfaces of the passivation openings, electrode vias, and additional piezoelectric vias 104b, and have recesses, for example, including portions of the passivation openings, electrode vias, and additional piezoelectric vias 104b that are not filled by the pad layer 404.

[0128] Combination Figure 20 As shown, the sacrificial dielectric layer 109b and the first passivation layer 108 covered by the sacrificial dielectric layer 109b are removed to form a first cavity. For example, the sacrificial dielectric layer 109b and the first passivation layer 108 covered by the sacrificial dielectric layer 109b can be removed by an etching process. This etching process may include applying an etchant to the region where the sacrificial dielectric layer 109b is located through a release hole 500 in the piezoelectric layer 104, thereby removing the sacrificial dielectric layer 109b and the first passivation layer 108 covered by the sacrificial dielectric layer 109b, and forming the first cavity at the location previously occupied by the sacrificial dielectric layer 109b and the first passivation layer 108 covered by the sacrificial dielectric layer 109b. The etchant may include, for example, a buffer oxide etching (BOE) or hydrofluoric acid (e.g., diluted hydrofluoric acid (DHF)). The buffer oxide etchant is a mixture of hydrofluoric acid (HF) and NH4F. The etching process has a high etching selectivity for adjacent material layers such as the sacrificial dielectric layer 109b, cavity boundary layer 110, first passivation layer 108, piezoelectric layer 104, and first electrode structure 402, and substantially does not remove the cavity boundary layer 110, piezoelectric layer 104, and first electrode structure 402. Furthermore, the cavity boundary layer 110 separates the sacrificial dielectric layer 109b from the carrier bonding layer 111 and support dielectric layer 109, thereby protecting the carrier bonding layer 111 and support dielectric layer 109 from damage by the etching process.

[0129] Combination Figure 20 As shown, this forms the resonant main structure 10 and the carrier structure 20. The specific structures of the resonant main structure 10 and the carrier structure 20 are similar to those shown in the diagram. Figure 1 The descriptions are consistent, so I will not repeat them here.

[0130] Combination Figure 21 As shown, the substrate layer 300 forming the cap substrate 405 requires grinding and etching of the semiconductor wafer to create the recess. Combined with... Figure 22As shown, a stress-adjusting layer 310 and a barrier layer 311 are sequentially disposed on the recessed side of the substrate layer 300 to form a cover substrate 405. Figure 23 As shown, a cover bonding layer 301 is formed on one side of the barrier layer 311 of the cover substrate 405 to obtain a cover structure 30. This bonds the cover structure 30 to the resonant host structure 10, and the cover structure 30 and the resonant host structure 10 enclose a second cavity. The material of the substrate layer 300 may be the same as or different from the material of the carrier substrate 200. For example, the material of the substrate layer 300 may be or may include semiconductor materials, insulating materials, piezoelectric materials, etc., such as high-resistivity silicon, low-resistivity silicon, glass, silicon carbide, lithium niobate (LiNbO3), lithium carbonate (LiTaO3), etc. For example, the substrate layer 300 may be a wafer, such as a silicon wafer or other semiconductor wafer. The material of the stress-adjusting layer 310 may be silicon dioxide, silicon nitride, or a composite layer thereof. The material of the barrier layer 311 may be aluminum nitride or aluminum oxide. The cover bonding layer 301 may include organic materials, such as dry film, photoresist, or similar materials.

[0131] In some embodiments, forming a cover bonding layer 301 on a cover substrate 405 may include: depositing a bonding material layer on the cover substrate 405, followed by a patterning process on the bonding material layer to remove portions of the bonding material layer and form the cover bonding layer 301. In some embodiments, since the cover bonding layer 301 is made of a dry film or photoresist material, a photolithography process including exposure and development can be used to pattern the cover bonding layer 301, and the patterning process may not require an etching process. In some embodiments, the cover bonding layer 301 may be disposed on an edge portion of the cover substrate 405 and may be annular.

[0132] Subsequently, the side of the cover substrate 405 with the cover bonding layer 301 is faced towards the resonant host structure 10, and a bonding process is performed to bond the cover structure 30 to the resonant host structure 10. In some embodiments, since the cover bonding layer 301 is bonded to the underlying structure after patterning, and the bonding surface of the underlying structure may have an uneven morphology, using a relatively soft organic material such as a dry film or photoresist for the cover bonding layer 301 can facilitate the bonding process and make the bonded structure have high stability and reliability.

[0133] For example, the cover bonding layer 301 may be bonded to the piezoelectric layer 104 and the dicing pad 210. In some embodiments, the cover bonding layer 301 fills the recess of the dicing pad 210, thereby increasing the bonding area between the cover bonding layer 301 and the underlying structure and improving the bonding strength between the cover structure 30 and the resonant body structure 10.

[0134] In some embodiments, the wafer structure can be tested via test pads before the cover structure 30 is bonded to the resonant body structure 10. For example, the wafer structure can be tested using a first conductive pad 220 electrically connected to a first electrode E1 and a second conductive pad 230 electrically connected to a second electrode E2. The testing may include a wafer acceptance test (WAT), but this disclosure is not limited thereto. In some embodiments, the testing may include testing relevant performance parameters of the resonator (e.g., frequency, etc.), and adjustments may be made to relevant structural parameters of the resonator (e.g., thickness, etc.) based on the test results, so that the subsequently formed resonator meets the expected requirements. In this document, a wafer structure includes a wafer and various components formed on the wafer.

[0135] Combination Figure 24 As shown, after bonding the cap structure 30, the carrier substrate 200 of the carrier structure 20 can be ground to reduce the thickness of the carrier substrate 200.

[0136] Combination Figure 25 As shown, an etching process is performed on the carrier structure 20 and the first passivation layer 108 to form a first carrier via 20a and a second carrier via 20b in the carrier structure 20, and a recessed structure 406 in the etch channel region 401, and a first passivation opening and a second passivation opening in the first passivation layer 108. The recessed structure 406 of the carrier structure 20 has a recess that reaches the cavity boundary layer 110, and the filler in the recessed structure 406 contacts the cavity boundary layer 110, the carrier bonding layer 111, and the carrier substrate 200. The first carrier via 20a and the first passivation opening are spatially connected to each other and expose a portion of the surface of the first electrode structure 402 away from the piezoelectric layer 104, for example, exposing a portion of the surface of the first electrode edge bump P1; the second carrier via 20b and the second passivation opening are spatially connected to each other and expose a portion of the surface of the additional electrode structure 403 away from the piezoelectric layer 104, for example, exposing a portion of the surface of the additional electrode bump AP1.

[0137] For example, the etching process removes portions of the carrier substrate 200, the carrier bonding layer 111, and the first passivation layer 108 to form a first carrier via 20a and a first passivation opening, exposing a portion of the surface of the first electrode structure 402 away from the piezoelectric layer 104, and forming a second carrier via 20b and a second passivation opening to expose a portion of the surface of the additional electrode structure 403 away from the piezoelectric layer 104. In some embodiments, at least a portion of the first filling portion and at least a portion of the second filling portion of the carrier bonding layer 111, as well as portions of the carrier bonding layer 111, the carrier substrate 200, and the first passivation layer 108 overlapping with the first filling portion and the second filling portion in a direction perpendicular to the main surface of the piezoelectric layer 104, are removed in the etching process. In some embodiments, the number and / or thickness of material layers removed to form the first carrier via 20a may be substantially the same as the number and / or thickness of material layers removed to form the second carrier via 20b.

[0138] For example, the first carrier via 20a and the second carrier via 20b are located in the carrier substrate 200 and the carrier bonding layer 111, and extend through the carrier substrate 200 and the carrier bonding layer 111 and communicate with the corresponding passivation opening space. A portion of the first carrier via 20a is located in the first filling portion of the carrier bonding layer 111 and is surrounded by the first boundary opening of the cavity boundary layer 110; a portion of the second carrier via 20b is located in the second filling portion of the carrier bonding layer 111 and is surrounded by the second boundary opening of the cavity boundary layer 110. For example, during the formation of the carrier vias, the first filling portion and the second filling portion of the carrier bonding layer 111 may be partially removed, or may be completely removed, such that the portions of the first carrier via 20a and the second carrier via 20b near the passivation opening are located in the regions of the first boundary opening and the second boundary opening. In some embodiments, the portion of the first carrier via 20a near the first passivation opening and the orthographic projection of the first passivation opening on the main surface of the piezoelectric layer 104 may be located within the orthographic projection of the first boundary layer opening 110a of the cavity boundary layer 110 on the main surface of the piezoelectric layer 104; the portion of the second carrier via 20b near the second passivation opening and the orthographic projection of the second passivation opening on the main surface of the piezoelectric layer 104 may be located within the orthographic projection of the second boundary layer opening 110b of the cavity boundary layer 110 on the main surface of the piezoelectric layer 104.

[0139] In some embodiments, the etching process described above for forming the first carrier via 20a and the second carrier via 20b may substantially not remove the cavity boundary layer 110 and the supporting dielectric layer 109. The above-described arrangement of the carrier structure 20 can reduce the number of material layers that need to be removed during the etching process, thereby simplifying the etching process and reducing the difficulty of forming the carrier vias.

[0140] Combination Figure 26As shown, a first rewiring layer 302a and a second rewiring layer 302b are formed on the carrier structure 20. The first rewiring layer 302a fills the first carrier via 20a and the first passivation opening to contact and electrically connect with the first electrode structure 402; the second rewiring layer 302b fills the second carrier via 20b and the second passivation opening to contact and electrically connect with the additional electrode structure 403. The first rewiring layer 302a and the second rewiring layer 302b can be formed from the same conductive material layer and can be formed in the same patterning process. For example, the first rewiring layer 302a may include a first conductive via and a first wire connected to each other; the second rewiring layer 302b may include a second conductive via and a second wire connected to each other.

[0141] Combination Figure 27 As shown, a third passivation layer 303 is formed on the side of the carrier structure 20, the first redistribution layer 302a, and the second redistribution layer 302b away from the piezoelectric layer 104. The third passivation layer 303 fills the recessed structure 406 of the carrier structure 20. In some embodiments, the redistribution layer may not completely fill the carrier vias and / or passivation openings, and the third passivation layer 303 may fill the portion of the carrier vias that is not filled by the carrier vias and / or passivation openings. The third passivation layer 303 may also have a first opening and a second opening, the first opening exposing a portion of the surface of the first redistribution layer 302a, and the second opening exposing a portion of the surface of the second redistribution layer 302b.

[0142] Combination Figure 28 As shown, a first conductive bump 304a is formed in the first opening, and a second conductive bump 304b is formed in the second opening. The first conductive bump 304a is electrically connected to the first redistribution layer 302a, and the second conductive bump 304b is electrically connected to the second redistribution layer 302b. The conductive bump may be or include a solder bump. In some embodiments, forming the conductive bump may include forming a bump material and performing a reflow soldering process on the bump material. For example, a portion of the third passivation layer 303 may be etched away first to form a first opening and a second opening in the third passivation layer 303 that expose the first redistribution layer 302a and the second redistribution layer 302b, respectively. The bump material is filled into the openings and electrically connected to the first redistribution layer 302a and the second redistribution layer 302b, respectively.

[0143] For example, combining Figure 28 As shown, a first bump material and a second bump material are formed on the side of the first redistribution layer 302a and the second redistribution layer 302b away from the piezoelectric layer 104, respectively. The first bump material and the second bump material may be solder paste or may be formed on the respective redistribution layers, for example, by a printing process. In this step, the cross-sectional shape of the bump material may be square or similar. Then, combined with... Figure 29As shown, a reflow soldering process is performed on the first bump material and the second bump material to form a first conductive bump 304a and a second conductive bump 304b; after the reflow soldering process, the conductive bumps may have a spherical or similar shaped surface; for example, the conductive bumps may include solder balls.

[0144] Combination Figure 29 As shown, the manufacturing process of the bulk acoustic wave resonator is now largely complete. In some embodiments, the bulk acoustic wave resonator is manufactured using a wafer-level packaging process, and the resulting package structure includes multiple dies, each of which may contain one or more bulk acoustic wave resonators. It should be understood that... Figures 3 to 29 Only cross-sectional views of the region corresponding to a single resonator in each step of the packaging process are shown. Other resonators located in the same or different dies within the overall packaging structure are formed simultaneously using similar or identical steps and may have similar or identical structures. In some embodiments, after forming multiple conductive bumps, the formed wafer-level packaging structure may be diced in the dicing region 401 to separate the multiple dies from each other, making the multiple dies independent of each other and each including one or more bulk acoustic wave resonators; for example, the dies may include filters composed of multiple bulk acoustic wave resonators.

[0145] This disclosure provides a filter comprising a plurality of resonators (e.g., bulk acoustic wave resonators) connected to each other in series and / or parallel. The filter also possesses the technical effects described above for the resonators. In some embodiments, each bulk acoustic wave resonator in the filter may have a structure similar to or identical to the bulk acoustic wave resonator provided in this disclosure and may be connected to each other via conductive traces. For example, in the process step of patterning the first electrode structure layer 400 (e.g., the first electrode layer 105), in addition to forming the first electrode E1 and additional electrode AE1 of the plurality of resonators, the process may also include forming conductive traces connecting the first electrode E1 of the respective resonators; in the process step of patterning the second electrode layer 103, in addition to forming the second electrode E2 of the plurality of resonators, the process may also include forming conductive traces connecting the second electrode E2 of the respective resonators.

[0146] In some embodiments, for multiple resonators interconnected (e.g., in series) in a filter, it is not necessary to provide conductive connectors and test pads in each resonator. For example, one of the multiple resonators (e.g., a first resonator) may be provided with conductive connectors, and test pads may not be required in the first resonator; and another of the multiple resonators (e.g., a second resonator) may be provided with test pads, and conductive connectors may not be required in the second resonator. Interconnect pads 240 and additional electrode structures 403 for electrical connections between the second conductive connector 305b and the second electrode E2 may be provided or omitted. Since the multiple resonators are connected in series, voltages can be applied to the corresponding electrodes of the multiple resonators through the conductive connectors in the first resonator; and the filter comprising the multiple resonators can be tested through the test pads of the second resonator.

[0147] Combination Figure 30 As shown, the cover bonding layer 301 and the dicing pad 210 can be made of the same metal material. In this case, the cover bonding layer 301 may not include the protrusions that fill the recesses of the dicing pad 210.

[0148] Combination Figure 31 As shown, the cover bonding layer 301 and the dicing pad 210 can be made of the same metal material, and the dicing pad 210 does not have a recess that is recessed toward the first electrode structure layer 400.

[0149] Combination Figure 32 As shown, the conductive connector is directly connected to the corresponding electrode structure in the first electrode structure layer 400 through conductive vias. At this time, the first redistribution layer 302a fills the first carrier via 20a and the first passivation opening. In this embodiment, the conductive bump is directly electrically connected to the corresponding electrode through conductive vias. This manufacturing process can save on the number of masks, increase design freedom, thereby simplifying the process and saving costs.

[0150] Combination Figure 33 As shown, a first passivation layer 108 is provided at the resonant main structure 10 and the first cavity to protect the first electrode structure layer 400.

[0151] Combination Figure 34 As shown, the recessed structure 406 of the carrier structure 20 has a recess that reaches the first passivation layer 108, that is, the filler in the recessed structure 406 is in contact with the first passivation layer 108, the supporting dielectric layer 109, the cavity boundary layer 110, the carrier bonding layer 111 and the carrier substrate 200.

[0152] Figures 30 to 34 The other structural features of the bulk acoustic resonator shown are similar to those of the bulk acoustic resonator described in the foregoing embodiments, and have the same or similar technical effects as the bulk acoustic resonator, so they will not be described again here.

[0153] In this embodiment, the dicing pad 210 and recessed structure 406 provided in the dicing area 401 can open the dicing channel and carrier structure 20 in advance to release stress, providing buffer and stress release space for thermal expansion and contraction of the device during process and subsequent packaging. This can effectively reduce the risk of chip edge peeling or cracking caused by stress concentration during reflow soldering and chip dicing, thereby improving overall yield and long-term reliability. In addition, at least a portion of the dicing pad 210 is bonded to the cover bonding layer 301, and the dicing pad 210 has a recess that faces the first electrode structure layer 400, which can also include the dicing area 401 in the bonding interface, increasing the total bonding area and mechanical anchor points between the cover structure 30 and the resonant main body structure 10, thereby enhancing bonding strength and hermeticity, preventing the bonding interface from failing under mechanical or thermal stress, and enhancing structural stability.

[0154] Furthermore, by placing the conductive connectors of the resonator and the cover structure 30 on different sides of the piezoelectric layer 104, problems such as delamination and bump breakage caused by the cover bonding layer 301 can be avoided or reduced, thereby improving the device reliability of the resonator and filter. In addition, the first and second conductive pads 230 located on the second side of the piezoelectric layer 104 are only used as test pads, so their influence on resistance can be disregarded, allowing for a relatively small thickness of these conductive pads, thus reducing costs. Moreover, by using one or more conductive pads of the pad layer 404 as bonding pads and providing recesses, and filling the recesses of the bonding pads with the cover bonding layer 301, the bonding strength between the cover structure 30 and the resonant body structure 10 can be improved, thereby enhancing the device reliability and performance. Additionally, in some embodiments, the overall structural strength of the carrier structure 20 and the resonator device can also be improved through the related arrangement of the carrier structure 20, thereby enhancing the device reliability and performance.

[0155] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the technical solutions described herein. As used in the technical solutions described herein, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein refers to any and all possible combinations of one or more of the associated listed elements. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

Claims

1. A method for manufacturing a bulk acoustic resonator, characterized in that, include: A substrate is obtained, and a second electrode material, a piezoelectric material, and a first electrode material are sequentially deposited on the substrate; The first electrode material is patterned to form a first electrode structure, thereby obtaining a first electrode structure layer. A carrier structure is deposited on the side of the first electrode structure layer away from the piezoelectric material; The substrate is removed, and the second electrode material is patterned to form the second electrode, thus obtaining the second electrode layer. A piezoelectric material is patterned to form a piezoelectric layer, thereby obtaining the resonant main structure. The interior of the carrier structure is etched to form a first cavity, and part of the first electrode structure is located in the first cavity; The cover wafer is ground and etched to form a substrate layer with depressions; A stress-adjusting layer and a barrier layer are sequentially disposed on the side of the substrate layer with a depression to form a cover substrate; The cover substrate is bonded to the side of the barrier layer near the resonant main structure near the second electrode layer by the cover bonding layer to form a second cavity, and a portion of the second electrode layer is located in the second cavity.

2. The manufacturing method according to claim 1, characterized in that, Also includes: After patterning the piezoelectric material, multiple piezoelectric vias extending through the piezoelectric layer are formed; Piezoelectric vias include piezoelectric vias located in the cut-out area and piezoelectric vias located in the internal area of ​​the device; The cutting channel region is located on two opposite sides of the resonant main structure in the second direction; A conductive material layer is deposited on the piezoelectric layer and the second electrode layer, and the conductive material layer fills each piezoelectric via. A patterning process is performed on the conductive material layer to form a dicing pad in the dicing area and a first conductive pad in the internal area of ​​the device; both the dicing pad and the first conductive pad have a recess that is recessed toward the first electrode structure layer.

3. The manufacturing method according to claim 2, characterized in that, Bonding the side of the cover substrate near the barrier layer to the side of the resonant main structure near the second electrode layer via a cover bonding layer includes: A bonding material layer is deposited on the side of the cap substrate near the barrier layer; A patterning process is performed on the bonding material layer to remove a portion of the bonding material layer, forming a cap bonding layer and obtaining a cap structure. The side of the cover structure with the cover bonding layer is bonded to the piezoelectric layer and the cleavage pad.

4. The manufacturing method according to claim 2, characterized in that, Also includes: After the carrier structure is formed, an etching process is performed on the carrier structure in the cutting channel area to form a recessed structure on the side of the carrier structure away from the resonant main structure. The orthogonal projection of the concave structure onto the resonant main structure lies within the cutting channel region.

5. The manufacturing method according to any one of claims 1 to 4, characterized in that, Also includes: Before forming the carrier structure, a first passivation layer is deposited on the side of the first electrode structure layer away from the piezoelectric material.

6. The manufacturing method according to claim 5, characterized in that, The carrier structure includes: A dielectric material layer is formed on the side of the first passivation layer away from the piezoelectric layer; A patterning process is performed on the dielectric material layer to remove portions of the dielectric material layer and form a support dielectric layer and a sacrificial dielectric layer that are separated from each other. A cavity boundary layer is formed on the side of the piezoelectric layer away from the second electrode layer; the cavity boundary layer covers the sidewall of the sacrificial dielectric layer and the surface away from the piezoelectric layer, the sidewall of the supporting dielectric layer and the surface away from the piezoelectric layer, and a portion of the surface of the first passivation layer; A carrier bonding layer is formed on the side of the cavity boundary layer away from the piezoelectric layer; A carrier substrate is provided, and the carrier substrate is bonded to the carrier bonding layer.

7. The manufacturing method according to claim 6, characterized in that, The internal structure of the carrier is etched to form a first cavity, including: An etching process is performed on the piezoelectric layer to form one or more release holes in the piezoelectric layer; the release holes extend through the piezoelectric layer and expose a portion of the surface of the sacrificial dielectric layer away from the carrier substrate. An etchant is applied to the area containing the sacrificial dielectric layer through a release hole to remove the sacrificial dielectric layer and the first passivation layer covered by the sacrificial dielectric layer, thereby forming a first cavity.

8. The manufacturing method according to claim 6, characterized in that, A cavity boundary layer is formed on the side of the piezoelectric layer away from the second electrode layer, including: A cavity boundary material layer is deposited on the side of the piezoelectric layer away from the second electrode layer; A portion of the cavity boundary material layer is etched away to form a cavity boundary layer with a first boundary layer opening and a second boundary layer opening.

9. The manufacturing method according to claim 8, characterized in that, Also includes: After forming the carrier structure, an etching process is performed on the carrier structure and the first passivation layer to form a first carrier via and a second carrier via in the carrier structure, and to form a first passivation opening and a second passivation opening in the first passivation layer; wherein, the portion of the first carrier via near the first passivation opening and the orthographic projection of the first passivation opening on the main surface of the piezoelectric layer are located within the orthographic projection of the first boundary layer opening of the cavity boundary layer on the main surface of the piezoelectric layer; the portion of the second carrier via near the second passivation opening and the orthographic projection of the second passivation opening on the main surface of the piezoelectric layer are located within the orthographic projection of the second boundary layer opening of the cavity boundary layer on the main surface of the piezoelectric layer. A first conductive connector and a second conductive connector are formed on the carrier structure; the first conductive connector is filled into a first carrier through-hole and a first passivation opening, and the second conductive connector is filled into a second carrier through-hole and a second passivation opening; wherein, the first conductive connector extends through the carrier structure to be electrically connected to the first electrode structure, and the second conductive connector extends through the carrier structure and is electrically connected to the second electrode through an intermediate connecting member.

10. A filter, characterized in that, This includes a bulk acoustic resonator manufactured using the manufacturing method of a bulk acoustic resonator as described in any one of claims 1 to 9.

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