Passive switched capacitor filter with tunable complex poles

Abstract

The present disclosure relates to passive switched-capacitor filters with tunable complex poles. A filter circuit employing both an active filter circuit and a switched-capacitor filter circuit is disclosed. The active filter circuit can reject high frequency blocking signals near the sampling frequency of the switched-capacitor filter circuit to generate a pre-filtered signal. The switched-capacitor filter circuit can employ feedback to introduce complex poles into the transfer circuit of the filter circuit. A load driver circuit can be used to buffer the output of the switched-capacitor filter circuit in order to drive a desired load circuit.

Description

Technical Field

[0001] This disclosure relates to the specific implementation of integrated circuits, and more specifically, to the specific implementation of filter circuits. Background Technology

[0002] Communication systems typically include multiple integrated circuits that can send and receive signals among themselves. Signals can be transmitted and received via wires, cables, or other suitable conductors. Alternatively, signals can be transmitted and received wirelessly.

[0003] The transmitted signal is affected by various noise sources, which can degrade signal fidelity. Wireless signals may also be degraded due to interactions with other wireless signals, changes in the medium through which the signal propagates, and so on. Such degradation can make decoding these signals difficult, potentially leading to the loss of encoded information.

[0004] Communication systems typically employ filtering to improve signal quality before decoding the information embedded in the signal. Filtering attenuates the frequency range associated with unwanted signals and / or noise, thereby improving the quality of the desired signal. Filters can be implemented using both active and passive circuit components. Attached Figure Description

[0005] Figure 1 A block diagram illustrating an implementation scheme for a filter circuit.

[0006] Figure 2 A block diagram illustrating an implementation scheme for an active pre-filter circuit.

[0007] Figure 3 A block diagram illustrating an implementation scheme for a passive switched capacitor filter circuit.

[0008] Figure 4 An example waveform of the clock phase used by a passive switched capacitor filter circuit is depicted.

[0009] Figure 5 A block diagram illustrating an implementation scheme with interleaved passive filter circuitry.

[0010] Figure 6 A block diagram illustrating an implementation scheme for the receiver circuit.

[0011] Figure 7 This is a flowchart illustrating an implementation scheme for a method of filtering signals.

[0012] Figure 8 This is a block diagram of an implementation scheme for a device that may include filter circuitry.

[0013] Figure 9This is a block diagram of various implementations of a computer system that may include filter circuitry.

[0014] Figure 10 An example of a non-transitory computer-readable storage medium for storing circuit design information is shown. Detailed Implementation

[0015] Many computer systems use wireless communication systems to exchange data with other computer systems. For example, mobile computer systems (such as cellular phones or tablets) can connect to wireless cellular networks to send and receive information. Such mobile computer systems can also use WiFi or other wireless network technologies to connect to a variety of computer systems.

[0016] In wireless communication systems, anti-aliasing filters are typically used before the analog-to-digital converter stage. These filters help remove out-of-band signals (often referred to as "blocking") that may be aliased back into the band of interest during analog-to-digital conversion.

[0017] In broadband receivers, Nyquist-rate analog-to-digital converter circuits with limited or, in some cases, no oversampling ratios can be used due to power consumption considerations. In such cases, the combination of a flat passband response and selectivity requirements relative to adjacent channels may necessitate that the transfer function of the filter circuit contains complex poles.

[0018] For example, a third-order filter can be implemented using a Tow-Thomas double second-order followed by a first-order amplifier as the core of the filter. However, such a solution can consume a significant amount of power due to the use of three amplifier circuits. Furthermore, this solution does not scale well because higher-order filters require additional amplifier circuitry.

[0019] Another technique involves using a transconductance stage that converts the input voltage into a current that is dumped into a holding capacitor. The output signal is then sampled and integrated in the charge domain. The sampling and integration operations are performed in continuous phase to achieve real poles, which can result in a relatively slow transition in the filter response from the passband to the stopband in the frequency domain.

[0020] Similar techniques can be used to achieve discrete-time feedback by retaining the history of signal charge in the sampling capacitor, which produces complex poles. Such complex poles can sharpen the near-band signal transfer function of the filter circuit. In this specific implementation, the feedback factor is fixed, and the quality factor is finite (e.g., It is also related to the filter bandwidth, as it is determined by the ratio of the geometric mean to the arithmetic mean of the integrating capacitors.

[0021] The embodiments shown in the accompanying figures and described below provide techniques for generating complex poles in the filter transfer function. By employing a hybrid architecture that combines a discrete-time (DT) core with continuous-time (CT) feedback to leverage the benefits of both techniques, the power consumption of the filter circuitry can be reduced. Furthermore, since signal processing is performed in the voltage domain, without using a front-end across the conductor capacitor level, design problems such as nonlinearity and limited bandwidth expansion are avoided.

[0022] exist Figure 1 The block diagram of the filter circuit is shown in the figure. As shown, the filter circuit 100 includes a pre-filter circuit 101, a switched capacitor filter circuit 102, and a load driver circuit 103.

[0023] The pre-filter circuit 101 is configured to filter the input signal 104 to generate a pre-filtered signal 105. As described below, the pre-filter circuit 101 can be an active filter, comprising amplifier circuitry and one or more passive circuit elements, such as resistors and capacitors. In various embodiments, using the pre-filter circuit 101 allows suppression of high-frequency blocking signals near the sampling frequency of the switched capacitor filter circuit 102. Additionally, the pre-filter circuit 101 can be configured to provide tunable gain.

[0024] The switched-capacitor filter circuit 102 is configured to generate a filtered signal 106 using a pre-filtered signal 105 and a clock phase 108. In various embodiments, the clock phase 108 includes a plurality of non-overlapping clock signals that determine multiple time periods during which the switched-capacitor filter circuit 102 performs various functions. As described below, the switched-capacitor filter circuit 102 may include a plurality of switches and capacitors that do not consume any quiescent power. Furthermore, the switched-capacitor filter circuit 102 may implement complex poles in the transfer function of the filter circuit 100 and may provide most of the filtering suppression of the filter circuit 100.

[0025] In order to generate the filtered signal 106, the switched capacitor filter circuit 102 is configured to: couple the pre-filtered signal 105 to the filter node 109 during a first time period, wherein the filter node 109 is coupled to the ground power supply node via a first capacitor; and couple a second capacitor between the filter node 109 and the ground power supply node during a second time period after the first time period.

[0026] The switched capacitor filter circuit 102 is also configured to couple the output signal 107 to the filter node 109 via a third capacitor during a second time period; and to couple a fourth capacitor between the filter node 109 and the ground power supply node during a third time period after the second time period.

[0027] Load driver circuit 103 is configured to generate output signal 107 using filtered signal 106. In various embodiments, filtered signal 106 may correspond to voltage levels across different filter capacitors included in switched capacitor filter circuit 102. In different embodiments, load driver circuit 103 may be used to drive load impedance, such as analog-to-digital converter circuit. In some embodiments, load driver circuit 103 may be implemented using buffer circuitry or any suitable unity-gain amplifier circuitry.

[0028] Go to Figure 2 A block diagram depicting an embodiment of the pre-filter circuit 101 is shown. As shown, the pre-filter circuit 101 includes an amplifier circuit 201, a resistor 202, and an impedance network 206, which includes a capacitor 203 and a resistor 204.

[0029] Amplifier circuit 201 is configured to receive an input signal at a first input terminal via resistor 202 and amplify the combination of input signal 104 and feedback signal 208 to generate a pre-filtered signal 105. In some embodiments, a second input terminal of amplifier circuit 201 is coupled to ground power supply node 207. In various embodiments, the gain of amplifier circuit can be set based on the corresponding values ​​of resistors 202 and 204.

[0030] In other embodiments, amplifier circuit 201 is also configured to filter input signal 104 to generate pre-filtered signal 105. In some cases, amplifier circuit 201, together with impedance network 206, may be configured to perform low-pass filter operation with a cutoff frequency determined by the corresponding values ​​of resistor 204 and capacitor 203. In various embodiments, impedance network 206 generates feedback signal 208 at node 205, which is coupled to resistor 202 and the input of amplifier circuit 201.

[0031] Amplifier circuit 201 can be implemented as an operational amplifier circuit, a differential amplifier circuit, or any other suitable amplifier circuit. Resistors 202 and 204 can be implemented using polysilicon, aluminum, or any other suitable material available in semiconductor manufacturing processes. Capacitor 203 can be implemented using a metal-oxide-metal (MOM) capacitor structure, a metal-insulator-metal (MIM) structure, or any other suitable capacitor structure available in semiconductor manufacturing processes.

[0032] Go to Figure 3A block diagram depicts an embodiment of a switched capacitor filter circuit 102. As shown, the switched capacitor filter circuit 102 includes capacitors 301 to 304 and switches 305 to 307. In various embodiments, the switched capacitor filter circuit 102 corresponds to a passive bi-second order, which can be used as a structural unit to form a higher-order filter circuit.

[0033] Switch 305 is configured to respond to clock phase The activation of the clock phase couples the pre-filtered signal 105 to node 308 (also known as the "filter node"), which is coupled to the ground power supply node 207 via capacitor 301. When deactivated, switch 305 is turned off and the pre-filtered signal 105 is decoupled from node 308.

[0034] Switch 306 is configured to respond to clock phase The activation of the clock phase couples node 309 to node 308 (which is coupled to ground power node 207 via capacitor 302). Node 309 is also coupled via capacitor 303 to the output signal 107 generated by buffer circuit 311 (shown for reference). In various embodiments, buffer circuit 311 may correspond to load driver circuit 103. When the clock phase... When deactivated, switch 306 is turned off and node 309 is decoupled from node 308.

[0035] Switch 307 is configured to respond to clock phase The activation of the clock couples node 308 to node 310 (which is coupled to ground power node 207 via capacitor 304). In various embodiments, the voltage level across capacitor 304 corresponds to the filtered signal 106. When the clock phase... When deactivated, switch 307 is turned off and node 310 is decoupled from node 308.

[0036] In various implementations, the feedback factor of the switched capacitor filter circuit 102 depends on the ratio of capacitors 302 and 303, as described in Equation 1, where For feedback factors, The value of capacitor 302, and This is the value of capacitor 303.

[0037] Furthermore, using CT mapping and approximation, the natural frequency and quality factor of the switched capacitor filter circuit 102 can be determined according to Equations 2 and 3, respectively. For natural frequency, For quality factor, The value of capacitor 301, The value of capacitor 302, The value of capacitor 304, and Clock phase The frequency.

[0038] The bandwidth of the switched capacitor filter circuit 102 can be used with the sampling frequency. This can be extended, as shown in Equation 2. Furthermore, as shown in Equation 3, the quality factor of the switched capacitor filter circuit 102 can be obtained through... The switching capacitor filter circuit 102 is controlled by the ratio of the values ​​of capacitor 302 to capacitor 304, which provides additional degrees of freedom. It is worth mentioning that the circuit is stable because the Barkhausen oscillation condition is not satisfied.

[0039] The sub-component consisting of switch 306 and capacitors 302 and 303 can be referred to as an integral branch. The order of the switched-capacitor filter circuit (e.g., switched-capacitor filter circuit 102) can be increased by adding more integral branches driven by corresponding clock phases. For example, Order filters can be used This is achieved by using a phase, thereby driving the corresponding integral branch. In this case, Each of the phases has Duty cycle, of which Sampling period Capacitors 301 to 304 can be implemented in various embodiments using MOM capacitor structures, MIM capacitor structures, or any other suitable capacitor structures available in semiconductor manufacturing processes. It should be noted that the corresponding values ​​of capacitors 301 to 304 can be programmable.

[0040] although Figure 3 The implementation is depicted as filtering a single-ended signal (i.e., the pre-filtered signal 105), but in other implementations, the switched-capacitor filter circuit 102 can be configured to filter a differential signal. Various circuit modifications can be employed to filter the differential signal. For example, in some implementations, capacitor 301 can be used to sample the two signals included in the differential signal.

[0041] Switches 305 to 307 may be implemented using one or more transistors or switching devices. In various embodiments, such transistors or switching devices may include n-channel metal-oxide field-effect transistors (MOSFETs) and p-channel MOSFETs, fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), or any other suitable transistors or switching devices.

[0042] Go to Figure 4 The diagram illustrates an example waveform depicting the clock phase used by a passive switched capacitor filter circuit. In various implementations, Figure 1 The clock phase depicted can be used with any suitable switched-capacitor filter circuit (e.g., switched-capacitor filter circuit 102). It should be noted that although in Figure 4 The implementation depicts only four clock phases, but in other implementations, any suitable number of clock phases may be used.

[0043] At time t0, the clock phase in clock phase 108 It is activated and remains active until time t1, at which point the clock phase... It is deactivated. Additionally, at time t1, the clock phase in clock phase 108... It is activated and remains active until time t2.

[0044] At time t2, the clock phase Deactivated, and the clock phase in clock phase 108 Activated. Clock phase. The activity continues until time t3. The sequence of active clock phases continues until the final clock phase. It is activated at time tn. Clock phase. It is deactivated at time t0 because the loop then repeats itself.

[0045] As described above, some switched capacitor filter circuits, such as switched capacitor filter circuit 102, can be generalized as follows: Order 1 filter. For example, order 2 is 1. The filter can be obtained by using It is formed by phases, each phase having Duty cycle, of which This is the sampling period. Additionally, it can be... The slices are interleaved, which can increase the oversampling ratio. This allows for a multiple increase in the sampling rate, thus relaxing the anti-aliasing pre-filtering requirements by pushing the sampling rate to higher frequencies.

[0046] Figure 5The figure depicts a block diagram of an n-order, n-channel interleaved switched capacitor filter circuit. As shown, the switched capacitor filter circuit 500 includes capacitors 501 to 504 and 505a to 505n, and switches 506 to 511.

[0047] Switch 506 is configured to respond to clock phase The activation of the clock phase couples the pre-filtered signal 105 to node 512, which is coupled to ground power node 207 via capacitor 501. When deactivated, switch 506 is turned off and the pre-filtered signal 105 is decoupled from node 512.

[0048] In a similar manner, switch 511 is configured to respond to clock phase. The activation of the clock phase couples the pre-filtered signal 105 to node 513, which is coupled to ground power node 207 via capacitor 504. When deactivated, switch 511 is turned off and the pre-filtered signal 105 is decoupled from node 513.

[0049] Switch 507a is configured to respond to clock phase The activation of the clock phase couples node 514 to node 512 (which is coupled to ground power node 207 via capacitor 502a). Node 514a is also coupled to output signal 107 via capacitor 505a. When deactivated, switch 507a is turned off and node 514a is decoupled from node 512.

[0050] In a similar manner, switch 509a is configured to respond to clock phase. The activation of the clock phase couples node 514a to node 513. When deactivated, switch 509a is turned off and node 514a is decoupled from node 513.

[0051] The switch 507n is configured to respond to clock phase. The activation of the clock phase couples node 514n to node 512 (which is coupled to ground power node 207 via capacitor 502n). Node 514n is also coupled to output signal 107 via capacitor 505n. When deactivated, switch 507n is turned off and node 514n is decoupled from node 512.

[0052] The switch 509n is configured to respond to clock phase. The activation of node 514n couples node 513 to node 513. When the clock phase... When deactivated, switch 509n is turned off and node 514n is decoupled from node 513.

[0053] It should be noted that the other integration branches between the first integration branch, consisting of capacitors 502a and 505a and switches 507a and 509b, and the nth integration branch, consisting of capacitors 502n and 505n and switches 507a and 509b, will use clock phase. to The corresponding clock phase is used for operation.

[0054] Switch 508 is configured to respond to clock phase The activation of the clock couples node 512 to node 515 (which is coupled to ground power node 207 via capacitor 503). In various embodiments, the voltage level across capacitor 503 corresponds to the filtered signal 106. When the clock phase... When deactivated, switch 508 is turned off and node 512 is decoupled from node 515.

[0055] In a similar manner, switch 510 is configured to respond to clock phase. The activation of the clock phase couples node 513 to node 515. When deactivated, switch 510 is turned off and node 513 is decoupled from node 515.

[0056] For the same noise density, Figure 5 The staggered arrangement depicted allows for a reduction in the size of the sampling capacitors (e.g., capacitor 501). The slew rate specification for the pre-filter circuit 101 can be reduced by using multiple smaller capacitors coupled to the pre-filtered signal 105 at different times. Therefore, the switched capacitor filter circuit 102 is formed together with the pre-filter circuit 101. This is a first-order filter circuit. It should be noted that such filter circuits have a hybrid continuous-time feedback and discrete-time core. In some implementations, continuous-time feedback can reduce the additional switching load on the load driver circuit 103 that may be caused by the discrete-time feedback path.

[0057] Capacitors 501 to 505 can be implemented in various embodiments using MOM capacitor structures, MIM capacitor structures, or any other suitable capacitor structures available in semiconductor manufacturing processes. It should be noted that the corresponding values ​​of capacitors 501 to 505 can be programmable.

[0058] although Figure 5The implementation is depicted as filtering a single-ended signal (i.e., the pre-filtered signal 105), but in other implementations, the switched-capacitor filter circuit 500 can be configured to filter a differential signal. Various circuit modifications can be employed to filter the differential signal. For example, in some implementations, capacitors 501 and 504 can be used to sample the two signals included in the differential signal.

[0059] Switches 506 to 511 may be implemented using one or more transistors or switching devices. In various embodiments, such transistors or switching devices may include n-channel MOSFETs and p-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transistors or switching devices.

[0060] Go to Figure 6 A block diagram illustrating an implementation scheme of the receiver circuit is shown. As shown, the receiver circuit 600 includes a filter circuit 601, an analog-to-digital converter circuit 602, and a logic circuit 603.

[0061] Filter circuit 601 is configured to use input signal 604 to generate filtered signal 605. In various embodiments, filter circuit 601 may correspond to, for example... Figure 1 The filter circuit 100 described herein can perform any or all of the operations described above. In some embodiments, the input signal 604 can be received via wire, cable, or other suitable conductor. In other embodiments, the input signal 604 can be received wirelessly by an antenna coupled to the input of the filter circuit 601.

[0062] Analog-to-digital converter (ADC) circuit 602 is configured to generate digital data 606 using a filtered signal 605. To generate digital data 606, ADC circuit 602 may also be configured to sample the filtered signal 605 at multiple time points and convert the corresponding samples into digital words whose values ​​correspond to the magnitudes of the filtered signal 605 at the multiple time points. In various embodiments, ADC circuit 602 may be implemented as a flash ADC circuit or any other suitable type of ADC circuit.

[0063] Logic circuit 603 is configured to generate output data 607 using digital data 606. To generate output data 607, logic circuit 603 may be configured to perform one or more digital signal processing operations on the digital data 606. For example, logic circuit 603 may be configured to perform a finite impulse response filter operation, an infinite impulse response filter operation, or any other suitable digital signal processing operation. In various embodiments, logic circuit 603 may be implemented using any suitable combination of sequential logic circuitry and combinational logic circuitry. For example, logic circuit 603 may be implemented using processor circuitry or microcontroller circuitry.

[0064] In summary, various implementations of filter circuits have been disclosed. Broadly speaking, filter circuits include pre-filter circuits, switched-capacitor filter circuits, and buffer circuits. A pre-filter circuit can be configured to filter an input signal to generate a pre-filtered signal. A switched-capacitor filter circuit can be configured to couple the pre-filtered signal to a first filter node during a first time period, wherein the first filter node is coupled to a ground power supply node via a first capacitor; and to couple a second capacitor between the first filter node and the ground power supply node during a second time period following the first time period. Furthermore, a switched-capacitor filter circuit can also be configured to couple an output signal to the first filter node via a third capacitor during the second time period; and to couple a fourth capacitor between the first filter node and the ground power supply node during a third time period following the second time period. A buffer circuit can be configured to generate an output signal using the voltage level across the fourth capacitor.

[0065] Go to Figure 7 A flowchart of an implementation scheme for a method of filtering signals is disclosed. It can be applied to various filter circuits, such as... Figure 1 The method of the filter circuit 100 depicted in the figure begins with block 701.

[0066] The method includes pre-filtering the input signal by a filter circuit to generate a pre-filtered signal (block 702). In various embodiments, pre-filtering the input signal includes generating a feedback signal using an impedance network coupled between the input and output of the amplifier circuit. In some embodiments, the impedance network includes at least a first resistor and a fifth capacitor. In some cases, the first resistor and the feedback capacitor may be coupled in series. In other embodiments, generating the pre-filtered signal includes amplifying the input signal.

[0067] The method also includes coupling a pre-filtered signal to a first filter node (block 703) by a filter circuit during a first time period. In various embodiments, the first filter node is coupled to a ground power supply node via a first capacitor. In various embodiments, the value of the first capacitor is programmable.

[0068] The method further includes coupling a second capacitor between the first filter node and the ground power supply node by a filter circuit during a second time period following the first time period (block 704). In various embodiments, the value of the second capacitor is programmable.

[0069] The method also includes coupling the output signal to the first filter node (block 705) via a third capacitor during a second time period. In various embodiments, the value of the third capacitor is programmable.

[0070] The method also includes coupling a fourth capacitor between the first filter node and the ground power supply node by a filter circuit during a third time period following the second time period (box 706).

[0071] The method also includes generating an output signal using the voltage level across the fourth capacitor by a filter circuit (block 707). In various embodiments, generating the output signal includes buffering the voltage level across the fourth capacitor by a buffer circuit included in the filter circuit to generate the output signal.

[0072] In various embodiments, the method may further include coupling a pre-filtered signal to a second filter node by a filter circuit during a first time period, wherein the second filter node is coupled to a ground power supply node via a sixth capacitor. In such cases, the method may further include coupling a second capacitor between the second filter node and the ground power supply node via the filter circuit during the first time period. The method may also include: coupling an output signal to the second filter node via a third capacitor via the filter circuit during the first time period; and coupling a fourth capacitor between the second filter node and the ground power supply node via the filter circuit during a fourth time period after the third time period.

[0073] In some implementations, the method may further include converting the output signal into digital data by an analog-to-digital converter circuit. The method ends in block 708.

[0074] Now for reference Figure 8The diagram illustrates a block diagram of an example embodiment of the device. In some embodiments, the components of device 800 may be included within a system-on-a-chip. In some embodiments, device 800 may be included in a mobile device that may be battery-powered. Therefore, the power consumption of device 800 may be an important design consideration. In the illustrated embodiment, device 800 includes a structure 810, a computing complex 820, an input / output (I / O) bridge 850, a cache / memory controller 845, a graphics unit 875, and a display unit 865. In some embodiments, as a supplement to or alternative to the illustrated components, device 800 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0075] Structure 810 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 800. In some embodiments, portions of structure 810 may be configured to implement various different communication protocols. In other embodiments, structure 810 may implement a single communication protocol, and components coupled to structure 810 may internally switch from a single communication protocol to other communication protocols.

[0076] In the illustrated embodiments, computing complex 820 includes a bus interface unit (BIU) 825, a cache 830, and cores 835 and 840. In various embodiments, computing complex 820 may include a variety of numbers of processors, processor cores, and caches. For example, computing complex 820 may include one, two, four, or any other suitable number of processor cores. In one embodiment, cache 830 is a set-associative L2 cache. In some embodiments, cores 835 and 840 may include internal instruction and data caches. In some embodiments, coherence units (not shown) in architecture 810, cache 830, or elsewhere in device 800 may be configured to maintain coherence between the various caches of device 800. BIU 825 may be configured to manage communication between computing complex 820 of device 800 and other components. Processor cores (such as cores 835 and 840) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions. These instructions can be stored in computer-readable media, such as memory coupled to the cache / memory controller 845 discussed below.

[0077] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling may include intermediate elements. For example, in Figure 8In this context, the graphics unit 875 can be described as being "coupled" to memory via structure 810 and cache / memory controller 845. In contrast, in... Figure 8 In the exemplary implementation, the graphics unit 875 is "directly coupled" to the structure 810 because there are no intermediate elements.

[0078] The cache / memory controller 845 can be configured to manage data transfer between the structure 810 and one or more caches and memories. For example, the cache / memory controller 845 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 845 may be directly coupled to memory. In some embodiments, the cache / memory controller 845 may include one or more internal caches. The memory coupled to the cache / memory controller 845 can be any type of volatile memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), dual data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low-power versions of SDRAM, such as LPDDR4, etc.), RAMBUSDRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be coupled onto a circuit board to form a memory module, such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), etc. Alternatively, these devices can be mounted with integrated circuits in a chip-stacked configuration, a package-stacked configuration, or a multi-chip module configuration. The memory coupled to the cache / memory controller 845 can be any type of non-volatile memory, such as NAND flash memory, NOR flash memory, nanometer RAM (NRAM), magnetoresistive RAM (MRAM), phase-change RAM (PRAM), raceway memory, memristor memory, etc. As noted above, the memory can store program instructions executable by the computing complex 820 to enable the computing device to perform the functionality described herein.

[0079] The graphics unit 875 may include one or more processors, such as one or more graphics processing units (GPUs). For example, the graphics unit 875 may receive graphics-oriented instructions, such as OpenGL. ® Metal ® Or DIRECT3D ®Instructions. The graphics unit 875 can execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 875 is typically configured to process large blocks of data in parallel and can construct an image in a frame buffer for output to a display, which may be included in a device or may be a separate device. The graphics unit 875 may include a transformation engine, a lighting engine, a triangle engine, and a rendering engine in one or more graphics processing pipelines. The graphics unit 875 can output pixel information for displaying the image. In various embodiments, the graphics unit 875 may include programmable shader circuitry, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may or may not be graphics-dependent).

[0080] Display unit 865 may be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 865 may be configured as a display pipeline. Additionally, display unit 865 may be configured to blend multiple frames to produce an output frame. Furthermore, display unit 865 may include one or more interfaces (e.g., MIPI) for coupling to a user display (e.g., a touchscreen or an external display). ® Or embedded display port (eDP)).

[0081] I / O bridge 850 may include various components configured to implement functionalities such as Universal Serial Bus (USB) communication, security, audio, and low-power always-on. I / O bridge 850 may also include interfaces such as pulse-width modulation (PWM), general-purpose input / output (GPIO), serial peripheral interface (SPI), and internal integrated circuit (I2C). Various types of peripheral devices and equipment can be coupled to device 800 via I / O bridge 850.

[0082] In some embodiments, device 800 includes network interface circuitry (not explicitly shown) that can be connected to structure 810 or I / O bridge 850. This network interface circuitry can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuitry can be configured to communicate via a wired local area network (LAN), a wireless LAN (e.g., via Wi-Fi), or a wireless LAN. ™ The network interface circuitry can communicate via one or more cellular networks using one or more radio access technologies, or wide area networks (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuitry is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuitry is configured to use device-to-device communication (e.g., Bluetooth). ® or Wi-Fi ™Communication can be achieved through direct connection, etc. In various implementations, this network interface circuitry can provide device 800 with connectivity to various types of other devices and networks.

[0083] Now go to Figure 9 This illustrates various types of systems that may include any of the circuits, devices, or systems discussed above. Systems or devices 900 that may utilize one or more of the techniques described herein, in combination with or otherwise, can be used in a wide range of fields. For example, system or device 900 may be used as part of the hardware of a system such as a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular or mobile phone 940, or a television 950 (or a set-top box coupled to a television).

[0084] Similarly, the disclosed components can be used in wearable devices 960, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0085] System or device 900 can also be used in a variety of other contexts. For example, system or device 900 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing cloud-based services 970. Furthermore, system or device 900 can be implemented in a wide range of dedicated everyday devices, including common household devices 980 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Components can also be implemented in various modes of transportation. For example, system or device 900 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 990.

[0086] Figure 9 The applications shown are merely illustrative and are not intended to limit the potential future applications of the disclosed systems or devices. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0087] Various example circuits have been described in detail above in this disclosure. It is intended that this disclosure cover not only embodiments including such circuits, but also computer-readable storage media that include design information specifying such circuits. Therefore, this disclosure is intended to support claims that specify storage media for circuits in formats that cover not only means including the disclosed circuits, but also analog models for programming computing systems to generate hardware circuits, manufacturing systems configured to generate hardware (e.g., integrated circuits) including the disclosed circuits. Claims for such storage media are intended to cover entities that, for example, generate circuit designs but do not themselves perform complete operations (such as design simulation, design synthesis, circuit fabrication, etc.).

[0088] Figure 10 A block diagram illustrating an example of a non-transitory computer-readable storage medium storing design information 1015 according to some embodiments is provided. In the illustrated embodiment, a computing system 1040 is configured to process the design information 1015. This may include executing instructions included in the design information 1015, interpreting instructions included in the design information 1015, compiling, transforming, or otherwise updating the design information 1015, etc. Thus, in some embodiments, the design information 1015 (e.g., by programming the computing system 1040) controls the computing system 1040 to perform the various operations discussed below.

[0089] In the illustrated example, computing system 1040 processes design information 1015 to generate both a hardware circuit computer simulation model 1060 and low-level design information 1050. In other embodiments, computing system 1040 may generate only one of these outputs, generate other outputs based on design information 1015, or both. Regarding the hardware circuit computer simulation model 1060, computing system 1040 may execute instructions in a hardware description language, including register-transfer-level (RTL) code, behavioral code, structural code, or some combination thereof. The simulation model may perform the functionality specified by design information 1015, facilitate verification of the functional correctness of the hardware design, generate power consumption estimates, generate timing estimates, etc.

[0090] In the illustrated example, computing system 1040 also processes design information 1015 to generate low-level design information 1050 (e.g., gate-level design information, netlists, etc.). As shown, this may include synthesis operations such as constructing multi-level networks, optimizing the network using technology-independent techniques, technology-dependent techniques, or both, and outputting a gate network (with potential constraints based on a library of available gate pairs, size adjustments, delays, power, etc.). Based on the low-level design information 1050 (potentially and other inputs), semiconductor manufacturing system 1020 is configured to manufacture integrated circuit 1030 (which may correspond to the functionality of a hardware circuit computer simulation model 1060). Note that computing system 1040 may generate different simulation models based on design information at various descriptive levels, including low-level design information 1050, design information 1015, etc. Data representing low-level design information 1050 and hardware circuit computer simulation model 1060 may be stored on non-transitory computer-readable storage medium 1010 or on one or more other media.

[0091] In some implementations, low-level design information 1050 controls (e.g., programs) the semiconductor manufacturing system 1020 to manufacture integrated circuit 1030. Therefore, when processed by the manufacturing system, the design information can program the manufacturing system to manufacture circuits including the various circuits disclosed herein.

[0092] The non-transitory computer-readable storage medium 1010 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1010 may be: mounting media, such as CD-ROM, floppy disk, or magnetic tape devices; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory, magnetic media (e.g., hard disk drive), or optical storage devices; registers or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 1010 may also include other types of non-transitory memory or combinations thereof. Therefore, the non-transitory computer-readable storage medium 1010 may include two or more memory media that may reside in different locations (e.g., different computer systems connected via a network).

[0093] Design information 1015 may be specified using any computer language (including hardware description languages) of various suitable computer languages, such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The formats of various design information can be recognized by one or more applications executed by computing system 1040, semiconductor manufacturing system 1020, or both. In some embodiments, design information 1015 may also include one or more cell libraries specifying the synthesis, layout, or both of integrated circuit 1030. In some embodiments, design information 1015 is specified wholly or partially in the form of a netlist specifying cell library elements and their connectivity. Individually, the design information discussed herein may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information may specify circuit elements to be manufactured but not their physical layout. In this case, design information may be combined with layout information to actually manufacture the specified circuit.

[0094] In various implementations, integrated circuit 1030 may include one or more custom macrocells, such as memory and analog or mixed-signal circuitry. In such cases, design information 1015 may include information associated with the included macrocells. This information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. Mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0095] The semiconductor manufacturing system 1020 may include any of the various suitable elements configured to manufacture integrated circuits. This may include elements for, for example, depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 1020 may also be configured to perform various tests on the manufactured circuits to ensure proper operation.

[0096] In various embodiments, integrated circuit 1030 and hardware circuit computer simulation model 1060 are configured to operate according to a circuit design specified by design information 1015, which may include performing any of the functionalities described herein. For example, integrated circuit 1030 may include Figures 1 to 6 Any of the various components shown. Additionally, integrated circuit 1030 can be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0097] As used herein, a phrase in the form of “design information specifying a circuit configured to…” does not imply that the circuit in question must be manufactured to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components. Similarly, stating that “instructions of a hardware description programming language” are “executable” for programming a computing system to generate a computer simulation model does not mean that the instructions must be executed to satisfy the element, but rather specifies the characteristics of those instructions. In this case, additional features associated with the model (or the circuit represented by the model) may similarly relate to the characteristics of these instructions. Therefore, an entity selling a computer-readable medium having instructions that satisfy the stated characteristics may provide an infringing product even if another entity actually executes those instructions on the medium.

[0098] It is important to note that a given design, at least within a digital logic context, can be implemented using multiple different gate arrangements, circuit techniques, etc. As an example, different designs may choose or connect gates based on design trade-offs (e.g., focusing on power consumption, performance, circuit area, etc.). Furthermore, different manufacturers may have proprietary libraries, gate designs, physical gate implementations, etc. Different entities may also use different tools to process design information at various layers (e.g., from behavioral specifications to the physical layout of gates).

[0099] However, once a digital logic design is specified, those skilled in the art do not need to perform extensive experiments or studies to determine these specific implementations. Instead, they understand the process for reliably and predictably producing one or more circuit implementations that provide the functionality described by design information 1015. Different circuit implementations may affect the performance, area, power consumption, etc., of a given design (potentially trade-offs between different design goals), but the logic function remains unchanged between different circuit implementations of the same circuit design.

[0100] In some implementations, instructions included in design information 1015 provide RTL information (or other higher-level design information) and can be executed by a computing system to synthesize a gate-level netlist representing the hardware circuitry based on the RTL information as input. Similarly, these instructions provide behavioral information and can be executed by the computing system to synthesize a netlist or other lower-level design information included in low-level design information 1050. Low-level design information 1050 can program semiconductor manufacturing system 1020 to manufacture integrated circuit 1030.

[0101] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0102] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. The permissive description of such advantages (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0103] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive unless stated otherwise in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art who are aware of the benefits of this disclosure.

[0104] For example, the features in the present application may be combined in any suitable manner. Therefore, new claims may be directed to any such combinations of features during the prosecution of the present application (or an application claiming priority thereto). In particular, with reference to the appended claims, features of the dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0105] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent on a single other claim, additional dependencies are also contemplated. Any combination of the features of the dependent claims consistent with the present disclosure is contemplated, and combinations of these features may be claimed in the present patent application or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0106] Where appropriate, it is also contemplated that a claim drafted in one format or statutory type (e.g., means-plus-function) is intended to support a corresponding claim in another format or statutory type (e.g., method).

[0107] As the present disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout the present disclosure will be used to determine how to interpret claims drafted based on the present disclosure.

[0108] Unless the context clearly dictates otherwise, references to an element in the singular (i.e., a noun or noun phrase preceded by "a", "an" or "the") are intended to mean "one or more". Thus, a reference to "an element" in a claim, without accompanying context, does not exclude additional instances of that element. A "plurality" of elements refers to a set of two or more of the elements.

[0109] The word "may" is used herein in a permissive sense (i.e., having the potential of, being capable of) rather than a mandatory sense (i.e., must).

[0110] The terms "comprise" and "include", as well as their variants, are open-ended and mean "including but not limited to".

[0111] When the term "or" is used with respect to a list of options in the present disclosure, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, the recitation "x or y" is equivalent to "x or y, or both", and accordingly covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in the exclusive sense.

[0112] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0113] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0114] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors plus other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0115] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementations where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0116] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as being “configured” to perform a task refers to a tangible thing, such as a device, circuit, or system having processor units and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0117] In some cases, various units / circuits / components may be described herein as a collection of entities that perform tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated otherwise.

[0118] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0119] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that a structure is “configured” to perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the “component for [performing a function]” structure to state the elements of the claims.

[0120] Different “circuits” may be described in this disclosure. These circuits, or “circuits,” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits.

[0121] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular "decoding unit" can be described as having the function of executing "the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units," meaning that the decoding unit is "configured" to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0122] In various implementations, as discussed in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of such circuits / cells / components relative to each other and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art with the microarchitecture definition provided according to this disclosure can implement the structure without excessive experimentation and by applying common techniques, by decoding the description of the circuits / cells / components in a hardware description language (HDL) (such as Verilog or VHDL). The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, this HDL description is a way of transforming the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0123] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0124] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the sheer volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An apparatus, the apparatus comprising: A pre-filter circuit, configured to filter an input signal to generate a pre-filtered signal; A switched capacitor filter circuit, wherein the switched capacitor filter circuit is configured as follows: During a first time period, the pre-filtered signal is coupled to a first filter node, wherein the first filter node is coupled to a ground power supply node via a first capacitor; During a second time period following the first time period, the second capacitor is coupled between the first filter node and the ground power node. During the second time period, the output signal is coupled to the first filter node via a third capacitor; as well as During a third time period following the second time period, a fourth capacitor is coupled between the first filter node and the ground power node. as well as A buffer circuit is configured to generate the output signal using the voltage level across the fourth capacitor.

2. The apparatus of claim 1, wherein the pre-filter circuit comprises: An amplifier circuit configured to amplify a combination of the input signal and the feedback signal to generate the pre-filtered signal; as well as An impedance network coupled between the input and output of the amplifier circuit, wherein the impedance network is configured to use the pre-filtered signal to generate the feedback signal.

3. The apparatus of claim 2, wherein the impedance network comprises at least a first resistor and a fifth capacitor.

4. The apparatus of claim 1, wherein the switched capacitor filter circuit is further configured to: During the first time period, the pre-filtered signal is coupled to a second filter node, wherein the second filter node is coupled to the ground power node via a sixth capacitor; During the first time period, the second capacitor is coupled between the second filter node and the ground power node; During the first time period, the output signal is coupled to the second filter node via the third capacitor; as well as During a fourth time period following the third time period, the fourth capacitor is coupled between the second filter node and the ground power node.

5. The apparatus of claim 1, wherein the value of the first capacitor is programmable.

6. The apparatus of claim 1, wherein the value of the third capacitor is programmable.

7. A method, the method comprising: The input signal is pre-filtered by a filter circuit to generate a pre-filtered signal. The filter circuit couples the pre-filtered signal to a first filter node during a first time period, wherein the first filter node is coupled to a ground power node via a first capacitor. The filter circuit couples the second capacitor between the first filter node and the ground power node during a second time period following the first time period. During the second time period, the filter circuit couples the output signal to the first filter node via the third capacitor. The filter circuit couples a fourth capacitor between the first filter node and the ground power node during a third time period following the second time period. as well as The output signal is generated by using the voltage level across the fourth capacitor through the filter circuit.

8. The method of claim 7, wherein pre-filtering the input signal comprises: The feedback signal is generated using an impedance network coupled between the output and input of the amplifier circuit. as well as The feedback signal is combined with the input signal at the input terminal of the amplifier circuit.

9. The method of claim 8, wherein the impedance network comprises at least a first resistor and a fifth capacitor.

10. The method of claim 7, wherein pre-filtering the input signal comprises amplifying the input signal.

11. The method according to claim 7, further comprising: During the first time period, the pre-filtered signal is coupled to the second filter node via the filter circuit, wherein the second filter node is coupled to the ground power node via the sixth capacitor. During the first time period, the filter circuit couples the second capacitor between the second filter node and the ground power node. During the first time period, the filter circuit couples the output signal to the second filter node via the third capacitor. as well as The filter circuit couples the fourth capacitor between the second filter node and the ground power node during a fourth time period following the third time period.

12. The method of claim 7, wherein the value of the first capacitor is programmable.

13. The method of claim 7, further comprising converting the output signal into digital data by an analog-to-digital converter circuit.

14. A system comprising: A filter circuit configured to generate a filtered signal using an input signal; An analog-to-digital converter circuit, the analog-to-digital converter circuit being configured to use the filtered signal to generate digital data; as well as Logic circuits configured to use the digital data to generate output data; and In order to generate the filtered signal, the filter circuit is further configured as follows: The input signal is pre-filtered to generate a pre-filtered signal; During a first time period, the pre-filtered signal is coupled to a first filter node, wherein the first filter node is coupled to a ground power supply node via a first capacitor; During a second time period following the first time period, a second capacitor is coupled between the first filter node and the ground power node; During the second time period, the filtered signal is coupled to the first filter node via a third capacitor; During a third time period following the second time period, a fourth capacitor is coupled between the first filter node and the ground power node. as well as The filtered signal is generated using the voltage level across the fourth capacitor.

15. The system of claim 14, wherein, in order to pre-filter the input signal, the filter circuit is further configured to amplify a combination of the input signal and the feedback signal to generate the pre-filtered signal.

16. The system of claim 15, wherein the filter circuit is further configured to generate the feedback signal using an impedance network coupled between the pre-filtered signal and the input signal.

17. The system of claim 16, wherein the impedance network comprises at least a first resistor and a fifth capacitor.

18. The system of claim 14, wherein the filter circuit is further configured to: During the first time period, the pre-filtered signal is coupled to a second filter node, wherein the second filter node is coupled to the ground power node via a sixth capacitor; During the first time period, the second capacitor is coupled between the second filter node and the ground power node; During the first time period, the filtered signal is coupled to the second filter node via the third capacitor; as well as During a fourth time period following the third time period, the fourth capacitor is coupled between the second filter node and the ground power node.

19. The system of claim 14, wherein the value of the first capacitor is programmable.

20. The system of claim 14, wherein the value of the third capacitor is programmable.

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