A TX circuit output impedance matching circuit

Abstract

The application discloses a kind of for TX circuit output impedance matching circuit, belongs to integrated circuit design technical field.The circuit includes off-chip precision resistance, TX circuit and global impedance calibration circuit;TX circuit includes analog impedance loop and drive unit circuit, and with global impedance calibration circuit etching on same wafer.The resistance deviation of global impedance calibration circuit is measured with off-chip precision resistance and on-chip programmable resistance array by comparison circuit, and finite state machine is with the feedback of comparison circuit output, and on-chip programmable resistance array is closed-loop regulated to preset error range by impedance adjustment code, and according to impedance adjustment code generation coarse adjustment code and fine adjustment code.Coarse adjustment code is output to drive unit circuit and carries out coarse calibration, realizes wide-range impedance initial adjustment;Fine adjustment code is output to analog impedance loop and carries out fine calibration, realizes high-precision continuous locking.The application cooperates by coarse, fine calibration, and both wide adjustment range and high adjustment precision are considered, signal reflection is effectively reduced, and transmission signal integrity is improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to an output impedance matching circuit for TX circuits. Background Technology

[0002] In high-speed serial interfaces (such as SerDes, DDR, PCIe, etc.), whether the output impedance of the TX (transmitter) circuit matches the characteristic impedance of the transmission line during data transmission directly determines the magnitude of signal reflection loss in the channel, affecting the signal quality at the receiving end. Better impedance matching results in higher signal integrity and a lower bit error rate. SST (Source-Level Series Termination) drivers, as a voltage-mode drive structure, offer advantages over CML (Current-Mode) drivers, including lower power consumption, simpler circuit structure, and more flexible and adjustable output swing, and are widely used in the TX circuit design of high-speed interfaces. However, the output impedance of the SST driver depends entirely on the on-chip resistors and the on-resistance of the transistors. Both are extremely sensitive to PVT (process, voltage, temperature) variations under advanced processes such as FinFET. Deviations in on-chip resistors can reach 16%, and deviations in the equivalent resistance of transistors can reach 20%, resulting in a cumulative output impedance deviation of up to 36%, far exceeding the tolerance range allowed by the communication protocol. Therefore, an impedance calibration mechanism must be introduced to ensure the transmission performance of the TX circuit.

[0003] There are two main approaches to impedance calibration for existing SST drivers. The first is a digital coarse calibration scheme based on the number of drive units: multiple SST drive units with identical output impedance are connected in parallel, and the total output impedance of the drive stage is changed by controlling the number of parallel units via an enable signal. This scheme has the advantage of a large adjustment range and simple structure, but it is limited by the number of units—a large number of parallel units are needed to cover a 36% impedance deviation, and the impedance step size provided by each unit is limited (e.g., when 50 5000Ω units are connected in parallel, the single-step adjustment is only about 2Ω), making it difficult to meet the requirements of high-speed interfaces in terms of adjustment accuracy. At the same time, a large number of parallel units increases the parasitic capacitance of the output stage, reducing the driving capability of high-frequency signals. The second approach is a continuous fine calibration scheme based on an analog impedance loop: the structure of the main drive circuit is replicated on-chip, and a transistor controlled by operational amplifier feedback is set as a programmable resistor in the replicated branch. The voltage across the replicated load is clamped by a negative feedback loop, and the gate bias voltage of the programmable resistor is continuously adjusted to achieve precise calibration of the output impedance. This scheme offers high adjustment accuracy, but the programmable resistor needs to be biased in the deep linear region to achieve continuous adjustment. Its effective adjustment range is relatively narrow, and when the PVT fluctuates significantly, it may exceed the loop adjustment capability and fail to lock. In addition, the equivalent resistance of the transistor in the deep linear region differs significantly under DC and AC conditions, which may lead to impedance mismatch during high-frequency signal transmission. Summary of the Invention

[0004] The technical problem to be solved by the present invention is that the existing SST driver impedance calibration scheme has the following drawbacks: the digital coarse calibration method based on parallel drive units has a large adjustment step size, limited accuracy, and requires a large number of parallel units, which leads to increased power consumption and parasitic capacitance; the continuous fine calibration method based on analog impedance loop has a narrow adjustment range, may not be able to lock under large PVT fluctuations, and has a large impedance deviation at high frequencies.

[0005] To address the aforementioned technical problems, this invention provides an output impedance matching circuit for a TX circuit, comprising: an off-chip precision resistor, a TX circuit, and a global impedance calibration circuit; the TX circuit includes an analog impedance loop and a driving unit circuit.

[0006] The TX circuit and the global impedance calibration circuit are etched on the same wafer.

[0007] The global impedance calibration circuit includes an on-chip programmable resistor array, a comparator circuit, and a finite state machine; the comparator circuit is used to measure the resistance deviation between an off-chip precision resistor and the on-chip programmable resistor array.

[0008] The finite state machine uses the output signal of the comparator circuit as feedback to adjust the on-chip programmable resistor array through impedance adjustment code, so that the resistance value deviation between the on-chip programmable resistor array and the off-chip precision resistor is within a preset error range.

[0009] The finite state machine generates corresponding coarse and fine adjustment codes based on the impedance adjustment code. The coarse adjustment code is output to the driving unit circuit to control it to perform coarse calibration, and the fine adjustment code is output to the analog impedance loop to control it to perform fine calibration, thus completing the output impedance matching of the TX circuit.

[0010] The present invention has at least the following beneficial effects

[0011] This invention combines coarse calibration based on parallel drive units with fine calibration based on analog impedance loops to form a layered hybrid impedance matching architecture. On the one hand, controlling the number of parallel drive units enables a wide range of initial impedance adjustment, effectively covering a wide range of impedance deviations caused by PVT variations, avoiding the problem of insufficient adjustment range leading to locking failure or high-frequency mismatch in pure analog schemes. On the other hand, a global impedance calibration circuit monitors on-chip resistance deviations in real time, generating fine adjustment codes to perform high-precision continuous adjustment of the analog impedance loop, overcoming the shortcomings of relying solely on parallel units, such as large adjustment steps, limited accuracy, and increased power consumption and parasitics due to the large number of units required. The coarse and fine calibrations work together to ensure impedance matching capability over a wide dynamic range while achieving high-precision fine locking. This allows the TX circuit to maintain a stable and accurate output impedance under different process corners, power supply voltages, and operating temperatures, effectively reducing signal reflection and improving the integrity of transmitted signals. At the same time, it avoids excessively increasing the number of parallel units to improve accuracy and the resulting power consumption and parasitic problems, achieving a balance between calibration range and accuracy. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the overall circuit structure of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Please see Figure 1 The present invention provides an output impedance matching circuit for a TX circuit, comprising: an off-chip precision resistor, a TX circuit, and a global impedance calibration circuit; the TX circuit includes an analog impedance loop and a drive unit circuit;

[0015] The TX circuit and the global impedance calibration circuit are etched on the same wafer.

[0016] The global impedance calibration circuit includes an on-chip programmable resistor array, a comparator circuit, and a finite state machine; the comparator circuit is used to measure the resistance deviation between an off-chip precision resistor and the on-chip programmable resistor array.

[0017] The finite state machine uses the output signal of the comparator circuit as feedback to adjust the on-chip programmable resistor array through impedance adjustment code, so that the resistance value deviation between the on-chip programmable resistor array and the off-chip precision resistor is within a preset error range.

[0018] The finite state machine generates corresponding coarse and fine adjustment codes based on the impedance adjustment code. The coarse adjustment code is output to the driving unit circuit to control it to perform coarse calibration, and the fine adjustment code is output to the analog impedance loop to control it to perform fine calibration, thus completing the output impedance matching of the TX circuit.

[0019] In this embodiment, the global impedance calibration circuit is used to monitor the resistance deviation of on-chip resistors caused by PVT in real time. Specifically, the global impedance calibration circuit includes an on-chip programmable resistor array, a comparator circuit, and a finite state machine. The comparator circuit measures the resistance deviation between the off-chip precision resistor and the on-chip programmable resistor array, and outputs the comparison result to the finite state machine in the form of a digital signal. The off-chip precision resistor is a high-precision resistor (e.g., 100Ω), whose resistance value is not affected by PVT changes, and serves as the reference for global impedance calibration.

[0020] The finite state machine uses the output signal of the comparator circuit as feedback to adjust the resistance value of the on-chip programmable resistor array through impedance adjustment codes, so that the resistance value deviation between the on-chip programmable resistor array and the external precision resistor converges to a preset error range (e.g., within ±1%). When the resistance value of the on-chip programmable resistor array is calibrated to be basically consistent with the external precision resistor (within the preset error range), the finite state machine locks the current impedance adjustment code.

[0021] The finite state machine generates corresponding coarse and fine adjustment codes based on the locked impedance adjustment code. The coarse adjustment code includes the enable control code EN. <n:0>The output is sent to the drive unit circuit; the drive unit circuit consists of N drive units connected in parallel, with enable control code EN. <n:0>Each bit controls the enable terminal of the corresponding drive unit, determining whether the drive unit is connected to the circuit. This changes the total output impedance of the drive stage by altering the number of drive units connected in parallel, achieving a wide range of coarse calibration. Fine adjustment codes include pull-up and pull-down codes, output to the analog impedance loop. This loop consists of M parallel-connected replication drive units with a replication ratio of M:N. The loop follows the same signal conduction path as the drive units. Through negative feedback, it continuously adjusts the gate bias voltage (i.e., control signals Vctrlp and Vctrln) of the programmable transistors in the replication branch, performing high-precision continuous fine calibration of the output impedance. This also compensates for changes in the replication ratio caused by coarse adjustment, eliminating the need for adjustments to the replication load.

[0022] The specific process of the coarse and fine calibration described above is as follows: After the global impedance calibration circuit is powered on, it runs continuously. The finite state machine adjusts the on-chip programmable resistor array in a closed loop according to the comparison result. When the deviation converges to the preset error range, the impedance adjustment code is locked. The FSM calculates the offset of the on-chip resistor relative to the ideal value based on the locked impedance adjustment code, and generates the coarse and fine adjustment codes accordingly. First, coarse calibration is performed: the enable control code EN is adjusted according to the offset. <n:0>The number of parallel-connected drive units is changed to adjust the output impedance to near the target value (e.g., covering ±10% deviation). Fine calibration is then performed: the actual resistance of the replicated load is recalculated based on the offset and replication ratio, and the pull-up and pull-down adjustment codes are adjusted accordingly. The clamping reference voltage at the non-inverting input of the error amplifier in the analog impedance loop is changed. Through a negative feedback loop, the control signals Vctrlp and Vctrln are converged to the target value. These control signals adjust the resistance values ​​of the programmable resistors composed of field-effect transistors (FETs) Mcp and Mcn in each drive unit, ensuring that the pull-up and pull-down branch impedances of the final parallel-connected drive circuit converge precisely to the target value (e.g., 50Ω), thus achieving precise matching between the TX circuit output impedance and the transmission line characteristic impedance.

[0023] Therefore, this invention achieves wide-range impedance initial adjustment through coarse calibration and high-precision continuous locking through fine calibration. The two work together to enable the TX circuit to maintain stable and accurate output impedance matching under different process angles, power supply voltages and operating temperatures, effectively reducing signal reflection and improving the integrity of transmitted signals.

[0024] Preferably, the comparator circuit includes NMOS transistors MN01 and MN02, an error amplifier Amp, and a dynamic comparator; one end of the off-chip precision resistor and one end of the on-chip programmable resistor array are connected to the power supply terminal Vdd; the other end of the off-chip precision resistor, the drain of MN01, and the inverting input terminal of the error amplifier Amp are connected; the gates of MN01 and MN02 are connected to a bias voltage; the sources of MN01 and MN02 are grounded; the other end of the on-chip programmable resistor array, the drain of MN02, and the non-inverting input terminal of the error amplifier Amp are connected; the output terminal of the error amplifier Amp is connected to the first input terminal of the dynamic comparator; the second input terminal of the dynamic comparator is connected to a reference voltage Vref; the output terminal of the dynamic comparator is connected to a finite state machine; the impedance adjustment code output by the finite state machine acts on the on-chip programmable resistor array.

[0025] In this embodiment, the comparator circuit operates as follows: an external precision resistor (e.g., 100Ω) and an on-chip programmable resistor array are located in the upper half of two parallel branches. MN01 and MN02 are common-gate biased, forming a current mirror structure to provide equal bias current to the two branches. Since the resistance value of the external precision resistor is unaffected by PVT changes, while the resistance value of the on-chip programmable resistor array shifts with PVT changes, the voltage drops across the corresponding resistors are different, causing a deviation between the drain voltage of MN01 (i.e., the voltage at the inverting input of the error amplifier Amp) and the drain voltage of MN02 (i.e., the voltage at the non-inverting input of the error amplifier Amp). This deviation reflects the direction and extent of the resistance value shift of the on-chip programmable resistor array relative to the external precision resistor. The error amplifier Amp amplifies this voltage difference and outputs it to the first input of a dynamic comparator; the second input of the dynamic comparator is connected to a reference voltage Vref. The dynamic comparator compares the analog voltage output by the error amplifier Amp with the reference voltage Vref and converts it into a digital level signal, which is then output to the finite state machine. When the resistance of the on-chip programmable resistor array is too high, the voltage drop across it is also too high. The voltage at the non-inverting input of the error amplifier Amp is lower than that at the inverting input, causing the operational amplifier to output a single-polarity analog voltage. The dynamic comparator then outputs a first logic level (e.g., high) to the finite state machine, indicating "resistance too high." Conversely, when the resistance of the on-chip programmable resistor array is too low, the voltage drop across it is too low, causing the voltage at the non-inverting input of the error amplifier Amp is higher than that at the inverting input. The amplifier Amp outputs an analog voltage of opposite polarity, and the dynamic comparator then outputs a second logic level (e.g., low) to the finite state machine, indicating "resistance too low." The dynamic comparator, in conjunction with the reference voltage Vref, quantifies the comparison result into two states: "on-chip resistance too high" or "on-chip resistance too low." Its output is a single digital flag signal, not a continuously changing value, allowing the finite state machine to quickly and clearly determine the current deviation direction.

[0026] Furthermore, the dynamic comparator and the finite state machine are driven by the same clock signal CLK. The dynamic comparator samples and compares the output of the error amplifier Amp in each clock cycle and outputs the comparison result to the finite state machine. The finite state machine synchronously acquires the comparison result at the same clock edge and updates the impedance adjustment code according to its state. The finite state machine is based on a closed-loop feedback adjustment architecture, using the output signal of the comparator circuit as feedback to adjust the impedance adjustment code cycle by cycle, so that the resistance value of the on-chip programmable resistor array gradually approaches the resistance value of the off-chip precision resistor. For example, when the comparator outputs a logic level indicating "resistance too high," the finite state machine increases the impedance adjustment code to decrease the resistance value of the on-chip programmable resistor array; conversely, when the comparator outputs a logic level indicating "resistance too low," the finite state machine decreases the impedance adjustment code to increase the resistance value of the on-chip programmable resistor array. After repeated adjustments over several clock cycles, the resistance value of the on-chip programmable resistor array converges to within a preset error range (e.g., within ±1%) of the resistance value of the off-chip precision resistor. At this point, the finite state machine locks the current impedance adjustment code, completing global impedance calibration.

[0027] Preferably, the analog impedance loop includes: 2N+1 on-chip resistors R connected in series between the power supply terminal Vdd and the ground terminal GND, error amplifiers Amp1 and Amp2, and on-chip resistors... On-chip resistors On-chip resistors PMOS transistors MP1 and MP2, and NMOS transistors MN1 and MN2; the fine adjustment code includes a pull-up adjustment code (UP code). <n:0>and dropdown adjustment code DN code <n:0>From the power supply terminal Vdd towards the ground terminal GND, a digitally controlled switch S1 is connected in parallel between the end of each of the 1st to Nth on-chip resistors R and the non-inverting input terminal of the error amplifier Amp1. The N digitally controlled switches S1 are adjusted by pull-up codes UP. <n:0>Control is off. A digitally controlled switch S2 is connected in parallel between the end of each of the (N+1)th to (2Nth)th on-chip resistors R and the non-inverting input of the error amplifier Amp2. The N digitally controlled switches S2 are adjusted by the pull-down code DN. <n:0>Control shutdown; the source of MP1 is connected to the power supply terminal Vdd; the drain of MP1 and the source of MP2 are connected; the drain of MP2 is connected to an on-chip resistor. One end; on-chip resistor The other end is connected to the inverting input of the error amplifier Amp1 and the on-chip resistor. One end; MP2's gate ground (GND); on-chip resistor The other end is connected to the inverting input of the error amplifier Amp2 and the on-chip resistor. One end; on-chip resistor The other end is connected to the drain of MN1; the source of MN1 is connected to the drain of MN2; the gate of MN1 is connected to the power supply terminal Vdd; the source of MN2 is grounded to GND; the gate of MP1 is connected to the output terminal of error amplifier Amp1 and the output terminal of control signal Vctrlp; the gate of MN2 is connected to the output terminal of error amplifier Amp2 and the output terminal of control signal Vctrln; control signals Vctrlp and Vctrln are used to control the drive unit circuit.

[0028] In this embodiment, the simulated impedance loop is used to perform fine calibration of the TX circuit output impedance based on the completed coarse calibration. MP1, MP2, , , MP2, MN1, and MN2 form a replica path, which replicates the signal path that the drive unit is conducting at a certain moment. MP2 and MN1 are common source and common gate devices (gate connected to GND and Vdd respectively), which play a role in level shifting and protection, so that the impedance characteristics of the replica path are consistent with those of the main drive unit.

[0029] During circuit operation, error amplifiers Amp1 and Amp2 each form two independent negative feedback loops. The non-inverting input of error amplifier Amp1 receives the UP code... <n:0>The selected voltage node (i.e., the pull-up reference voltage) is connected to the inverting input terminal. and The public node (denoted as) The output terminal is connected to the gate of MP1. When When the voltage deviates from the pull-up reference voltage, Amp1 adjusts its output voltage Vctrlp; changing the gate bias of MP1, thereby adjusting the on-resistance of MP1, and changing the flow through MP1→MP2→ The current in the branch eventually makes The voltage is clamped to be equal to the pull-up reference voltage. The non-inverting input of the error amplifier Amp2 receives the DN code. <n:0>The selected voltage node (i.e., the pull-down reference voltage) is connected to the inverting input. and The public node (denoted as) The output terminal is connected to the gate of MN2. When When the voltage deviates from the pull-down reference voltage, Amp2 adjusts its output voltage Vctrln; it changes the gate bias of MN2, thereby adjusting the on-resistance of MN2 and changing the current flowing through it. The current in the →MN1→MN2 branch ultimately makes The voltage is clamped to be equal to the pull-down reference voltage. The numerically controlled switch S1 closes when the corresponding control code bit is at an active level, while the other switches open to select the corresponding resistor divider node.

[0030] Through the combined effect of the two negative feedback loops mentioned above, the replicated load... The voltages at both ends are precisely set, and the impedances of the pull-up and pull-down paths converge to the target values ​​accordingly. At this time, the control signal Vctrlp output by error amplifier Amp1 and the control signal Vctrln output by error amplifier Amp2 reflect the precise bias states of the pull-up and pull-down branches, respectively. These two control signals are sent to the gates of the programmable transistors (Mcp and Mcn) of each drive unit in the drive unit circuit, so that the impedances of the pull-up and pull-down branches of the main drive unit accurately replicate the impedance states of the replicated link in the analog impedance loop, thereby achieving high-precision fine calibration of the output impedance of the TX circuit.

[0031] Through the above-mentioned analog impedance loop structure, based on the parallel coarse calibration of the drive unit which has already adjusted the output impedance to near the target value, high-precision continuous adjustment of the output impedance is further realized, so that the final output impedance of the TX circuit accurately matches the characteristic impedance of the transmission line (e.g., 100Ω), effectively reducing signal reflection and improving the integrity of the transmitted signal.

[0032] Preferably, the driving unit circuit includes N driving units, and the coarse adjustment code includes an enable control code EN. <n:0>The enable control code EN <n:0>Used to control whether the enable signal is connected to the drive unit.

[0033] Preferably, each driving unit includes: a first pre-driving unit, a second pre-driving unit, on-chip resistors Rs1~Rs4, PMOS transistors Mcp, Mpp and Mnp, and NMOS transistors Mcn, Mpn and Mnn;

[0034] The input terminal of the first pre-drive unit is connected to the input data signal Dinn; the enable terminals of the first and second pre-drive units are connected and controlled by the enable control code EN. <n:0>The control determines whether an enable signal is connected; the first output terminal of the first pre-drive unit is connected to the gate of Mnp; the second output terminal of the first pre-drive unit is connected to the gate of Mnn; the drain of Mnp is connected to one end of the on-chip resistor Rs1; the drain of Mnn is connected to one end of the on-chip resistor Rs2; the other ends of the on-chip resistors Rs1 and Rs2 are connected to the input terminal of the second signal transmission line; the source of Mnp and the drain of Mcp are connected to the source of Mpp; the source of Mcp is connected to the power supply terminal Vdd; the gate of Mcp is connected to the control signal Vctrlp; M The source of nn and the source of Mpn are connected to the drain of Mcn; the source of Mcn is connected to ground GND; the gate of Mcn is connected to the control signal Vctrln; the input terminal of the second pre-drive unit is connected to the input data signal Dinp; the first output terminal of the second pre-drive unit is connected to the gate of Mpp; the second output terminal of the second pre-drive unit is connected to the gate of Mpn; the drain of Mpp is connected to one end of the on-chip resistor Rs3; the drain of Mpn is connected to one end of the on-chip resistor Rs4; the other ends of the on-chip resistor Rs3 and the other ends of the on-chip resistor Rs4 are connected to the input terminal of the first signal transmission line.

[0035] In this embodiment, the driving unit circuit is used to achieve a wide-range coarse calibration of the TX circuit output impedance under the control of the coarse adjustment code. The driving unit circuit includes N driving units, each of which is an SST (source-level series termination) driving unit with the same structure. The N driving units are connected in parallel, and their output terminals are all connected to the signal transmission line of the TX circuit. Enable control code EN <n:0>This is an N-bit digital control code, with each bit corresponding to a drive unit. When a bit is active, the corresponding drive unit is enabled and connected to the output path; when a bit is inactive, the corresponding drive unit is disabled and disconnected from the output path (the output is in a high-impedance state). By changing EN... <n:0>The number of effective bits can be adjusted to change the total number of drive units connected in parallel, thereby changing the total output impedance of the drive stage and achieving coarse calibration over a wide range.

[0036] In each driver unit, Mpp and Mnp form a pull-up differential switch pair, and Mpn and Mnn form a pull-down differential switch pair, controlled by the input data signals Dinp and Dinn, respectively. When TX sends a high level, the second pre-drive unit converts Dinp to an active level to turn on Mpp, and the first pre-drive unit converts Dinn to an inactive level to turn off Mnp. At the same time, the pull-down branch is turned off accordingly, and the output is pulled up to Vdd through the Mpp→Rs3 path. When TX sends a low level, Mnp turns on and Mpp turns off, the pull-down branch is switched accordingly, and the output is pulled down to GND through the Rs4→Mpn path. Rs1~Rs4 are source-level series terminating resistors, which work in conjunction with the characteristic impedance of the transmission line to achieve impedance matching.

[0037] After the above N drive units are connected in parallel, the output terminals of each drive unit (the first signal transmission line and the second signal transmission line) are connected together to form a differential output pair. During the coarse calibration process, the finite state machine calculates the offset of the on-chip resistor relative to the ideal value based on the impedance adjustment code locked by the global impedance calibration circuit, and adjusts the enable control code EN accordingly. <n:0>When the on-chip resistance is too high, increase EN. <n:0>Increasing the number of significant bits and the number of parallel-connected driver units reduces the total output impedance; when the on-chip resistance is too small, decreasing EN... <n:0>The number of significant bits in the output reduces the number of parallel-connected drive units, thus increasing the total output impedance. Therefore, the enable control code EN... <n:0>By adjusting the number of parallel drive units, a wide range of coarse calibration of the output impedance is achieved. After coarse calibration, the control signals Vctrlp and Vctrln output by the analog impedance loop adjust the on-resistance of Mcp and Mcn in each drive unit, respectively, to finely adjust the pull-up and pull-down branch impedances of each drive unit, ultimately making the overall output impedance of the N parallel drive units precisely match the characteristic impedance of the transmission line.

[0038] Therefore, N drive units are enabled by the control code EN. <n:0>Under the control of the system, the selection of the number of parallel circuits and coarse calibration are achieved. Under the control of the control signals Vctrlp and Vctrln, fine calibration of the pull-up / pull-down branch impedance within each unit is achieved. The two work together to complete the full-range, high-precision matching of the output impedance of the TX circuit.

[0039] To enable those skilled in the art to more clearly understand the working process of this circuit, this embodiment provides the following specific examples:

[0040] Assume the goal of this circuit is to match the output impedance of the TX driver circuit to a precise 100Ω off-chip resistor and a transmission line characteristic impedance of 100Ω. Ideally, the driver unit circuit consists of 40 driver units connected in parallel. Each driver unit has an output impedance of 4000Ω under ideal process conditions. Therefore, the total output impedance of 40 units connected in parallel is 4000 / 40 = 100Ω, which, after voltage division by the on-chip series terminating resistors, is equivalent to 100Ω. The replication branch consists of two driver units connected in parallel, with a replication ratio of 2:40. Ideally, the replication load is 100*40 / 2 = 2000Ω, and the pull-up / pull-down resistors for the replication branch are 1000Ω. The following explanation uses a 10% increase in on-chip resistance due to process variations as an example to illustrate the circuit's operation in stages.

[0041] Phase 1: Global Impedance Calibration – Obtaining Deviation Information

[0042] After power-on, the global impedance calibration circuit is activated; the external precision resistor is 100Ω (unaffected by PVT), and the initial value of the on-chip programmable resistor array is 100Ω; due to process variations, the actual resistance of the on-chip programmable resistor array increases by 10%, becoming 110Ω; MN01 and MN02 form a current mirror, with equal bias currents in both paths (assumed to be 1mA). The voltage drop of the external resistor branch is 1mA × 100Ω = 100mV; the voltage drop of the on-chip resistor branch is 1mA × 110Ω = 110mV. The voltage difference (10mV) between the two paths is amplified by the error amplifier Amp and then fed into the dynamic comparator. The dynamic comparator compares the amplified voltage with the reference voltage Vref and outputs a digital flag signal to the finite state machine (FSM). The FSM samples the comparison result each clock cycle. If the comparator output indicates "resistance too high," the FSM increases the impedance adjustment code and decreases the resistance of the on-chip programmable resistor array. If the output indicates "resistance too low," the FSM decreases the impedance adjustment code and increases the resistance of the on-chip programmable resistor array. After several clock cycles of repeated closed-loop adjustment, the on-chip programmable resistor array is adjusted to 100Ω (consistent with the external precision resistor, within the preset ±1% error range), and the FSM locks the current impedance adjustment code. At this point, based on the comparison between the locked impedance adjustment code and the ideal code, the FSM calculates that the on-chip resistance has increased by 10% relative to the ideal value, i.e., the PVT deviation Δ = +10%. This deviation will guide subsequent coarse and fine calibrations.

[0043] Phase Two: Coarse Calibration – Adjusting the Number of Parallel Units

[0044] The system enters the coarse calibration stage based on the deviation Δ = +10% obtained from the global impedance calibration.

[0045] Due to process variations, the on-chip resistors Rs1 to Rs4 in each drive unit were also increased by 10%. The total output impedance of the drive unit is determined by the source series resistance Rs and the equivalent on-resistance of the programmable transistors Mcp / Mcn. During the coarse calibration phase, the gate bias voltages of Mcp and Mcn have not yet been finely adjusted (they are in the initial bias state), therefore, the series resistance value in each drive unit increases by 10%, and the output impedance deviates from the ideal value of 4000Ω. The total output impedance of 40 units connected in parallel also deviates from the target by 100Ω.

[0046] If the 2000-ohm pull-up and pull-down resistors can be represented as a series resistance of 1600Ω plus the on-resistance of the two transistors of 400Ω, then the series resistance increases to 1600 * 1.1Ω. Due to the change in source-drain voltage, the on-resistance of the transistors also changes. Increasing the number of transistors in parallel makes precise matching impossible. The purpose of fine calibration is to calibrate the impedance of each transistor to the corresponding precise value.

[0047] To offset the increased resistance, the number of parallel drive units needs to be increased to reduce the total output impedance back to around 100Ω. The FSM calculates based on Δ=+10%: 3 / 4 of the change is adjusted through coarse calibration, and the remaining 1 / 4 through fine calibration. This requires adding approximately 3 drive units and using the enable control code EN. <n:0>The number of points has been adjusted from 40 to 43.

[0048] After coarse calibration, the total output impedance of the drive unit circuit recovered from 110Ω to around 100Ω. At this point, fine calibration is still needed to calibrate the output impedance to 100Ω, covering the approximately 7.5% impedance deviation caused by PVT, achieving a wide range of initial adjustment. However, there is still a 2.5% error that needs to be adjusted by the fine calibration circuit.

[0049] Phase 3: Fine Calibration – Precise Loop Locking

[0050] After the coarse calibration is completed, the fine calibration is initiated. At this point, the deviation Δ = +10% provided by the global impedance calibration circuit has been transmitted to the analog impedance loop.

[0051] In the drive unit, the equivalent impedance of the pull-up branch consists of the sum of the series resistance Rs and the on-resistance of the programmable transistor Mcp / Mpp, while the equivalent impedance of the pull-down branch consists of the sum of the series resistance Rs and the on-resistance of the programmable transistor Mcn / Mpn. After coarse calibration adjusts the total output impedance to near the target value by changing the number of parallel units, the remaining impedance deviation needs to be further precisely corrected through the analog loop.

[0052] In the replicated branch of the analog impedance loop, This represents the series resistor of the pull-up branch (corresponding to Rs1 / Rs3 in the drive unit). The series resistance of the pull-down branch (corresponding to Rs2 / Rs4 in the drive unit) represents the resistance of MP1, while the on-resistances of MN2 and MP1 represent the equivalent on-resistances of the programmable transistors in the pull-up and pull-down branches, respectively. Therefore, the equivalent impedance of the pull-up path of the replicated branch is... + + ( The on-resistance of MP1 is... (where MP2 is the on-resistance), the equivalent impedance of the pull-down path is + + ( The on-resistance of MN2; (where MN1 is the on-resistance).

[0053] Ideal pressure distribution:

[0054] Under ideal process angles, the replication ratio is 2:40, and the target equivalent impedance of the pull-up branch is 1000Ω, i.e. + + (The Vctrlp bias is adjusted to a certain value, equivalent to 1000Ω). Similarly, the equivalent impedance of the pull-down branch is also 1000Ω. (Duplicate load) The design value is 2000Ω (equivalent to 20 times the equivalent load under 100Ω transmission line matching).

[0055] The voltage division ratio of the pull-up branch is: Therefore, the reference voltage at the non-inverting input of the pull-up branch error amplifier Amp1 is set at 1 / 4 VDD of the resistor divider network (based on the initial UP code). <n:0>(Control); The reference voltage at the non-inverting input of the pull-down branch error amplifier Amp2 is set at 3 / 4 VDD (from the initial DN code). <n:0>control).

[0056] Adjustment of voltage distribution relationship after PVT deviation occurs:

[0057] When the on-chip resistors increase by 10% overall due to PVT deviation: and The actual resistance increases to 10%. (Replicated load) The actual resistance increased from 2000Ω to 2200Ω. After coarse calibration, 43 drive units were connected in parallel, and the replication ratio became 2:43. At this point, in order to compensate for the remaining 1 / 4 change of Δ=+10%, the pull-up and pull-down impedances of the replication branch need to be adjusted to 50*43 / 2=1075Ω (after the impedances of the pull-up and pull-down branches are accurately adjusted, a precise 100Ω output resistance can be obtained by connecting them in parallel). The new voltage division ratio is then: Pull-up branch: Drop-down branch: ;because The voltage divider was increased by 10%, and the replication ratio changed. To maintain the equivalent impedance of the pull-up and pull-down branches at 50Ω, the voltage divider ratio changed—the required voltage divider for the pull-up branch decreased from 1 / 4 (25%) to 1075Ω / 4350Ω (approximately 24.7%). The FSM recalculated and adjusted the UP code. <n:0>and DN code <n:0>FSM based on deviation Recalculate the target value of the clamping voltage: Pull-up branch (Amp1): The new clamping reference voltage should be ,in, .Right now FSM updated the UP code accordingly. <n:0>The numerical control switch S1 is controlled to select the corresponding voltage node in the resistor divider network, and the non-inverting input terminal of Amp1 is set at the target voltage.

[0058] Pull-down branch (Amp2): The new clamping reference voltage should be ,Right now FSM updates DN code accordingly. <n:0>Control the numerical control switch S2 to select the corresponding voltage node, and set the non-inverting input terminal of Amp2 at the target voltage.

[0059] After the reference voltage adjustment is completed, the two negative feedback loops start working: in the pull-up branch, the non-inverting input of Amp1 is connected to the new clamping reference voltage. (Approximately 24.7% VDD), inverting input connected to The node's output drives the MP1 gate (Vctrlp). The loop forces... Node voltage equals .because The actual value is 10% higher, while The impedance is 2200Ω. According to the series voltage divider, if the equivalent impedance of the pull-up branch is 1075Ω (i.e., The series resistance of MP1 and MP2 is equivalent to 1075Ω. It is exactly equal to 1075 / 4350 VDD. Amp1 changes the on-resistance of MP1 by adjusting Vctrlp, making... The series equivalent impedance with the on-resistances of MP1 and MP2 converges precisely to 1075Ω.

[0060] Similarly, in the pull-down branch, the non-inverting input of Amp2 is connected to the new clamping reference voltage. Inverting input terminal connected The node's output drives the gate (Vctrln) of MN2. The loop forces... Node voltage equals By adjusting Vctrln, the on-resistance of MN2 is changed, so that... The equivalent impedance in series with the on-resistance of MN2 converges precisely to 1075Ω. After the two negative feedback loops stabilize, the equivalent impedances of both the pull-up and pull-down paths of the replication branch are locked at 1075Ω. At this point, Vctrlp output from error amplifier Amp1 and Vctrln output from Amp2 reflect the gate voltages required for precise biasing of the pull-up and pull-down branches, respectively.

[0061] In summary, this invention addresses the problems of existing SST driver impedance calibration schemes, such as the large adjustment step size, limited accuracy, and increased power consumption and parasitic capacitance caused by the large number of parallel units in the digital coarse calibration method based on parallel drive units, as well as the narrow adjustment range, the inability to lock under large PVT fluctuations, and the large impedance deviation at high frequencies of the continuous fine calibration method based on analog impedance loops. The invention provides a circuit for matching the output impedance of TX circuits. This circuit includes an off-chip precision resistor, a TX circuit, and a global impedance calibration circuit. The TX circuit includes an analog impedance loop and a drive unit circuit, and the TX circuit and the global impedance calibration circuit are etched on the same wafer. The global impedance calibration circuit measures the resistance deviation between the off-chip precision resistor and the on-chip programmable resistor array through a comparator circuit. The finite state machine uses the output of the comparator circuit as feedback to adjust the on-chip programmable resistor array to a preset error range through an impedance adjustment code closed loop. It also generates coarse and fine adjustment codes based on the impedance adjustment codes. The coarse adjustment code achieves large-range impedance coarse calibration by controlling the number of parallel drive units, while the fine adjustment code achieves high-precision continuous fine calibration by adjusting the gate bias voltage of the programmable transistor in the replication branch through the analog impedance loop. The two work together to ensure impedance matching capability over a large dynamic range and achieve high-precision fine locking. This allows the TX circuit to maintain stable and accurate output impedance matching under different process angles, power supply voltages, and operating temperatures, effectively reducing signal reflection and improving the integrity of transmitted signals.

[0062] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A circuit for matching the output impedance of a TX circuit, characterized in that, include: Off-chip precision resistors, TX circuit, and global impedance calibration circuit; the TX circuit includes an analog impedance loop and a drive unit circuit. The TX circuit and the global impedance calibration circuit are etched on the same wafer. The global impedance calibration circuit includes an on-chip programmable resistor array, a comparator circuit, and a finite state machine; the comparator circuit is used to measure the resistance deviation between an off-chip precision resistor and the on-chip programmable resistor array. The finite state machine uses the output signal of the comparator circuit as feedback to adjust the on-chip programmable resistor array through impedance adjustment code, so that the resistance value deviation between the on-chip programmable resistor array and the off-chip precision resistor is within a preset error range. The finite state machine generates corresponding coarse and fine adjustment codes based on the impedance adjustment code. The coarse adjustment code is output to the driving unit circuit to control it to perform coarse calibration, and the fine adjustment code is output to the analog impedance loop to control it to perform fine calibration, thus completing the output impedance matching of the TX circuit.

2. The output impedance matching circuit for a TX circuit according to claim 1, characterized in that, The comparator circuit includes NMOS transistors MN01 and MN02, an error amplifier Amp, and a dynamic comparator. One end of the off-chip precision resistor and one end of the on-chip programmable resistor array are connected to the power supply terminal Vdd. The other end of the off-chip precision resistor, the drain of MN01, and the inverting input of the error amplifier Amp are connected. The gates of MN01 and MN02 are connected to a bias voltage. The sources of MN01 and MN02 are grounded. The other end of the on-chip programmable resistor array, the drain of MN02, and the non-inverting input of the error amplifier Amp are connected. The output of the error amplifier Amp is connected to the first input of the dynamic comparator. The second input of the dynamic comparator is connected to a reference voltage Vref. The output of the dynamic comparator is connected to a finite state machine. The impedance adjustment code output by the finite state machine acts on the on-chip programmable resistor array.

3. The output impedance matching circuit for a TX circuit according to claim 2, characterized in that, The dynamic comparator and the finite state machine are driven by the same clock signal CLK.

4. The output impedance matching circuit for a TX circuit according to claim 1, characterized in that, The simulated impedance loop includes: 2N+1 on-chip resistors R connected in series between the power supply terminal Vdd and the ground terminal GND, error amplifiers Amp1 and Amp2, and on-chip resistors. On-chip resistors On-chip resistors PMOS transistors MP1 and MP2, and NMOS transistors MN1 and MN2; the fine adjustment code includes a pull-up adjustment code (UP code). <n:0>and dropdown adjustment code DN code <n:0>From the power supply terminal Vdd towards the ground terminal GND, a digitally controlled switch S1 is connected in parallel between the end of each of the 1st to Nth on-chip resistors R and the non-inverting input terminal of the error amplifier Amp1. The N digitally controlled switches S1 are adjusted by pull-up codes UP. <n:0>Control is off. A digitally controlled switch S2 is connected in parallel between the end of each of the (N+1)th to (2Nth)th on-chip resistors R and the non-inverting input of the error amplifier Amp2. The N digitally controlled switches S2 are adjusted by the pull-down code DN. <n:0>Control shutdown; the source of MP1 is connected to the power supply terminal Vdd; the drain of MP1 and the source of MP2 are connected; the drain of MP2 is connected to an on-chip resistor. One end; on-chip resistor The other end is connected to the inverting input of the error amplifier Amp1 and the on-chip resistor. One end; MP2's gate ground (GND); on-chip resistor The other end is connected to the inverting input of the error amplifier Amp2 and the on-chip resistor. One end; on-chip resistor The other end is connected to the drain of MN1; the source of MN1 is connected to the drain of MN2; the gate of MN1 is connected to the power supply terminal Vdd; the source of MN2 is grounded to GND; the gate of MP1 is connected to the output terminal of error amplifier Amp1 and the output terminal of control signal Vctrlp; the gate of MN2 is connected to the output terminal of error amplifier Amp2 and the output terminal of control signal Vctrln; control signals Vctrlp and Vctrln are used to control the drive unit circuit.

5. The output impedance matching circuit for a TX circuit according to claim 1, characterized in that, The drive unit circuit includes N drive units, and the coarse adjustment code includes the enable control code EN. <n:0>The enable control code EN <n:0> Used to control whether the enable signal is connected to the drive unit.

6. The output impedance matching circuit for a TX circuit according to claim 5, characterized in that, Each driving unit includes: a first pre-driving unit, a second pre-driving unit, on-chip resistors Rs1~Rs4, PMOS transistors Mcp, Mpp and Mnp, and NMOS transistors Mcn, Mpn and Mnn; The input terminal of the first pre-drive unit is connected to the input data signal Dinn; the enable terminals of the first and second pre-drive units are connected and controlled by the enable control code EN. <n:0>The control determines whether an enable signal is connected; the first output terminal of the first pre-drive unit is connected to the gate of Mnp; the second output terminal of the first pre-drive unit is connected to the gate of Mnn; the drain of Mnp is connected to one end of the on-chip resistor Rs1; the drain of Mnn is connected to one end of the on-chip resistor Rs2; the other ends of the on-chip resistors Rs1 and Rs2 are connected to the input terminal of the second signal transmission line; the source of Mnp and the drain of Mcp are connected to the source of Mpp; the source of Mcp is connected to the power supply terminal Vdd; the gate of Mcp is connected to the control signal Vctrlp; M The source of nn and the source of Mpn are connected to the drain of Mcn; the source of Mcn is connected to ground GND; the gate of Mcn is connected to the control signal Vctrln; the input terminal of the second pre-drive unit is connected to the input data signal Dinp; the first output terminal of the second pre-drive unit is connected to the gate of Mpp; the second output terminal of the second pre-drive unit is connected to the gate of Mpn; the drain of Mpp is connected to one end of the on-chip resistor Rs3; the drain of Mpn is connected to one end of the on-chip resistor Rs4; the other ends of the on-chip resistor Rs3 and the other ends of the on-chip resistor Rs4 are connected to the input terminal of the first signal transmission line.< / n:0>

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