Shaping circuit and ethernet device

Abstract

The application discloses a shaping circuit and an Ethernet device, and belongs to the field of circuits. The shaping circuit provided by the application comprises a first NMOS tube, a second NMOS tube, a switch unit and a control unit. The drain end of the first NMOS tube and the gate end of the second NMOS tube are connected with an input port, and the gate end of the first NMOS tube and the drain end of the second NMOS tube are connected with a first power supply port. The source end of the first NMOS tube and the source end of the second NMOS tube are connected with an output port. The first end of the switch unit is connected with the input port, the second end of the switch unit is connected with the control unit, the third end of the switch unit is connected with a third power supply port, and the fourth end of the switch unit is connected with the output port. In the case that the shaping circuit is in a transmission mode, the first end of the switch unit and the fourth end of the switch unit are in a conduction state, and the voltage amplitude of an output signal of the output port is the same as the voltage amplitude of an input signal of the input port.

Description

Technical Field

[0001] This application belongs to the field of circuits, specifically relating to a shaping circuit and an Ethernet device. Background Technology

[0002] In the field of circuits, in order to obtain a specific pulse signal, a shaping circuit can be used to shape the existing signal to obtain a pulse signal that meets the requirements.

[0003] In related technologies, a typical high-voltage shaping circuit can be composed of two cross-coupled NMOS transistors. For example... Figure 1 As shown, the shaping circuit may include two NMOS transistors MN2 and MN3. The drain of MN2 and the gate of MN3 are connected to the input port IN, and the gate of MN2 and the drain of MN3 are connected to the power supply port VDDPST18. The source of MN2 and the source of MN3 are connected to the output port OUT. The shaping circuit has a shaping mode and a transmission mode. The corresponding input port IN has an overvoltage mode (i.e., 3.3V operating mode) and a constant voltage mode (i.e., 1.8V operating mode). When the shaping circuit is in shaping mode, the input port IN is in overvoltage mode, and the shaping circuit can shape an input signal with a 0-3.3V swing into a signal output with a 0-1.65V swing. When the shaping circuit is in transmission mode, the input port IN is in constant voltage mode, and the shaping circuit can transmit an input signal with a 0-1.8V swing to the output port OUT.

[0004] However, the related technology suffers from a problem where the shaping circuit cannot transmit signals at full swing in transmission mode. Specifically, when the shaping circuit is in transmission mode, the input port IN is in constant voltage mode, and the gate voltage of MN2 depends on the power supply voltage of the power supply port VDDPST18, and is limited by the threshold voltage V of MN2. THN The voltage swing of the input signal with a swing of 0-1.8V output by the shaping circuit is 0-(1.8-V). THN The output signal at the OUT port inevitably loses approximately 1 V. THN The swing amplitude is insufficient to meet the requirements for full-amplitude signal transmission. Summary of the Invention

[0005] This application provides a shaping circuit and an Ethernet device that can solve the problem in related technologies where the shaping circuit cannot transmit signals at full swing when it is in transmission mode.

[0006] In a first aspect, embodiments of this application provide a shaping circuit, which has an input port, an output port, a first power supply port, a second power supply port and a third power supply port, and includes: a first NMOS transistor, a second NMOS transistor, a switching unit and a control unit; The drain of the first NMOS transistor and the gate of the second NMOS transistor are connected to the input port; the gate of the first NMOS transistor and the drain of the second NMOS transistor are connected to the first power supply port; the source of the first NMOS transistor and the source of the second NMOS transistor are connected to the output port. The first end of the switching unit is connected to the input port, the second end of the switching unit is connected to the control unit, the third end of the switching unit is connected to the third power port, and the fourth end of the switching unit is connected to the output port. The control unit is also connected to the input port, the first power port, the second power port and the third power port respectively; When the shaping circuit is in transmission mode, the first terminal and the fourth terminal of the switching unit are in a conducting state, and the voltage amplitude of the output signal of the output port is the same as the voltage amplitude of the input signal of the input port.

[0007] Secondly, embodiments of this application provide an Ethernet device that may include the shaping circuit described in the first aspect.

[0008] In this embodiment, the shaping circuit has an input port, an output port, a first power port, a second power port, and a third power port. The shaping circuit includes: a first NMOS transistor, a second NMOS transistor, a switching unit, and a control unit. The drain of the first NMOS transistor and the gate of the second NMOS transistor are connected to the input port, and the gate of the first NMOS transistor and the drain of the second NMOS transistor are connected to the first power port. The source of the first NMOS transistor and the source of the second NMOS transistor are connected to the output port. The first terminal of the switching unit is connected to the input port, the second terminal of the switching unit is connected to the control unit, the third terminal of the switching unit is connected to the third power port, and the fourth terminal of the switching unit is connected to the output port. The control unit is also connected to the input port, the first power port, the second power port, and the third power port, respectively. When the shaping circuit is in transmission mode, the first terminal and the fourth terminal of the switching unit are in a conducting state, and the voltage amplitude of the output signal of the output port is the same as the voltage amplitude of the input signal of the input port. In this way, when the shaping circuit is in transmission mode, the control module can control the first and fourth terminals of the switching unit to be in a conducting state, so that the input port and the output port are connected. Then, the input signal from the input port can be transmitted to the output port through the switching unit, so that the voltage amplitude of the output signal at the output port is the same as the voltage amplitude of the input signal at the input port. This realizes full-swing signal transmission when the shaping circuit is in transmission mode, improving the data transmission performance of the shaping circuit. Attached Figure Description

[0009] Figure 1 This is a schematic structural diagram of a typical high-voltage shaping circuit provided in related technologies; Figure 2 for Figure 1 The signal timing diagram of the shaping circuit in overvoltage mode is shown below; Figure 3 for Figure 1 The signal timing diagram of the shaping circuit in normal voltage mode is shown below; Figure 4 A schematic structural diagram of a shaping circuit provided in an embodiment of this application; Figure 5 A schematic structural diagram of another shaping circuit provided in an embodiment of this application; Figure 6-1 A schematic structural diagram of a shaping circuit in normal voltage mode provided for an embodiment of this application; Figure 6-2 A schematic structural diagram of another shaping circuit provided in the embodiment of this application in normal voltage mode; Figure 6-3 A signal timing diagram of a shaping circuit in constant voltage mode provided in an embodiment of this application; Figure 7-1 A schematic structural diagram of a shaping circuit in overvoltage mode provided for an embodiment of this application; Figure 7-2 A schematic structural diagram of another shaping circuit provided in an embodiment of this application in overvoltage mode; Figure 7-3 A signal timing diagram of a shaping circuit in overvoltage mode provided in an embodiment of this application; Figure 8 This is a schematic structural diagram of an Ethernet device provided in an embodiment of this application.

[0010] Explanation of reference numerals in the attached figures: 10 - Shaping circuit; MN2 - First NMOS transistor; MN3 - Second NMOS transistor; 100 - Switching unit; MP5 - Switching transistor; 200 - Control unit; MN1 - Third NMOS transistor; 210 - Level selection unit; MP1 - First PMOS transistor; MP2 - Second PMOS transistor; MP3 - Third PMOS transistor; MP4 - Fourth PMOS transistor; MN0 - Fourth NMOS transistor; IN - Input port; OUT - Output port; VDDPST18 - First power port; VDDPST18L - Second power port; VDDPST33 - Third power port; 800 - Ethernet device. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0012] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0013] In related technologies, such as Figure 1As shown, a typical high-voltage shaping circuit may include two NMOS transistors MN2 and MN3. The drain of MN2 and the gate of MN3 are connected to the input port IN, and the gate of MN2 and the drain of MN3 are connected to the power supply port VDDPST18. The source of MN2 and the source of MN3 are connected to the output port OUT. Figure 1 The input port of the shaping circuit shown has both overvoltage and normal voltage modes.

[0014] Among them, reference Figure 2 The overvoltage mode, also known as the 3.3V operating mode, has VDDPST18 = 1.65V in the circuit. From... Figure 2 It is easy to see that during the T1-T4 time period, the input signal on the input port IN undergoes a rising edge transition from 0 to 3.3V; during the T5-T8 time period, the input signal on the input port IN transitions from 3.3V to 0V. The transmission process of the rising edge of the input signal includes: During the time interval T1-T2, the input signal is ≤1.65V. THN In the circuit, MN2 is in the on state, MN3 is in the off state, and the output level at the OUT port is pulled up to 1.65V by MN2. THN ; During the T2-T3 time period, 1.65VV THN <Input signal ≤ 1.65V + V THN In the circuit, MN2 gradually turns off, MN3 gradually turns on, and the output port OUT level rises from 1.65V. THN It was gradually pulled up to around 1.65V by MN3; During the T4-T5 time period, 1.65V+V THN <Input signal, MN3 in the circuit is fully open, and the output port OUT is locked at 1.65V; The transmission process of the falling edge of the high-voltage signal includes: During the T5-T6 time period, 1.65V+V THN < Input signal, MN3 in the circuit is fully turned on, and the output port OUT is still locked at 1.65V.

[0015] During the T6-T7 time period, 1.65VV THN <Input signal ≤ 1.65V + V THN In the circuit, MN2 gradually turns on, MN3 gradually turns off, and the output port OUT level is gradually pulled down from 1.65V to 1.65V by MN3. THN nearby; During the T7-T8 time period, the input signal is <1.65V. THN In the circuit, MN2 is fully open, and the output level at the OUT port is pulled down to 0V by MN2.

[0016] Thus, when the shaping circuit is in shaping mode, the input port IN is in overvoltage mode. The shaping circuit can shape the input signal with a swing of 0-3.3V into an output signal with a swing of 0-1.65V, so that the receiving circuit, which operates in the 1.65V power supply domain, can process the output signal.

[0017] In addition, the shaping circuit also has a transmission mode, and the corresponding input port IN also has a constant voltage mode. (Reference) Figure 3 The normal voltage mode is also known as the 1.8V operating mode, where VDDPST18 = 1.8V in the circuit. From... Figure 3 It is easy to see that during the T1-T3 time period, the input signal on the input port IN undergoes a rising edge transition from 0 to 1.8V; during the T4-T6 time period, the input signal on the input port IN undergoes a falling edge transition from 1.8V to 0V.

[0018] The transmission process of the rising edge of the input signal includes: During the time interval T1-T2, the input signal is ≤1.8V. THN In the circuit, MN2 is in the ON state, MN3 is in the OFF state, and the output level at the OUT port is pulled up to 1.8V by MN2. THN .

[0019] During the T2-T3 time period, 1.8VV THN With the input signal, MN2 in the circuit gradually turns off, and MN3 also fails to conduct, so the output port OUT is locked at 1.8V. THN .

[0020] The transmission process of the falling edge of the input signal includes: During the T4-T5 time period, 1.8VV THN With the input signal, MN2 in the circuit gradually turns off, while MN3 remains off, and the output port OUT is locked at 1.8V. THN .

[0021] During the T5-T6 time period, the input signal is ≤1.8V. THN In the circuit, MN2 is in the on state, and the output level of the OUT port is pulled down to 0V by MN2.

[0022] As described above, in a typical high-voltage shaping circuit operating at 1.8V, the output signal at the OUT port will inevitably lose approximately 1V during signal transmission. THN The amplitude of the swing.

[0023] Based on this, in order to solve the problem that shaping circuits in related technologies cannot transmit signals at full swing in transmission mode, the shaping circuit provided in this application embodiment has a switching unit between the input port and the output port of the shaping circuit. When the shaping circuit is in transmission mode, the input port and the output port are connected by turning on the switching unit. Then, the input signal from the input port can be directly transmitted to the output port through the switching unit, so that the voltage amplitude of the output signal at the output port is the same as the voltage amplitude of the input signal at the input port. This realizes the function of full swing signal transmission at the output port when the input port of the shaping circuit is in constant voltage mode, improves the data transmission performance of the shaping circuit, and solves the problem that shaping circuits in related technologies cannot transmit signals at full swing in transmission mode.

[0024] The shaping circuit provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0025] Figure 4 This is a schematic structural diagram of a shaping circuit provided in an embodiment of this application.

[0026] like Figure 4 As shown, the shaping circuit 10 provided in this application embodiment may have an input port IN, an output port OUT, a first power supply port VDDPST18, a second power supply port VDDPST18L and a third power supply port VDDPST33. The shaping circuit 10 provided in this application embodiment may include: a first NMOS transistor MN2, a second NMOS transistor MN3, a switching unit 100 and a control unit 200. The drain of the first NMOS transistor MN2 and the gate of the second NMOS transistor MN3 are connected to the input port IN. The gate of the first NMOS transistor MN2 and the drain of the second NMOS transistor MN3 are connected to the first power supply port VDDPST18. The source of the first NMOS transistor MN2 and the source of the second NMOS transistor MN3 are connected to the output port OUT. The first end of the switching unit 100 is connected to the input port IN, the second end of the switching unit 100 is connected to the control unit 200, the third end of the switching unit 200 is connected to the third power supply port VDDPST33, and the fourth end of the switching unit 200 is connected to the output port OUT. The control unit 200 is also connected to the input port IN, the first power port VDDPST18, the second power port VDDPST18L and the third power port VDDPST33 respectively. When the shaping circuit 10 is in transmission mode, the first terminal and the fourth terminal of the switching unit 100 are in a conducting state, and the voltage amplitude of the output signal of the output port OUT is the same as the voltage amplitude of the input signal of the input port.

[0027] In the embodiments of this application, the first NMOS transistor MN2 and the second NMOS transistor MN3 can be two cross-coupled NMOS transistors, which can form a low-level selection circuit.

[0028] In this embodiment, the shaping circuit has a shaping mode and a transmission mode, and the corresponding input port IN has an overvoltage mode and a normal voltage mode. When the shaping circuit is in shaping mode, the input port is in overvoltage mode, also known as 3.3V operating mode. In this mode, the input signal at input port IN is a high-speed signal with a swing of 0-3.3V. When the shaping circuit is in transmission mode, the input port is in normal voltage mode, also known as 1.8V operating mode. In this mode, the input signal at input port IN is a high-speed signal with a swing of 0-1.8V.

[0029] In the case where the shaping circuit is in transmission mode, the input port IN is in constant voltage mode. The transmission gate circuit composed of the first NMOS transistor MN2 and the switching unit 100 can realize that the 0-1.8V swing input signal passes through the shaping circuit and outputs a 0-1.8V swing output signal, realizing the function of the shaping circuit to transmit signals at full swing in constant voltage mode.

[0030] In this embodiment of the application, when the shaping circuit is in transmission mode, the input port IN is in constant voltage mode. The input port IN can receive input signals from 0 to 1.8V. The switching unit 100 is in the on state, and the input port IN and the output port OUT are connected. Thus, the output port OUT can output a full swing (0 to 1.8V) output signal.

[0031] The switching unit 100 can be a unit with switching function, which connects the input port IN and the output port OUT when the input port is in constant voltage mode. For example, the switching unit 100 can be composed of at least one NMOS transistor / PMOS transistor, etc. The embodiments of this application do not limit the specific number and type of components of the switching unit 100.

[0032] It should be noted that in the related technology, when the shaping circuit is in transmission mode, the input port IN is in constant voltage mode. The input signal from the input port IN needs to be transmitted to the output port OUT through the first NMOS transistor MN2, which is limited by the threshold voltage V of the first NMOS transistor MN2. THN The output port OUT level is locked at 1.8V. THN This results in a loss of approximately 1V in the output signal. THNThe amplitude of the signal swing is large. Compared with related technologies, in this embodiment, the input port IN is connected to the output port OUT through the switching unit 100. Since a new transmission channel is established between the input port IN and the output port OUT, and the switching unit 100 controls the conduction and cutoff of this transmission channel, when the shaping circuit is in transmission mode, the input port IN is in constant voltage mode. Since the switching unit 100 is in the conducting state, the 1.8V input signal can pass through the switching unit 100 and output a 1.8V output signal from the output port OUT. This realizes the full-swing signal transmission of the shaping circuit in constant voltage mode, improves the data transmission performance of the shaping circuit, and solves the problem in related technologies that the shaping circuit cannot transmit signals with full swing in constant voltage mode.

[0033] The shaping circuit provided in this application embodiment has an input port, an output port, a first power port, a second power port, and a third power port. The shaping circuit includes a first NMOS transistor, a second NMOS transistor, a switching unit, and a control unit. The drain of the first NMOS transistor and the gate of the second NMOS transistor are connected to the input port, and the gate of the first NMOS transistor and the drain of the second NMOS transistor are connected to the first power port. The source of the first NMOS transistor and the source of the second NMOS transistor are connected to the output port. The first end of the switching unit is connected to the input port, the second end of the switching unit is connected to the control unit, the third end of the switching unit is connected to the third power port, and the fourth end of the switching unit is connected to the output port. The control unit is also connected to the input port, the first power port, the second power port, and the third power port. When the shaping circuit is in transmission mode, the first end and the fourth end of the switching unit are in a conducting state, and the voltage amplitude of the output signal at the output port is the same as the voltage amplitude of the input signal at the input port. In this way, when the shaping circuit is in transmission mode, the control module can control the first and fourth terminals of the switching unit to be in a conducting state, so that the input port and the output port are connected. Then, the input signal from the input port can be transmitted to the output port through the switching unit, so that the voltage amplitude of the output signal at the output port is the same as the voltage amplitude of the input signal at the input port. This realizes full-swing signal transmission when the shaping circuit is in transmission mode, improving the data transmission performance of the shaping circuit.

[0034] Furthermore, when a switching unit 100 is provided between the input port IN and the output port OUT of the shaping circuit 10, in order to prevent the high-voltage input signal from leaking to the output port OUT through the switching unit 100 and affecting the shaping function of the shaping circuit when the input port IN is in overvoltage mode, the first terminal and the fourth terminal of the switching unit 100 are in an open state when the shaping circuit is in shaping mode, and the voltage amplitude of the output signal of the output port OUT is different from the voltage amplitude of the input signal of the input port.

[0035] For example, when the shaping circuit is in shaping mode, the input port IN is in overvoltage mode, the switching unit 100 is in the off state, and the level selection circuit composed of the first NMOS transistor MN2 and the second NMOS transistor MN3, supplemented by the first power supply port VDDPST18 (e.g., a 1.65V protection power supply), can shape a 0-3.3V swing input signal into a 0-1.65V swing output signal. For the specific shaping process, please refer to [reference needed]. Figure 2 This will not be elaborated upon here.

[0036] It should be noted that, since the input port IN is in overvoltage mode when the shaping circuit is in shaping mode, the switching unit 100 remains in the off state, which can prevent the 3.3V swing input signal from leaking to the output port through the switching unit 100, thus not affecting the shaping function of the shaping circuit.

[0037] Thus, in the shaping circuit provided in this application embodiment, since the switching unit 100 is in the off state when the input port IN of the shaping circuit is in overvoltage mode, the high voltage input signal can be prevented from leaking to the output port through the switching unit 100, thereby not affecting the shaping function of the shaping circuit.

[0038] In one specific embodiment, the voltage values ​​at the first power port VDDPST18, the second power port VDDPST18L, and the third power port VDDPST33 are different in the shaping mode / transmission mode, thereby realizing the data shaping process / data transmission process of the shaping circuit respectively.

[0039] In the shaping circuit, when the shaping circuit is in shaping mode, the voltages of the first power port VDDPST18 and the second power port VDDPST18L are both half the voltage amplitude of the input signal at the input port IN, and the voltage of the third power port VDDPST33 has the same voltage amplitude as the input signal at the input port IN. For example, when the shaping circuit is in shaping mode, taking the voltage amplitude of the input signal at the input port IN as 3.3 volts, the voltages of the first power port VDDPST18 and the second power port VDDPST18L are both 1.65 volts, and the voltage of the third power port VDDPST33 is 3.3 volts.

[0040] When the shaping circuit is in transmission mode, the voltage of the first power port VDDPST18 and the voltage of the third power port VDDPST33 are the same as the voltage amplitude of the input signal at the input port IN. For example, if the voltage amplitude of the input signal at the input port IN is 1.8 volts, the voltage of the first power port VDDPST18 and the voltage of the third power port VDDPST33 are both 1.8 volts, and the voltage of the second power port VDDPST18L is 0 volts.

[0041] For example, refer to Figure 5 , Figure 5 The shaping circuit 10 shown can have multiple interfaces. The interfaces of the shaping circuit in shaping mode and transmission mode are described in Table 1 below.

[0042]

[0043] Table 1 To achieve precise control of the switching unit, the shaping circuit provided in this application includes a control unit to control the on and off states of the switching unit 100. For example, such as Figure 4 As shown, in the shaping circuit 10, the control unit 200 is connected to the second terminal of the switching unit 100.

[0044] When the input port IN of the shaping circuit 10 is in overvoltage mode, the control unit 200 can control the switching unit 100 to disconnect, so as to prevent the high voltage input signal from leaking to the output port through the switching unit 100 and affecting the shaping function of the shaping circuit.

[0045] In the case where the input port IN of the shaping circuit 10 is in constant pressure mode, the control unit 200 can control the switching unit 100 to turn on, and the input signal from the input port can be directly transmitted to the output port through the switching unit, thus realizing the full swing signal transmission of the shaping circuit in constant pressure mode.

[0046] Thus, in the shaping circuit provided in this application embodiment, the control unit 200 controls the switching unit 100 to turn on / off, thereby achieving precise switching of the on / off state of the switching unit 100 and realizing the switching of different working modes of the shaping circuit.

[0047] In a specific example, refer to Figure 5 The control unit 200 may include a level selection unit 210 and a third NMOS transistor MN1; The level selection unit 210 is connected to the input port IN, the second terminal of the switch unit 100, the first power port VDDPST18, the second power port VDDPST18L and the third power port VDDPST33 respectively. The drain of the third NMOS transistor MN1 is connected to the second terminal of the switching unit 100; the source of the third NMOS transistor MN1 is connected to the second power supply port VDDPST18L; and the gate of the third NMOS transistor MN1 is connected to the first power supply port VDDPST18. When the shaping circuit is in shaping mode, the level selection unit 210 outputs a first control signal to the switching unit 100, so that the first terminal and the fourth terminal of the switching unit 100 are in an open state. When the shaping circuit is in transmission mode, the third NMOS transistor MN1 outputs a second control signal to the switching unit 100, so that the first terminal of the switching unit and the fourth terminal of the switching unit 100 are in a conducting state.

[0048] Thus, in the shaping circuit provided in this application embodiment, the switching unit 100 is turned off by setting the level selection unit 210, and the switching unit 100 is turned on by setting the third NMOS transistor MN1, so as to realize the precise switching of the on / off state of the switching unit 100, thereby realizing the switching of different working modes of the shaping circuit.

[0049] In a specific example, refer to Figure 5The level selection unit 210 may include: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4; the source terminal of the first PMOS transistor MP1 and the gate terminal of the second PMOS transistor MP2 are connected to the input port IN; the gate terminal of the first PMOS transistor MP1 and the source terminal of the second PMOS transistor MP2 are connected to the first power supply port VDDPST18; the drain terminal of the first PMOS transistor MP1 and the drain terminal of the second PMOS transistor MP2 are connected to the source terminal of the third PMOS transistor MP3; and the gate terminal of the third PMOS transistor MP3 is connected to the first power supply port. The third PMOS transistor MP3 is connected to the second terminal of the switching unit 100 via the VDDPST18 port; the drain of the fourth PMOS transistor MP4 is connected to the input port IN; the source of the fourth PMOS transistor MP4 is connected to the second power supply port VDDPST18L; and the drain of the fourth PMOS transistor MP4 is connected to the second terminal of the switching unit 100. The substrates of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all connected to the third power supply port VDDPST33.

[0050] In order to meet the requirements of high-speed switching, fast response and low power consumption of the switching unit 100, reference is made. Figure 5 In one specific embodiment, the switching unit 100 may include a switching transistor MP5, which may be a PMOS transistor; the source terminal of the switching transistor MP5 is connected to the input port IN, the gate terminal of the switching transistor MP5 is connected to the control unit 200, the substrate terminal of the switching transistor MP5 is connected to the third power supply port VDDPST33, and the drain terminal of the switching transistor MP5 is connected to the output port OUT.

[0051] When the shaping circuit is in shaping mode, the level selection unit 210 outputs a high-level signal to the gate terminal of the switching transistor MP5, the third NMOS transistor MN1 is in the off state, and the switching transistor MP5 is in the off state. When the shaping circuit is in transmission mode, the third NMOS transistor MN1 outputs a low-level signal to the gate terminal of the switching transistor MP5. The level selection unit 210 is not connected to the gate terminal of the switching transistor MP5, and the switching transistor MP5 is in the on state.

[0052] For example, when the shaping circuit is in transmission mode, the input port of the shaping circuit is in constant voltage mode, and the switching transistor MP5 is in the on state, so that the input port and the output port are connected. The input signal from the input port can be directly transmitted to the output port through the switching unit, realizing the full swing transmission of the signal at the output port of the shaping circuit.

[0053] When the shaping circuit is in shaping mode, the input port of the shaping circuit is in overvoltage mode, and the switching transistor MP5 is in the off state to disconnect the input port from the output port, so as to prevent the high voltage input signal from leaking to the output port through the switching unit 100 and affecting the shaping function of the shaping circuit.

[0054] Thus, in the shaping circuit provided in the application embodiment, the switching unit 100 can be set as a PMOS transistor, which can meet the requirements of high-speed switching, fast response and low power consumption of the switching unit 100.

[0055] In the case where the switching transistor MP5 is a PMOS transistor, the on / off state of the switching transistor MP5 is controlled by the level of the gate terminal P_GATE of the switching transistor MP5.

[0056] For example, when the input port IN of the shaping circuit is in constant voltage mode, the gate terminal P_GATE of the control switching transistor MP5 is set to a low level, thereby controlling the switching transistor MP5 to turn on.

[0057] For example, when the input port IN of the shaping circuit is in overvoltage mode, the gate terminal P_GATE of the control switching transistor MP5 is set to a high level, thereby controlling the switching transistor MP5 to turn off.

[0058] Specifically, in this embodiment of the application, at least one MOS transistor can be used to control the level of the gate terminal P_GATE of the switching transistor MP5.

[0059] For example, this application uses a third NMOS transistor MN1 and a level selection unit 210 to control the level (low / high) of the gate terminal P_GATE of the switching transistor MP5, as shown in the reference. Figure 5 The gate terminal of the switching transistor MP5 is connected to the drain terminal of the third NMOS transistor MN1 and the level selection unit 210, respectively.

[0060] Specifically, the third NMOS transistor MN1 controls the gate P_GATE of the switching transistor MP5 to a low level. In particular, when the input port IN of the shaping circuit is in constant voltage mode, the third NMOS transistor MN1 is in the on state, the voltage at the second power supply port VDDPST18L is 0V, and the gate of the switching transistor MP5 is in a low-level state.

[0061] It should be noted that when the input port IN of the shaping circuit is in constant voltage mode, since the third NMOS transistor MN1 is in the on state and the voltage of the second power supply port VDDPST18L is 0V, the level of the gate terminal P_GATE of the switching transistor MP5 can be pulled down to 0V, thereby making the level of the gate terminal P_GATE of the switching transistor MP5 low, thus turning on the switching transistor MP5.

[0062] Thus, since the control unit 200 includes a third NMOS transistor MN1, when the input port IN of the shaping circuit is in constant voltage mode, by turning on the third NMOS transistor MN1, the level of the gate terminal P_GATE of the switching transistor MP5 is pulled down to 0V, thereby making the level of the gate terminal P_GATE of the switching transistor MP5 low, and thus turning on the switching transistor MP5.

[0063] Additionally, when the input port IN of the shaping circuit 10 is in overvoltage mode, to prevent the high-voltage input signal from leaking through the switching unit 100 to the output port OUT and affecting the shaping function of the shaping circuit, the gate terminal P_GATE of the switching transistor MP5 is set to a high level, thus turning off the switching transistor MP5. In this case, the third NMOS transistor MN1 is in the off state, which can prevent the gate terminal P_GATE of the switching transistor MP5 from being pulled low by the second power supply port VDDPST18L.

[0064] The level selection unit 210 can control the gate terminal P_GATE of the switching transistor MP5 to a high level. When the input port IN of the shaping circuit is in overvoltage mode, the level selection unit 210 outputs a high-level signal to the gate terminal of the switching transistor MP5, thereby making the gate terminal P_GATE of the switching transistor MP5 high, thus disconnecting the switching transistor MP5 and preventing the high-voltage input signal from leaking to the output port through the switching unit 100 and affecting the shaping function of the shaping circuit.

[0065] In this way, the level selection unit 210 is formed by the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the four NMOS transistors MN0. When the input port IN of the shaping circuit is in overvoltage mode, the level selection unit 210 provides a high-level signal to the gate terminal of the switching transistor MP5, so that the switching transistor MP5 is always kept in the off state.

[0066] In addition, the level selection unit 210 may also include a fourth NMOS transistor MN0, the gate of which is connected to the source of the third PMOS transistor MP3, and the drain and source of the fourth NMOS transistor MN0 are connected to the second power supply port VDDPST18L.

[0067] In this way, the fourth NMOS transistor MN0 can be used as a voltage regulator capacitor in the level selection unit 210 to reduce voltage fluctuations on the P_GATE_Pre signal line.

[0068] In addition, when the input port IN of the shaping circuit is in constant voltage mode, the level selection unit 210 and the gate terminal of the switching transistor MP5 are not connected. This can prevent the level of the gate terminal P_GATE of the switching transistor MP5 from being pulled high by the high-level signal output by the level selection unit 210. Instead, the level of the gate terminal P_GATE of the switching transistor MP5 is pulled low to 0V by turning on the third NMOS transistor MN1, thereby turning on the switching transistor MP5.

[0069] The following is about Figure 5 The operation of the shaping circuit 10 shown in normal pressure mode / overpressure mode will be explained in detail.

[0070] like Figure 6-1 , Figure 6-2 and Figure 6-3 The diagram shown is a schematic of the shaping circuit 10 in normal voltage mode. In normal voltage mode, the shaping circuit can complete the lossless transmission of a 200MHz high-speed signal with a 0-1.8V swing.

[0071] like Figure 6-1 The diagram shows the operation of the shaping circuit when the input signal voltage at input port IN is 1.8V. In this case, the voltage at port VDDPST33 is 1.8V, the voltage at port VDDPST18 is 1.8V, and the voltage at port VDDPST18L is 0V. The high-level selection circuit composed of MP1 and MP2 pulls the P_GATE_Pre node up to approximately 1.8V; the level-selection circuit composed of MP3-4 and MN0 cuts off the transmission of the P_GATE_Pre signal; and by turning on MN1, the 0V voltage at port VDDPST18L pulls the gate voltage of MP5 down to 0V, ensuring that MP5 remains on; MP5 then pulls the OUT terminal of the circuit up to 1.8V; thus completing the 1.8V level transmission.

[0072] like Figure 6-2The diagram shows the operation of the shaping circuit when the input signal voltage at input port IN is 0V. In this case, the voltage at port VDDPST33 is 1.8V, the voltage at port VDDPST18 is 1.8V, and the voltage at port VDDPST18L is 0V. The high-level selection circuit composed of MP1 and MP2 transmits the 1.8V level from port VDDPST18 to node P_GATE_Pre; the level gating circuit composed of MP3, MP4, and MN0 cuts off the transmission of the signal at node P_GATE_Pre; by turning on MN1, the gate terminal of switching transistor MP5 is pulled down to 0V to ensure that MP5 is always in the on state; the OUT terminal of the circuit is pulled down to 0V through MN5 or MN2; thus, the transmission of the 0V level is completed.

[0073] like Figure 6-3 The diagram shows the signal timing of the shaping circuit 10 in constant voltage mode. When the voltage of the input signal at the input port IN is 1.8V, the voltage of the output signal at the output port OUT is 1.8V; when the voltage of the input signal at the input port IN is 0V, the voltage of the output signal at the output port OUT is 0V.

[0074] In this way, when the input port IN of the shaping circuit 10 is in constant voltage mode, the switching transistor MP5 can remain in the conducting state. The transmission gate circuit structure formed by MP5 and MN2 can complete the transmission of a 200MHz high-speed signal with a swing of 0-1.8V without loss. The 0-1.8V swing input signal is output as a 0-1.65V swing output signal after passing through the shaping circuit. This realizes the full-swing signal transmission of the shaping circuit in constant voltage mode, improves the data transmission performance of the shaping circuit, and solves the problem in related technologies that the shaping circuit cannot transmit signals with a full swing in constant voltage mode.

[0075] In addition, such as Figure 7-1 , Figure 7-2 and Figure 7-3 The diagram shows the shaping circuit 10 in overvoltage mode. In overvoltage mode, the shaping circuit can shape a 0-3.3V swing input signal into a 0-1.65V swing output signal so that the receiving circuit operating in the 1.65V power supply domain can process the signal.

[0076] like Figure 7-1The diagram shows the operation of the shaping circuit when the input signal voltage at input port IN is 3.3V. In this case, the voltage at port VDDPST33 is 3.3V, the voltage at port VDDPST18 is 1.65V, and the voltage at port VDDPST18L is 1.65V. The high-level selection circuit, composed of two PMOS transistors MP1 and MP2, transmits the 3.3V level at input port IN to node P_GATE_Pre. The 3.3V level at node P_GATE_Pre is then transmitted through MP3 to the gate node P_GATE of MP5, ensuring that MP5 remains off. The low-level selection circuit, composed of MN2 and MN3, blocks the transmission of signals higher than 1.65V. Thus, the shaping circuit completes the shaping operation from 3.3V to 1.65V.

[0077] Among them, VDDPST18 and VDDPST18L with a voltage of 1.65V serve as protection levels to ensure that the voltage difference between the gate, source, and drain of any PMOS or NMOS in the circuit does not exceed 1.8V, thus avoiding damage to the devices in the circuit caused by excessive voltage difference.

[0078] like Figure 7-2 The diagram shows the operation of the shaping circuit when the input signal voltage at input port IN is 0V. In this case, the voltage at port VDDPST33 is 3.3V, the voltage at port VDDPST18 is 1.65V, and the voltage at port VDDPST18L is 1.65V. The high-level selection circuit, composed of two PMOS transistors MP1 and MP2, transmits the 1.65V level at port VDDPST18 to node P_GATE_Pre. The 1.65V level at node P_GATE_Pre and the 1.65V level at port VDDPST18L are then transmitted through MP3 and MP4 to the gate node P_GATE of MP5, ensuring that MP5 remains off. The low-level selection circuit, composed of MN2 and MN3, transmits the 0V level to output port OUT. Thus, the shaping circuit completes the transmission of the 0V signal.

[0079] like Figure 7-3 The diagram shows the signal timing of the shaping circuit 10 in overvoltage mode. When the voltage of the input signal at the input port IN is 3.3V, the voltage of the output signal at the output port OUT is 1.65V; when the voltage of the input signal at the input port IN is 0V, the voltage of the output signal at the output port OUT is 0V.

[0080] Thus, when the input port IN of the shaping circuit 10 is in overvoltage mode, the low-level selection circuit composed of MN2 and MN3, supplemented by a 1.65V protection power supply, can complete the function of shaping a 0-3.3V swing input signal into a 0-1.65V swing output signal. Furthermore, when the input port IN of the shaping circuit 10 is in overvoltage mode, the switching transistor MP5 can always remain off, ensuring that the 3.3V level on the input port IN is not mistakenly transmitted to the subsequent receiving circuit operating in the 1.65V power supply domain.

[0081] Based on the same technical concept as the shaping circuit provided in the above embodiments, this application provides an Ethernet device including the shaping circuit provided in any of the above embodiments.

[0082] Figure 8 This is a schematic diagram of an Ethernet device provided in an embodiment of this application.

[0083] like Figure 8 As shown, the Ethernet device 800 provided in this application embodiment includes the shaping circuit 10 provided in any of the above embodiments.

[0084] It should be noted that the Ethernet device provided in this application includes the shaping circuit provided in any of the above embodiments, and can realize all the functions of the shaping circuit provided in any of the above embodiments. To avoid repetition, it will not be described again here.

[0085] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0086] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A shaping circuit, characterized in that, The shaping circuit has an input port (IN), an output port (OUT), a first power supply port (VDDPST18), a second power supply port (VDDPST18L), and a third power supply port (VDDPST33). The shaping circuit includes a first NMOS transistor (MN2), a second NMOS transistor (MN3), a switching unit (100), and a control unit (200). The drain of the first NMOS transistor (MN2) and the gate of the second NMOS transistor (MN3) are connected to the input port (IN); the gate of the first NMOS transistor (MN2) and the drain of the second NMOS transistor (MN3) are connected to the first power supply port (VDDPST18); the source of the first NMOS transistor (MN2) and the source of the second NMOS transistor (MN3) are connected to the output port (OUT). The first end of the switching unit (100) is connected to the input port (IN), the second end of the switching unit (100) is connected to the control unit (200), the third end of the switching unit (200) is connected to the third power port (VDDPST33), and the fourth end of the switching unit (200) is connected to the output port (OUT). The control unit (200) is also connected to the input port (IN), the first power port (VDDPST18), the second power port (VDDPST18L) and the third power port (VDDPST33), respectively. When the shaping circuit is in transmission mode, the first terminal and the fourth terminal of the switching unit (100) are in a conducting state, and the voltage amplitude of the output signal of the output port (OUT) is the same as the voltage amplitude of the input signal of the input port.

2. The shaping circuit according to claim 1, characterized in that, When the shaping circuit is in shaping mode, the first terminal and the fourth terminal of the switching unit (100) are in an open state, and the voltage amplitude of the output signal of the output port (OUT) is different from the voltage amplitude of the input signal of the input port.

3. The shaping circuit according to claim 2, characterized in that, The control unit (200) includes a level selection unit (210) and a third NMOS transistor (MN1). The level selection unit (210) is connected to the input port (IN), the second terminal of the switch unit (100), the first power port (VDDPST18), the second power port (VDDPST18L) and the third power port (VDDPST33), respectively. The drain of the third NMOS transistor (MN1) is connected to the second terminal of the switching unit (100); the source of the third NMOS transistor (MN1) is connected to the second power supply port (VDDPST18L); and the gate of the third NMOS transistor (MN1) is connected to the first power supply port (VDDPST18). When the shaping circuit is in shaping mode, the level selection unit (210) outputs a first control signal to the switching unit (100) so that the first terminal and the fourth terminal of the switching unit (100) are in an open state. When the shaping circuit is in transmission mode, the third NMOS transistor (MN1) outputs a second control signal to the switching unit (100), so that the first terminal of the switching unit and the fourth terminal of the switching unit (100) are in a conducting state.

4. The shaping circuit according to claim 3, characterized in that, The level selection unit (210) includes: a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), and a fourth PMOS transistor (MP4); the source terminal of the first PMOS transistor (MP1) and the gate terminal of the second PMOS transistor (MP2) are connected to the input port (IN); the gate terminal of the first PMOS transistor (MP1) and the source terminal of the second PMOS transistor (MP2) are connected to the first power supply port (VDDPST18); the drain terminal of the first PMOS transistor (MP1) and the drain terminal of the second PMOS transistor (MP2) are connected to the source terminal of the third PMOS transistor (MP3); and the gate terminal of the third PMOS transistor (MP3) is connected to the first power supply port (VDDPST18). The source port (VDDPST18) is connected, the drain of the third PMOS transistor (MP3) is connected to the second terminal of the switching unit (100); the gate of the fourth PMOS transistor (MP4) is connected to the input port (IN), the source of the fourth PMOS transistor (MP4) is connected to the second power supply port (VDDPST18L), and the drain of the fourth PMOS transistor (MP4) is connected to the second terminal of the switching unit (100); the substrates of the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS transistor (MP4) are all connected to the third power supply port (VDDPST33).

5. The shaping circuit according to claim 4, characterized in that, The level selection unit (210) further includes a fourth NMOS transistor (MN0), the gate of which is connected to the source of the third PMOS transistor (MP3), and the drain and source of the fourth NMOS transistor (MN0) are connected to the second power supply port (VDDPST18L).

6. The shaping circuit according to claim 3, characterized in that, The switching unit (100) includes a switching transistor (MP5), which is a PMOS transistor; The source terminal of the switching transistor (MP5) is connected to the input port (IN), the gate terminal of the switching transistor (MP5) is connected to the control unit (200), the substrate terminal of the switching transistor (MP5) is connected to the third power supply port (VDDPST33), and the drain terminal of the switching transistor (MP5) is connected to the output port (OUT).

7. The shaping circuit according to claim 6, characterized in that, When the shaping circuit is in shaping mode, the level selection unit (210) outputs a high-level signal to the gate terminal of the switching transistor (MP5), the third NMOS transistor (MN1) is in the off state, and the switching transistor (MP5) is in the off state. When the shaping circuit is in transmission mode, the third NMOS transistor (MN1) outputs a low-level signal to the gate terminal of the switching transistor (MP5), the level selection unit (210) is not connected to the gate terminal of the switching transistor (MP5), and the switching transistor (MP5) is in the on state.

8. The shaping circuit according to any one of claims 1-7, characterized in that, When the shaping circuit is in shaping mode, the voltage of the first power port (VDDPST18) and the voltage of the second power port (VDDPST18L) are both half the voltage amplitude of the input signal of the input port (IN), the voltage of the third power port (VDDPST33) is the same as the voltage amplitude of the input signal of the input port (IN), and the voltage amplitude of the input signal of the input port (IN) is 3.3 volts.

9. The shaping circuit according to any one of claims 1-7, characterized in that, When the shaping circuit is in transmission mode, the voltage of the first power port (VDDPST18) and the voltage of the third power port (VDDPST33) are the same as the voltage amplitude of the input signal of the input port (IN), the voltage amplitude of the input signal of the input port (IN) is 1.8 volts, and the voltage of the second power port (VDDPST18L) is 0 volts.

10. An Ethernet device, characterized in that, Includes the shaping circuit as described in any one of claims 1-9.

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