Digital control circuit based on fast comparator and method of use

Abstract

The application discloses a kind of digital control circuit based on fast comparator and use method, belong to integrated circuit technical field.It includes polling control unit, its output channel selection signal;Reference generating unit, according to preselected reference configuration mode and initial digital reference reference corresponding to DAC channel selection signal, configure intermediate digital reference reference, and dynamically adjust intermediate digital reference reference, obtain final digital reference reference;Analog comparator of built-in digital-to-analog converter, it compares analog reference voltage or external contrast voltage corresponding to VIN channel selection signal with the analog voltage to be measured corresponding to VIP channel selection signal, and outputs level signal.The technical scheme of the application can switch reference operating mode by software, without changing hardware, adapting to dynamic monitoring scene, and it can dynamically adjust intermediate digital reference, improve voltage determination anti-interference ability, and support VIP and VIN / DATA two comparisons, with higher configuration flexibility.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a digital control circuit based on a fast comparator and its usage method. Background Technology

[0002] In scenarios involving chip power management, sensor monitoring, and low-power wake-up, there is a strong demand for real-time monitoring of multi-channel voltage. Traditional solutions often rely on software-controlled ADCs (analog-to-digital converters) for polling or fixed-threshold comparators, which suffers from problems such as excessive software intervention, high power consumption, fixed thresholds, poor anti-interference, and inflexible configuration, making it difficult to meet the monitoring requirements of low power consumption, high reliability, and adaptability to multiple scenarios.

[0003] Current mainstream multi-channel comparison monitoring schemes adopt time-division multiplexing polling and fixed reference threshold architectures: hardware polls channels in a fixed order, using a fixed voltage as the comparison reference, and the output result can be used for wake-up. However, this scheme only supports fixed thresholds and fixed hysteresis, lacks hardware-configurable filtering, has a single comparison mode, and fixed output configuration. It still requires a lot of software involvement, resulting in insufficient robustness and flexibility. Existing patented solutions include: a fast comparator, a mixed-signal circuit, and an on-board controller. One of these discloses an on-board fast comparator circuit that achieves voltage comparison through a fixed reference source and relies on an external controller to complete the result processing. Another is a comparator control circuit that discloses a configurable comparator circuit, but it still requires software to configure the threshold, and the hysteresis and filtering functions are not implemented with hardware-based autonomous control. These patented solutions do not solve the problems of software dependence, insufficient configuration flexibility, and poor real-time performance. Summary of the Invention

[0004] Existing technologies suffer from limitations such as a single reference mode, support only fixed thresholds, lack of support for dynamic stepped references and fixed hysteresis, inability to dynamically adjust, and weak anti-interference capabilities. To address these issues, this application provides a digital control circuit and its usage method based on a fast comparator.

[0005] To achieve the above objectives, the first technical solution adopted in this application is: a digital control circuit based on a fast comparator, comprising: a polling control unit that outputs a channel selection signal, wherein the channel selection signal is composed of either a VIP (Voltage Input Positive) channel selection signal or a VIN (Voltage Input Negative) channel selection signal or a DAC (digital-to-analog converter) channel selection signal; a reference generation unit that configures an intermediate digital reference reference according to a pre-selected reference configuration mode and an initial digital reference reference corresponding to the DAC channel selection signal, and dynamically adjusts the intermediate digital reference reference based on the hysteresis parameter corresponding to the DAC channel selection signal and the historical comparison results output by the analog comparator, to obtain and output a final digital reference reference with hysteresis compensation, wherein the pre-selected reference configuration mode supports at least two reference configuration modes; and an analog comparator with a built-in digital-to-analog converter that converts the final digital reference reference into an analog reference voltage through the digital-to-analog converter, and compares the analog reference voltage or the external comparison voltage corresponding to the VIN channel selection signal with the analog voltage to be measured corresponding to the VIP channel selection signal, and outputs a level signal.

[0006] The second technical solution adopted in this application is: a method for using a digital control circuit based on a fast comparator, comprising: a channel selection signal output step, wherein the control unit outputs a channel selection signal, wherein the channel selection signal is composed of a VIP channel selection signal, combined with either a VIN channel selection signal or a DAC channel selection signal; a reference generation step, wherein the reference generation unit configures an intermediate digital reference reference according to a pre-selected reference configuration mode and an initial digital reference reference corresponding to the DAC channel selection signal, and dynamically adjusts the intermediate digital reference reference based on the hysteresis parameter corresponding to the DAC channel selection signal and the historical comparison results output by the analog comparator, thereby obtaining and outputting a final digital reference reference with hysteresis compensation, wherein the pre-selected reference configuration mode supports at least two reference configuration modes; and a comparison step, wherein the analog comparator with a built-in digital-to-analog converter converts the final digital reference reference into an analog reference voltage through the digital-to-analog converter, and compares the analog reference voltage or the external comparison voltage corresponding to the VIN channel selection signal with the analog voltage to be measured corresponding to the VIP channel selection signal, and outputs a level signal.

[0007] The beneficial effects of the technical solution of this application are as follows: The technical solution of this application can match the initial digital reference of the corresponding channel according to the channel selection signal, generate an intermediate digital reference by combining multiple pre-selected reference configuration modes, and switch the reference working mode by software without modifying the hardware, which is suitable for dynamic monitoring scenarios. At the same time, it can combine the channel-specific hysteresis parameters and the historical comparison results of the comparator to dynamically adjust the intermediate digital reference and output the final digital reference after hysteresis compensation, thereby improving the anti-interference capability of voltage judgment. Moreover, it supports both VIP and VIN / DATA comparison, which makes the configuration more flexible. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a specific embodiment of a digital control circuit based on a fast comparator according to this application; Figure 2 This is a schematic diagram of an analog comparator based on a fast comparator digital control circuit according to this application; Figure 3 This is a schematic diagram of the reference generation unit outputting the final digital reference of a digital control circuit based on a fast comparator according to this application; Figure 4 This is a flowchart illustrating a specific implementation of a digital control circuit based on a fast comparator according to this application.

[0010] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0011] The preferred embodiments of this application will now be described in detail with reference to the accompanying drawings, so that the advantages and features of this application can be more easily understood by those skilled in the art, thereby providing a clearer and more definite definition of the scope of protection of this application.

[0012] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0013] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. The specific embodiments described below can be combined with each other to form new embodiments. The same or similar ideas or processes described in one embodiment may not be repeated in other embodiments.

[0014] like Figure 1 As shown, in one specific embodiment of a digital control circuit based on a fast comparator in this application, the digital control circuit based on a fast comparator includes: a polling control unit 1, which outputs a channel selection signal.

[0015] In one specific embodiment of this application, the polling control unit 1 can be used as the hardware scheduling core. That is, the polling control unit 1 can be implemented using a hardware state machine, without the need for continuous software involvement. It can work automatically according to a preset process simply by configuring the registers in advance.

[0016] In one specific embodiment of this application, the polling control unit 1 can be an autonomous polling state machine.

[0017] Therefore, the hardware autonomous polling state machine is designed to be a hardware state machine that can autonomously schedule the entire process without continuous CPU intervention. It has low software dependence, lower power consumption, and faster response.

[0018] In one specific embodiment of this application, the working state of the polling control unit 1 can be divided into four stages: IDLE (idle), DAC conversion, CMP (Compare) comparison, and OUT output.

[0019] As an example, the trigger signal for IDLE to enter DAC conversion is a compare start trigger signal, which polls control unit 1. It can be started by external trigger or internal timer periodically, that is, it can be configured to be triggered by external trigger or internal timer periodically to achieve on-demand or timed start.

[0020] As an example, the DAC conversion to CMP comparison or the CMP comparison to OUT output is determined by the inherent timing of the DAC and comparator. As long as the setup time and conversion time requirements are met, fast comparison can be achieved.

[0021] As an example, the OUT output can be used for DAC conversion or for IDLE idle mode. This allows for loop and end control, enabling users to choose to continue to the next round of comparison or terminate the comparison. It supports direct software termination, automatic termination after a certain number of comparisons, or termination triggered by an external signal.

[0022] In one specific embodiment of this application, the channel selection signal may consist of either a VIP channel selection signal, or either a VIN channel selection signal or a DAC channel selection signal.

[0023] In one specific embodiment of this application, the polling control unit 1 can poll each channel of either the VIP channel group or the VIN channel group or the DAC channel group at a preset time interval and output a channel selection signal.

[0024] As an example, during the polling comparison process, the selection signal of each channel is switched to the next valid channel in sequence according to the configured time interval.

[0025] As an example, each channel can be configured independently.

[0026] As an example, the valid channels are configured by software, and the valid channels corresponding to VIP, VIN, and DAC can be configured independently.

[0027] As an example, you can flexibly choose to compare the VIP with the external VIN or with the internal DAC reference.

[0028] As an example, channels can establish one-to-one, one-to-many, many-to-one, and many-to-many correspondences.

[0029] As an example, the number of valid VIP channels n p With the number of valid VIN channels n n The relationship can be: n p =n n =1, or n p =1, n n >1, or n p >1, n n =1, or n p >1, n n >1.

[0030] As yet another example, the number of valid VIP channels n p With the number of effective DAC channels n d The relationship can be: np =n d =1, or n p =1, n d >1, or n p >1, n d =1, or n p >1, n d >1.

[0031] Therefore, it supports two comparison modes: VIP and VIN, and VIP and DATA, and can perform one-to-one, one-to-many, many-to-one, and many-to-many matching to achieve multiple matching relationships.

[0032] As an example, to ensure accurate and effective comparisons, the preset time interval is greater than the total duration of any complete comparison round. That is, the next set of channel comparisons can only begin after one set of channel comparisons has been completed.

[0033] like Figure 1 As shown, in a specific embodiment of a digital control circuit based on a fast comparator in this application, the digital control circuit based on a fast comparator includes: a reference generation unit 2, which configures an intermediate digital reference reference according to a pre-selected reference configuration mode and an initial digital reference reference corresponding to a DAC channel selection signal, and dynamically adjusts the intermediate digital reference reference based on the hysteresis parameter corresponding to the DAC channel selection signal and the historical comparison results output by the analog comparator, to obtain and output a final digital reference reference with hysteresis compensation.

[0034] In one specific embodiment of this application, the pre-selected baseline configuration mode can support at least two baseline configuration modes.

[0035] In one specific embodiment of this application, such as Figure 3 As shown, the pre-selected baseline configuration mode supports three modes: step-up mode, step-down mode, and constant value mode.

[0036] As an example, the range of the step-up pattern can be [DATA_1, DATA_1+RAMP_UP]. DATA_1+RAMP_UP can be the upper limit of the step-up pattern.

[0037] As an example, the range of the step descent pattern can be [DATA_1 - RAMP_DOWN, DATA_1]. DATA_1 - RAMP_DOWN can be the lower limit of the step descent pattern.

[0038] As an example, the constant value mode can be a constant value, that is, an initial digital reference base DATA_1.

[0039] In one specific embodiment of this application, such as Figure 3As shown, the step-up mode and step-down mode are set with step size and change frequency.

[0040] In one specific embodiment of this application, such as Figure 3 As shown, the reference generation unit 2, in both the step-up mode and the step-down mode, takes the initial digital reference reference as the starting point and configures the intermediate digital reference reference according to the step size and change frequency corresponding to the pre-selected reference configuration mode.

[0041] As an example, the step size and frequency of change for both the step-up and step-down modes can be configured by software.

[0042] As an example, in the step-up mode, starting from the initial digital reference DATA_1, the step size is accumulated over time according to the software-configured step size. The rate of change is controlled by the change frequency. The increase stops after reaching the upper limit DATA_1+RAMP_UP, and finally the intermediate digital reference is obtained.

[0043] As an example, in the step-down mode, starting from the initial digital reference DATA_1, the step size is gradually decreased over time according to the software-configured step size. The rate of change is controlled by the change frequency. The change stops after reaching the lower limit DATA_1-RAMP_DOWN, and finally the intermediate digital reference is obtained.

[0044] In one specific embodiment of this application, such as Figure 3 As shown, reference generation unit 2, in constant value mode, configures the initial digital reference reference as an intermediate digital reference reference.

[0045] Therefore, it supports three benchmarks: constant, step-up, and step-down, and the step size and frequency of change can be configured by software to adapt to dynamic monitoring scenarios.

[0046] In one specific embodiment of this application, such as Figure 3 As shown, reference generation unit 2 determines the difference between the intermediate digital reference reference and the hysteresis parameter as the final digital reference reference when the historical comparison result shows that the historical VIP channel selection signal is greater than the historical analog reference voltage.

[0047] As an example, when the historical comparison result is that the historical VIP channel selection signal is greater than the historical analog reference voltage, that is, when the comparison result is 1, the hysteresis DELTA_L is subtracted from DATA_2 as the reference benchmark, and 0 is output only when VIP is less than DATA_2-DELTA_L.

[0048] In one specific embodiment of this application, such as Figure 3As shown, reference generation unit 2 determines the sum of intermediate digital reference and hysteresis parameter as the final digital reference when the historical comparison result shows that the historical VIP channel selection signal is less than the historical analog reference voltage.

[0049] As an example, when the historical comparison result is that the historical VIP channel selection signal is less than the historical analog reference voltage, that is, when the comparison result is 0, a hysteresis amount DELTA_H is added to DATA_2 as a reference benchmark, and 1 is output only when VIP is greater than DATA_2+DELTA_H.

[0050] As an example, DELTA_H and DELTA_L are software configurable.

[0051] In one specific embodiment of this application, the reference generation unit, when configuring hysteresis parameters, performs single-boundary monitoring or dual-boundary monitoring on the final digital reference reference through an upper limit digital reference reference and a lower limit digital reference reference.

[0052] As an example, the final digital reference baseline is either the upper limit value MAX or the lower limit value MIN. This structure can be applied to boundary monitoring. Single boundary monitoring can be achieved by configuring hysteresis, i.e., at least one of DELTA_H and DELTA_L is 0, or dual boundary monitoring, i.e., neither DELTA_H nor DELTA_L is 0.

[0053] Therefore, a dynamic hysteresis mechanism can be configured, integrating dynamic correction of hysteresis threshold and single / double boundary monitoring, and hysteresis control can be implemented at the hardware level.

[0054] like Figure 1 As shown, in a specific embodiment of a digital control circuit based on a fast comparator in this application, the digital control circuit based on a fast comparator includes: an analog comparator 3 with a built-in digital-to-analog converter, which converts the final digital reference into an analog reference voltage through the digital-to-analog converter, compares the analog reference voltage or the external comparison voltage corresponding to the VIN channel selection signal with the analog voltage to be measured corresponding to the VIP channel selection signal, and outputs a level signal.

[0055] As an example, VIP and VIN can come from an externally simulated PAD.

[0056] As an example, the channel selection signals VIP_SEL, VIN_SEL, DAC_SEL, and the enable signals for the DAC and analog comparator 3 can all be generated by the polling control unit 1.

[0057] As an example, the input data DATA_REF of the DAC is a digital reference, which can be derived from reference generation unit 2.

[0058] As an example, the bit width of DATA_REF can be determined by the DAC.

[0059] As examples, VIP_SEL, VIN_SEL, and DAC_SEL can all be multi-bit one-hot codes, and the bit width can be determined by the number of channels n.

[0060] As an example, at any given time, only one channel can be selected.

[0061] As examples, VIP_SEL, VIN_SEL, and DAC_SEL can be configured with different channels independently, and the reverse input selection logic requires that VIN_SEL and DAC_SEL cannot be selected at the same time.

[0062] In one specific embodiment of this application, such as Figure 2 As shown, when polling to the VIP channel and VIN channel, the inverting input of analog comparator 3 is connected to the external channel voltage as the external comparison voltage.

[0063] As an example, when a channel is selected by VIN_SEL, all channels of DAC_SEL are set to 0, and the inverting input of analog comparator 3 can be connected to an external channel voltage as an analog reference.

[0064] In one specific embodiment of this application, such as Figure 2 As shown, when polling the VIP channel and DAC channel, the final digital reference output by the reference generation unit 2 is converted into an analog reference by the DAC and connected to the inverting input of the analog comparator 3.

[0065] As an example, when a certain channel is selected by DAC_SEL, all VIN_SEL values ​​are set to 0. The final digital reference output by the reference generation unit 2 is converted into an analog reference by the DAC and then connected to the inverting input of the analog comparator 3.

[0066] In one specific embodiment of this application, analog comparator 3 can compare VIP and a reference voltage, and output a digital logic level of 1 or 0, respectively, indicating that the VIP voltage is greater than or less than the reference voltage. In one specific embodiment of this application, the digital control circuit based on the fast comparator may further include: a low-pass filter unit 4, which performs low-pass filtering on the level signal to obtain a filtered level signal.

[0067] As an example, the low-pass filter unit 4 can be used to filter out high-frequency noise from the comparator output.

[0068] As an example, the cutoff frequencies for 0-to-1 switching and 1-to-0 switching in low-pass filter unit 4 can be flexibly configured via software.

[0069] Therefore, a low-pass filter unit and an independent filter unit can be configured, supporting independent configuration of rising and falling edge cutoff frequencies, suppressing signal glitches and random jitter, and improving the stability and accuracy of the comparison results with the reference standard.

[0070] In one specific embodiment of this application, the digital control circuit based on the fast comparator may further include: an output processing unit 5, which performs polarity configuration on the level signal or the filtered level signal, outputs the polarity-configured level signal to the outside, and outputs an interrupt request signal when a level transition occurs.

[0071] As an example, output processing unit 5 can selectively acquire the unfiltered raw comparison result or the comparison result after low-pass filtering for secondary post-processing.

[0072] As an example, for each positive input channel selected by VIP_SEL, the output processing unit 5 can be set with an independent and configurable output polarity, and the output logic can be flexibly defined.

[0073] As an example, the output signal can be connected to an external digital PAD, other peripherals, or used as an interrupt signal source.

[0074] As examples, interrupt types can include output rising edge changes, output falling edge changes, output level changes, and new round of comparison service requests.

[0075] Therefore, the flexible output processing unit can select raw / filtered results, independently configure the polarity of the channels, and support multiple types of interrupt wake-up.

[0076] It should be noted that all the configurable functions mentioned above can be either set to default parameters via hardware or flexibly modified via software register configuration. Once configured, the comparator polling operation requires no continuous software intervention and can be driven by a single clock signal.

[0077] Therefore, this application can be widely used in low-power wake-up scenarios for chips. Under the condition that the module does not lose power and the clock is supplied normally, the circuit can automatically perform polling comparison, and the comparison result or interrupt signal can be used as a wake-up source to realize real-time monitoring and fast wake-up in low-power mode.

[0078] The beneficial effects of the technical solution of this application are as follows: The technical solution of this application can match the initial digital reference of the corresponding channel according to the channel selection signal, generate an intermediate digital reference by combining multiple pre-selected reference configuration modes, and switch the reference working mode by software without modifying the hardware, which is suitable for dynamic monitoring scenarios. At the same time, it can combine the channel-specific hysteresis parameters and the historical comparison results of the comparator to dynamically adjust the intermediate digital reference and output the final digital reference after hysteresis compensation, thereby improving the anti-interference capability of voltage judgment. Moreover, it supports both VIP and VIN / DATA comparison, which makes the configuration more flexible.

[0079] Figure 4 This is a schematic diagram of a specific implementation of a digital control circuit based on a fast comparator according to this application.

[0080] exist Figure 4 In the specific embodiment shown, the method of using the digital control circuit based on the fast comparator may include: a channel selection signal output step S401, in which the polling control unit outputs a channel selection signal, wherein the channel selection signal consists of a VIP channel selection signal, combined with either a VIN channel selection signal or a DAC channel selection signal; a reference generation step S402, in which the reference generation unit configures an intermediate digital reference reference according to a pre-selected reference configuration mode and an initial digital reference reference corresponding to the DAC channel selection signal, and dynamically adjusts the intermediate digital reference reference based on the hysteresis parameter corresponding to the DAC channel selection signal and the historical comparison results output by the analog comparator, to obtain and output a final digital reference reference with hysteresis compensation, wherein the pre-selected reference configuration mode supports at least two reference configuration modes; and a comparison step S403, in which the analog comparator with a built-in digital-to-analog converter converts the final digital reference reference into an analog reference voltage through the digital-to-analog converter, and compares the analog reference voltage or the external comparison voltage corresponding to the VIN channel selection signal with the analog voltage to be measured corresponding to the VIP channel selection signal, and outputs a level signal.

[0081] The method of using the fast comparator-based digital control circuit provided in this application can be executed by the fast comparator-based digital control circuit described in any of the above embodiments. The implementation principle and technical effect are similar, and will not be repeated here.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A digital control circuit based on a fast comparator, characterized in that, include: The polling control unit outputs a channel selection signal, wherein the channel selection signal is composed of either a VIP channel selection signal or a VIN channel selection signal or a DAC channel selection signal. The reference generation unit configures an intermediate digital reference reference according to a pre-selected reference configuration mode and an initial digital reference reference corresponding to the DAC channel selection signal, and dynamically adjusts the intermediate digital reference reference based on the hysteresis parameter corresponding to the DAC channel selection signal and the historical comparison results output by the analog comparator, to obtain and output a final digital reference reference with hysteresis compensation. The pre-selected reference configuration mode supports at least two reference configuration modes. An analog comparator with a built-in digital-to-analog converter converts the final digital reference into an analog reference voltage through the digital-to-analog converter, compares the analog reference voltage or the external comparison voltage corresponding to the VIN channel selection signal with the analog voltage to be measured corresponding to the VIP channel selection signal, and outputs a level signal.

2. The digital control circuit based on a fast comparator according to claim 1, characterized in that, The polling control unit polls each channel in either the VIP channel group or the VIN channel group or the DAC channel group at a preset time interval and outputs a channel selection signal. Each channel is set independently, and the preset time interval is greater than the total duration of any complete round of comparison.

3. The digital control circuit based on a fast comparator according to claim 2, characterized in that, When polling the VIP channel and VIN channel, the inverting input of the analog comparator is connected to an external channel voltage as an external comparison voltage; When polling the VIP channel and DAC channel, the final digital reference reference output by the reference generation unit is converted into an analog reference reference by the DAC and connected to the inverting input of the analog comparator.

4. The digital control circuit based on a fast comparator according to claim 2, characterized in that, The polling control unit initiates polling periodically via external triggering or an internal timer, and the polling control unit is an autonomous polling state machine.

5. The digital control circuit based on a fast comparator according to claim 1, characterized in that, The pre-selected baseline configuration mode supports three modes: step-up mode, step-down mode, and constant value mode. The step-up mode and the step-down mode are set with step size and change frequency. The reference generation unit, in the step-up mode and the step-down mode, takes the initial digital reference reference as the starting point and configures the intermediate digital reference reference according to the step size and change frequency corresponding to the pre-selected reference configuration mode. The reference generation unit configures the initial digital reference reference as an intermediate digital reference reference in the constant value mode.

6. The digital control circuit based on a fast comparator according to claim 5, characterized in that, The reference generation unit determines the difference between the intermediate digital reference reference and the hysteresis parameter as the final digital reference reference when the historical comparison result shows that the historical VIP channel selection signal is greater than the historical analog reference voltage. The reference generation unit determines the sum of the intermediate digital reference reference and the hysteresis parameter as the final digital reference reference when the historical comparison result shows that the historical VIP channel selection signal is less than the historical analog reference voltage.

7. The digital control circuit based on a fast comparator according to claim 6, characterized in that, The final digital reference benchmark is configured with an upper limit digital reference benchmark and a lower limit digital reference benchmark; The reference generation unit, when configuring the hysteresis parameter, performs single-boundary monitoring or dual-boundary monitoring on the final digital reference reference through the upper limit digital reference reference and the lower limit digital reference reference.

8. The method according to claim 1, characterized in that, The fast comparator-based digital control circuit also includes: A low-pass filter unit performs low-pass filtering on the level signal to obtain a filtered level signal.

9. The method according to claim 8, characterized in that, The fast comparator-based digital control circuit also includes: The output processing unit configures the polarity of the level signal or the filtered level signal, outputs the polarity-configured level signal, and outputs an interrupt request signal when a level transition occurs.

10. A method for using a digital control circuit based on a fast comparator, characterized in that, include: The channel selection signal output step involves polling the control unit to output a channel selection signal, wherein the channel selection signal consists of either a VIP channel selection signal or a VIN channel selection signal or a DAC channel selection signal. In the reference generation step, the reference generation unit configures an intermediate digital reference reference according to the pre-selected reference configuration mode and the initial digital reference reference corresponding to the DAC channel selection signal, and dynamically adjusts the intermediate digital reference reference based on the hysteresis parameter corresponding to the DAC channel selection signal and the historical comparison results output by the analog comparator, so as to obtain and output the final digital reference reference with hysteresis compensation. The pre-selected reference configuration mode supports at least two reference configuration modes. In the comparison step, the analog comparator with the built-in digital-to-analog converter converts the final digital reference into an analog reference voltage through the digital-to-analog converter, and compares the analog reference voltage or the external comparison voltage corresponding to the VIN channel selection signal with the analog voltage to be measured corresponding to the VIP channel selection signal, and outputs a level signal.

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