System and method for generating fine-tuned pulse width modulation signals

Abstract

A fine control pulse width modulation signal generator includes a preliminary pulse width modulation signal generator configured to generate a base pulse width modulation signal from a clock signal, a slew rate controller configured to modify edges of the base pulse width modulation signal, and a comparator having a first input that accepts an output of the slew rate controller and a second input that accepts a comparison threshold, the comparator configured to output a fine control pulse width modulation signal based on a comparison between the first input and the second input. The fine control pulse width modulation signal can be used by a switching power supply to fine control an output voltage of the power supply. Methods are also described.

Description

[0001] Cross-reference with related applications This disclosure is a non-provisional content of, and claims to benefit from, U.S. Provisional Application No. 63 / 783571, filed April 4, 2025, entitled “PULSE WIDTH MODULATION SIGNAL GENERATION USING FIELDPROGRAMMABLE GATE ARRAYS AND DIGITAL-TO-ANALOG CONVERTERS FOR 1MHZ”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to a signal generation system, and more particularly to a system for generating pulse width modulated signals with user-specified quality. Background Technology

[0003] Modern power supply modules allow users to control the output signal voltage level. In a direct current (DC) power supply, the final output signal is typically a signal with a constant DC output voltage. It is important that the output voltage is stable, meaning it remains relatively constant over time within small tolerances. It is also crucial that the user can precisely control the power supply's output voltage level to meet the desired application.

[0004] Power supplies use different types of circuits to generate output voltage signals depending on their design. Discrete linear regulators can be used to generate signals that meet the aforementioned output tolerance and fine control requirements. However, especially when used in larger power supplies, discrete linear regulators may be too large to be physically installed under certain design constraints. When small physical size is critical, switching power supplies are typically used. In switching power supplies (such as buck converters), pulse width modulation (PWM) signals are typically used to control solid-state switches, such as metal-oxide-semiconductor field-effect transistor (MOSFET) switches in voltage generation circuits. MOSFET switches are very small. When the PWM signal controlling the MOSFET has a low duty cycle, the MOSFET switch is off for a longer period than it is on, resulting in a relatively low output voltage from the voltage generation circuit. Conversely, when the PWM signal has a higher duty cycle, the output voltage of the voltage generation circuit will also be higher.

[0005] When using Field Programmable Gate Arrays (FPGAs) in circuit design, circuit design choices may be limited by the constraints of the FPGA's operational architecture. For example, a Phase-Locked Loop (PLL) can be implemented in an FPGA to generate a clock signal at a higher frequency than the inherent frequency at which the FPGA operates. However, the limitations of the FPGA architecture may prevent the PWM generator from using such a PLL to precisely control the PWM generator at these higher frequencies.

[0006] Using a standard PWM generator in an FPGA presents the challenge of precisely controlling the PWM duty cycle. As discussed above, a crucial factor in power supply design is allowing users to finely control the final output voltage of the power supply by adjusting the duty cycle of the PWM signal. As described, modifying the PWM signal's duty cycle will cause the switching power supply to increase or decrease its final output voltage.

[0007] As mentioned above, FPGA architectures typically have a maximum clock rate at which they can operate without errors. For example, the maximum master clock or master clock frequency of an FPGA is approximately 100 MHz, which translates to a clock cycle of 10 ns. If the frequency of the desired PWM signal generated by the FPGA is approximately 1 MHz, this translates to a clock cycle of 1000 ns. Recalling the above, fine control over the desired output voltage is crucial. Using the clock cycle above as an example, when the FPGA architecture limits the minimum variation of the PWM to 10 ns, generating the PWM by modulating a 1000 ns clock cycle results in only a 1% variation in the PWM, which is relatively large. This limitation on the clock signal resolution caused by the maximum clock speed in the FPGA directly restricts the user's ability to precisely control the duty cycle of the PWM implemented using the FPGA. Furthermore, the inability to finely control the PWM duty cycle limits the amount of fine control the user can achieve at a given final output voltage from the power supply. Attached Figure Description

[0008] Figure 1 This is a functional block diagram of a pulse width modulation (PWM) signal generator according to an embodiment of the present disclosure.

[0009] Figure 2 This is a description of embodiments based on the present disclosure. Figure 1 The graph shows the output voltage curves of various parts of the PWM signal generator.

[0010] Figure 3A According to the embodiments Figure 1 An example of a PWM signal generator with a slew rate controller element.

[0011] Figure 3B According to the embodiments Figure 1 Another example of a PWM signal generator is a slew rate controller element.

[0012] Figure 3C According to the embodiments Figure 1 Another example of a PWM signal generator is a slew rate controller element.

[0013] Figure 4 In some embodiments, in Figure 1A schematic block diagram of the comparator used in the duty cycle controller component of a PWM signal generator.

[0014] Figure 5 This is a schematic block diagram of an example voltage generator according to an embodiment, the example voltage generator including... Figure 1 Some or all of the components of a PWM signal generator.

[0015] Figure 6 This is a flowchart illustrating an example operation for generating a controllable PWM signal according to an embodiment. Detailed Implementation

[0016] Embodiments of this disclosure include integrating field-programmable gate array (FPGA) control with a digital-to-analog converter (DAC) to generate pulse-width modulation (PWM) signals with resolution below 1 ns at a frequency of 1 MHz. Other embodiments include finely tunable PWM signal generators from clock generators with fine control of less than 1%.

[0017] This disclosure relates to generating finely tunable PWM control signals. PWM signals can be used to control MOSFETs in synchronous switching power supplies, such as buck converters. In embodiments, the duty cycle of the PWM signal is directly related to the output of the buck converter. Therefore, higher resolution in the PWM control signal allows for more precise control of the buck converter's output.

[0018] In some embodiments, the FPGA generates a master clock at 100MHz or 125MHz. Due to the FPGA architecture, clock signals operating at faster rates may encounter propagation delay issues. For example, if the FPGA generates a 100MHz clock but is limited to a variability of only 10ns in its clock signal, the overall resolution of the clock signal generated by the FPGA is limited to 1% of the clock variability in the clock signal.

[0019] To achieve finer resolution, this disclosure relates to modifying the generated PWM signal (which can also be generated by an FPGA) to use additional circuitry to produce a finely controllable PWM signal. The FPGA generates the PWM signal from the master clock, which will be described in detail below. (Refer to...) Figure 1This describes a PWM generator 100, which includes a PWM signal generator 10, a slew rate controller 20, and a duty cycle controller 30. As described in further detail below, the PWM signal generator 10 accepts a master clock signal, such as a 100MHz clock signal generated by an FPGA, and outputs a PWM signal with a predetermined duty cycle and adjustable accuracy of 1%. Other inputs to the PWM signal generator 10 include the desired PWM frequency and a basic or total duty cycle. The PWM signal output from the PWM signal generator 10 can be generated from the master clock signal based on an overall design such as the FPGA master clock. In one embodiment, the PWM signal generator 10 generates a 25MHz PWM signal from a 100MHz master clock signal. Although the basic duty cycle is limited by the master clock signal, the output of the PWM signal generator 10 can be referred to as a PWM signal with a selectable basic duty cycle.

[0020] The slew rate controller 20 includes circuitry or circuitry functions that control one of the edges of the PWM signal output from the PWM signal generator 10. The function of the slew rate controller 20 can be controlled via control lines, such as... Figure 1 As shown. Reference Figure 2 The original master clock signal is as described in 210. In this embodiment, the master clock signal 210 has a frequency of 100MHz and can be generated by the FPGA. In other embodiments, the master clock signal can be generated by another clock source. Regardless of how it is generated, the master clock signal 210 can be presented to... Figure 1 Example clock signal for PWM signal generator 10.

[0021] The PWM signal generator 10 uses the master clock signal 210 to generate a PWM signal 220 with a desired frequency. In the illustrated embodiment, the PWM signal 220 has a frequency of 25 MHz and a duty cycle of 50%. Compared to the master clock signal 210, the PWM signal 220 remains high for two full cycles of the master clock signal and then transitions to low for another two cycles of the master clock signal.

[0022] Return to reference Figure 1 The slew rate controller 20 uses various circuits to modify the PWM signal 220. Ultimately, as described below, modifying the PWM signal 220 provides (compared to what is available from the PWM signal generator 10) a finer ability to tune the desired PWM duty cycle, since the PWM signal generator is limited to 1% accuracy. Return to Reference Figure 2 slew rate controller 20 ( Figure 1 The example output is described as a slew rate PWM signal 230. Figure 2The slew-down PWM signal 230 is compared with the PWM signal 220, and the difference between these signals is based on the difference between the falling edges of the two PWM signals. The original PWM signal 220 includes a falling edge 222, which falls immediately or very quickly between the high and low values ​​of the PWM signal 220. Referring to the slew-down PWM signal 230, the falling edge 232 takes a longer time to transition from the high value to the low value of the slew-down PWM signal 230. The rate of decrease of the PWM signal 230 is called the slew rate, which is the change in the output value of a signal (such as the slew-down PWM signal 230) from a high value to a low value. The falling edge portion 222 of the PWM signal 220 has a very fast or instantaneous slew rate, while the falling edge portion 232 of the slew-down PWM signal 230 has a lower slew rate. Typically, although not required, the slew rate of the falling edge 232 is controlled by the slew rate controller 20 (…). Figure 1 The control is configured to complete the high-to-low transition before the next rising edge of the PWM signal 220.

[0023] Depending on the embodiment, in the slew rate controller 20 ( Figure 1 Different circuits can be used within the circuit to control the slew rate of the falling edge 232 of the slew rate PWM signal 230. (See reference...) Figure 3A The slew rate controller 50 can be Figure 1 An example of a slew rate controller 20. The slew rate controller 50 includes a diode 52, which may be a Schottky diode, coupled to a capacitor 54 and a current sink, or a current generator 56. When switched on, the current generator 56 provides a path between the capacitor 54 coupled to the output of the slew rate controller 50 and a ground reference.

[0024] The input to the slew rate controller 50 is the PWM signal generator 10. Figure 1 The output of ) is shown in the example below. Figure 2 As illustrated by PWM signal 220. The slew rate controller 50 causes the falling edge 232 of PWM signal 230 to fall more slowly than the falling edge 222 of PWM signal 220, or to have a lower slew rate. More specifically, when PWM signal 220 is in its high state, capacitor 54 is charged using the energy provided by the high-state signal. Then, when PWM signal 220 would otherwise immediately fall to its low state, as... Figure 2As explained, the slew rate controller 50 delays or slows down the transition time between the high and low states, thereby increasing the slew time and reducing the slew rate at the falling edge 232. In practice, when the PWM signal 220 input to the slew rate controller 50 transitions from high to low, the current generator 56 provides a path to the ground reference. Controlling the operation of the current generator 56 controls the rate at which the energy stored in the capacitor 54 is discharged to the ground reference. The diode 52, acting as a unidirectional device, prevents the energy stored in the capacitor 54 from being discharged back into the capacitor 54 through the diode. Instead, the capacitor 54 discharges at a controlled rate through the current generator 56 until it is fully discharged and the falling edge 232 of the slew rate PWM signal 230 reaches its low state. This controlled discharge of the capacitor 54... Figure 2 The following explanation is based on the falling edge or the slewing portion 232 of the PWM signal 230.

[0025] Return to reference Figure 3A The size of capacitor 54, the charging level of capacitor 54, and the discharge rate of current generator 56 control the slew rate of the falling edge 232 of the slew-dropping PWM signal 230. For example, increasing the rate at which current generator 56 draws current from capacitor 54 to ground reference will cause the falling edge 232 to drop from a high state to a low state more quickly, while decreasing the rate at which current generator 56 draws current to ground reference will cause the falling edge 232 to drop more slowly. Therefore, embodiments of this disclosure can control the slew rate of the PWM signal in real time by controlling the operation of current generator 56.

[0026] In addition to using a current generator 56 to control the slew rate (such as...) Figure 3A Besides the slew rate controller found in 50, other forms of slew rate control can also be used. For example, Figure 3B A slew rate controller 60 is shown, in which Figure 3A The current generator 56 has been replaced by a single resistor 66. The other circuit components of the slew rate controller 60 remain unchanged from the slew rate controller 50, and their functions will not be repeated for the sake of simplicity. Figure 3B In the slew rate controller 60, when the PWM signal 220 drops from its high state to its low state, energy is discharged from the capacitor 54 to the ground reference through the resistor 66. Figure 3B slew rate controller 60 and Figure 3AOne difference between the slew rate controller 50 and the other is that resistor 66 is static, meaning that the rate at which capacitor 54 discharges to ground reference depends on the resistor 66 and the resistor-capacitor (RC) network of capacitor 54. Although not explicitly stated, discharging a capacitor (such as capacitor 54) through a fixed RC network follows a non-linear path, where energy discharges faster after the PWM signal 220 transitions from high to low while capacitor 54 is being rapidly discharged, compared to a later portion of the discharge. Therefore, compared to… Figure 3A Compared to the 230 slew PWM signal, using Figure 3B The slew rate controller 60 and the fixed RC network will cause the lower edge portion 232 to have a curved or inverted J-shaped shape, in contrast, when using the slew rate controller 50 ( Figure 3A When the PWM signal 230 is applied, the shape of the lower edge 232 is relatively linear.

[0027] Figure 3C Another slew rate controller 70 is shown, which is similar to Figure 3B The slew rate controller 60, in addition to the slew rate controller 70, includes a controllable resistor 76. In this embodiment, the resistance of the controllable resistor 76 can be modified or changed during the slew-down portion when the PWM signal 220 transitions from high to low. This controllable resistor allows the system to control the rate at which the slew-down PWM signal 230 falls at its lower edge 232, thereby modifying the parameters of the RC network formed by the resistor 76 and the capacitor 54. Compared to the output of the slew rate controller 60, this modifies the shape of the discharge curve. Figure 3A Similar to the current generator 56 in the slew rate controller 50, resistor 76 can... Figure 3C The slew rate controller 70 is controlled in real time.

[0028] Although the illustrated embodiments of this disclosure have described modification of the falling edge of the PWM signal 220, the rising edge of the PWM signal 200 may be modified to control the overall output of a new PWM signal with finer control. In other embodiments, both the rising and falling edges of the PWM signal 220 may be modified.

[0029] Return to reference Figure 1 The output of the slew rate controller 20 is then passed to the duty cycle controller 30 to generate a final PWM signal with a controllable duty cycle. In some embodiments, the duty cycle controller 30 includes a comparator, such as... Figure 4 The comparator 90 is described. Comparator 90 includes a non-inverting input 92 and an inverting input 94. In the described embodiment, the non-inverting input 92 is coupled to a slew rate controller 20. Figure 1The inverting input 94 receives the threshold used by comparator 90, while the inverting input 94 receives the threshold value used by comparator 90. Modifying the threshold value for comparator 90 will cause the comparator's output to control the duty cycle of the new PWM signal, as shown by the reference. Figure 2 The threshold discussed is an example of duty cycle control coupled with duty cycle controller 30, such as... Figure 1 As explained.

[0030] Figure 2 This describes a new PWM signal 240, which in some embodiments reflects Figure 4 The output of comparator 90.

[0031] refer to Figure 4 By comparing the new PWM signal 240 with the original PWM signal 220, it can be seen that the duty cycle of the new PWM signal 240 is larger than that of the original PWM signal 220. It is also noted that the falling edge of the new PWM signal 240 coincides with the crossover point 236 on the slew-down PWM signal 230, which marks the intersection of the falling edge portion 232 of the slew-down PWM signal 230 and the adjustable comparator threshold 234. Therefore, adjusting the level of the adjustable comparator threshold 234 controls the timing of the falling edge of the new PWM signal 240. Furthermore, controlling the duration of the falling edge of the new PWM signal 240 adjusts its duty cycle. In other words, controlling... Figure 4 The threshold of comparator 90 adjusts the duty cycle of the new PWM signal 240. More specifically, in the illustrated embodiment, increasing the threshold of comparator 90 decreases the duty cycle of the new PWM signal 240, while decreasing the threshold of comparator 90 increases the duty cycle. It is also noted that in this embodiment, the rising edge of the new PWM signal 240 is always aligned with the rising edge of the original PWM signal 220. The threshold of the inverting input 94 coupled to comparator 90 can be an example of duty cycle control coupled to duty cycle controller 30, such as... Figure 1 As explained.

[0032] Therefore, the duty cycle of the new PWM signal 240 can be specified by controlling the slew rate of the falling edge portion 232 of the slew rate PWM signal 230. The duty cycle of the new PWM signal 240 can also be controlled by the duty cycle controller 30 (…). Figure 1 Comparator 90 in ) Figure 4The threshold value is further specified. As described below, in some embodiments, only one of these values ​​needs to be controlled to modify the duty cycle of the new PWM 240, while in other embodiments two control elements and / or other elements may be used. Generally, modifying the slew rate of the slew-down PWM signal 230 provides a relatively large change in the duty cycle of the new PWM signal 240 compared to actually changing the threshold value of comparator 90. However, as illustrated above, one or both of the controls can be used to generate a new PWM signal 240 with the desired final duty cycle.

[0033] Figure 5 This is a schematic block diagram of a voltage generator 500 according to an embodiment, the voltage generator 500 including... Figure 1 The PWM signal generator 512 comprises some or all of the components of a PWM signal generator. In the illustrated embodiment, FPGA 510 generates a master clock signal, which the PWM signal generator 512 uses to generate a base PWM signal. In the illustrated context, the PWM signal generator 512 is shown as being embodied within the FPGA 510 itself, but in other embodiments, the pulse width modulation signal generator 512 may be external to the FPGA. The PWM signal generator 512 may be... Figure 1 An embodiment of the PWM signal generator 10 is described above. The PWM signal generator 512 generates a PWM signal based on a master clock signal (such as the master clock signal of the FPGA 510). However, as recalled above, the PWM signal generator 512 can only control the duty cycle of the PWM signal with relatively large steps based on the master clock frequency. In the example above, the PWM signal generator 512 can only control the output PWM signal to 1% resolution. As described herein, using additional components, embodiments of this disclosure can achieve higher precision in the final PWM signal than can be obtained simply by manipulating the master clock signal.

[0034] Next, the PWM signal from the PWM signal generator 512 is fed to the slew rate controller 520, which can be... Figure 1 An embodiment of the slew rate controller 20. As described above, the slew rate controller 20 can control the leading edge or falling edge of the PWM signal; however, in the illustrated embodiment, the slew rate controller 520 controls the falling edge of the PWM signal and is therefore referred to as a lower slew rate controller. Next, the PWM signal with the falling edge output of the slew rate controller 520 is supplied to the duty cycle controller 530, which can be... Figure 1 An embodiment of the duty cycle control device 530. In some embodiments, the duty cycle controller 530 may include a comparator, such as Figure 4The comparator 90, although other circuitry may be used instead, provides duty cycle control functionality. The outputs of the digital-to-analog converter (DAC) 505 and DAC 507, which will be described in detail below, can provide feedback control for the slew rate controller 520 and the duty cycle controller 530 during operation.

[0035] According to embodiments of this disclosure, the output of the duty cycle controller 530 is a final, finely controllable PWM signal with a specified duty cycle. This final new PWM signal, such as... Figure 2 The new PWM voltage signal 240 is supplied to the switching power supply 550, which may be a buck converter, to generate the final output voltage. As described above, the switching power supply generates the final controllable output voltage, which is determined by the duty cycle of the PWM signal driving the MOSFETs within the switching power supply 550. Therefore, by adjusting the duty cycle of the PWM signal driving the switching power supply 550, the final output voltage of both the switching power supply 550 and the voltage generator 500 can be controlled to a very fine degree.

[0036] In some embodiments, the final output voltage from the switching power supply 550 is coupled back to the output voltage monitor 560, which generates a signal based on the difference between the desired output voltage from the voltage generator 500 and the actual output voltage. In some embodiments, this is referred to as an error signal, which can be fed back to the error controller 516 within the FPGA 510. In some embodiments, the analog error signal is converted into a digital signal by an analog-to-digital converter (ADC) 565, which is then passed back to the error controller 516 of the FPGA 510. In the illustrated embodiments, the function of the error controller 516 is described as being embodied in the FPGA 510, although in other embodiments the error controller may be separate from the FPGA. By providing feedback from the output voltage monitor 560, the digital error signal from the ADC 565 forms a measurement feedback control loop through which the error controller 516 can modify the operation of other components of the voltage generator 500 to generate the final output voltage with high accuracy.

[0037] Error controller 516 can generate a slew rate control signal to actively control slew rate controller 520 to control the shape of the modified PWM signal output from the slew rate controller. In the illustrated embodiment, error controller 516 generates digital slew rate control, which is converted to analog slew rate control by DAC 507. The analog slew rate control is then fed to slew rate controller 520 to actively control the slew rate, as referenced above. Figure 3A and 3C As described above, slew rate control can control the discharge rate of current generator 56. Figure 3A ) or modify the controllable resistor 76 ( Figure 3B In other embodiments of the slew rate controller 520, slew rate control may control other aspects of the slew rate controller 520.

[0038] Furthermore, the error controller 516 can use an error signal from the output voltage monitor 560 as a data source to control the DAC 505 to adjust the controllable threshold applied to the duty cycle controller 530, as detailed above. As described with reference to DAC 507, the output from the error controller 516 can be a digital signal representing the threshold, which the DAC 505 then converts into an analog threshold signal before applying it to the duty cycle controller 530, which in some embodiments is a comparator. In some embodiments, the reference voltage output by the DAC 505 increases or decreases the threshold voltage applied to the comparator in linear steps, while in other embodiments, the reference voltage output of the DAC 505 uses logarithmic increases or decreases to control the threshold voltage. This novel method of controlling one or both of the slew rate controller 520 and the duty cycle controller 530 enhances the accuracy of generating PWM signals in embodiments according to this disclosure.

[0039] In some embodiments, Figure 5 More or fewer components described separately may be physically embodied within the FPGA 510 itself. For example, one or both of the slew rate controller 520 and the duty cycle controller 530 may be embodied in the FPGA 510. And in other embodiments, the DACs 505 and 507 may also be part of the FPGA 510, depending on the implementation details. Similarly, although the PWM signal generator 512 is shown as being implemented within the FPGA 510, it may be standalone or separate from the FPGA.

[0040] Furthermore, in the illustrated embodiment, FPGA 510 includes one or more user inputs 503 through which the desired output of voltage generator 500 can be specified. The user inputs can be controlled by a menu on voltage generator 500 itself, or specified in another way, such as input from a control computer.

[0041] Figure 6 This is a flowchart illustrating an example operation in process 600 for generating a controllable PWM signal according to an embodiment. Process 600 begins by receiving a clock signal in operation 602. As described above, the clock signal may be derived from the FPGA's master clock, or it may be generated using other circuitry.

[0042] Operation 604 generates a basic PWM signal from the master clock signal. This function can be, for example, […]. Figure 5The PWM signal generator 512 performs the operation. Next, in operation 606, the slew rate of the generated PWM signal is controlled. For example, as described above, the falling edge or rising edge of the PWM signal, or both, is modified by a slew rate modifier. In the above description, the falling edge of the rescaled clock signal is controlled by a slew rate controller 20, which can take various forms, such as... Figure 3A , 3B As shown in 3C, although other embodiments are possible without departing from the spirit of the invention. Controlling the slew rate of the falling edge of the PWM signal prolongs the transition time between the high and low states of the PWM signal. The slew rate can be controlled by various methods described above, which generate skews of different shapes and durations.

[0043] Operation 608 generates a comparison setpoint used in the following operations. In some embodiments, the setpoint may start from a set initial value, which may be modified during the operation of process 600, as further described below.

[0044] Next, in operation 610, the duty cycle controller generates a new PWM signal from the PWM signal with the modified slew rate, as described above. In one embodiment, the comparator evaluates the level of the instantaneously modified PWM signal against a threshold set in operation 608, and the comparator's output becomes a new PWM signal with the modified duty cycle, as described above.

[0045] Finally, operation 612 will come from the duty cycle controller (such as...) Figure 4 A new PWM signal is applied to the comparator 90 (e.g., a buck converter). The output of the switching power supply then becomes the output voltage as desired and set by the user.

[0046] In operation 614, a feedback signal can be generated from the new PWM signal output by the duty cycle controller in operation 610 or from the final output voltage signal from the switching power supply in operation 612. In any form, the feedback signal generated in 614 is based on a comparison of the desired signal with the actual instantaneous signal. Then, as described above, process 600 uses the feedback signal to control the circuitry or system in the power generation circuit. The feedback can be used to control the original PWM signal created in operation 604. For example, in the described embodiment, the clock signal from operation 602 is reduced to a clock signal with 25% of the original clock rate. However, using the feedback signal from operation 614, the scaled clock rate can be scaled to different values. Moreover, although as described above and in Figure 2 The PWM signal 220 described herein has a 50% duty cycle, but another base duty cycle can also be selected for the base PWM signal.

[0047] As an alternative or supplement, the feedback signal from operation 614 can be used to control the slew rate controller (such as...). Figure 1 The slew rate is set by a slew rate controller 20), which generates a PWM slew rate in operation 606. Modifying the slew rate can take various forms, such as increasing or decreasing the rate of linear slew change at the falling edge of the PWM signal, or increasing or decreasing the rate of nonlinear slew change. (See above for reference.) Figure 3A , 3B 3C describes various ways to modify the slew rate.

[0048] Furthermore, as an alternative to or supplement to the two uses of the feedback signal described above, the feedback signal from operation 614 can be used to modify the threshold set in operation 608, which is used by the duty cycle controller in operation 610, to create the final modified PWM signal. The feedback from operation 614 to operations 604, 606, and 608 is shown in dashed lines to indicate that any or all of these feedback mechanisms can be used in any combination to modify the final PWM signal as described above, and by extension, to modify the final output voltage signal to the final output voltage specified by the user. While not typical, the original duty cycle of the final PWM may precisely match the desired duty cycle, and no adjustment based on the feedback signal from operation 614 is required.

[0049] Various aspects of this disclosure can operate on specially created hardware, on firmware, on a digital signal processor, or on a specially programmed general-purpose computer including a processor that operates according to programmed instructions. The terms controller or processor used herein are intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and special-purpose hardware controllers. One or more aspects of this disclosure can be embodied in computer-usable data and computer-executable instructions, such as in one or more program modules executed by one or more computers (including monitoring modules) or other devices. Typically, program modules include routines, programs, objects, components, data structures, etc., which perform a specific task or implement a specific abstract data type when executed by a processor in a computer or other device. Computer-executable instructions can be stored on a non-transitory computer-readable medium, such as a hard disk, optical disk, removable storage medium, solid-state memory, random access memory (RAM), etc. As those skilled in the art will understand, the functionality of a program module can be combined or distributed in various aspects as needed. Furthermore, this functionality can be wholly or partially embodied in firmware or hardware equivalents, such as integrated circuits, FPGAs, etc. Specific data structures may be used to implement one or more aspects of this disclosure more efficiently, and such data structures are considered within the scope of the computer-executable instructions and computer-available data described herein.

[0050] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, a computer-readable medium means any medium accessible by a computing device. By way of example and not limitation, a computer-readable medium may include computer storage media and communication media.

[0051] Computer storage media refers to any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technologies, optical disc read-only memory (CD-ROM), digital video disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable medium implemented in any technology. Computer storage media does not include the signal itself or the transient form of signal transmission.

[0052] A communication medium is any medium that can be used for communication of computer-readable information. By way of example and not limitation, a communication medium may include coaxial cable, fiber optic cable, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0053] Furthermore, this written description also refers to specific features. It is to be understood that the disclosure in this specification includes all possible combinations of these specific features. For example, where a specific feature is disclosed in the context of a particular aspect, that feature may also be used, to the extent possible, in the context of other aspects.

[0054] Furthermore, when a method having two or more defined steps or operations is mentioned in this application, the defined steps or operations may be performed in any order or simultaneously, unless the context precludes such possibilities.

[0055] Example Illustrative examples of the disclosed technology are provided below. Embodiments of the technology may include one or more of the examples described below, and any combination thereof.

[0056] Example 1 is a fine-control pulse width modulation signal generator that may include a preliminary pulse width modulation signal generator configured to generate a basic pulse width modulation signal from a clock signal, a slew rate controller configured to modify the edges of the basic pulse width modulation signal, and a comparator having a first input that receives the output of the slew rate controller and a second input that receives a comparison threshold, the comparator being configured to output a fine-control pulse width modulation signal based on a comparison between the first input and the second input.

[0057] Example 2 is a signal generator based on Example 1, wherein a slew rate controller is actively controlled.

[0058] Example 3 is a signal generator according to Example 1 or Example 2, wherein the slew rate controller includes a controllable current trap.

[0059] Example 4 is a signal generator based on any one of Examples 1-3, wherein the slew rate controller includes a resistor-capacitor network.

[0060] Example 5 is a signal generator based on any one of Examples 1-4, where the resistance in the resistor-capacitor network is controllable.

[0061] Example 6 is a signal generator based on any one of Examples 1-5, wherein the comparator threshold applied to the second input is controllable.

[0062] Example 7 is a signal generator based on any one of Examples 1-6, wherein the initial pulse width modulation signal generator is embodied in a field programmable gate array.

[0063] Example 8 is a signal generator based on any one of Examples 1-7, where the clock signal is the master clock signal of a field-programmable gate array.

[0064] Example 9 is a power supply that may include: a pulse width signal generator having a preliminary pulse width modulation signal generation circuit configured to generate a basic pulse width modulation signal from a clock, a slew rate controller configured to modify the edges of the basic pulse width modulation signal, and a comparator having a first input that receives the output of the slew rate controller and a second input that receives a comparison threshold, the comparator being configured to output a second pulse width modulation signal based on a comparison between the first and second inputs, and a switching power supply coupled to the output of the comparator and configured to generate the output voltage of the power supply.

[0065] Example 10 is based on the power supply of Example 9, wherein the switching power supply includes a switching transistor controlled by a second pulse width modulation signal output by a comparator.

[0066] Example 11 is a power supply according to Example 9 or Example 10, which may further include error correction circuitry coupled to the output voltage of the power supply and configured to generate an error signal indicating the difference between the output voltage of the power supply and the desired output voltage of the power supply.

[0067] Example 12 is a power supply based on any of Examples 9-11, wherein error correction circuitry is coupled to a controller in the power supply.

[0068] Example 13 is based on a power supply from any of Examples 9-12, wherein the controller is configured to modify the operation of one or more of the slew rate controller and comparison threshold.

[0069] Example 14 is a power supply based on any one of Examples 9-13, wherein one or both of the initial pulse width modulation signal generation circuit and the controller are part of a field programmable gate array.

[0070] Example 15 is a method for generating a fine-tuned pulse width modulation (PWM) signal, which may include generating a base PWM signal, controlling the slew rate of the edges of the base PWM signal to generate a modified PWM signal, comparing the modified PWM signal with a threshold, and outputting the fine-tuned PWM signal based on the comparison between the modified PWM signal and the threshold.

[0071] Example 16 is based on the method of Example 15, and may further include generating a feedback signal that compares the modified pulse width modulation signal with the desired pulse width modulation signal.

[0072] Example 17 is based on the method of Example 15 or Example 16, which may further include using a feedback signal to modify the slew rate of the edge of the underlying pulse width modulation signal.

[0073] Example 18 is a method based on any one of Examples 15-17, which may also include modifying the threshold based on the feedback signal.

[0074] Example 19 is a method according to any one of Examples 15-18, which may further include accepting a clock signal from a field-programmable gate array, and wherein generating a basic pulse width modulation signal includes generating a basic pulse width modulation signal from the clock signal.

[0075] The previously described versions of the disclosed subject matter have numerous advantages that are described or understood by those skilled in the art. Nevertheless, these advantages or features are not claimed in all versions of the disclosed apparatus, system, or method.

[0076] Furthermore, specific features are mentioned in this written description. It should be understood that the disclosure in this specification includes all possible combinations of these specific features. Where a specific feature is disclosed in the context of a particular aspect or example, that feature may also be used, to the extent possible, in the context of other aspects and examples.

[0077] Furthermore, when a method having two or more defined steps or operations is mentioned in this application, the defined steps or operations may be performed in any order or simultaneously, unless the context precludes such possibilities.

[0078] Although specific examples of the invention have been illustrated and described for purposes of explanation, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Therefore, the invention should not be limited to anything other than the appended claims.

Claims

1. A finely controlled pulse width modulation signal generator, comprising: A preliminary pulse width modulation signal generator is constructed to generate a basic pulse width modulation signal from a clock signal; A slew rate controller is configured to modify the edges of the underlying pulse width modulation signal; and A comparator having a first input that accepts the output of the slew rate controller and a second input that accepts a comparison threshold, the comparator being configured to output a fine-control pulse width modulation signal based on a comparison between the first input and the second input.

2. The signal generator according to claim 1, wherein the slew rate controller is actively controlled.

3. The signal generator according to claim 2, wherein the slew rate controller comprises a controllable current trap.

4. The signal generator according to claim 1, wherein the slew rate controller comprises a resistor-capacitor network.

5. The signal generator according to claim 4, wherein the resistance in the resistor-capacitor network is controllable.

6. The signal generator of claim 1, wherein the comparator threshold applied to the second input is controllable.

7. The signal generator of claim 1, wherein the preliminary pulse width modulation signal generator is embodied in a field-programmable gate array.

8. The signal generator according to claim 7, wherein the clock signal is the master clock signal of the field-programmable gate array.

9. A power supply, comprising: A pulse width signal generator includes: The initial pulse width modulation signal generation circuit is configured to generate a basic pulse width modulation signal from a clock signal. A slew rate controller, configured to modify the edges of the underlying pulse width modulation signal, and A comparator having a first input that accepts the output of the slew rate controller and a second input that accepts a comparison threshold, the comparator being configured to output a second pulse width modulation signal based on a comparison between the first input and the second input; and A switching power supply, which is coupled to the output of a comparator and configured to generate the output voltage of the power supply.

10. The power supply of claim 9, wherein the switching power supply includes a switching transistor controlled by the second pulse width modulation signal output from the comparator.

11. The power supply of claim 9, further comprising an error correction circuit coupled to the output voltage of the power supply and configured to generate an error signal indicating the difference between the output voltage of the power supply and the desired output voltage of the power supply.

12. The power supply of claim 11, wherein the error correction circuit is coupled to a controller in the power supply.

13. The power supply of claim 12, wherein the controller is configured to modify the operation of one or more of the slew rate controller and the comparison threshold.

14. The power supply of claim 12, wherein one or both of the preliminary pulse width modulation signal generation circuit and the controller are part of a field-programmable gate array.

15. A method for generating a finely tuned pulse width modulation signal, comprising: Generate the basic pulse width modulation signal; Control the slew rate of the edges of the base pulse width modulation signal to generate the modified pulse width modulation signal; The modified pulse width modulation signal is compared with the threshold. and The fine-tuned pulse width modulation signal is output based on the comparison between the modified pulse width modulation signal and the threshold.

16. The method of claim 15, further comprising generating a feedback signal that compares the modified pulse width modulation signal with the desired pulse width modulation signal.

17. The method of claim 16, further comprising using the feedback signal to modify the slew rate of the edge of the base pulse width modulation signal.

18. The method of claim 16, further comprising modifying the threshold based on the feedback signal.

19. The method of claim 15, further comprising receiving a clock signal from a field-programmable gate array, wherein generating a basic pulse width modulation signal comprises generating a basic pulse width modulation signal from the clock signal.

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