Gate drive circuit and bridge drive circuit for power switches

Abstract

Disclosed are a gate drive circuit and a bridge drive circuit. The gate drive circuit includes a first supply node receiving a first supply voltage, a second supply node receiving a second supply voltage, a first output switch circuit coupled between the first supply node and a first output terminal of the gate drive circuit, a second output switch circuit coupled between a second output terminal of the gate drive circuit and the second supply node, and an open line detection circuit coupled to the first output terminal. The first output terminal and the second output terminal of the gate drive circuit are both configured to be coupled to a control terminal of a power switch to provide a switching drive signal. The open line detection circuit and the first output terminal together are used to detect whether a connection between the first output terminal or the second output terminal of the gate drive circuit and the control terminal of the power switch tube appears an open line condition.

Description

Technical Field

[0001] This invention relates primarily to an electronic circuit, and more particularly, but not exclusively, to a gate drive circuit and a bridge drive circuit for driving power switches. Background Technology

[0002] In power conversion applications, gate drive circuits are commonly used to drive power switching devices such as power metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs). Bridge drive circuits are also widely used in high-power or high-voltage power conversion or power management applications. However, most widely used gate drive circuits currently employ compact and inexpensive package structures, which cannot provide detection for package configuration faults such as open output pins or poor solder joints. Summary of the Invention

[0003] In view of one or more problems in the prior art, the object of the present invention is to provide a gate drive circuit and a bridge drive circuit that can detect the open wire status of the output terminal, and thus have better performance.

[0004] In one aspect of the present invention, a gate driving circuit is provided. The gate driving circuit includes: a first power supply node for receiving a first power supply voltage; a second power supply node for receiving a second power supply voltage less than the first power supply voltage; a first output switching circuit coupled between the first power supply node and a first output terminal of the gate driving circuit; a second output switching circuit coupled between a second output terminal of the gate driving circuit and the second power supply node, wherein the first and second output terminals of the gate driving circuit are configured to be coupled to a control terminal of a power switch to provide a switching drive signal; and an open-circuit detection circuit coupled to the first output terminal, wherein, before the power switch switches, the open-circuit detection circuit, together with the first output terminal, detects whether an open circuit exists between the first or second output terminal and the control terminal of the power switch.

[0005] In another aspect of the invention, a gate driving circuit is provided. The gate driving circuit includes: a first terminal for receiving a pulse width modulation signal, the pulse width modulation signal including a logic high level and a logic low level; a second terminal for receiving a first supply voltage; a third terminal for receiving a second supply voltage less than the first supply voltage; a first output switching circuit coupled between the second terminal and a fourth terminal of the gate driving circuit; a second output switching circuit coupled between a fifth terminal of the gate driving circuit and the third terminal, wherein the fourth and fifth terminals are configured to be coupled to a control terminal of a power switch to provide a switching driving signal to control the power switch's on / off state based on the pulse width modulation signal; and an open-circuit detection circuit coupled to the fourth terminal, wherein before the power switch switches, the open-circuit detection circuit, together with the fourth terminal, detects whether an open circuit exists between the fourth or fifth terminal and the control terminal of the power switch.

[0006] In another aspect of the invention, a bridge drive circuit is provided. The bridge drive circuit includes: a reference terminal; a first power supply node for receiving a positive power supply voltage relative to the reference terminal voltage; a second power supply node for receiving a negative power supply voltage relative to the reference terminal voltage; a first output switch circuit coupled between the first power supply node and a first output terminal of the bridge drive circuit; a second output switch circuit coupled between a second output terminal of the bridge drive circuit and the second power supply node, wherein the first and second output terminals of the bridge drive circuit are configured together to be coupled to a control terminal of a power switch to provide a switch drive signal to control the switching operation of the power switch; and an open-circuit detection circuit coupled to the first output terminal of the bridge drive circuit, wherein before the switching operation of the power switch, the open-circuit detection circuit, together with the first output terminal, detects whether an open circuit exists between the first or second output terminal and the control terminal of the power switch.

[0007] According to an embodiment of the present invention, the open-wire detection circuit, together with the first output terminal that controls the power switch to turn on, is used to detect the open-wire connection of the first output terminal or the second output terminal coupled to the power switch control terminal, which can prevent the shoot-through problem of the half-bridge circuit caused by the power switch failing to turn off due to the open-wire condition. Attached Figure Description

[0008] To better understand the present invention, it will be described in detail with reference to the following drawings:

[0009] Figure 1 This is a circuit diagram of a gate drive circuit 100 for driving a power switch according to an embodiment of the present invention.

[0010] Figure 2This is a circuit diagram of an isolated gate drive circuit 100a according to an embodiment of the present invention.

[0011] Figure 3 This is a circuit diagram of an open-line detection circuit 103A for a gate drive circuit 100b according to an embodiment of the present invention.

[0012] Figure 4 This is a circuit diagram of an open-line detection circuit 103B for a gate drive circuit 100c according to an embodiment of the present invention.

[0013] Figure 5 This is a circuit diagram of a bridge drive circuit 200 for driving a half-bridge circuit according to an embodiment of the present invention.

[0014] Figure 6 This is a flowchart of a method 700 for a gate drive circuit according to an embodiment of the present invention. Detailed Implementation

[0015] The following will describe in detail specific embodiments of the isolated resonant converter and control method of the present invention. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to implement the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0016] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0017] Figure 1This is a circuit diagram of a gate drive circuit 100 for driving a power switch according to an embodiment of the present invention. The gate drive circuit 100 can be used to drive a power switch. The power switch can be any controllable semiconductor device, such as any controllable switching device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), silicon carbide (SiC), gallium nitride (GaN), etc. In one embodiment, in practical applications, the gate drive circuit 100 can be used to drive the power switch to perform switching operations of turning on and off. Figure 1 In the illustrated embodiment, the power switch can be exemplified as the power switch MQ shown in the figure. However, those skilled in the art will understand that this is merely exemplary and not intended to be limiting.

[0018] In one embodiment, the gate drive circuit 100 may include a first output switch circuit 101, a second output switch circuit 102, an open-circuit detection circuit 103, and multiple terminals. For example... Figure 1 As shown, the gate drive circuit 100 may include a plurality of terminals: a first terminal 11 serving as an input terminal IN, a second terminal 12 serving as a reference ground terminal GND, a third terminal 13 serving as a first power supply node VDD, a fourth terminal 14 serving as a first output terminal OUT+, a fifth terminal 15 serving as a second output terminal OUT-, and a sixth terminal 16 serving as a second power supply node VEE.

[0019] exist Figure 1 In the illustrated embodiment, the input terminal IN can be used to receive a pulse width modulation signal PWMIN. The pulse width modulation signal PWMIN can have a set logic state (e.g., logic high level) and a reset logic state (e.g., logic low level).

[0020] A high-potential supply voltage VVDD is provided to the first power supply node VDD to control the conduction of the power switch MQ. The high-potential supply voltage VVDD is output to the first output terminal OUT+ through the first output switch circuit 101. Figure 1 In the illustrated embodiment, the first output switch circuit 101 is coupled between the first power supply node VDD and the first output terminal OUT+. The first output switch circuit 101 includes a pMOSFET, which can be controlled to turn on and off by logic control signals provided by the drive control circuit 106. That is, in Figure 1 In response to the set logic state of the pulse width modulation signal PWMIIN, the high-potential supply voltage VVDD is applied to the first output terminal OUT+ through the pMOSFET of the first output switching circuit 101 to control the conduction of the power switch MQ.

[0021] Simultaneously, the low-potential supply voltage VVEE is lower than the high-potential supply voltage VVDD. The low-potential supply voltage VVEE is provided to the second power supply node VEE to turn off the power switch MQ. The low-potential voltage VVEE can be output to the second output terminal OUT- through the second output switching circuit 102. Figure 1 In the illustrated embodiment, the second output switching circuit 102 is coupled between the second output terminal OUT- and the second power supply node VEE, and may include an nMOSFET as shown. This nMOSFET can also be controlled to turn on and off by the drive control circuit 106. That is, in Figure 1 In response to the reset logic state of the pulse width modulation signal PWMIIN, the low potential voltage VVEE is applied to the second output terminal OUT- through the nMOSFET of the second output switching circuit 102 to control the power switch MQ to turn off.

[0022] like Figure 1 As shown, the first output terminal OUT+ can be adapted to connect to the control terminal G of the power switch MQ, for example, with or without the gate resistor device RG1; while the second output terminal OUT- can be adapted to connect to the control terminal G of the power switch MQ, for example, with or without the gate resistor device RG2. In a specific embodiment, the gate resistor devices RG1 and RG2 may include parasitic resistance.

[0023] Continue as Figure 1 As shown, the first terminal D of power switch MQ is coupled to power node N1, and the second terminal S of power switch MQ is coupled to power node N2. A voltage drop VDS may exist between the first terminal D and the second terminal S of power switch MQ. The voltage drop VDS can be used to indicate the potential difference (VN1-VN2) between power node N1 and power node N2. When power switch MQ is in the off state, the electrical conduction path (e.g., current flow path) between power node N1 and power node N2 is blocked or interrupted. When power switch MQ is on, the electrical conduction path between power node N1 and power node N2 is connected, allowing current to flow between power node N1 and power node N2.

[0024] In one embodiment, when the gate drive circuit 100 is configured for practical application, the first output terminal OUT+ can be adapted to be coupled to a common drive connection node N3 (e.g., with or without the first resistor RG1); the second output terminal OUT- can be adapted to be coupled to the common drive connection node N3 (e.g., with or without the second resistor RG2). The common drive connection node N3 can be adapted to be coupled to the control terminal G of the power switch MQ. The first output terminal OUT+ and the second output terminal OUT- are configured to be coupled to the control terminal G of the power switch MQ, and a switch drive signal DROUT is provided based on the pulse width modulation signal PWMIN to control the switching operation of the power switch MQ. The switch drive signal DROUT can have a reset logic state to drive the power switch MQ to turn off and a set logic state to drive the power switch MQ to turn on.

[0025] In one embodiment, drive control circuitry 106 is coupled between input terminal IN and output switching circuits (101, 102). Drive control circuitry 106 can be configured to control first output switching circuitry 101 and second output switching circuitry 102 to provide switch drive signal DROUT to power switch MQ.

[0026] In one embodiment, the high-potential supply voltage VVDD is an internal supply voltage that powers various circuit modules, such as the drive control single channel 106, and the first and second output switch circuits 101 and 102. In practical applications, the first capacitor CVDD is coupled to the first power supply node VDD. In one embodiment, the first capacitor CVDD and the second capacitor CVEE are connected in series and coupled between the first power supply node VDD and the second power supply node VEE. The common connection point of the first capacitor CVDD and the second capacitor CVEE can be coupled to the power node N2 of the power switch MQ, such as... Figure 1 As shown.

[0027] exist Figure 1 In the illustrated embodiment, the gate drive circuit 100 further includes an open-line detection circuit 103 connected to the first output terminal OUT+. The open-line detection circuit 103 and the first output terminal OUT+ are configured to detect an open line condition at either output terminal (first output terminal OUT+ or second output terminal OUT-) connected to the power switch MQ control terminal G before the power switch MQ switches to operation. In one embodiment, the open-line detection circuit 103 provides a fault signal FLAG based on the detection result of the open line condition.

[0028] In one embodiment, open-line detection can be performed when an open-line detection enable signal ODT with a set state is issued after the gate drive circuit 100 is started or initialized and before the power switch MQ starts working.

[0029] exist Figure 1In the illustrated embodiment, the gate drive circuit 100 further includes a first undervoltage protection circuit UVLO1 (labeled 104) and a signal processing circuit 105. The first undervoltage protection circuit UVLO1 is configured to detect and determine whether the high-potential supply voltage VVDD is less than a first undervoltage threshold V before performing open-line detection. UV1 In one embodiment, if the high-potential supply voltage VVDD is less than a first undervoltage threshold V UV1 The first undervoltage protection circuit UVLO1 controls the switch drive signal DROUT to be locked in the reset logic state, and at the same time the open-line detection enable signal ODT will not be set or enabled.

[0030] The signal processing circuit 105 can be configured to perform signal processing on the pulse width modulation signal PWMIN, such as level shifting. However, in another embodiment, the pulse width modulation signal PWMIN can also be directly passed to the drive control circuit 106, without the signal processing circuit 105 needing to process the pulse width modulation signal PWMIN.

[0031] In a further embodiment, the gate drive circuit 100 may be configured to enable or activate the open-line detection circuit 103 during a detection time window. This detection time window has a certain detection time width. In one embodiment, the detection time window is enabled when both the high-potential supply voltage VVDD and the low-potential supply voltage VVEE are established, and the second output switch circuit 102 coupled between the second output terminal OUT- and the second power supply node VEE is in a low-impedance state.

[0032] It should be noted that the term "low impedance state" as used herein refers to a state with relatively low impedance. In one embodiment, the low impedance state may be characterized by the source and drain of the nMOSFET in the second output switching circuit 102 being electrically connected together. In a first embodiment, the nMOSFET in the second output switching circuit 102 is turned on, and the second output switching circuit 102 is in a low impedance state. In another embodiment, the source and drain of the nMOSFET in the second output switching circuit 102 may be electrically connected together in other ways to achieve a low impedance between the second output terminal OUT- and the second power supply node VEE. Correspondingly, the "high impedance state" refers to a state with relatively high impedance. That is, the impedance between the second output terminal OUT- and the second power supply node VEE is high. In one embodiment, the source and drain of the nMOSFET in the second output switching circuit 102 are decoupled from each other, and the second output switching circuit 102 is in a high impedance state, with no electrical connection between the source and drain of the nMOSFET in the second output switching circuit 102.

[0033] In one embodiment, the drive control circuit 106 is configured to provide a logic control signal with a set logic state to the gate of the nMOSFET in the second output switch circuit 102, allowing and controlling the second output switch circuit 102 to be in the low impedance state as described above. In another embodiment, a controllable interconnect structure may be used to establish an additional electrical connection between the source and drain of the nMOSFET in the second output switch circuit 102 to maintain the second output switch circuit 102 in a low impedance state.

[0034] In one embodiment, the first output switching circuit 101 and the second output switching circuit 102 are configured as separate push-pull architectures. In practical applications, they have... Figure 1 The gate drive circuit 100 of the illustrated split-gate configuration can independently control the turn-on path (via the first output switch circuit 101 and the first output terminal OUT+) and the turn-off path (via the second output switch circuit 102 and the second output terminal OUT-) of the power switch MQ. Compared to a configuration with a single gate output, i.e., a configuration with only one gate output terminal, the gate drive circuit 100 of the split-gate configuration has two separate first output terminals OUT+ and second output terminals OUT-, which not only saves diodes but also reduces the turn-on communication speed when the power switch MQ is turned on.

[0035] Figure 2 This is a circuit diagram of an isolated gate drive circuit 100a according to an embodiment of the present invention. For simplicity, components, structures, or elements in the gate drive circuit 100a that have substantially the same / similar functions as those in the gate drive circuit 100 are all referred to by the same reference numerals as those in the gate drive circuit 100. Those skilled in the art will understand that the gate drive circuit 100a can be considered as an exemplary embodiment of the gate drive circuit 100, which further includes an isolation region 107 and a primary-side control circuit 120. Therefore, referring to... Figure 1 The above description of the gate drive circuit 100 also applies to the gate drive circuit 100a.

[0036] In one embodiment, isolation region 107 provides capacitive isolation between the primary and secondary sides of gate drive circuit 100a. Primary-side control circuit 120 is located on the primary side. Drive control circuit 106, first output switch circuit 101, and second output switch circuit 102 are located on the secondary side.

[0037] exist Figure 2 In the illustrated embodiment, the first terminal 11 is used as an input terminal IN and is configured to receive a pulse width modulation signal PWMIN having a set logic state and a reset logic state. The second terminal 12 is used as the primary-side reference ground terminal GND of the primary-side circuit of the gate drive circuit 100a.

[0038] The gate drive circuit 100a may also include a terminal 18, which can be used as the primary-side power supply terminal of the gate drive circuit 100a to provide a power supply voltage VCC to, for example, the primary-side control circuit 120. In practical applications, a third capacitor CVCC is coupled to terminal 18 as a power supply capacitor.

[0039] exist Figure 2 In the illustrated embodiment, the first power supply node VDD can be used as the positive power supply terminal on the secondary side of the gate drive circuit 100a, configured to receive a high-potential supply voltage VVDD. The second power supply node VEE can be used as the negative power supply terminal on the secondary side of the gate drive circuit 100a, configured to receive a low-potential supply voltage VVEE. With this configuration, the gate drive circuit 100a can be adapted to power conversion applications in high-power or high-voltage applications. Those skilled in the art will understand that this is merely illustrative. In low-power or low-voltage applications, the isolation region 107, the circuitry on the primary side (e.g., primary-side control circuit 120), and the associated terminals on the primary side (e.g., terminal 18) may be optional or unnecessary.

[0040] The primary-side control circuit 120 is configured to transmit a pulse width modulation signal PWMIN to the secondary-side via the signal isolation and transmission channel of the isolation region 107. The signal transmitted to the secondary-side can be labeled as follows: Figure 2 The CPWM is shown. In one embodiment, the pulse width modulation signal PWMIN can be processed by the primary-side control circuit 120 before passing through the signal isolation and transmission channel, such as... Figure 2 As shown. However, in other embodiments, the pulse width modulation signal PWMIN may not undergo signal processing through the primary-side control circuit 120 before passing through the signal isolation and transmission channel. Those skilled in the art will understand that in some examples, the isolation region 107 and the primary-side circuitry are optional. The pulse width modulation signal PWMIN can be directly provided to components such as the input of the AND gate circuit 105a or the drive control circuit 106.

[0041] In one example, the primary-side control circuit 120 may include a second undervoltage protection circuit UVLO2 (labeled 121) for detecting whether the supply voltage VCC is less than a second undervoltage threshold V. UV2 In one embodiment, if the supply voltage VCC is less than the second undervoltage threshold V UV2 The second undervoltage protection circuit UVLO2 can, for example, use the active clamping circuit built into the drive control circuit 106 to force the switch drive signal DROUT to be locked in the reset logic state.

[0042] In one example, the primary-side control circuit 120 may further include a filter circuit 122 for filtering out noise from the pulse width modulation signal PWMIN. In one embodiment, the primary-side control circuit 120 may further include a control signal processing circuit 123 for level shifting the pulse width modulation signal PWMIN.

[0043] exist Figure 2 In the illustrated embodiment, the gate drive circuit 100a further includes a charge pump circuit 109. The charge pump circuit 109 is coupled between the first power supply node VDD and the second power supply node VEE, and is configured to provide a low-potential power supply voltage VVEE based on a high-potential power supply voltage VVDD. The charge pump circuit 109 includes a capacitor that begins operation after the first undervoltage protection circuit UVLO1 is activated.

[0044] The drive control circuit 106 is configured to detect whether the high-potential voltage VVDD reaches a first establishment threshold voltage V1. After the high-potential voltage VVDD reaches the first establishment threshold voltage V1, an open-line detection enable signal ODT with a set state is sent to initiate open-line detection. In one embodiment, if the high-potential voltage VVDD is lower than the first establishment threshold voltage V1, the open-line detection circuit 103 remains disabled because the high-potential voltage VVDD has not yet been established. In one embodiment, when the high-potential voltage VVDD remains at 6V, it indicates that the high-potential voltage VVDD has been established. The first establishment threshold voltage V1 can be set, for example, to 5.9V.

[0045] The drive control circuit 106 is also configured to detect whether the low potential voltage VVEE is less than a second establishment threshold voltage V2. In one embodiment, when the low potential voltage VVEE is less than the second establishment threshold voltage V2 (e.g., -2.9V), it indicates that the low potential voltage VVEE has been established.

[0046] In one embodiment, the drive control circuit 106 can activate the open circuit detection circuit 103 by sending an open circuit detection enable signal ODT to start the detection time window. The open circuit detection enable signal ODT is sent after both the high-potential supply voltage VVDD and the low-potential supply voltage VVEE have been established. At this time, the second output switch circuit 102 connected between the second output terminal OUT- and the second power node VEE enters a low-impedance state.

[0047] In one embodiment, when an open-wire condition is detected, the gate drive circuit 100a generates a fault signal FLAG to disable the switching operation of the power switch MQ. Otherwise, when no open-wire condition is detected, the gate drive circuit 100a allows the switch drive signal DROUT, which is in a set state, to be output to the control terminal of the power switch MQ, allowing the power switch MQ to be turned on.

[0048] Figure 3This is a circuit diagram of an open-circuit detection circuit 103A for a gate drive circuit 100b according to an embodiment of the present invention. For simplicity, components, structures, or elements in the gate drive circuit 100b that have substantially the same / similar functions as those in the gate drive circuit 100 are all referred to by the same reference numerals as those in the gate drive circuit 100. Those skilled in the art will understand that the gate drive circuit 100b can be considered as an exemplary embodiment of the open-circuit detection circuit 103A. Furthermore, referring to... Figure 1 and Figure 2 The above description of gate drive circuits 100 to 100a also applies to gate drive circuit 100b.

[0049] As previously mentioned, when both the high-potential supply voltage VVDD and the low-potential supply voltage VVEE are established and the second output switch circuit 102, coupled between the second output terminal OUT- and the second power supply node VEE, is in a low-impedance state, the open-line detection circuit 103A is enabled. The open-line detection circuit 103A is configured to: within a detection time window, detect whether there is an open line between any output terminal (the first output terminal OUT+ or the second output terminal OUT-) and the control terminal G of the power switch MQ, and generate a fault signal FLAG based on the open-line detection status.

[0050] In one embodiment, the open-line detection circuit 103A compares the voltage VO+ at the first output terminal OUT+ with a first threshold voltage Vth1, and indicates an open-line condition when the voltage VO+ at the first output terminal OUT+ is greater than the first threshold voltage Vth1 during a detection time window. In one embodiment, in response to the voltage VO+ at the first output terminal OUT+ being greater than the first threshold voltage Vth1, the open-line detection circuit 103A provides a fault signal FLAG with a first logic state (e.g., logic high) to indicate that an open-line condition has occurred. In one embodiment, the first threshold voltage Vth1 is greater than the low-level supply voltage VVEE. For example, when the first threshold voltage Vth1 is -1V, the low-level supply voltage VVEE is -3V.

[0051] exist Figure 3In the illustrated embodiment, the open-line detection circuit 103A includes a comparator CMP, a delay circuit, and an AND gate AND1. In one embodiment, before the open-line detection is performed, the drive control circuit 106 detects whether both the high-potential supply voltage VVDD and the low-potential supply voltage VVEE have been established, and provides a logic control signal with a set logic state to control the nMOSFET in the second switching circuit 102 to turn on, so that the second output switching circuit 102 is in a low-impedance state. When both supply voltages have been established and the second output switching circuit 102 is in a low-impedance state, the drive control circuit 106 provides an open-line detection enable signal ODT to the enable terminal of the comparator CMP to enable open-line detection. The non-inverting input of the comparator CMP is coupled to the first output terminal OUT+ to receive the voltage VO+ on the first output terminal OUT+. The inverting input of the comparator CMP receives a first threshold voltage Vth1. The delay circuit provides an internal delay time. The delay circuit has an input terminal that receives the logic control signal and an output terminal coupled to the first input terminal of the AND gate AND1. In one embodiment, the logic control signal provided by the drive control circuit 106 is also provided to the gate of the nMOSFET in the second output switching circuit 102. The output of the comparator CMP is coupled to the second input of the AND gate AND1. The output of the AND gate AND1 provides a fault signal FLAG to the drive control circuit 106 based on the detected open-circuit condition.

[0052] If an open circuit occurs between any output terminal (first output terminal OUT+ or second output terminal OUT-) and the control terminal of the power switch MQ, the voltage VO+ on the first output terminal OUT+ will fluctuate and will inevitably be greater than the low-potential supply voltage VVEE (e.g., -3V). In one embodiment, when the voltage VO+ on the first output terminal OUT+ is greater than the first threshold voltage Vth1 (e.g., -1V), a fault signal FLAG with a first logic state is provided, and the drive control circuit 106 disables the switching operation of the power switch MQ, for example, by locking the switch drive signal DROUT in the drive reset logic state through an internal low-level active clamping circuit.

[0053] If no open-circuit condition is detected during the detection time window, the voltage VO+ on the first output terminal OUT+ is approximately equal to the low-potential supply voltage VVEE (e.g., -3V), and a fault signal FLAG with a second logic state is provided. Therefore, the open-circuit detection test passes. After confirming that there is no open-circuit condition, the drive control circuit 106 allows the power switch MQ to switch operation, and allows the provision of a switch drive signal DROUT with a set state to the control terminal of the power switch MQ to allow the power switch MQ to conduct.

[0054] Figure 4This is a circuit diagram of an open-line detection circuit 103B for a gate drive circuit 100c according to another embodiment of the present invention. Similarly, refer to... Figures 1 to 3 The above description of gate drive circuits 100-100b also applies to gate drive circuit 100c. Open circuit detection circuit 103B is configured to detect whether there is an open circuit between any output terminal (first output terminal OUT+ or second output terminal OUT-) and the control terminal G of power switch MQ within a detection time window, and generate a fault signal FLAG based on the detected open circuit condition.

[0055] In one embodiment, the open-circuit detection circuit 103B provides a conduction path between the first output terminal OUT+ and the third power supply node N0, and indicates the open-circuit condition when the current flowing through the conduction path is positive within a detection time window. In one embodiment, the voltage of the third power supply node N0 is greater than the low-potential supply voltage VVEE. In a further embodiment, the voltage of the third power supply node N0 is less than the on-threshold voltage of the power switch MQ to prevent short circuits.

[0056] For ease of description and understanding, the direction of the current flowing out from the gate drive circuit 100c through its first output terminal OUT+ is considered the reference current direction. That is, the current direction consistent with this reference current direction is called positive current, and the current direction opposite to this reference current direction is called negative current.

[0057] exist Figure 4 In the illustrated embodiment, the open-line detection circuit 103B includes a comparator CMP1, a third output switching circuit 131, a third resistive element R1, and a bias voltage source Vos. In one embodiment, before the open-line detection is performed, the drive control circuit 106 detects whether both the high-potential supply voltage VVDD and the low-potential supply voltage VVEE have been established, and provides a logic control signal with a set logic state to control the nMOSFET in the second switching circuit 102 to turn on, so that the second output switching circuit 102 is in a low-impedance state.

[0058] When the power supply voltage is established and the second output switch circuit 102 is in a low impedance state, the drive control circuit 106 provides an open-line detection enable signal ODT to the third output switch circuit 131, providing a conduction path between the first output terminal OUT+ and the third power supply node N0. Figure 4 As shown, when current Id flows into the gate drive circuit 100c from the first output terminal OUT+, the current flowing through the conduction path is considered a negative current. When current Id flows out of the gate drive circuit 100c from the first output terminal OUT+, as... Figure 4 As indicated by the arrow, the current flowing through the conductive path is considered a positive current.

[0059] like Figure 4 As shown, the nMOSFET in the third output switching circuit 131 has a drain coupled to the first output terminal OUT+, a source coupled to the third voltage node N0 through the third resistor R1, and a control terminal that receives the open-line detection enable signal ODT. The non-inverting input of comparator CMP1 is coupled to the source of the nMOSFET in the third output switching circuit 131 via the bias voltage source Vos. The inverting input of comparator CMP1 is coupled to the third voltage node N0. The output of comparator CMP1 outputs a fault signal FLAG to the drive control circuit 106.

[0060] exist Figure 4 In the illustrated embodiment, the gate drive circuit 100c further includes a terminal 17. Terminal 17 serves as the power ground terminal VS of the gate drive circuit 100c. In this case, the potential of the power ground terminal VS is essentially 0V, the high-potential supply voltage VVDD is a positive supply voltage relative to the potential of the power ground terminal VS, for example, 6V, and the low-potential supply voltage VVEE is a negative supply voltage relative to the potential of the power ground terminal VS, for example, -3V.

[0061] In a further embodiment, the power ground VS is also used as the reference ground of the drive control circuit 106.

[0062] In another embodiment, the power ground terminal VS can be used as the third voltage node N0 for open-line detection, such as Figure 4 The open-wire detection circuit 103B is shown.

[0063] Figure 5 This is a circuit diagram of a bridge drive circuit 200 for driving a half-bridge circuit according to an embodiment of the present invention. Figure 5 As shown, the bridge drive circuit 200 is used to control the first power switch MQ1 and the second power switch MQ2. The first power switch MQ1 and the second power switch MQ2 are configured in a half-bridge structure (labeled as half-bridge circuit 10).

[0064] In one embodiment, the half-bridge circuit 10 may include a first power switch MQ1 and a second power switch MQ2 connected in series, coupled between the system power supply terminal PS and system ground PGND. The common node of the first power switch MQ1 and the second power switch MQ2 may be configured as a floating node SW. When the first power switch MQ1 and the second power switch MQ2 are turned on in a complementary manner, voltage changes and fluctuations will occur at the floating node SW. In practical applications, inductive power devices are often coupled to the common node SW. The system supply voltage VBUS is provided to the system power terminal PS. In one embodiment, the system supply voltage VBUS can be very high; in high-voltage applications, the system supply voltage VBUS can reach 300-600V or higher.

[0065] In one embodiment, the bridge drive circuit 200 may include a first gate drive region 210, a second gate drive region 220, and an isolation region 230. The first gate drive region 210 is used to drive the control terminal G1 of the first power switch MQ1. The second gate drive region 220 is used to drive the control terminal G2 of the second power switch MQ2.

[0066] The first gate driving region 210 and the second gate driving region 220 are configured to be separate from each other. The isolation region 230 is used to provide electrical isolation between the first gate driving region 210 and the second gate driving region 220 of the bridge driving circuit 200.

[0067] In one embodiment, the gate drive circuit 100 and the various modified embodiments described above can be used to implement the first gate drive region 210 or the second gate drive region 220.

[0068] In one embodiment of the power conversion device, the first power switch MQ1 may also be another power switch, which may work in conjunction with the second power switch MQ2 in a non-half-bridge configuration, or vice versa.

[0069] exist Figure 5 In the illustrated embodiment, the bridge drive circuit 200 may include multiple terminals. For example... Figure 5 As shown, the plurality of terminals include: terminal 11 serving as the first input terminal HIN, terminal 11a serving as the second input terminal LIN, terminal 12 serving as the reference ground terminal GND, terminal 13 serving as the first high-side power supply node HVDD, terminal 14 serving as the first high-side output terminal HON, terminal 15 serving as the second high-side output terminal HPFF, terminal 16 serving as the second high-side power supply node HVEE, terminal 17 serving as the high-side power ground terminal HS, terminal 13a serving as the first low-side power supply node LVDD, terminal 14a serving as the first low-side output terminal LON, terminal 15a serving as the second low-side output terminal LOFF, terminal 16a serving as the second low-side power supply node LVEE, and terminal 18 providing the supply voltage VCC.

[0070] In one embodiment, the bridge drive circuit 200 with isolation region 230 can be used for high-power, high-voltage power conversion applications. In one embodiment, terminals 13-17 are located in the first gate drive region 210; terminals 11, 11a, 12, 13a-17a are located in the second gate drive region 220 of the drive circuit 200. The second gate drive region 220 is suitable for power conversion applications in low-power or low-voltage situations.

[0071] exist Figure 5 In the illustrated embodiment, the first input terminal HIN is used to receive, for example, a first pulse width modulation signal PWMIN+, and the second input terminal LIN is used to receive a second pulse width modulation signal PWMIN-. In this case, the first pulse width modulation signal PWMIN+ and the second pulse width modulation signal PWMIN- together define or determine the pulse width modulation signal PWMIN as described above. In one embodiment, the first input terminal HIN may be internally pulled to a reset logic state (e.g., logic low), while the second input terminal LIN may be internally pulled to a set logic state (e.g., logic high). The term "internal" here refers to the internal structure of the bridge drive circuit 200. In one embodiment, the bridge drive circuit 200 may be configured to further provide overlap protection between the first and second inputs (also known as HIN / LIN overlap protection).

[0072] In one embodiment, the first gate driving region 210 may include a first output switching circuit 101 coupled between a first high-side power supply node HVDD and a first high-side output terminal HON, a second output switching circuit 102 coupled between a second high-side output terminal HOFF and a second high-side power supply node HVEE, and an open-line detection circuit 103a connected to the first high-side output terminal HON. Those skilled in the art will understand that... Figure 3-4 The open-line detection circuit 103A or 103B shown can be used as an embodiment of the open-line detection circuit 103a.

[0073] The first high-side output terminal HON and the second high-side output terminal HOFF are configured to be coupled to the control terminal G1 of the first power switch MQ1 to provide a first switch drive signal DROUT to control the switching operation of the first power switch MQ1. In one embodiment, the first high-side output terminal HON is used to turn on the first power switch MQ1, while the second high-side output terminal HOFF is used to turn off the first power switch MQ1. Before the switching operation of the first power switch MQ1, the open-circuit detection circuit 103a and the first high-side output terminal HON are used to detect the open circuit status between the first high-side output terminal HON (or the second high-side output terminal HOFF) and the control terminal G1 of the first power switch MQ1. Further, the open-circuit detection circuit 103a provides a fault signal FLAG based on the detected open circuit status.

[0074] In one embodiment, the high-side power ground HS of the first gate drive region 210 is used as a power reference terminal and coupled to a floating node between the first power switch MQ1 and the second switch MQ2, instead of being coupled to the system power ground PGND.

[0075] In one embodiment, the first gate drive region 210 may further include a clamping circuit 108. The clamping circuit 108 is coupled between the second high-side output terminal HOFF and the high-side power ground terminal HS to prevent the potential of the second high-side output terminal HOFF from exceeding a preset value. In one embodiment, the clamping circuit 108 includes, for example... Figure 5 The resistive element shown.

[0076] In one embodiment, the first gate drive region 210 may further include a charge pump circuit 1091. The charge pump circuit 1091 is coupled to a first high-side power supply node HVDD and a high-side power ground terminal HS, providing a second high-side supply voltage to a second high-side power supply node HVEE to control the turn-off speed of the first power switch MQ1. The charge pump circuit 1091 includes a first capacitor C1 located outside the bridge drive circuit 200 to implement the charge pump function of the charge pump circuit 1091. Figure 5 As shown, the first end of the first capacitor C1 is connected to the terminal HVP of the bridge drive circuit 200, and the second end of the first capacitor C1 is connected to the terminal HVN of the bridge drive circuit 200.

[0077] The second gate driving region 220 may include a primary-side control circuit 120a. The primary-side control circuit 120a may be... Figure 2 This is a modified embodiment of the primary-side control circuit 120 shown. The primary-side control circuit 120a is located in the second gate drive region 220 and may include a second undervoltage protection circuit UVLO2, a level offset circuit 122a, and a control signal processing circuit 123a.

[0078] In one embodiment, the level offset circuit 122a is used to convert a specific logic signal from a low-voltage application to a high-voltage application. In another embodiment, the control signal processing circuit 123a is used to set an internal delay so that the set logic state of the first pulse width modulation signal PWMIN+ does not overlap with the set logic state of the second pulse width modulation signal PWMIN-.

[0079] In addition, the control signal processing circuit 123a is also used to provide short pulse signals to the bistable circuit 1051, such as an RS flip-flop, so as to provide a low-side pulse width modulation signal to the drive control circuit 106a at the output of the bistable circuit 1051.

[0080] The second gate drive region 220 may include a voltage regulator circuit 1053, an AND gate circuit 1052, and a third undervoltage protection circuit UVLO3 (labeled 104a). The voltage regulator circuit 1053 receives the supply voltage VCC and converts it into a first low-side supply voltage, which is then supplied to the first low-side supply node LVDD. The third undervoltage protection circuit UVLO3 detects whether the first low-side supply voltage is less than a third undervoltage threshold V before an open-line detection is performed. UV3 .

[0081] In one embodiment, the second gate driving region 220 includes: a first output switch circuit 101a coupled between a first low-side power supply node LVDD and a first low-side output terminal LON; a second output switch circuit 102a coupled between a second low-side output terminal LOFF and a second low-side power supply node LVEE; and an open-line detection circuit 103b connected to the first low-side output terminal LON. Those skilled in the art will understand that... Figure 3-4 The open-line detection circuit 103A or 103B shown can be used as an embodiment of the open-line detection circuit 103b.

[0082] The first low-side output terminal LON and the second low-side output terminal LOFF are adapted to be coupled to the control terminal G2 of the second power switch MQ2 to provide a second switch drive signal DROUT1 to control the switching operation of the second power switch MQ2. In one embodiment, the first low-side output terminal LON is used to turn on the second power switch MQ2, while the second low-side output terminal LOFF is used to turn off the second power switch MQ2. Before the switching operation of the second power switch MQ2, the open-circuit detection circuit 103b and the first low-side output terminal LON are used to detect the open circuit status between the first low-side output terminal LON (or the second low-side output terminal LOFF) and the control terminal G2 of the second power switch MQ2. Further, the open-circuit detection circuit 103b provides a fault signal FLAG1 based on the detected open circuit status.

[0083] In one embodiment, the first switch drive signal DROUT and the second switch drive signal DROUT1 are configured to control the first power switch MQ1 and the second power switch MQ2 to be turned on or off in a complementary manner.

[0084] When there is an open circuit between the second high-side output terminal HOFF and the control terminal G1 of the first power switch MQ1, the first power switch MQ1 cannot be turned off. Similarly, when there is an open circuit between the second low-side output terminal LOFF and the control terminal G2 of the second power switch MQ2, the second power switch MQ2 cannot be turned off. If either the first power switch MQ1 or the second power switch MQ2 cannot be turned off, a shoot-through problem will occur between the complementary first power switches MQ1 and the second power switches MQ2. Due to the presence of open circuit detection circuits 103a and 103b, corresponding open circuit detection can be provided to prevent the shoot-through problem in the half-bridge circuit 10.

[0085] In one embodiment, the second gate drive region 220 further includes a clamping circuit 108a connected to the second low-side output terminal LOFF and the low-side power supply ground terminal PGND, for preventing the voltage of the second low-side output terminal LOFF from exceeding a predetermined level.

[0086] In one embodiment, the second gate drive region 220 further includes a charge pump circuit 1092. The charge pump circuit 1092 is coupled to the first low-side power supply node LVDD and the low-side power ground terminal PGND, providing a second low-side supply voltage to the second low-side power supply node LVEE to control the turn-off speed of the second power switch MQ2. The charge pump circuit 1092 includes a second capacitor C2 located outside the bridge drive circuit 200 to implement the charge pump function of the charge pump circuit 1092. Figure 5 As shown, the first end of the second capacitor C2 is connected to the terminal LVP of the bridge drive circuit 200, and the second end of the second capacitor C2 is connected to the terminal LVN of the bridge drive circuit 200.

[0087] Figure 6 This is a flowchart of a method 700 for use in a gate drive circuit according to an embodiment of the present invention. Method 700 includes the following steps.

[0088] In step 701, a first supply voltage and a second supply voltage are established. The first supply voltage is provided to the first power supply node of the gate drive circuit, and the second supply voltage is provided to the second power supply node of the gate drive circuit. A first output switch circuit is coupled between the first power supply node and the first output terminal of the gate drive circuit. A second output switch circuit is coupled between the second output terminal of the gate drive circuit and the second power supply node.

[0089] In step 702, the second output switch circuit coupled between the second output terminal of the gate drive circuit and the second power supply node is in a low impedance state.

[0090] In step 703, an open wire detection is initiated within the detection time window.

[0091] In step 704, the open wire connection between the first output terminal or the second output terminal and the power switch control terminal is detected, and a fault signal is generated based on the open wire connection.

[0092] In one embodiment, an open circuit is indicated when the voltage at the first output terminal is greater than a first threshold voltage. In another embodiment, a conduction path is provided between the first output terminal and a third voltage node, and an open circuit is indicated when the current flowing through the conduction path is positive.

[0093] In step 705, when an open circuit occurs, the switching operation of the power switch is disabled. Alternatively, when no open circuit is detected, a switch drive signal with a set state is allowed to be provided to the control terminal of the power switch to allow the power switch to turn on, as shown in step 706.

[0094] The advantages of the various embodiments of the present invention are not limited to those described above. Other advantages of the various embodiments of the present invention will become clearer after reading the entire specification and studying the specific details in the accompanying drawings.

[0095] Note that in the flowchart described above, the functions marked in the boxes can also be arranged differently. Figure 6 The sequence shown occurs. For example, two consecutively represented boxes can actually be executed in essentially parallel order, and they can sometimes be executed in reverse order, depending on the specific function involved.

[0096] In the specification, terms such as "first" and "second" may be used merely to distinguish one entity or action from another, and do not necessarily imply any relationship or order between these entities or actions. Numerical orders such as "first," "second," and "third" refer only to different individuals among a plurality and do not imply any order or sequence, unless specifically defined in the language of the claims. The order of the text in any claim does not imply that the processing steps must be performed in a provisional or logical order according to such order, unless specifically specified in the language of the claims. Without departing from the scope of the invention, these processing steps may be interchanged in any order, provided that such interchange does not contradict the language of the claims and does not result in logical absurdity.

[0097] The specific embodiments described above are merely illustrative of the invention and are not exhaustive, nor are they intended to limit the scope of the invention. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of elements in the embodiments can be understood by those skilled in the art. Other variations and modifications to the embodiments disclosed in this invention do not depart from the spirit and scope of protection of this invention.

Claims

1. A gate driving circuit, comprising: The first power supply node is used to receive the first power supply voltage; The second power supply node is used to receive a second power supply voltage that is lower than the first power supply voltage; The first output switching circuit is coupled between the first power supply node and the first output terminal of the gate drive circuit. The second output switch circuit is coupled between the second output terminal of the gate drive circuit and the second power supply node, wherein the first output terminal and the second output terminal of the gate drive circuit are configured to be coupled to the control terminal of a power switch to provide a switch drive signal. as well as An open-wire detection circuit is coupled to the first output terminal. Before the power switch switches, the open-wire detection circuit and the first output terminal together detect whether there is an open wire between the first output terminal or the second output terminal and the control terminal of the power switch.

2. The gate driving circuit of claim 1, wherein the gate driving circuit enables the open-line detection circuit during a detection time window, wherein the detection time window is enabled when both the first supply voltage and the second supply voltage are established and the second output switching circuit is in a low impedance state.

3. The gate drive circuit of claim 2, wherein the open-line detection circuit is configured to compare the voltage of the first output terminal with a first threshold voltage, and during the detection time window, indicate the open-line condition when the voltage of the first output terminal exceeds the first threshold voltage.

4. The gate drive circuit of claim 2, wherein the open-line detection circuit is configured to provide a conduction path between a first output terminal of the gate drive circuit and a third power supply node, and to indicate the open-line condition when the current flowing through the conduction path is positive during the detection time window.

5. The gate drive circuit of claim 4, wherein the voltage of the third power supply node is greater than the second power supply voltage and less than the turn-on threshold voltage of the power switch.

6. The gate driving circuit of claim 1, further comprising: One input terminal is used to receive a pulse width modulation signal, which has a logic high level and a logic low level; A drive control circuit is used to control the switch drive signal based on the pulse width modulation signal; as well as A reference terminal is configured as the reference ground terminal of the drive control circuit.

7. The gate driving circuit of claim 6, further comprising: The charge pump circuit provides a second supply voltage to the second power supply node based on the first supply voltage and the voltage at the reference terminal.

8. The gate driving circuit as claimed in claim 1, wherein: When this open-circuit condition is detected, the gate drive circuit disables the switching operation of the power switch; as well as When the open circuit is not detected, the gate drive circuit allows the power switch to be turned on.

9. A gate driving circuit, comprising: The first terminal is used to receive a pulse width modulation signal, which includes a logic high level and a logic low level. The second terminal is used to receive the first power supply voltage; The third terminal is used to receive a second supply voltage that is lower than the first supply voltage. A first output switch circuit is coupled between the second terminal and a fourth terminal of the gate drive circuit; The second output switch circuit is coupled between a fifth terminal and the third terminal of the gate drive circuit, wherein the fourth terminal and the fifth terminal are configured to be coupled to the control terminal of a power switch to provide a switch drive signal to control the power switch to turn on and off based on the pulse width modulation signal. as well as An open-wire detection circuit is coupled to the fourth terminal, wherein before the power switch switches, the open-wire detection circuit and the fourth terminal together detect whether there is an open wire between the fourth terminal or the fifth terminal and the control terminal of the power switch.

10. The gate driving circuit of claim 9, further comprising: An isolation region is provided to provide capacitive isolation between a primary side and a secondary side of the gate drive circuit; A drive control circuit controls the drive control signal based on the pulse width modulation signal; as well as The sixth terminal is configured as the reference ground terminal of the drive control circuit.

11. The gate driving circuit of claim 10, further comprising: The seventh terminal is located on the primary side of the gate drive circuit and is used as the primary side reference ground terminal of the primary side circuit of the gate drive circuit. The eighth terminal is located on the primary side of the gate drive circuit and is used as the primary side power supply terminal of the gate drive circuit. as well as The fourth, fifth, and sixth terminals are all located on the secondary side of the gate drive circuit.

12. The gate drive circuit of claim 10, wherein the drive control circuit is further configured to enable the open-line detection circuit during a detection time window, wherein, The detection time window is enabled when both the first and second supply voltages are established and the second output switching circuit is in a low impedance state.

13. The gate drive circuit of claim 12, wherein the open-line detection circuit is configured to compare the voltage of the fourth terminal with a first threshold voltage, and indicate the open-line condition when the voltage of the fourth terminal is greater than the first threshold voltage within the detection time window.

14. The gate drive circuit of claim 12, wherein the open-circuit detection circuit is configured to provide a conduction path between the fourth terminal and the sixth terminal, and, during the detection time window, indicate the open-circuit condition when the current flowing through the conduction path is positive; and The first supply voltage is positive relative to the voltage at the sixth terminal, and the second supply voltage is negative relative to the voltage at the sixth terminal.

15. The gate driving circuit of claim 10, further comprising: A clamping circuit is coupled between the fifth and sixth terminals of the gate drive circuit to prevent the voltage at the fifth terminal from exceeding a preset threshold.

16. The gate drive circuit of claim 10, wherein: When the open circuit is detected, the drive control circuit disables the switching operation of the power switch. as well as When the open circuit is not detected, the drive control circuit allows the power switch to be turned on.

17. The gate driving circuit of claim 11, further comprising: A charge pump circuit, coupled to the second terminal and the sixth terminal, provides a second supply voltage based on the first supply voltage and the voltage at the sixth terminal to control the power switch to turn off, wherein the second supply voltage is negative relative to the voltage at the sixth terminal.

18. A bridge drive circuit, comprising: One reference end; The first power supply node is used to receive a positive power supply voltage that is positive relative to the reference terminal voltage; The second power supply node is used to receive a negative power supply voltage that is negative relative to the reference terminal voltage; The first output switching circuit is coupled between the first power supply node and the first output terminal of the bridge drive circuit; The second output switch circuit is coupled between the second output terminal of the bridge drive circuit and the second power supply node, wherein the first output terminal and the second output terminal of the bridge drive circuit are configured together to be coupled to a control terminal of a power switch to provide a switch drive signal to control the switching operation of the power switch. as well as An open-wire detection circuit is coupled to the first output terminal of the bridge drive circuit. Before the power switch switches, the open-wire detection circuit and the first output terminal together detect whether there is an open wire between the first output terminal or the second output terminal and the control terminal of the power switch.

19. The bridge drive circuit as described in claim 18, wherein: The reference terminal is used as a floating node between a high-side power switch and a low-side power switch, which are connected in a half-bridge configuration; and This power switch is the high-side power switch.

20. The bridge drive circuit as described in claim 18, wherein: The reference terminal is a power ground terminal of the bridge drive circuit, wherein the half-bridge circuit includes a high-side power switch coupled between a power supply node and a floating node, and a low-side power switch coupled between the floating node and the power ground terminal; and This power switch is the low-side power switch of the half-bridge circuit.

21. The bridge drive circuit of claim 18 is further configured to enable the open-line detection circuit during a detection time window, wherein the detection time window is enabled when both the first supply voltage and the second supply voltage are established and the second output switching circuit is in a low-impedance state.

22. The bridge drive circuit of claim 21, wherein the open-line detection circuit is configured to compare the voltage of the first output terminal with a first threshold voltage, and during the detection time window, indicate the open-line condition when the voltage of the first output terminal is greater than the first threshold voltage.

23. The bridge drive circuit as described in claim 21, wherein: The open-circuit detection circuit is configured to provide a conduction path between the first output terminal and a third power supply node, and to indicate the open-circuit condition when the current flowing through the conduction path is positive during the detection time window. as well as The voltage of the third power supply node relative to the reference terminal voltage is less than the turn-on threshold voltage of the power switch.

24. The bridge drive circuit as described in claim 21, wherein: The open-circuit detection circuit is configured to provide a conduction path between the first output terminal and the reference terminal, and to indicate the open-circuit condition when the current flowing through the conduction path is positive during the detection time window.

25. The bridge drive circuit of claim 18, further comprising: A charge pump circuit, coupled to the first power supply node and the reference terminal, is configured to provide a second power supply voltage to control the power switch to turn off.

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