Single ended driver and bidirectional overcurrent protection for thermoelectric coolers

Abstract

This specification relates to single-ended driver and bidirectional overcurrent protection for thermoelectric coolers. According to embodiments, an electronic circuit (100) includes: a first supply terminal (212) and a second supply terminal (106); a first inductor terminal (SW1) and a second inductor terminal (SW2); an output terminal (VOUT); a first switch (202) coupled between the first supply terminal (212) and the first inductor terminal (SW1); a second switch (204) coupled between the first inductor terminal (SW1) and the second supply terminal (106); a third switch (206) coupled between the first supply terminal (212) and the second inductor terminal (SW2); a fourth switch (208) coupled between the second inductor terminal (SW2) and the output terminal (VOUT); and a controller.

Description

Cross-reference to related applications

[0001] This patent application claims the benefit and priority of Indian Provisional Patent Application No. 202541034510, filed on April 8, 2025, and Indian Provisional Patent Application No. 202541034609, filed on April 8, 2025, which are hereby incorporated herein by reference in their entirety. Technical Field

[0002] This specification generally relates to electronic systems and methods, and in certain embodiments, to single-ended drivers and bidirectional overcurrent protection for thermoelectric coolers. Background Technology

[0003] In optical communication systems, laser diodes are used to transmit signals across fiber optic cables. To ensure stable laser characteristics, the temperature of the laser diode must be maintained at a relatively constant level during operation. For example, in telecommunications applications, the temperature error of the laser diode relative to the target is less than five millidegree Celsius (<5 m°C). To control the temperature of the laser diode, telecommunications systems include thermoelectric cooler (TEC) components. The TEC heats or cools the laser diode according to the direction of the current flowing through it. To ensure the temperature stability of the laser diode, the TEC is coupled to a control loop that regulates the heat generated or absorbed by the TEC. Summary of the Invention

[0004] According to an embodiment, an electronic circuit includes: first and second supply terminals; first and second inductor terminals; an output terminal; a first switch coupled between the first supply terminal and the first inductor terminal; a second switch coupled between the first inductor terminal and the second supply terminal; a third switch coupled between the first supply terminal and the second inductor terminal; a fourth switch coupled between the second inductor terminal and the output terminal; and a controller configured to: close the fourth switch, open the third switch, and operate the first and second switches in alternating phases when the output voltage at the output terminal is higher than a first threshold; close the second switch, open the first switch, and operate the third and fourth switches in alternating phases when the output voltage is lower than a second threshold lower than the first threshold; and operate the first and fourth switches according to a first clock signal and the second and third switches according to a second clock signal that does not overlap with the first clock signal when the output voltage is between the first and second thresholds.

[0005] According to an embodiment, an electronic circuit includes: first and second supply terminals; first and second inductor terminals; an output terminal coupled to the second inductor terminal; a first transistor having a current path coupled between the first supply terminal and the first inductor terminal; a second transistor having a current path coupled between the first inductor terminal and the second supply terminal; and a current sensing circuit including: a third transistor having a control terminal coupled to a control terminal of the first transistor and a first current path terminal coupled to the first supply terminal; a first amplifier having a first input coupled to a second current path terminal of the third transistor and a second input coupled to the current path of the first transistor; a fourth transistor having a first current path terminal coupled to the second current path terminal of the third transistor and a control terminal coupled to the output of the first amplifier; a second amplifier having a first input coupled to the second current path terminal of the fourth transistor; and a first resistor coupled to the second current path terminal of the fourth transistor.

[0006] According to an embodiment, a method includes: operating first and second switches at a fixed switching frequency to regulate an output voltage at an output terminal, wherein the first switch is coupled between a first supply terminal and a first inductor terminal, wherein the second switch is coupled between the first inductor terminal and a second supply terminal, wherein an inductor is coupled between the first inductor terminal and the second inductor terminal, and wherein the output terminal is coupled to the second inductor terminal; turning off the first switch and turning on the second switch in response to an inductor current through the inductor being higher than a first current threshold to initiate a first discharge phase of the inductor; maintaining the first switch off and the second switch on during the first discharge phase of the inductor; and restarting operation of the first and second switches at the fixed switching frequency in response to the inductor current dropping below a second current threshold lower than the first current threshold to exit the first discharge phase.

[0007] According to an embodiment, an electronic circuit includes: first and second supply terminals; first and second inductor terminals; an output terminal coupled to the second inductor terminal; a first transistor having a current path coupled between the first supply terminal and the first inductor terminal; a second transistor having a current path coupled between the first inductor terminal and the second supply terminal; and a current sensing circuit including: a third transistor having a first current path terminal, a second current path terminal, and a control terminal coupled to a control terminal of the second transistor, the second current path terminal being coupled to the second supply terminal; a first amplifier having a first input coupled to the first current path terminal of the third transistor and a second input coupled to the current path of the second transistor; a fourth transistor having a first current path terminal coupled to the first current path terminal of the third transistor and a control terminal coupled to the output of the first amplifier; a second amplifier having a first input coupled to the second current path terminal of the fourth transistor; and a first resistor coupled to the second current path terminal of the fourth transistor. Attached Figure Description

[0009] To more fully understand this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is a block diagram of an example system including an example thermoelectric cooler (TEC) element and an example driver power stage for the TEC element, according to embodiments of the present disclosure.

[0011] Figure 2 According to embodiments of this disclosure Figure 1 A schematic diagram of the driver power stage;

[0012] Figure 3 It is in forward mode (also known as buck mode) according to embodiments of this disclosure. Figure 2 A schematic diagram of an example configuration of the driver power stage;

[0013] Figure 4 It is in reverse mode (also known as inverted buck-boost mode) according to embodiments of this disclosure. Figure 2 A schematic diagram of an example configuration of the driver power stage;

[0014] Figure 5 According to embodiments of this disclosure Figure 2 A schematic diagram of the driver power stage, wherein the first to fourth switches are implemented by an example N-channel metal-oxide-semiconductor (NMOS) transistor;

[0015] Figure 6According to embodiments of this disclosure Figure 2 A schematic diagram of the driver power stage, wherein the second and fourth switches are implemented by example NMOS transistors, and the first and third switches are implemented by example P-channel metal-oxide-semiconductor (PMOS) transistors;

[0016] Figure 7 It is a description Figure 2 Timing diagram of possible inductor currents in the driver power stage;

[0017] Figure 8 This is a block diagram of an example system according to embodiments of the present disclosure, which includes components for... Figure 2 Example controller for the driver power stage and example overcurrent (OI) current sensor subsystem for the driver power stage;

[0018] Figure 9 According to embodiments of this disclosure Figure 8 A schematic diagram of the high-side supply mode sensor;

[0019] Figure 10 It is according to the embodiments of this disclosure for use Figure 8 A schematic diagram of an example calibration circuit for a high-side supply mode OI comparator;

[0020] Figure 11 According to embodiments of this disclosure Figure 8 A schematic diagram of the low-side supply mode sensor;

[0021] Figure 12 According to embodiments of this disclosure Figure 8 Low-side absorption mode sensor and for Figure 8 A schematic diagram of an example calibration circuit for a low-side absorption mode OI comparator;

[0022] Figure 13 According to embodiments of this disclosure Figure 8 A schematic diagram of a high-side absorption mode sensor;

[0023] Figure 14 According to embodiments of this disclosure Figure 8 A schematic diagram of the supply mode state machine;

[0024] Figure 15 According to embodiments of this disclosure Figure 8 A schematic diagram of the absorption mode state machine;

[0025] Figure 16 This is a timing diagram according to an embodiment of the present disclosure, depicting the situation in supply mode during buck mode operation. Figure 2 Examples of undercurrent (UI) protection and OI protection for the driver power stage;

[0026] Figure 17 This is a timing diagram according to an embodiment of the present disclosure, depicting the absorption mode during intermediate mode operation. Figure 2 Example UI protection and OI protection for the driver power level; and

[0027] Figure 18 This timing diagram, based on an embodiment of the present disclosure, depicts the absorption mode during inverted buck-boost mode operation. Figure 2 Example UI protection and OI protection for the driver power level.

[0028] Unless otherwise indicated, the corresponding numbers and symbols in the different figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments, and the figures are not necessarily drawn to scale. Detailed Implementation

[0029] The manufacture and use of the disclosed embodiments are discussed in detail below. However, it should be understood that this disclosure provides many applicable inventive concepts that may be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of particular ways of making and using this disclosure and do not limit the scope of this disclosure.

[0030] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments based on the description. These embodiments can be obtained without one or more of the specific details described or by utilizing other methods, components, materials, etc. In some cases, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. The terms "embodiment" or "example" used in this specification indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" or "in one example," which may appear in different places in this specification, do not necessarily refer entirely to the same embodiment. Furthermore, specific forms, structures, or features may be combined in any suitable manner in one or more embodiments.

[0031] For illustration, several aspects of this disclosure are described below with reference to example applications. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the order in which actions or events are shown, as some actions may be performed in a different order and / or simultaneously with other actions or events.

[0032] In optical communication systems, laser diodes are used to transmit signals across fiber optic cables. To ensure stable laser characteristics, a driver power stage controls the voltage on a thermoelectric cooler (TEC) element or the current through the TEC element to maintain the laser diode at a relatively constant temperature (e.g., <5 m°C difference from the target temperature). A TEC element is a solid-state device used to transfer heat from one side of the TEC element to the other, based on the electrical energy consumed by the TEC element. For example, the TEC element uses the thermoelectric effect, specifically the Peltier effect, to transfer heat from one side of the TEC element to the other, depending on the polarity of the TEC element relative to the applied voltage or current.

[0033] The TEC element is driven by a differential driver power stage. For example, each of the two terminals of the TEC element is coupled to a supply terminal of the driver power stage, and the driver power stage controls the voltage at each supply terminal to control the current through the TEC element and the voltage across the TEC element. Driving the TEC element via a differential supply terminal and lacking an inductor-capacitor (LC) filter at the output increases the power dissipation of the TEC element and thus reduces the efficiency of power transfer to the TEC element. In laser diode applications, the driver power stage of the TEC element is expected to generate a control voltage across the TEC element while achieving high power transfer efficiency (e.g., >90%).

[0034] To improve the efficiency of a differential driver power stage, an LC filter can be added to the supply terminals of the driver power stage. However, the added LC filter occupies additional board space and increases the total monetary cost of the TEC system (e.g., the TEC driver (containing the driver power stage) and TEC components). Furthermore, the equivalent series resistance (ESR) of the inductor added to the LC filter increases the power losses of the TEC system. Other differential driver power stages contain only a single LC filter, reducing the amount of board space occupied and the monetary cost of the TEC system. However, due to the asymmetric drive architecture, such differential driver power stages exhibit glitches at zero crossings.

[0035] Zero-crossing glitches refer to overshoots or undershoots in the target voltage or current when the voltage on or through the TEC element transitions across zero. Zero-crossing glitches can pose numerous challenges at the application level. For example, voltage or current overshoots during zero-crossing propagate to the TEC element and cause transient temperature glitches in the laser diode, large enough to be detected as telecommunications interference. Voltage or current overshoots can also couple to the silicon substrate or printed circuit board (PCB) traces and act as common-mode noise, which couples to the negative temperature coefficient (NTC) of the thermistor used to monitor the laser diode's temperature. Common-mode noise coupled to the NTC causes transient errors in the thermistor-based temperature measurements.

[0036] Hardware filters can be added to prevent glitches at zero crossings. However, adding hardware filters requires additional board space, which is extremely limited in optical transceivers. Furthermore, adding hardware filters increases the monetary cost of the TEC system. Another method to prevent glitches at zero crossings is to reduce the operating frequency of the differential driver power stage during zero crossings. In this way, the driver power stage (compared to normal operation) slowly transitions the voltage or current supplied by the driver power stage to the target voltage or current. This method is empirical or ad-hoc and requires a long development time to ensure reliable operation.

[0037] The embodiments disclosed herein are described in a specific context, such as a driver power stage for a TEC element. Some embodiments may be used in other circuits, such as power electronic circuits, driver circuits for power transistors, and / or monitoring circuits for power transistors. Some embodiments include a single-ended driver power stage for controlling the TEC element in three operating modes based on the output voltage from the driver power stage. Therefore, some embodiments advantageously meet the target power delivery efficiency for laser diode applications while reducing TEC system cost, reducing board space consumption, and achieving glitch-free zero crossings. Thus, some embodiments advantageously reduce TEC system cost, reduce the number of off-chip components, and reduce board area consumption and overall system size.

[0038] In addition to monitoring overcurrent events during the charging phase to control the inductor current in the driver power stage of the TEC system, some embodiments also monitor undercurrent events during the discharging phase. In some embodiments, current sensing does not require off-chip components or additional voltage sensing pins to sense the inductor current. In some embodiments, current sensing does not use series loss components to monitor the current, thus improving the efficiency of the TEC system.

[0039] Some embodiments include calibration as part of overcurrent monitoring to reduce the DC error of overcurrent detection to a minimum (e.g., 25 mA). In some embodiments, calibration is performed without drawing large inductor currents, which reduces power loss during calibration. By avoiding drawing large inductor currents during calibration, some embodiments effectively reduce the time and cost required to perform calibration. For example, by avoiding drawing large inductor currents during calibration, test benches evaluating the example TEC systems described herein may not require additional instruments to draw larger currents. Advantageously, in some embodiments, calibration allows overcurrent monitoring to be performed using comparators without extremely low offset. In some embodiments, calibration is unaffected by switching noise. Therefore, overcurrent monitoring according to some embodiments is highly reliable under a wide range of operating conditions. According to some embodiments, overcurrent monitoring is suitable for both fixed-frequency and variable-frequency (e.g., pulse-skipping modulation) operation and can detect overcurrent in the inductor cyclically in both positive and negative directions.

[0040] Figure 1 This is a block diagram of a system 100 according to an embodiment of the present disclosure. System 100 includes a thermoelectric cooler (TEC) element 102 and a driver power stage 104 for the TEC element 102. Figure 1 In the example, driver power stage 104 is a single-ended driver power stage used to control the heat transferred through TEC element 102 in three operating modes based on the output voltage (VOUT) from driver power stage 104. For example, the output voltage (VOUT) is measured relative to example common terminal 106. Figure 1 In this example, common terminal 106 is at zero volts (V). For example, common terminal 106 is an analog ground terminal, such as a chassis ground terminal. In some examples, common terminal 106 is referred to as a supply terminal or a reference terminal.

[0041] exist Figure 1In the example shown, the driver power stage 104 controls the heat transferred through the TEC element 102 by controlling the voltage on the TEC element 102 or the current through the TEC element 102. For example, based on the polarity of the TEC element 102, the driver power stage 104 can use the TEC element 102 to cool or heat the laser diode by changing the voltage on the TEC element 102 from negative to positive and vice versa. The polarity of the TEC element 102 refers to the way the TEC element 102 is coupled to the driver power stage 104. For example, if the positive terminal of the TEC element 102 is coupled to the output terminal of the driver power stage 104 and the negative terminal of the TEC element 102 is coupled to the common terminal 106, then the TEC element 102 has a positive polarity. In the case of positive polarity, the TEC element 102 acts as a heat source when a positive voltage or current is applied and as a heat sink when a negative voltage or current is applied.

[0042] Alternatively, if the positive terminal of TEC element 102 is coupled to common terminal 106 and the negative terminal of TEC element 102 is coupled to the output terminal of driver power stage 104, then TEC element 102 has a negative polarity. With negative polarity, TEC element 102 acts as a heat sink when a positive voltage or current is applied, and as a heat source when a negative voltage or current is applied. With either polarity, driver power stage 104... Figure 3 In the example, the TEC element 102 is controlled in three operating modes. These three operating modes include buck mode, inverting buck-boost mode, and intermediate mode.

[0043] For example, when the output voltage is greater than a first threshold (e.g., When the output voltage is less than a second threshold (e.g., ...), the driver power stage 104 controls the TEC element 102 in buck operating mode (also known as forward mode). When the output voltage is between the first and second thresholds (e.g., ...), the driver power stage 104 controls the TEC element 102 in an inverted buck-boost operating mode (also known as reverse mode). When the driver power stage 104 controls the TEC element 102 in intermediate operating mode, the driver power stage 104 controls the TEC element 102.

[0044] Figure 2 According to embodiments of this disclosure Figure 1 A schematic diagram of the driver power stage 104. In Figure 2 In the example, the driver power stage 104 includes a first switch 202, a second switch 204, a third switch 206, and a fourth switch 208. Figure 2In the example, inductor 210 is coupled between nodes SW1 and SW2. For example, node SW1 is between switches 202 and 204, and node SW2 is between switches 206 and 208. Therefore, nodes SW1 and SW2 are referred to as the first and second inductor terminals in some examples.

[0045] exist Figure 2 In the example shown, switches 202 and 206 (labeled S1 and S3, respectively) are high-side switches coupled to supply terminal 212 (labeled AVDD). For example, supply terminal 212 can be at a voltage between 3 V and 5.5 V. Furthermore, switch 204 (labeled S2) is a low-side switch coupled to common terminal 106 (labeled AVSS). Figure 2 In the example, switch 208 (labeled S4) is a floating switch coupled to the load. For example, in Figure 2 In this context, the load is TEC element 102. Furthermore, in... Figure 2 In the example, the output terminal of the driver power stage 104 is coupled to the example capacitor 214, thereby smoothing the output voltage (VOUT) to the TEC element 102.

[0046] As described above, the driver power stage 104 controls the TEC element 102 in three operating modes: buck mode, inverting buck-boost mode, and intermediate mode. Figure 2 In the example, the intermediate operating mode involves the controller (described below) operating the driver power stage 104 in two stages using waveforms PHI1 (also referred to as PHI1) and PHI2 (also referred to as PHI2). For example, waveforms PHI1 and PHI2 represent first and second clock signals that do not overlap (e.g., to avoid current flow from supply terminal 212 to common terminal 106). When operating in intermediate mode, driver power stage 104 generates positive and negative voltages. Equation 1 below shows the DC transfer relationship between the output voltage (VOUT) from driver power stage 104 and the voltage (AVDD) at supply terminal 212 in intermediate mode. In Equation 1, D represents the duty cycle of waveform PHI1. Waveform PHI2 is a complementary waveform to PHI1, but with an offset to create a dead time between PHI1 and PHI2.

[0047]

[0048] Equation 1

[0049] exist Figure 2In the example shown, for duty cycles greater than 0.5 (e.g., D > 0.5), the output voltage from driver power stage 104 is positive (e.g., VOUT > 0V). For duty cycles less than 0.5 (e.g., D < 0.5), the output voltage from driver power stage 104 is negative (e.g., VOUT < 0V). Figure 2 In the example, for a duty cycle of 0.5 (e.g., D=0.5), the output voltage from driver power stage 104 is zero volts (VOUT=0V). Therefore, to ensure no glitches at the zero crossing, the controller for driver power stage 104 (described below) sets the duty cycle to 0.5 as the zero-crossing event approaches. A duty cycle closer to 1 or 0 can cause glitches at the zero crossing because the transition is affected by the finite rise and fall times of the PHI1 and PHI2 waveforms.

[0050] exist Figure 2 In the example shown, the open-loop characteristic of driver power stage 104 is monotonic, with no discontinuities near the zero-crossing point. For example, there is a linear relationship between the duty cycle and the output voltage (VOUT), where the output voltage (VOUT) increases or decreases linearly as the duty cycle increases or decreases. Therefore, driver power stage 104 provides glitch-free zero crossing. Glitch-free zero crossing means that when the voltage on the TEC element or the current through the TEC element transitions across zero, the target voltage on the TEC element or the target current through the TEC element is reached, without overshoot or undershoot, or with acceptable low overshoot or undershoot. The monotonic characteristic of driver power stage 104 with no discontinuities at the zero-crossing point, along with the feedback loop from TEC element 102 to the thermistor and controller (described below), ensures seamless zero crossing of the temperature output from TEC element 102.

[0051] exist Figure 2 In the example shown, if the driver power stage 104 operates only in intermediate mode, then the average current through inductor 210 ( The current will be greater than that passing through TEC element 102. This is because the switches 202-208 (e.g., Therefore, the power dissipated by the driver power stage 104 will increase, which will reduce the efficiency of the driver power stage 104. Advantageously, in some embodiments, the efficiency of the driver power stage 104 is increased by operating the driver power stage 104 in three operating modes.

[0052] exist Figure 2In the example shown, when the output voltage is greater than a first threshold, the driver power stage 104 controls the TEC element 102 in buck mode (also known as forward mode). For example, when the controller (described below) changes the duty cycle of switches 202-208 (e.g., in intermediate mode) and the output voltage increases above the first threshold, the controller switches the operating mode of the driver power stage 104 to buck mode. Figure 2 In the example, the first threshold is selected based on the minimum duty cycle that the driver power stage 104 can support in buck mode. For example, the minimum duty cycle that the driver power stage 104 can support in buck mode is 0.1 (e.g., D=0.1).

[0053] exist Figure 2 In the example shown, the first threshold is 10% of the voltage at supply terminal 212 (e.g., Therefore, driver power stage 104 generates a positive voltage in buck mode. By switching driver power stage 104 to buck mode after crossing a threshold positive voltage, the controller ensures that driver power stage 104 operates in buck mode over a wider range of positive voltages and limits the range of positive voltages for driver power stage 104 to operate in intermediate modes. Therefore, the efficiency of driver power stage 104 increases when a positive voltage is generated.

[0054] Figure 3 It is in forward mode (also known as buck mode) according to embodiments of this disclosure. Figure 2 A schematic diagram of the configuration 300 of the driver power stage 104. In forward mode, node SW2 is always coupled to TEC element 102, while node SW1 switches between voltages (e.g., AVDD) at supply terminal 212 and voltages (e.g., AVSS) at common terminal 106 in alternating phases. For example, in forward mode, switch 206 is open, switch 208 is closed, and switches 202 and 204 switch between open and closed in response to PHI1 and PHI2 waveforms, respectively. Therefore, the current (IL) through inductor 210 flows from node SW1 to node SW2 (e.g., positive inductor current, also known as supply mode). In forward mode, the average current through inductor 210 is equal to the current through TEC element 102 (e.g., ...). In some examples, the switch is open or closed when it does not conduct current, and it is closed or connected when it conducts current.

[0055] Return to Figure 2When the output voltage is below the second threshold, the driver power stage 104 controls the TEC element 102 in an inverting buck-boost mode (also known as reverse mode). For example, when the controller (described below) changes the duty cycle of switches 202-208 (e.g., in intermediate mode) and the output voltage decreases below the second threshold, the controller switches the operating mode of the driver power stage 104 to an inverting buck-boost mode. Figure 2 In the example, the second threshold is selected based on the minimum duty cycle that the driver power stage 104 can support in inverted buck-boost mode. For example, the minimum duty cycle that the driver power stage 104 can support in inverted buck-boost mode is 0.1 (e.g., D=0.1).

[0056] exist Figure 2 In the example shown, the second threshold is -0.5 V (e.g., Therefore, driver power stage 104 generates a negative voltage in inverting buck-boost mode. By switching driver power stage 104 to inverting buck-boost mode after crossing a threshold negative voltage, the controller ensures that driver power stage 104 operates in inverting buck-boost mode over a wider range of negative voltages and limits the range of negative voltages for which driver power stage 104 operates in intermediate modes. Therefore, the efficiency of driver power stage 104 increases when a negative voltage is generated.

[0057] Figure 4 It is in reverse mode (also known as inverted buck-boost mode) according to embodiments of this disclosure. Figure 2 A schematic diagram of an example configuration 400 for the driver power stage 104. In reverse mode, node SW1 is always coupled to supply terminal 212, and node SW2 switches between the voltage at supply terminal 212 (e.g., AVDD) and the output voltage (VOUT) to TEC element 102 in alternating phases. For example, in reverse mode, switch 202 is open, switch 204 is closed, and switches 206 and 208 switch between open and closed in response to PHI2 and PHI1 waveforms, respectively. Therefore, the current (IL) through inductor 210 flows from node SW2 to node SW1 (e.g., inductor current, also known as absorption mode). In reverse mode, the absolute value of the average current through inductor 210 is greater than the absolute value of the current through TEC element 102 (e.g., ...). Furthermore, the absolute value of the average current through inductor 210 in reverse mode is less than the absolute value of the average current through inductor 210 in intermediate mode (e.g., ).

[0058] Return to Figure 2When the output voltage is between the first and second thresholds, the driver power stage 104 controls the TEC element 102 in an intermediate mode. For example, when the controller (described below) changes the duty cycle of switches 202-208 (e.g., in buck mode or in inverting buck-boost mode) and the output voltage is less than the first threshold (e.g., ...), And greater than the second threshold (e.g., When this occurs, the controller switches the operating mode of the driver power stage 104 to an intermediate mode. Therefore, the driver power stage 104 generates a near-zero voltage in the intermediate mode.

[0059] exist Figure 2 In the example shown, in the intermediate mode, node SW1 switches between the voltage at supply terminal 212 (e.g., AVDD) and the voltage at common terminal 106 (e.g., AVSS) in alternating phases. For example, in the intermediate mode, switches 202 and 204 switch between open and closed in response to the PHI1 and PHI2 waveforms, respectively. Additionally, in the intermediate mode, node SW2 switches between the voltage at supply terminal 212 (e.g., AVDD) and the output voltage (VOUT) to TEC element 102 in alternating phases. For example, in the intermediate mode, switches 206 and 208 switch between open and closed in response to the PHI2 and PHI1 waveforms, respectively. As described above, in the intermediate mode, driver power stage 104 generates a zero-volt output voltage for a duty cycle of 0.5. For example, the current (IL) through inductor 210 flows in two directions (e.g., between nodes SW1 and SW2) depending on the output voltage from driver power stage 104, and the current (IL) through inductor 210 can change direction within a switching cycle.

[0060] exist Figure 2 In the example shown, the operating efficiency of the driver power stage 104 is improved by operating in the three modes described herein. For example, compared to operating only in the intermediate mode, operating in the three modes described herein increases the efficiency of the driver power stage 104 by 8% for peak negative output voltage and by 12% for positive voltage. Additionally, compared to operating only in the intermediate mode, operating in the three modes described herein reduces the peak current through inductor 210 by 20%. Therefore, because the peak current through inductor 210 is reduced, an inductor with a smaller saturation current can be used to implement inductor 210. Thus, the size of inductor 210 can be reduced and its cost lowered.

[0061] exist Figure 2In the example shown, when driver power stage 104 generates a positive output voltage in buck mode, the efficiency of driver power stage 104 is at its peak level (e.g., 93%). As described above, TEC elements are used in telecommunications applications to control the temperature of laser diodes. Although TEC elements can be used to heat or cool controlled components, they are primarily used for cooling laser diodes in data center applications. Therefore, to utilize the peak efficiency of driver power stage 104, TEC element 102 is coupled to the output terminal of driver power stage 104 with negative polarity. When driver power stage 104 is in buck mode and TEC element 102 is coupled with negative polarity, driver power stage 104 supplies current (e.g., It achieves a peak efficiency of 91.9%.

[0062] exist Figure 2 In the example shown, one or more of switches 202-208 can be implemented by an N-channel metal-oxide-semiconductor (NMOS) transistor or a P-channel metal-oxide-semiconductor (PMOS) transistor. For example, Figure 5 According to embodiments of this disclosure Figure 2 A schematic diagram of the driver power stage 104, wherein the first to fourth switches 202-208 (labeled S1-S4) are implemented by example NMOS transistors 502-508. Figure 5 In the example, the gate voltage of the NMOS transistor 502 is twice the voltage at the supply terminal 212, and the gate voltage of the NMOS transistor 502 is the voltage at node SW1 (e.g., , ).

[0063] In the examples described herein, the transistor has a control terminal, a first current path terminal, and a second current path terminal. For a metal-oxide-semiconductor (MOS) based device, the control terminal is referred to as the gate, and the first and second current path terminals are referred to as the source and drain, respectively. In operation, a current path can be formed between the two current path terminals of the MOS-based device. For a bipolar device, the control terminal is referred to as the base, and the first and second current path terminals are referred to as the emitter and collector, respectively. In operation, a current path can be formed between the two current path terminals of the bipolar device.

[0064] In some examples, if the control voltage of the transistor, such as the gate-to-source voltage (V) of an N-channel transistor... GS ) or the source-to-gate voltage (V) of a P-channel transistor SGIf the voltage level is such that the transistor is at a level that allows it to conduct current, then the transistor is turned on. For example, the transistor is turned on when it is in linear operating mode or saturation operating mode. Conversely, if the control voltage of the transistor, such as the gate-to-source voltage (V) of an N-channel transistor, is not specified, the transistor is turned on. GS ) or the source-to-gate voltage (V) of a P-channel transistor SG If the transistor is at a level that prevents it from conducting current, then the transistor is turned off. For example, when the transistor is in the off operating state, it is turned off.

[0065] exist Figure 5 In the example shown, the gate voltage of the NMOS transistor 504 is the voltage at the supply terminal 212, and the gate voltage of the NMOS transistor 504 is zero volts (e.g., 、0). In Figure 5 In the example, the gate voltage of NMOS transistor 506 is the voltage at node SW2 plus five volts, and the gate voltage of NMOS transistor 506 is the voltage at node SW2 (e.g., , Furthermore, the gate voltage for turning on NMOS transistor 508 is the voltage at the output terminal of driver power stage 104 plus five volts, and the gate voltage for turning off NMOS transistor 508 is the voltage at the output terminal of driver power stage 104 (e.g., , ).

[0066] exist Figure 5 In the example shown, an integrated charge pump, supplied by supply terminal 212 (e.g., AVDD) and using high-density on-chip trench capacitors, generates the voltage level that drives the gates of NMOS transistors 502 and 506. Figure 5 As shown, NMOS transistors 502-508 are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, NMOS transistors 502-508 can be N-channel field-effect transistors (FETs), N-channel insulated-gate bipolar transistors (IGBTs), N-channel junction field-effect transistors (JFETs), NPN bipolar junction transistors (BJTs), or P-channel equivalent devices with slight modifications. NMOS transistors 502-508 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, NMOS transistors 502-508 can be implemented on / on a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate. To reduce the on-resistance (RON) of NMOS transistors 502-508, NMOS transistors 502-508 can be implemented as N-channel laterally diffused metal-oxide-semiconductor (LDMOS) transistors.

[0067] Figure 6 According to embodiments of this disclosure Figure 2 A schematic diagram of the driver power stage 104, wherein the second switch 204 and the fourth switch 208 are implemented by example NMOS transistors 604, 608, and the first switch 202 and the third switch 206 are implemented by example PMOS transistors 602, 606. Figure 6 In the example, no charge pump is used to drive the gates of the high-side transistors (e.g., PMOS transistors 602, 606). Therefore, the design complexity of the driver power stage 104 is reduced. For simplicity, the gate voltages for turning on NMOS transistors 604, 608 and PMOS transistors 602, 606 are not described herein. By implementing switch 208 with a single NMOS transistor (e.g., NMOS transistor 608), the area occupied by switch 208 is one-third of that in the case where switch 208 is implemented with a transmission gate.

[0068] like Figure 6 As shown, NMOS transistors 604 and 608 are N-channel MOSFETs. Alternatively, NMOS transistors 604 and 608 can be N-channel FETs, N-channel IGBTs, N-channel JFETs, NPN BJTs, or P-channel equivalents with slight modifications. Figure 6 In the examples, PMOS transistors 602 and 606 are P-channel MOSFETs (e.g., drain-extended PMOS transistors). Alternatively, PMOS transistors 602 and 606 can be P-channel FETs, P-channel IGBTs, P-channel JFETs, PNP BJTs, or N-channel equivalents with slight modifications. NMOS transistors 604 and 608 and PMOS transistors 602 and 606 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, NMOS transistors 604 and 608 and PMOS transistors 602 and 606 can be implemented in or on a Si substrate, SiC substrate, GaN substrate, or GaAs substrate.

[0069] Table 1 below shows the implementation of switches 202-208 (labeled S1-S4) as follows Figure 5 and 6 The table presents different selection options for NMOS and PMOS transistors. For example, the different NMOS and PMOS transistor selection options in Table 1 have on-resistance (RON) values ​​that contribute to achieving the target efficiency of 90% at peak current through inductor 210. Figure 2 In the example, the current through inductor 210 reaches its peak in the inverting buck-boost mode, while simultaneously generating a peak negative voltage.

[0070] Table 1

[0071]

[0072] As shown in Table 1, implementing the driver power stage 104 using NMOS transistors 502-508 (e.g., rows 3-5 and 7) occupies less area than implementing the driver power stage 104 using NMOS transistors 604, 608 (e.g., rows 4 and 5, respectively) and PMOS transistors 602, 606 (e.g., rows 2 and 6, respectively). Furthermore, compared to other methods, implementing the driver power stage 104 using NMOS transistors 502-508 (e.g., rows 3-5 and 7) helps reduce the total chip area footprint by 25%.

[0073] As described above, driver power stage 104 drives TEC element 102 in a single-ended manner, with one end of TEC element 102 grounded. Driver power stage 104 can drive both positive and negative voltages using a single unipolar supply, a single power inductor (e.g., inductor 210), and a single capacitor (e.g., capacitor 214), which reduces the board area occupied by the TEC system and lowers system cost. The four-switch topology of driver power stage 104 can be configured in multiple switching modes (e.g., buck mode, inverting buck-boost mode, and intermediate mode) by changing the switching order of the four switches as described herein.

[0074] As described above, the driver power stage 104 actively varies between different operating modes depending on whether the output voltage from the driver power stage 104 is greater than a first threshold, less than a second threshold, or between the first and second thresholds. For example, when the output voltage is greater than the first threshold, the driver power stage 104 operates in buck mode to generate a positive voltage. When the output voltage is less than the second threshold, the driver power stage 104 operates in inverted buck-boost mode to generate a negative voltage. When the output voltage is between the first and second thresholds, the driver power stage 104 operates in an intermediate mode to generate a near-zero voltage for zero crossing. For example, in the intermediate mode, the two-stage switching sequence of the driver power stage 104 ensures that the zero crossing of the driver power stage 104 occurs at a duty cycle of approximately 0.5, thereby providing glitch-free zero crossing and a simplified overall feedback loop to ensure very high temperature stability (e.g., <5 m°C difference from the target temperature).

[0075] The example multimode operation described herein improves the overall efficiency of power delivery to TEC element 102. For example, the multimode operation described herein improves the efficiency of power delivery at medium and higher levels. The efficiency of power delivery to TEC element 102 can be further improved by switching the polarity of TEC element 102 so that the driver power stage 104 drives TEC element 102 in its most efficient mode (e.g., buck mode) for most of the operation. Additionally, the example multimode operation described herein reduces the steady-state peak current through inductor 210 and allows the use of an inductor with a smaller saturation current. Therefore, the coverage area of ​​inductor 210 can be reduced.

[0076] exist Figure 2 In the example shown, to ensure proper operation of the driver power stage 104, in addition to monitoring for overcurrent (OI) events during the charging phase, the controller (described below) also monitors for undercurrent (UI) events during the discharging phase. For example, if a short circuit occurs at the output terminal of the driver power stage 104 during buck mode operation, and only the current (IL) through inductor 210 is monitored for OI events during the charging phase (e.g., when switch 202 is closed and switch 204 is open), then the current through inductor 210 may accumulate in subsequent phases. If the short-circuit state persists, then the current (IL) through inductor 210 may become uncontrollable.

[0077] Figure 7 It is a description Figure 2 Timing diagram of possible inductor currents in driver power stage 104. (See attached diagram.) Figure 7 As shown, if only the current through inductor 210 is monitored for OI events during the charging phase, the current through inductor 210 may accumulate and become uncontrollable during subsequent phases. However, if the current through inductor 210 is monitored for UI events during the discharging phase, in addition to monitoring for OI events during the charging phase, the current through inductor 210 remains at the target average value. For example, once the current (IL) through inductor 210 falls below the UI limit during the discharging phase, driver power stage 104 switches back to the charging phase. Similarly, once the current (IL) through inductor 210 exceeds the OI limit during the charging phase, driver power stage 104 switches back to the discharging phase. Therefore, the current through inductor 210 does not become uncontrollable, even in a short-circuit state.

[0078] Figure 8 This is a block diagram of a system 800 according to an embodiment of the present disclosure, the system comprising for Figure 2 The controller 802 of the driver power stage 104 and the OI current sensor subsystem 804 for the driver power stage 104. Figure 8In the example, there may be two possible OI events, one during supply mode (e.g., when the current through inductor 210 is positive) and one during absorption mode (e.g., when the current through inductor 210 is negative). To monitor these two OI events, the OI current sensor subsystem 804 includes a high-side supply mode sensor 806 (labeled HS-SNS-SRC), a high-side supply mode OI comparator 808, a low-side supply mode sensor 810 (labeled LS-SNS-SRC), and a low-side supply mode OI comparator 812. Figure 8 The OI current sensor subsystem 804 also includes a low-side absorption mode sensor 814 (identified as LS-SNS-SNK), a low-side absorption mode OI comparator 816, a low-side absorption mode UI comparator 818, a high-side absorption mode sensor 820 (identified as HS-SNS-SNK), and a high-side absorption mode UI comparator 822.

[0079] exist Figure 8 In the example shown, the OI current sensor subsystem 804 includes an OI / UI state machine 824 (labeled OI / UI-FSM) and calibration circuitry 826. Figure 8 In the example, the OI / UI state machine 824 includes a provisioning mode state machine 828 (identified as OI_SRC_VD FSM) and an absorptive mode state machine 830 (identified as OI_SNK_VD FSM). Additionally, Figure 8 The controller 802 includes a mode control state machine 832 (identified as MODE_CTRL_FSM), deglitches 834 and 836, and non-overlapping clock generation circuits 838 and 840. Figure 8 In the example, controller 802 also includes buck mode comparator 842 and inverting buck-boost mode comparator 844.

[0080] exist Figure 8 In the example shown, the OI current sensor subsystem 804 supports the three operating modes of the driver power stage 104 described herein. Figure 8 In the example, each of the high-side supply mode sensor 806, low-side supply mode sensor 810, low-side absorption mode sensor 814, and high-side absorption mode sensor 820 is a current sensing circuit that includes a duplicate transistor (e.g., a duplicate FET) to sense the current through inductor 210 in a lossless manner. Depending on the current mode of the driver power stage 104, different ones of the high-side supply mode sensor 806, low-side supply mode sensor 810, low-side absorption mode sensor 814, and high-side absorption mode sensor 820 sense the current through inductor 210.

[0081] exist Figure 8In the example shown, the high-side supply mode sensor 806, the low-side supply mode sensor 810, the low-side absorption mode sensor 814, and the high-side absorption mode sensor 820 are associated with switches (e.g., switches 202, 204) coupled to node SW1. By monitoring the switches coupled to node SW1 (e.g., switches 202, 204), the OI current sensor subsystem 804 reduces design constraints. For example, if sensors were implemented to monitor switches coupled to node SW2 (e.g., switches 206, 208), the sensors would receive a negative voltage associated with node SW2, and a high-voltage transistor would be required, which would complicate the design.

[0082] exist Figure 8 In the example shown, when the driver power stage 104 is in supply mode (e.g., when the current through inductor 210 is positive), the high-side supply mode sensor 806 senses the current through switch 202. Figure 8 In the example, the high-side supply mode sensor 806 provides a voltage that represents the sensed current through switch 202 and is directly related to the current through switch 202. For example, when the current through switch 202 increases, the voltage provided by the high-side supply mode sensor 806 increases. Conversely, when the current through switch 202 decreases, the voltage provided by the high-side supply mode sensor 806 decreases.

[0083] Therefore, when the driver power stage 104 is in supply mode (during both buck mode and intermediate mode operation), the high-side supply mode OI comparator 808 can monitor OI events. For example, the high-side supply mode OI comparator 808 compares a voltage representing the sensed current from the high-side supply mode sensor 806 with a supply mode OI reference voltage (labeled VREF_OI_SRC). Figure 8 In the example, the supply mode OI reference voltage is a programmable voltage and corresponds to or is proportional to the supply mode OI limit (also known as the supply mode OI threshold) between 2.5 amps (A) and 4.8 A.

[0084] exist Figure 8 In the example shown, when the driver power stage 104 is in supply mode, the low-side supply mode sensor 810 senses the current through switch 204. Figure 8 In the example, the low-side supply mode sensor 810 provides a voltage that represents the sensed current through switch 204 and is indirectly related to the current through switch 204. For example, when the current through switch 204 increases, the voltage provided by the low-side supply mode sensor 810 decreases. Conversely, when the current through switch 204 decreases, the voltage provided by the low-side supply mode sensor 810 increases.

[0085] Therefore, when the driver power stage 104 is in supply mode (during both buck mode and intermediate mode operation), the low-side supply mode UI comparator 812 can monitor UI events. For example, the low-side supply mode UI comparator 812 compares a voltage representing the sensed current from the low-side supply mode sensor 810 with a supply mode UI reference voltage (identified as VREF_UI_SRC). Figure 8 In the example, the supply mode UI reference voltage is a programmable voltage and corresponds to or is proportional to a supply mode UI limit (also known as the supply mode UI threshold) of 750 mA that is less than the supply mode OI limit.

[0086] exist Figure 8 In the example shown, when the driver power stage 104 is in absorption mode (e.g., when the current through inductor 210 is negative), the low-side absorption mode sensor 814 senses the current through switch 204. Figure 8 In the example, the low-side absorption mode sensor 814 provides a voltage that represents the sensed current through switch 204 and is indirectly related to the current through switch 204. For example, when the current through switch 204 increases, the voltage provided by the low-side absorption mode sensor 814 decreases. Conversely, when the current through switch 204 decreases, the voltage provided by the low-side absorption mode sensor 814 increases.

[0087] Therefore, when the driver power stage 104 is in absorption mode (during both inverting buck-boost mode and intermediate mode operation), the low-side absorption mode OI comparator 816 and the low-side absorption mode UI comparator 818 can monitor OI events and UI events, respectively. For example, the low-side absorption mode OI comparator 816 compares the voltage representing the sensed current from the low-side absorption mode sensor 814 with the absorption mode OI reference voltage (labeled VREF_OI_SNK). Figure 8 In the example, the absorption mode OI reference voltage is a programmable voltage and corresponds to or is proportional to an absorption mode OI limit (also known as the absorption mode OI threshold) between -2.5A and -4.8A. Additionally, the low-side absorption mode UI comparator 818 compares a voltage representing the sensed current from the low-side absorption mode sensor 814 with the low-side absorption mode UI reference voltage (identified as VREF_UI_SNK). Figure 8 In the example, the low-side absorption mode UI reference voltage is a programmable voltage and corresponds to or is proportional to a low-side absorption mode UI limit (also known as the low-side absorption mode UI threshold) of 750 mA that is higher than the absorption mode OI limit.

[0088] exist Figure 8In the example shown, when the driver power stage 104 is in absorption mode, the high-side absorption mode sensor 820 senses the current through switch 202. Figure 8 In the example, the high-side absorption mode sensor 820 provides a voltage that represents the sensed current through switch 202 and is directly related to the current through switch 202. For example, when the current through switch 202 increases, the voltage provided by the high-side absorption mode sensor 820 increases. Conversely, when the current through switch 202 decreases, the voltage provided by the high-side absorption mode sensor 820 decreases.

[0089] Therefore, when the driver power stage 104 is in absorption mode (during both inverting buck-boost mode and intermediate mode operation), the high-side absorption mode UI comparator 822 can monitor UI events. For example, the high-side absorption mode UI comparator 822 compares a voltage representing the sensed current from the high-side absorption mode sensor 820 with a high-side absorption mode UI reference voltage (identified as VREF_HS_UI_SNK). Figure 8 In the example, the high-side absorption mode UI reference voltage is a programmable voltage and corresponds to or is proportional to a high-side absorption mode UI limit (also known as the high-side absorption mode UI threshold) of 750 mA that is higher than the absorption mode OI limit.

[0090] exist Figure 8 In the example shown, based on comparison, the high-side supply mode OI comparator 808, the low-side supply mode UI comparator 812, the low-side absorption mode OI comparator 816, the low-side absorption mode UI comparator 818, and the high-side absorption mode UI comparator 822 provide signals to the OI / UI state machine 824 indicating whether a supply mode OI event, a supply mode UI event, an absorption mode OI event, and / or an absorption mode UI event has been detected. For example, in response to the output of the high-side supply mode sensor 806 and the supply mode OI reference voltage, the high-side supply mode OI comparator 808 provides an OI supply mode signal (identified as OI_SRC_COMP) to the supply mode state machine 828. Figure 8 In the example, in response to the output of the high-side supply mode sensor 806 exceeding the supply mode OI reference voltage (e.g., the absolute value of the current through switch 202 exceeds the supply mode OI threshold), the OI supply mode signal indicates that a supply mode OI event has been detected.

[0091] exist Figure 8In the example shown, in response to the output of the low-side supply mode sensor 810 and the supply mode UI reference voltage, the low-side supply mode UI comparator 812 provides a UI supply mode signal (identified as UI_SRC_COMP) to the supply mode state machine 828. For example, in response to the output of the low-side supply mode sensor 810 exceeding the supply mode UI reference voltage (e.g., the absolute value of the current through switch 204 is less than (e.g., drops below) the supply mode UI threshold), the UI supply mode signal indicates that a supply mode UI event has been detected. Figure 8 In the example, in response to the output of the low-side absorption mode sensor 814 and the absorption mode OI reference voltage, the low-side absorption mode OI comparator 816 provides an OI absorption mode signal (identified as OI_SNK_COMP) to the absorption mode state machine 830. For example, in response to the output of the low-side absorption mode sensor 814 being less than (e.g., falling below) the absorption mode OI reference voltage (e.g., the absolute value of the current through switch 204 exceeds the absorption mode OI threshold), the OI absorption mode signal indicates that an absorption mode OI event has been detected.

[0092] exist Figure 8 In the example shown, in response to the output of the low-side absorption mode sensor 814 and the low-side absorption mode UI reference voltage, the low-side absorption mode UI comparator 818 provides a low-side UI absorption mode signal (identified as UI_SNK_COMP) to the absorption mode state machine 830. For example, in response to the output of the low-side absorption mode sensor 814 exceeding the low-side absorption mode UI reference voltage (e.g., the absolute value of the current through switch 204 is less than (e.g., drops below) the low-side absorption mode UI threshold), the low-side UI absorption mode signal indicates that a low-side absorption mode UI event has been detected. Figure 8 In the example, in response to the output of the high-side absorption mode sensor 820 and the high-side absorption mode UI reference voltage, the high-side absorption mode UI comparator 822 provides a high-side UI absorption mode signal (identified as HS_UI_SNK_COMP) to the absorption mode state machine 830. For example, in response to the output of the high-side absorption mode sensor 820 being less than (e.g., dropping below) the high-side absorption mode UI reference voltage (e.g., the absolute value of the current through switch 202 being less than (e.g., dropping below) the high-side absorption mode UI threshold), the high-side UI absorption mode signal indicates that a high-side absorption mode UI event has been detected.

[0093] In some examples, calibration circuitry 826 can be used to facilitate the calibration of the high-side supply mode OI comparator 808 and the low-side absorption mode OI comparator 816. For example, upon startup of driver power stage 104, mode control state machine 832 provides calibration enable signals (identified as CAL_EN1 and CAL_EN2) to enable the corresponding calibration circuitry for the high-side supply mode OI comparator 808 and the low-side absorption mode OI comparator 816. Based on the calibration, mode control state machine 832 provides trimming signals (identified as TRIM1 and TRIM2) to calibrate the high-side supply mode OI comparator 808 and the low-side absorption mode OI comparator 816, respectively. For example, in Figure 10 An example implementation of the calibration circuit for the high-side supply mode OI comparator 808 is further shown and described. For example, in Figure 12 An example implementation of the calibration circuit for the low-side absorption mode OI comparator 816 is further shown and described.

[0094] exist Figure 8 In the example shown, the supply mode state machine 828 receives the OI supply mode signal and the UI supply mode signal. Additionally, the supply mode state machine 828 receives drive signals (identified as S1_DRV and S2_DRV, respectively) for switches 202 and 204. Figure 8 In the example, the supply mode state machine 828 deglitches the drive signal. In response to the deglitched drive signal, the OI supply mode signal, and the UI supply mode signal, the supply mode state machine 828 provides the supply mode OI detection signal (identified as OI_SRC_VD) to the mode control state machine 832.

[0095] For example, in response to an OI supply mode signal indicating the detection of a supply mode OI event and a closing value for a drive signal for switch 202 (e.g., indicating that switch 202 will close), the supply mode state machine 828 sets the supply mode OI detection signal to indicate that a supply mode OI event has been detected. In response to a UI supply mode signal indicating the detection of a supply mode UI event and a closing value for a drive signal for switch 204 (e.g., indicating that switch 204 will close), the supply mode state machine 828 resets the supply mode OI detection signal to indicate that the detected supply mode OI event has been cleared. For example, in... Figure 14 The example implementation of the supply mode state machine 828 is further shown and described.

[0096] exist Figure 8 In the example shown, the absorption mode state machine 830 receives the OI absorption mode signal, the low-side UI absorption mode signal, and the high-side UI absorption mode signal. Additionally, the absorption mode state machine 830 receives drive signals for switches 202 and 204. Figure 8In the example, the absorption mode state machine 830 deglitches the drive signal. In response to the deglitched drive signal, the OI absorption mode signal, the low-side UI absorption mode signal, and the high-side UI absorption mode signal, the absorption mode state machine 830 provides the absorption mode OI detection signal (identified as OI_SNK_VD) to the mode control state machine 832.

[0097] For example, in response to an OI absorption mode signal indicating the detection of an absorption mode OI event and a closing value of the drive signal for switch 204 (e.g., indicating that switch 204 will close), the absorption mode state machine 830 sets the absorption mode OI detection signal to indicate that an absorption mode OI event has been detected. In response to a low-side UI absorption mode signal indicating the detection of a low-side absorption mode UI event and a closing value of the drive signal for switch 204 (e.g., indicating that switch 204 will close), the absorption mode state machine 830 resets the absorption mode OI detection signal to indicate that the detected absorption mode OI event has been cleared. Alternatively, in response to a high-side UI absorption mode signal indicating the detection of a high-side absorption mode UI event and a closing value of the drive signal for switch 202 (e.g., indicating that switch 202 will close), the absorption mode state machine 830 resets the absorption mode OI detection signal to indicate that the detected absorption mode OI event has been cleared. For example, in Figure 15 An example implementation of the absorption mode state machine 830 is further shown and described.

[0098] exist Figure 8 In the example shown, during normal operation, the mode control state machine 832 controls the driver power stage 104 in one of the three operating modes described herein in response to a pulse width modulation (PWM) signal. For example, the PWM signal is generated based on a comparison between a target temperature of the controlled component (e.g., a laser diode) and a temperature measurement from a thermistor in or near the controlled component. Based on the comparison, a control circuit (not shown) generates a PWM signal that causes the measured temperature of the controlled component to become the target temperature. For example, the target temperature is in the range between -40°C and 125°C.

[0099] exist Figure 8 In the example shown, in response to the PWM signal, the mode control state machine 832 generates control signals for nodes SW1 and SW2 (identified as SW1_CTRL and SW2_CTRL, respectively). Figure 8 In the example, the control signal for node SW1 indicates whether node SW1 should be coupled to supply terminal 212 or to common terminal 106. Similarly, the control signal for node SW2 indicates whether node SW2 should be coupled to supply terminal 212 or to the output terminal of driver power stage 104. Figure 8In the example, deglitch circuits 834 and 836 deglitch the control signals, and non-overlapping clock generation circuits 838 and 840 generate drive signals for switches 202-208. For example, non-overlapping clock generation circuit 838 generates drive signals for switches 202 and 204 (labeled S1_DRV and S2_DRV, respectively). Additionally, non-overlapping clock generation circuit 830 generates drive signals for switches 206 and 208 (labeled S3_DRV and S4_DRV, respectively).

[0100] exist Figure 8 In the example shown, the drive signals for switches 202-208 control the operating mode of driver power stage 104. For example, when the first and second drive signals (e.g., S1_DRV, S2_DRV) control switches 202 and 204 to operate in alternating phases, and the third and fourth drive signals (e.g., S3_DRV, S4_DRV) control switches 206 and 208 to open and close, respectively, driver power stage 104 is in buck operation mode. In this example, the first and second drive signals (e.g., S1_DRV, S2_DRV) correspond to PHI1 and PHI2 waveforms, respectively. Additionally, when the first and second drive signals (e.g., S1_DRV, S2_DRV) control switches 202 and 204 to open and close, respectively, and the third and fourth drive signals (e.g., S3_DRV, S4_DRV) control switches 206 and 208 to operate in alternating phases, driver power stage 104 is in inverted buck-boost operation mode. In such examples, the third and fourth drive signals (e.g., S3_DRV, S4_DRV) correspond to the PHI2 and PHI1 waveforms, respectively.

[0101] exist Figure 8 In the example shown, when the first and fourth drive signals (e.g., S1_DRV, S4_DRV) control switches 202 and 208 to operate in alternating phases according to the first clock signal (e.g., PHI1 waveform), and the second and third drive signals (e.g., S2_DRV, S3_DRV) control switches 204 and 206 to operate in alternating phases according to the second clock signal (e.g., PHI2 waveform), the driver power stage 104 is in an intermediate operating mode. For example, the first and second clock signals have fixed frequencies, and the second clock signal does not overlap with the first clock signal to prevent shoot-through, as described above. To control which operating mode the driver power stage 104 is in, the mode control state machine 832 monitors the buck mode comparator 842 and the inverting buck-boost mode comparator 844.

[0102] exist Figure 8In the example shown, buck-mode comparator 842 and inverting buck-boost mode comparator 844 monitor the output voltage (VOUT). For example, buck-mode comparator 842 compares the output voltage with a first threshold (e.g., Vout). P The buck-mode comparator 842 compares the output voltage with a first threshold voltage. In response to the output voltage and a first threshold, the buck-mode comparator 842 provides a buck-mode control signal (identified as BUCK_VD) to the mode control state machine 832. Additionally, the inverting buck-boost mode comparator 844 compares the output voltage with a second threshold voltage (e.g., V). M The comparison is performed. In response to the output voltage and the second threshold, the inverting buck-boost mode comparator 844 provides an inverting buck-boost mode control signal (identified as INVBB_VD) to the mode control state machine 832. In response to the buck mode control signal and the inverting buck-boost mode control signal, the mode control state machine 832 transitions the driver power stage 104 to one of the three operating modes described herein.

[0103] For example, in response to the output voltage exceeding a first threshold, the buck mode control signal and the inverting buck-boost mode control signal instruct the mode control state machine 832 that the driver power stage 104 will switch to buck mode. In response to the output voltage being less than (e.g., falling below) a second threshold, the buck mode control signal and the inverting buck-boost mode control signal instruct the mode control state machine 832 that the driver power stage 104 will switch to inverting buck-boost mode. Additionally, in response to the output voltage being between the first and second thresholds, the buck mode control signal and the inverting buck-boost mode control signal instruct the mode control state machine 832 that the driver power stage 104 will switch to an intermediate mode.

[0104] As described above, a PWM signal is generated to make the measured temperature of the controlled component (e.g., a laser diode) become the target temperature. Additionally, the mode control state machine 832 generates drive signals for switches 202-208 based on the PWM signal to adjust the amount of heat supplied or absorbed by the TEC element 102. Therefore, in each operating mode, the mode control state machine 832 adjusts the duty cycle of the switching switches (e.g., switches 202, 204 in buck mode, switches 206, 208 in inverted buck-boost mode, or switches 202-208 in intermediate mode) to regulate the output voltage of the driver power stage 104 so that the measured temperature becomes the target temperature. For example, in an intermediate mode (e.g., when the output voltage is between the first and second thresholds), the mode control state machine 832 regulates the output voltage from the driver power stage 104 by adjusting the duty cycle of one or more of the first to fourth drive signals to switches 202-208.

[0105] exist Figure 8In the example shown, in response to the supply mode OI detection signal and / or absorption mode OI detection signal indicating that an OI event has been detected, the mode control state machine 832 provides control signals for nodes SW1 and SW2 to transition driver power stage 104 to a safe state. For example, in the safe state, driver power stage 104 reliably discharges inductor 210 to reduce the current through inductor 210 to a lower level.

[0106] Table 2

[0107]

[0108] As shown in Table 2, in response to the driver power stage 104 operating in buck mode and the supply mode OI detection signal indicating a supply mode OI event being detected, the mode control state machine 832 provides control signals for nodes SW1 and SW2 to couple node SW1 to common terminal 106 and node SW2 to the output terminal of driver power stage 104. As described above, the supply mode OI detection signal indicates a supply mode OI event is detected when the absolute value of the inductor current is higher than the supply mode OI threshold. Figure 8 In the example, to couple node SW1 to common terminal 106 and node SW2 to the output terminal of driver power stage 104, mode control state machine 832 provides control signals to open switch 202, close switch 204, open switch 206, and close switch 208. Therefore, inductor 210 can begin the discharge phase, causing the current through inductor 210 to reach the target level.

[0109] During the discharge phase, switch 202 remains open, switch 204 remains closed, switch 206 remains open, and switch 208 remains closed. Figure 8 In the example, in response to a supply mode OI detection signal indicating that a detected supply mode OI event has been cleared (e.g., the absolute value of the inductor current is below the supply mode UI threshold), the mode control state machine 832 restarts the operation of switches 202-208 in buck mode to exit the discharge phase of inductor 210. As shown in Table 2, in response to driver power stage 104 operating in intermediate mode and the supply mode OI detection signal indicating a detected supply mode OI event, the mode control state machine 832 operates in a similar manner.

[0110] Additionally, as shown in Table 2, in response to the driver power stage 104 operating in intermediate mode and the absorption mode OI detection signal indicating the detection of an absorption mode OI event, the mode control state machine 832 provides control signals for nodes SW1 and SW2 to couple node SW1 to supply terminal 212 and node SW2 to output terminal of driver power stage 104. As described above, the absorption mode OI detection signal indicates the detection of an absorption mode OI event when the absolute value of the inductor current is higher than the absorption mode OI threshold. Figure 8 In the example, in order to couple node SW1 to supply terminal 212 and node SW2 to output terminal of driver power stage 104, mode control state machine 832 provides control signals to close switch 202, open switch 204, open switch 206 and close switch 208.

[0111] Therefore, inductor 210 can begin the discharge phase, causing the current through inductor 210 to reach the target level. During the discharge phase, switch 202 remains closed, switch 204 remains open, switch 206 remains open, and switch 208 remains closed. Figure 8 In the example, in response to the absorption mode OI detection signal indicating that the detected absorption mode OI event has been cleared, the mode control state machine 832 restarts the operation of switches 202-208 in the intermediate mode to exit the discharge phase of inductor 210. For the intermediate mode, the absorption mode OI detection signal indicates that the detected absorption mode OI event has been cleared when the absolute value of the inductor current is lower than the high-side absorption mode UI threshold.

[0112] As shown in Table 2, in response to the driver power stage 104 operating in inverted buck-boost mode and the absorption mode OI detection signal indicating the detection of an absorption mode OI event, the mode control state machine 832 provides control signals for nodes SW1 and SW2 to couple node SW1 to common terminal 106 and node SW2 to the output terminal of driver power stage 104. As described above, the absorption mode OI detection signal indicates the detection of an absorption mode OI event when the absolute value of the inductor current is higher than the absorption mode OI threshold. Figure 8 In the example, in order to couple node SW1 to common terminal 106 and node SW2 to the output terminal of driver power stage 104, mode control state machine 832 provides control signals to open switch 202, close switch 204, open switch 206 and close switch 208.

[0113] Therefore, inductor 210 can begin the discharge phase, causing the current through inductor 210 to reach the target level. During the discharge phase, switch 202 remains open, switch 204 remains closed, switch 206 remains open, and switch 208 remains closed. Figure 8 In the example, in response to the absorption mode OI detection signal indicating that the detected absorption mode OI event has been cleared, the mode control state machine 832 restarts the operation of switches 202-208 in the inverting buck-boost mode to exit the discharge phase of inductor 210. For the inverting buck-boost mode, the absorption mode OI detection signal indicates that the detected absorption mode OI event has been cleared when the absolute value of the inductor current is lower than the low-side absorption mode UI threshold.

[0114] Figure 9 According to embodiments of this disclosure Figure 8 A schematic diagram of the high-side supply mode sensor 806. As described above, in supply mode, current flows from node SW1 to node SW2 through inductor 210, and the high-side supply mode sensor 806 senses the current through switch 202 to monitor supply mode OI events. Figure 9 In the example, relative to Figure 5 The driver power stage 104 illustrates a high-side supply mode sensor 806. For example, the high-side supply mode sensor 806 includes an example replica transistor 902 (identified as MN_REP) used in parallel with an NMOS transistor 502 to monitor the current through the NMOS transistor 502. For example, a controller 802 applies a drive signal for the NMOS transistor 502 to the gates of both the NMOS transistor 502 and the replica transistor 902. Figure 9 In the example, the replica transistor 902 is the same size as the NMOS transistor 502. .

[0115] exist Figure 9 In the example shown, the high-side supply mode sensor 806 also includes an operational amplifier (op-amp) 904 implemented in the current domain to achieve a faster response time for sensing (e.g., determining) the current through the NMOS transistor 502. Figure 9 In the example, op-amp 904 is implemented by a current-input amplifier comprising a PMOS input pair including example transistors 906 and 908. For example, the source of transistor 906 corresponds to the inverting input of op-amp 904, and the source of transistor 908 corresponds to the non-inverting input of op-amp 904. Additionally, the drain of transistor 908 corresponds to the output of op-amp 904. Figure 9 In the example, transistor 906 is biased through a first example current source 910, and transistor 908 is biased through a second example current source 912.

[0116] exist Figure 9In the example shown, in response to the feedback action of op-amp 904, op-amp 904 forces the voltage at the replica node (labeled REP) to be equal to or within acceptable limits of the voltage at node SW1. For example, the output of op-amp 904 drives the gate of example output transistor 914 (labeled MN_OUT) to make the voltage at replica node REP equal to the voltage at node SW1. Therefore, op-amp 904 forces the voltages at the sources of NMOS transistor 502 and replica transistor 902 to be equal. Therefore, the current through replica transistor 902 and output transistor 914 is a scaled replica of the current through NMOS transistor 502. For example, because (1) the gate-to-source voltages applied to NMOS transistor 502 and replica transistor 902 are the same and (2) NMOS transistor 502 is N times the size of replica transistor 902, the current through replica transistor 902 and output transistor 914 is a scaled replica of the current through NMOS transistor 502. The latter is equal to the current flowing through inductor 210.

[0117] exist Figure 9 In the example shown, the high-side supply mode sensor 806 includes an example sensing resistor 916 (labeled R). SNS A replica current is used to convert the replicated current into a sensed voltage (identified as VOUT_SNS_SRC). For example, output transistor 914 applies a replicated current to sense resistor 916 to convert the replicated current into a sensed voltage. Therefore, high-side supply-mode OI comparator 808 can compare the sensed voltage with a supply-mode OI reference voltage (identified as VREF_OI_SRC). In some examples, high-side supply-mode OI comparator 808 is referred to as an amplifier. Figure 9 As shown, the high-side supply mode sensor 806 requires no compensation, enabling it to operate over a wider bandwidth and better track the current through inductor 210. Furthermore, in response to the limited current through inductor 210, the high-side supply mode sensor 806 is active when NMOS transistor 502 is turned on. Therefore, the high-side supply mode sensor 806 has a low (e.g., negligible) impact on the efficiency of driver power stage 104.

[0118] exist Figure 9 In the example shown, replica transistor 902 and output transistor 914 are N-channel MOSFETs. Alternatively, replica transistor 902 and output transistor 914 can be N-channel FETs, N-channel IGBTs, N-channel JFETs, NPN BJTs, or P-channel equivalents with slight modifications. Figure 9In the example, transistors 906 and 908 are P-channel MOSFETs. Alternatively, transistors 906 and 908 can be P-channel FETs, P-channel IGBTs, P-channel JFETs, PNP BJTs, or N-channel equivalent devices with slight modifications. Transistors 902, 906, 908, and 914 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 902, 906, 908, and 914 can be implemented in or on a Si substrate, SiC substrate, GaN substrate, or GaAs substrate.

[0119] As described above, in some examples, the high-side supply-mode OI comparator 808 is calibrated. For example, the op-amp 904 and the high-side supply-mode OI comparator 808 introduce errors that may affect the triggering time of the high-side supply-mode OI comparator 808 relative to the sense current and the supply-mode OI reference voltage (e.g., corresponding to the peak inductor current limit). In particular, a mismatch between the current sources 910 and 912 biasing the op-amp 904 may cause a mismatch or offset between the replica current and the inductor current. Additionally, offsets between the inputs of the op-amp 904, mismatches between the NMOS transistor 502 and the replica transistor 902, and / or offsets between the inputs of the high-side supply-mode OI comparator 808 may cause DC errors in supply-mode OI event detection. Other sources of DC errors include the relative mismatch between the resistance of the sense resistor 916 and the combined resistance of the resistor 1016 and the reference resistor 1022 described below.

[0120] exist Figure 9 In the example shown, the high-side supply-mode sensor 806 only responds to a limited current through inductor 210 and is active when NMOS transistor 502 is turned on. Therefore, one technique for calibrating the high-side supply-mode OI comparator 808 for DC error is to draw a predefined, precise current through inductor 210 to ensure that the high-side supply-mode sensor 806 and the associated feedback loop operate as expected. For example, once a known reference current is drawn through inductor 210, the output voltage from the high-side supply-mode sensor 806 is... (For example, ), where N is the ratio of the size of NMOS transistor 502 to the size of replica transistor 902.

[0121] However, because the high-side supply mode sensor 806 operates over a wider current range (e.g., from 2A to 5A), a larger current is required to draw through inductor 210 for calibration to simulate actual operation. Therefore, calibration according to this technique would be power- and time-consuming. Furthermore, calibration according to this technique can lead to reliability issues on the chip. For example, for a chip implementing the high-side supply mode sensor 806, the maximum rated DC current that the chip can draw from the supply is approximately 1.5A. Therefore, the current drawn to perform calibration according to this technique may approach or exceed the chip's maximum rated current. Advantageously, in some embodiments, the examples described herein do not require drawing a large current through inductor 210 to calibrate the high-side supply mode OI comparator 808 for DC errors in the high-side supply mode sensor 806 and / or the high-side supply mode OI comparator 808.

[0122] Figure 10 It is according to the embodiments of this disclosure for use Figure 8 A schematic diagram of an example calibration circuit 1000 for a high-side supply mode OI comparator 808. Figure 10 In the example, relative to Figure 9 The high-side supply mode sensor 806 illustrates the calibration circuit 1000. To calibrate the DC error described above, the mode control state machine 832 controls the driver power stage 104 to couple nodes SW1 and SW2 to the supply terminal 212. For example, the mode control state machine 832 controls NMOS transistors 502 and 506 to turn on and NMOS transistors 504 and 508 to turn off. Therefore, the voltage across inductor 210 will be 0V. Consequently, no current will accumulate in inductor 210 during calibration, and the current through inductor 210 will be 0A in steady state.

[0123] exist Figure 10 In the example shown, after the mode control state machine 832 controls NMOS transistors 502 and 506 to turn on and NMOS transistors 504 and 508 to turn off, the mode control state machine 832 provides a calibration enable signal (identified as CAL_EN) to the first example calibration switch 1002 to begin calibration of the high-side supply mode OI comparator 808. Additionally, an inverter (e.g., a NOT gate) provides an inverted calibration enable signal (identified as CAL_ENB) in response to the calibration enable signal. For example, the inverted calibration enable signal drives the second example calibration switch 1004. In response to the calibration enable signal instructing calibration of the high-side supply mode OI comparator 808, calibration switch 1002 closes, and the inverted calibration enable signal drives calibration switch 1004 open. Figure 10 In the example, the calibration enable signal corresponds to Figure 8 The calibration enable signal is identified as CAL_EN1.

[0124] exist Figure 10 In the example shown, in response to calibration switch 1002 being closed and calibration switch 1004 being open, the first example current source 1006 sets the calibration current (labeled ICAL) through example current mirror 1008. Figure 10 In the example, the current mirror 1008 is implemented by example transistors 1010 and 1012. Figure 10 As shown, the calibration current is drawn through transistor 1010 and applied to a first example resistor 1014. For example, resistor 1014 has a resistance of 500 R. In response to the mirroring effect of current mirror 1008, the calibration current is also drawn through transistor 1012 and applied to a second example resistor 1016 to generate a reference voltage (denoted as V) at the inverting input of the high-side supply mode OI comparator 808. REF For example, resistor 1016 has a resistance R.

[0125] exist Figure 10 In the example shown, the calibration current drawn by transistor 1012 is also sensed by example sampling transistor 1018 (labeled MN_SAMP). Therefore, sampling transistor 1018 samples the calibration current. Figure 10 As shown, sampling transistor 1018 is used in parallel with replica transistor 902. For example, the gates of replica transistor 902 and sampling transistor 1018 are coupled together, and controller 802 applies a drive signal for NMOS transistor 502 to the gates of replica transistor 902 and sampling transistor 1018. Figure 10 In the example, sampling transistor 1018 is matched with replica transistor 902. For example, sampling transistor 1018 and replica transistor 902 are approximately the same size.

[0126] exist Figure 10In the example shown, the drain of sampling transistor 1018 is coupled to node SW1. Because NMOS transistor 502 is turned on during calibration, the drain of sampling transistor 1018 is effectively shorted to supply terminal 212. Therefore, in response to the feedback action of op-amp 904, op-amp 904 forces the voltage at the replica node (labeled REP) to be equal to or within acceptable limits of the voltage at supply terminal 212. Therefore, op-amp 904 forces the voltages at the sources of sampling transistor 1018 and replica transistor 902 to be equal. Therefore, replica transistor 902 replicates the current through sampling transistor 1018. For example, because (1) the gate-to-source voltages applied to sampling transistor 1018 and replica transistor 902 are the same and (2) sampling transistor 1018 is the same size as replica transistor 902, the current through replica transistor 902 and output transistor 914 is approximately equal to the current through sampling transistor 1018, which is equal to the calibration current.

[0127] exist Figure 10 In the example shown, output transistor 914 applies a calibration current to sensing resistor 916 to generate the sensed voltage (labeled VOUT_SNS_SRC) at the non-inverting input of high-side supply-mode OI comparator 808. Figure 10 In the example, the resistance of sensing resistor 916 is matched to the resistance of resistor 1016. For example, sensing resistor 916 and resistor 1016 have the same resistance. In some examples, the resistance of sensing resistor 916 is scaled relative to the resistance of resistor 1016. Therefore, the high-side supply mode OI comparator 808 can compare the sensed voltage with a reference voltage, both of which are based on a calibration current.

[0128] exist Figure 10 In the example shown, after calibration switch 1002 is closed and calibration switch 1004 is open, mode control state machine 832 provides a trimming signal (identified as TRIM1) to set a trimming code for the high-side supply mode OI comparator 808. For example, the high-side supply mode OI comparator 808 has a programmable offset between its inverting and non-inverting inputs. Furthermore, the dynamic range of the programmable offset is designed to cover the DC error sources described herein. Therefore, mode control state machine 832 sweeps through the trimming codes of the high-side supply mode OI comparator 808 (e.g., applying one or more of the trimming codes) until the high-side supply mode OI comparator 808 triggers (e.g., indicating that a supply mode OI event has been detected). For example, mode control state machine 832 sets the trimming code for the high-side supply mode OI comparator 808 to the trimming code where the high-side supply mode OI comparator 808 triggers. Figure 10 In the example, the trimming signal corresponds to Figure 8The trimming signal is identified as TRIM1.

[0129] exist Figure 10 In the example shown, after setting the trimming code for the high-side supply mode OI comparator 808, the mode control state machine 832 adjusts the driver power stage 104 and the calibration circuit 1000 for normal operation (e.g., non-calibration operation). For example, the mode control state machine 832 provides a calibration enable signal (identified as CAL_EN) indicating that calibration has been exited. Additionally, the mode control state machine 832 controls the NMOS transistors 502-508 to be in an idle state. Therefore, the mode control state machine 832 can control the NMOS transistors 502-508 in response to a PWM signal, as described above. Figure 10 In the example, in response to the calibration signal indicating that calibration has ended, calibration switch 1002 is turned off, and calibration switch 1004 is driven to close by the inverted calibration enable signal (identified as CAL_ENB).

[0130] exist Figure 10 In the example shown, in response to calibration switch 1002 being open and calibration switch 1004 being closed, the second example current source 1020 is set through example reference resistor 1022 (labeled R). REF The reference current for resistor 1016 is, for example, six microamps (µA). During normal operation, the supply mode OI reference voltage (identified as VREF_OI_SRC) is equal to the voltage across reference resistor 1022 and resistor 1016. Therefore, a user of system 800 can tune the resistance of reference resistor 1022 (e.g., a variable resistor) to adjust the supply mode OI reference voltage, and thus adjust the supply mode OI limit of driver power stage 104.

[0131] exist Figure 10 In the example shown, by using the high-side supply mode OI comparator 808 during calibration, the calibration circuit 1000 ensures that the DC error generated by the high-side supply mode OI comparator 808 is also compensated, in addition to those generated by the high-side supply mode sensor 806. Furthermore, the mode control state machine 832 does not need to monitor the calibration current set by the current source 1006 because the same current is replicated between the inverting and non-inverting inputs of the high-side supply mode OI comparator 808. Therefore, the calibration of the high-side supply mode OI comparator 808 is simplified.

[0132] Furthermore, compared to other technologies, the calibration current used by the calibration circuit 1000 is relatively small. For example, the calibration current is between 1 mA and 3 mA (e.g., Furthermore, the calibration circuit 1000 does not draw current through the inductor 210 during calibration, and the calibration current used by the calibration circuit 1000 is independent of the set OI limit. Therefore, compared to other methods, the calibration of the high-side supply mode OI comparator 808 consumes less power and can be performed in a shorter time period.

[0133] Furthermore, the described calibration improves the accuracy of OI event detection, thus enabling the driver power stage 104 to operate at a level closer to the OI limit (and corresponding saturation current level) of inductor 210 during normal operation. For example, when using the example calibration described herein, the DC accuracy for sensing OI events during normal operation is ±25 mA. By increasing the peak inductor current capability, the example calibration described herein increases (e.g., maximizes) the output power from driver power stage 104. Additionally, the example calibration described herein reduces the offset requirements of the high-side supply-mode sensor 806 and the high-side supply-mode OI comparator 808, resulting in a more compact design. Moreover, the example calibration described herein does not exhibit the reliability issues present in other calibration methods.

[0134] exist Figure 10 In the example shown, transistors 1010, 1012, and 1018 are N-channel MOSFETs. Alternatively, transistors 1010, 1012, and 1018 can be N-channel FETs, N-channel IGBTs, N-channel JFETs, NPN BJTs, or P-channel equivalent devices with slight modifications. Transistors 1010, 1012, and 1018 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 1010, 1012, and 1018 can be implemented in or on a Si substrate, SiC substrate, GaN substrate, or GaAs substrate.

[0135] Figure 11 According to embodiments of this disclosure Figure 8 A schematic diagram of the low-side supply mode sensor 810 is provided. As described above, in supply mode, current flows from node SW1 to node SW2 through inductor 210, and the low-side supply mode sensor 810 senses the current through switch 204 to monitor supply mode UI events. Figure 11 In the example, relative to Figure 5The driver power stage 104 illustrates a low-side supply mode sensor 810. For example, the low-side supply mode sensor 810 includes an example replica transistor 1102 (identified as MN_REP) used in parallel with an NMOS transistor 504 to monitor the current through the NMOS transistor 504. For example, a controller 802 applies a drive signal for the NMOS transistor 504 to the gates of both the NMOS transistor 504 and the replica transistor 1102. Figure 11 In the example, the replica transistor 1102 is the size of the NMOS transistor 504. .

[0136] exist Figure 11 In the example shown, the low-side supply mode sensor 810 also includes an example op-amp 1104, which is implemented in the current domain to achieve a faster response time to sense (e.g., determine) the current through the NMOS transistor 504. Figure 11 In the example, op-amp 1104 is implemented by a current-input amplifier comprising an NMOS input pair including example transistors 1106 and 1108. For example, the source of transistor 1106 corresponds to the inverting input of op-amp 1104, and the source of transistor 1108 corresponds to the non-inverting input of op-amp 1104. Additionally, the drain of transistor 1108 corresponds to the output of op-amp 1104. Figure 11 In the example, transistor 1106 is biased through a first example current source 1110, and transistor 1108 is biased through a second example current source 1112.

[0137] exist Figure 11 In the example shown, the inverting input of op-amp 1104 is coupled to common terminal 106 via example sense transistor 1114 (labeled MN_SNS), and the non-inverting input of op-amp 1104 is coupled to replica transistor 1102. Figure 11 In the example, sensing transistor 1114 is the size of NMOS transistor 504. .like Figure 11 As shown, the gate of sensing transistor 1114 is driven by supply terminal 212. Therefore, when replica transistor 1102 is turned on, sensing transistor 1114 pulls the inverting input of op-amp 1104 to the voltage at common terminal 106. In response to the feedback action of op-amp 1104, op-amp 1104 forces the voltage at the replica node (labeled REP) to be equal to or within acceptable limits of the voltage at common terminal 106.

[0138] For example, the output of op-amp 1104 drives the gate of output transistor 1116 (labeled MN_OUT) to make the voltages at the inverting and non-inverting inputs of op-amp 1104 equal. Figure 11 In the example, the voltage at the inverting input of op-amp 1104 is close to the voltage at common terminal 106. Therefore, op-amp 1104 makes the voltage at the non-inverting input of op-amp 1104 (e.g., replica node REP) equal to the voltage at common terminal 106. Therefore, op-amp 1104 forces the voltage at the source of replica transistor 1102 to be equal to the voltage at common terminal 106, which is also the voltage at the source of NMOS transistor 504. Therefore, the current through replica transistor 1102 and output transistor 1116 is a scaled replica of the current through NMOS transistor 504. For example, because (1) the gate-to-source voltages applied to NMOS transistor 504 and replica transistor 1102 are the same and (2) NMOS transistor 504 is N times the size of replica transistor 1102, the current through replica transistor 1102 and output transistor 1116 is a scaled replica of the current through NMOS transistor 502. The latter is equal to the current flowing through inductor 210.

[0139] exist Figure 11 In the example shown, the low-side supply mode sensor 810 includes an example sensing resistor 1118 (labeled R). SNS ), used to convert the replica current into the sensed voltage (denoted as V). SNS For example, output transistor 1116 pulls a replicated current through sensing resistor 1118 to convert the replicated current into a sensed voltage. Figure 11 In the example, the sensed voltage is equal to the difference between the voltage at supply terminal 212 and the product of the resistance of sensing resistor 1118 and the replica current (e.g., Therefore, the low-side supply mode UI comparator 812 can compare the sensed voltage with the supply mode UI reference voltage (identified as VREF_UI_SRC), in Figure 11 In the example, the supply mode UI reference voltage is pulled through example reference resistor 1122 (identified as R). REF The reference current (labeled I) REF The third example current source 1120 generates the current. In some examples, the low-side supply mode UI comparator 812 is referred to as an amplifier.

[0140] exist Figure 11 In the example shown, the low-side supply mode sensor 810 implements... Figure 9The high-side supply mode sensor 806 offers similar benefits. Additionally, the low-side supply mode sensor 810 is not calibrated because the supply mode UI reference voltage (e.g., corresponding to the supply mode UI threshold) can be intentionally skewed to cover DC errors without affecting the peak inductor current limit. For example, a user of system 800 can tune the resistance of reference resistor 1122 (e.g., a variable resistor) to adjust the supply mode UI reference voltage, thereby covering the DC errors introduced by the low-side supply mode sensor 810 and the low-side supply mode UI comparator 812. By skewing the supply mode UI reference voltage, the DC accuracy for sensing UI events during normal operation is ±200 mA.

[0141] exist Figure 11 In the example shown, transistors 1102, 1106, 1108, and 1114 are N-channel MOSFETs. Alternatively, transistors 1102, 1106, 1108, and 1114 can be N-channel FETs, N-channel IGBTs, N-channel JFETs, NPN BJTs, or P-channel equivalents with slight modifications. Figure 11 In the example, transistor 1116 is a P-channel MOSFET. Alternatively, transistor 1116 can be a P-channel FET, P-channel IGBT, P-channel JFET, PNP BJT, or an N-channel equivalent device with slight modifications. Transistors 1102, 1106, 1108, 1114, and 1116 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 1102, 1106, 1108, 1114, and 1116 can be implemented in or on a Si substrate, SiC substrate, GaN substrate, or GaAs substrate.

[0142] Figure 12 According to embodiments of this disclosure Figure 8 Low-side absorption mode sensor 814 and for Figure 8 A schematic diagram of the calibration circuit 1200 for the low-side absorption mode OI comparator 816. As described above, in absorption mode, current flows from node SW2 to node SW1 through inductor 210, and the low-side absorption mode sensor 814 senses the current through switch 204 to monitor absorption mode OI events. Figure 12 In the example, relative to Figure 5The driver power stage 104 illustrates a low-side absorption mode sensor 814 and calibration circuitry 1200. For example, the low-side absorption mode sensor 814 includes a replica transistor 1202 (labeled MN_REP) used in parallel with an NMOS transistor 504 to monitor the current through the NMOS transistor 504. For example, a controller 802 applies a drive signal for the NMOS transistor 504 to the gates of both the NMOS transistor 504 and the replica transistor 1202. Figure 12 In the example, the replica transistor 1202 is the same size as the NMOS transistor 504. .

[0143] exist Figure 12 In the example shown, the low-side absorption mode sensor 814 also includes an example op-amp 1204, implemented in the current domain to achieve a faster response time for sensing the current through the NMOS transistor 504. Figure 12 In the example, op-amp 1204 is implemented by a current-input amplifier comprising an NMOS input pair including example transistors 1206 and 1208. For example, the source of transistor 1206 corresponds to the inverting input of op-amp 1204, and the source of transistor 1208 corresponds to the non-inverting input of op-amp 1204. Additionally, the drain of transistor 1208 corresponds to the output of op-amp 1204. Figure 12 In the example, transistor 1206 is biased through a first example current source 1210, and transistor 1208 is biased through a second example current source 1212.

[0144] exist Figure 12 In the example shown, the inverting input of op-amp 1204 is coupled to example sampling transistor 1214 (identified as MN_SAMP), and the non-inverting input of op-amp 1204 is coupled to common terminal 106 via replica transistor 1202. Figure 12 In the example, sampling transistor 1214 is the size of NMOS transistor 504. .like Figure 12 As shown, the gate of sampling transistor 1214 is driven by supply terminal 212. Therefore, the inverting input of op-amp 1204 is set to the voltage at node SW1. Thus, when replica transistor 1202 is turned on, the feedback effect of op-amp 1204 forces the voltage at replica node (labeled REP) to be equal to or within acceptable limits of the voltage at node SW1.

[0145] For example, the output of op-amp 1204 drives the gate of example output transistor 1216 (labeled MN_OUT) so that the voltage at replica node REP is equal to the voltage at node SW1. Because the voltages at the gate, drain, and source of replica transistor 1202 and NMOS transistor 504 are equal, the current through replica transistor 1202 and output transistor 1216 is a scaled replica of the current through NMOS transistor 504. For example, because (1) the gate-to-source voltages applied to NMOS transistor 504 and replica transistor 1202 are the same and (2) NMOS transistor 504 is N times the size of replica transistor 1202, the current through replica transistor 1202 and output transistor 1216 is a scaled replica of the current through NMOS transistor 502. The latter is equal to the current flowing through inductor 210.

[0146] exist Figure 12 In the example shown, the low-side absorption mode sensor 814 includes an example sensing resistor 1218 (labeled R). SNS ), used to convert the replica current into the sensed voltage (denoted as V). SNS For example, output transistor 1216 pulls a replicated current through sensing resistor 1218 to convert the replicated current into a sensed voltage. Figure 12 In the example, the sensed voltage is equal to the difference between the voltage at supply terminal 212 and the product of the resistance of sensing resistor 1218 and the replica current (e.g., Therefore, the low-side absorption mode OI comparator 816 can compare the sensed voltage with the absorption mode OI reference voltage (identified as VREF_OI_SNK). Additionally, the low-side absorption mode UI comparator 818 can compare the sensed voltage with the low-side absorption mode UI reference voltage (identified as VREF_UI_SNK). In some examples, the low-side absorption mode OI comparator 816 and the low-side absorption mode UI comparator 818 are referred to as amplifiers. Figure 12 In the example, the low-side absorption mode sensor 814 achieves the same as... Figure 9 High-side supply mode sensor 806 and Figure 11 The low-side supply mode sensor 810 offers similar benefits.

[0147] As described above, in some examples, the low-side absorption mode OI comparator 816 is calibrated. For example, the op-amp 1204 and the low-side absorption mode OI comparator 816 introduce errors that may affect the triggering time of the low-side absorption mode OI comparator 816 relative to the sense current and the absorption mode OI reference voltage (e.g., corresponding to the peak inductor current limit). In particular, a mismatch between the current sources 1210 and 1212 biasing the op-amp 1204 may cause a mismatch or offset between the replica current and the inductor current. Additionally, offsets between the inputs of the op-amp 1204, mismatches between the NMOS transistor 504 and the replica transistor 1202, and / or offsets between the inputs of the low-side absorption mode OI comparator 816 may cause DC errors in absorption mode OI event detection. Other sources of DC errors include a relative mismatch between the resistance of the sense resistor 1218 and the combined resistance of the resistor 1234 and the reference resistor 1238, as described below.

[0148] As described above, advantageously, in some embodiments, the example calibration described herein does not require drawing a large current through inductor 210 to calibrate the low-side absorption mode OI comparator 816 for DC errors in the low-side absorption mode sensor 814 and / or the low-side absorption mode OI comparator 816. To calibrate the DC errors described above, mode control state machine 832 controls driver power stage 104 to couple node SW1 to common terminal 106 and node SW2 to the output terminal of driver power stage 104. For example, mode control state machine 832 controls NMOS transistors 502, 506 to turn off and NMOS transistors 504, 508 to turn on. Therefore, the output voltage from driver power stage 104 discharges to 0V. Thus, no current accumulates in inductor 210 during calibration, and the current through inductor 210 in steady state will be 0A.

[0149] exist Figure 12 In the example shown, after the mode control state machine 832 controls NMOS transistors 502 and 506 to turn off and NMOS transistors 504 and 508 to turn on, the mode control state machine 832 provides a calibration enable signal (identified as CAL_EN) to the first example calibration switch 1220 to begin calibration of the low-side absorption mode OI comparator 816. Additionally, an inverter (e.g., a NOT gate) provides an inverted calibration enable signal (identified as CAL_ENB) in response to the calibration enable signal. For example, the inverted calibration enable signal drives the second example calibration switch 1222. In response to the calibration enable signal instructing calibration of the low-side absorption mode OI comparator 816, calibration switch 1220 closes, and the inverted calibration enable signal drives calibration switch 1222 open. Figure 12 In the example, the calibration enable signal corresponds to Figure 8 The calibration enable signal is identified as CAL_EN2.

[0150] exist Figure 12 In the example shown, in response to calibration switch 1220 being closed and calibration switch 1222 being open, the third example current source 1224 sets the calibration current (labeled ICAL) through example current mirror 1226. Figure 12 In the example, current mirror 1226 is implemented by example transistors 1228 and 1230. Figure 12 As shown, the calibration current is drawn through transistor 1228 and applied to a first example resistor 1232. For example, resistor 1232 has a resistance of 500 R. In response to the mirroring effect of current mirror 1226, the calibration current is also drawn through transistor 1230 and applied to a second example resistor 1234 to generate a reference voltage (denoted as V) at the inverting input of the low-side absorption mode OI comparator 816. REF For example, resistor 1234 has a resistance R.

[0151] exist Figure 12 In the example shown, the calibration current drawn through transistor 1230 is also sensed through sampling transistor 1214. Therefore, sampling transistor 1214 samples the calibration current. As described above, sampling transistor 1214 is used in parallel with replica transistor 1202, and controller 802 applies a drive signal for NMOS transistor 504 to the gates of replica transistor 1202 and sampling transistor 1214. Furthermore, as described above, sampling transistor 1214 is matched to replica transistor 1202. For example, sampling transistor 1214 and replica transistor 1202 are approximately the same size.

[0152] exist Figure 12 In the example shown, the drain of sampling transistor 1214 is coupled to node SW1. Because the control NMOS transistor 504 is turned on during calibration, the drain of sampling transistor 1214 is effectively shorted to common terminal 106. Therefore, in response to the feedback action of op-amp 1204, op-amp 1204 forces the voltage at the replica node (labeled REP) to be equal to or within acceptable limits of the voltage at common terminal 106. Therefore, op-amp 1204 forces the voltages at the source of sampling transistor 1214 and the drain of replica transistor 1202 to be equal. Therefore, replica transistor 1202 replicates the current through sampling transistor 1214. For example, because (1) both sampling transistor 1214 and replica transistor 1202 are turned on and (2) sampling transistor 1214 is the same size as replica transistor 1202, the current through replica transistor 1202 and output transistor 1216 is approximately equal to the current through sampling transistor 1214, which is equal to the calibration current.

[0153] exist Figure 12 In the example shown, output transistor 1216 applies a calibration current to sensing resistor 1218 to generate the sensed voltage (labeled V) at the non-inverting input of low-side absorption mode OI comparator 816. SNS ).exist Figure 12 In the example, the resistance of sensing resistor 1218 is matched with the resistance of resistor 1234. For example, sensing resistor 1218 and resistor 1234 have the same resistance. In some examples, the resistance of sensing resistor 1218 is scaled relative to the resistance of resistor 1234. Therefore, the low-side absorption mode OI comparator 816 can compare the sensed voltage with a reference voltage, both of which are based on a calibration current.

[0154] exist Figure 12 In the example shown, after calibration switch 1220 is closed and calibration switch 1222 is open, mode control state machine 832 provides a trimming signal (identified as TRIM2) to set a trimming code for the low-side absorption mode OI comparator 816. For example, the low-side absorption mode OI comparator 816 has a programmable offset between its inverting and non-inverting inputs. Furthermore, the dynamic range of the programmable offset is designed to cover the DC error sources described herein. Therefore, mode control state machine 832 sweeps through the trimming codes of the low-side absorption mode OI comparator 816 (e.g., applying one or more of the trimming codes) until the low-side absorption mode OI comparator 816 triggers (e.g., indicating that an absorption mode OI event has been detected). For example, mode control state machine 832 sets the trimming code for the low-side absorption mode OI comparator 816 to the trimming code where the low-side absorption mode OI comparator 816 triggers. Figure 12 In the example, the trimming signal corresponds to Figure 8 The trimming signal is identified as TRIM2.

[0155] exist Figure 12 In the example shown, after setting the trimming code for the low-side absorption mode OI comparator 816, the mode control state machine 832 adjusts the driver power stage 104 and the calibration circuit 1200 for normal operation (e.g., non-calibration operation). For example, the mode control state machine 832 provides a calibration enable signal (identified as CAL_EN) indicating that calibration has ended. Additionally, the mode control state machine 832 controls the NMOS transistors 502-508 to be in an idle state. Therefore, the mode control state machine 832 can control the NMOS transistors 502-508 in response to a PWM signal, as described above. Figure 12In the example, in response to the calibration signal indicating that the calibration is complete, calibration switch 1220 is turned off, and calibration switch 1222 is driven to close by the inverted calibration enable signal (identified as CAL_ENB).

[0156] exist Figure 12 In the example shown, in response to calibration switch 1220 being open and calibration switch 1222 being closed, the fourth example current source 1236 is set through example reference resistor 1238 (identified as R). REF ) and the reference current of resistor 1234 (labeled as I) REF During normal operation, the absorption mode OI reference voltage (identified as VREF_OI_SNK) is equal to the voltage across reference resistor 1238 and resistor 1234. Therefore, a user of system 800 can tune the resistance of reference resistor 1238 (e.g., a variable resistor) to adjust the absorption mode OI reference voltage, and thus adjust the absorption mode OI limit of driver power stage 104.

[0157] exist Figure 12 In the example shown, by using the low-side absorption mode OI comparator 816 during calibration, the calibration circuit 1200 ensures that the DC error generated by the low-side absorption mode OI comparator 816 is compensated for in addition to those generated by the low-side absorption mode sensor 814. Furthermore, the mode control state machine 832 does not need to monitor the calibration current set by the current source 1224 because the same current is replicated between the inverting and non-inverting inputs of the low-side absorption mode OI comparator 816. Therefore, the calibration of the low-side absorption mode OI comparator 816 is simplified.

[0158] Furthermore, compared to other technologies, the calibration current used by the calibration circuit 1200 is relatively small. For example, the calibration current is between 1 mA and 3 mA (e.g., Furthermore, the calibration circuit 1200 does not draw current through the inductor 210 during calibration, and the calibration current used by the calibration circuit 1200 is independent of the set OI limit. Therefore, compared to other methods, the calibration of the low-side absorption mode OI comparator 816 consumes less power and can be performed in a shorter time period.

[0159] Furthermore, the described calibration improves the accuracy of OI event detection, thus enabling the driver power stage 104 to operate at a level relatively closer to the OI limit (and corresponding saturation current level) of inductor 210 during normal operation. For example, when using the example calibration described herein, the DC accuracy for sensing OI events during normal operation is ±25 mA. By increasing the peak inductor current capability, the example calibration described herein increases (e.g., maximizes) the output power from driver power stage 104. Additionally, the example calibration described herein reduces the offset requirements of the low-side absorption mode sensor 814 and the low-side absorption mode OI comparator 816, resulting in a more compact design. Moreover, the example calibration described herein does not exhibit the reliability issues present in other calibration methods.

[0160] exist Figure 12 In the example shown, the low-side absorption mode UI comparator 818 is not calibrated because the low-side absorption mode UI reference voltage (e.g., corresponding to the low-side absorption mode UI threshold) can be intentionally skewed to cover DC errors without affecting the peak inductor current limit. For example, a user of system 800 can tune the resistance of reference resistor 1238 to adjust the low-side absorption mode UI reference voltage, thereby covering the DC errors introduced by the low-side absorption mode sensor 814 and the low-side absorption mode UI comparator 818. By skewing the low-side absorption mode UI reference voltage, the DC accuracy for sensing UI events during normal operation is ±200 mA.

[0161] exist Figure 12 In the example shown, transistors 1202, 1206, 1208, and 1214 are N-channel MOSFETs. Alternatively, transistors 1202, 1206, 1208, and 1214 can be N-channel FETs, N-channel IGBTs, N-channel JFETs, NPN BJTs, or P-channel equivalents with slight modifications. Figure 12 In the examples, transistors 1216, 1228, and 1230 are P-channel MOSFETs. Alternatively, transistors 1216, 1228, and 1230 can be P-channel FETs, P-channel IGBTs, P-channel JFETs, PNP BJTs, or N-channel equivalent devices with slight modifications. Transistors 1202, 1206, 1208, 1214, 1216, 1228, and 1230 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 1202, 1206, 1208, 1214, 1216, 1228, and 1230 can be implemented in or on a Si substrate, SiC substrate, GaN substrate, or GaAs substrate.

[0162] Figure 13 According to embodiments of this disclosure Figure 8A schematic diagram of the high-side absorption mode sensor 820. As described above, in absorption mode, current flows from node SW2 to node SW1 through inductor 210, and the high-side absorption mode sensor 820 senses the current through switch 202 to monitor high-side absorption mode UI events. Figure 13 In the example, relative to Figure 5 The driver power stage 104 illustrates a high-side absorption mode sensor 820. For example, the high-side absorption mode sensor 820 includes an example replica transistor 1302 (identified as MN_REP) used in parallel with an NMOS transistor 502 to monitor the current through the NMOS transistor 502. For example, a controller 802 applies a drive signal for the NMOS transistor 502 to the gates of both the NMOS transistor 502 and the replica transistor 1302. Figure 13 In the example, the replica transistor 1302 is the same size as the NMOS transistor 502. .

[0163] exist Figure 13 In the example shown, the high-side absorption mode sensor 820 also includes an example operational amplifier (op-amp) 1304, implemented in the current domain to achieve a faster response time for sensing the current through the NMOS transistor 502. Figure 13 In the example, op-amp 1304 is implemented by a current-input amplifier comprising a PMOS input pair including example transistors 1306 and 1308. For example, the source of transistor 1306 corresponds to the inverting input of op-amp 1304, and the source of transistor 1308 corresponds to the non-inverting input of op-amp 1304. Additionally, the drain of transistor 1308 corresponds to the output of op-amp 1304. Figure 13 In the example, transistor 1306 is biased through a first example current source 1310, and transistor 1308 is biased through a second example current source 1312.

[0164] exist Figure 13In the example shown, in response to the feedback action of op-amp 1304, op-amp 1304 forces the voltage at the replica node (labeled REP) to be equal to or within acceptable limits of the voltage at supply terminal 212. For example, the output of op-amp 1304 drives the gate of example output transistor 1314 (labeled MN_OUT) so that the voltage at replica node REP is equal to the voltage at supply terminal 212. Therefore, op-amp 1304 forces the voltages at the drains of NMOS transistor 502 and replica transistor 1302 to be equal. Because (1) the gate-to-source voltages applied to NMOS transistor 502 and replica transistor 1302 are the same and (2) NMOS transistor 502 is N times the size of replica transistor 1302, the current through replica transistor 1302 and output transistor 1314 is the current through NMOS transistor 502. The latter is equal to the current through inductor 210. In this way, the current through replica transistor 1302 and output transistor 1314 is a scaled replica of the current through NMOS transistor 502.

[0165] exist Figure 13 In the example shown, the high-side absorption mode sensor 820 includes an example sensing resistor 1316 (labeled R). SNS ), used to convert the replica current into the sensed voltage (denoted as V). SNS For example, output transistor 1314 applies a replicated current to sensing resistor 1316 to convert the replicated current into a sensed voltage. Therefore, high-side absorption mode UI comparator 822 can compare the sensed voltage with a high-side absorption mode UI reference voltage (identified as VREF_HS_UI_SNK). Figure 13 In the example, the high-side absorption mode UI reference voltage is pulled through the example reference resistor 1320 (labeled R) by the third example current source 1318. REF The reference current (labeled I) REF This is used to generate the UI comparator 822. In some examples, the high-side absorption mode UI comparator 822 is referred to as an amplifier.

[0166] exist Figure 13 In the example shown, the high-side absorption mode sensor 820 achieves the same as... Figure 9 High-side supply mode sensor 806, Figure 11 Low-side supply mode sensor 810 and Figure 12Similar benefits are found in the low-side absorption mode sensor 814. Additionally, the high-side absorption mode sensor 820 is not calibrated because the high-side absorption mode UI reference voltage (e.g., corresponding to the high-side absorption mode UI threshold) can be intentionally skewed to cover DC errors without affecting the peak inductor current limit. For example, a user of system 800 can tune the resistance of reference resistor 1320 (e.g., a variable resistor) to adjust the high-side absorption mode UI reference voltage, thereby covering the DC errors introduced by the high-side absorption mode sensor 820 and the high-side absorption mode UI comparator 822. By skewing the high-side absorption mode UI reference voltage, the DC accuracy for sensing UI events during normal operation is ±200 mA.

[0167] exist Figure 13 In the example shown, transistors 1302 and 1314 are N-channel MOSFETs. Alternatively, transistors 1302 and 1314 can be N-channel FETs, N-channel IGBTs, N-channel JFETs, NPN BJTs, or P-channel equivalents with slight modifications. Figure 13 In the examples, transistors 1306 and 1308 are P-channel MOSFETs. Alternatively, transistors 1306 and 1308 can be P-channel FETs, P-channel IGBTs, P-channel JFETs, PNP BJTs, or N-channel equivalent devices with slight modifications. Transistors 1302, 1314, 1306, and 1308 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 1302, 1314, 1306, and 1308 can be implemented in or on a Si substrate, SiC substrate, GaN substrate, or GaAs substrate.

[0168] As described above, for example, in Figure 8-13 The example described herein includes an array of high-bandwidth, inherently stable current-input amplifiers for sensing a switching node (e.g., node SW1) of a driver power stage 104. Each amplifier generates an amplified version of the voltage across the monitored switch. For example, two current-input amplifiers monitor the current through a high-side switch (e.g., switch 202) for overcurrent protection, one in supply mode (e.g., for positive inductor current) and one in sink mode (e.g., for negative inductor current). Additionally, two current-input amplifiers monitor the current through a low-side switch (e.g., switch 204) for overcurrent protection, one in supply mode (e.g., for positive inductor current) and one in sink mode (e.g., for negative inductor current). Thus, the amplifier array supports current sensing in both positive and negative directions.

[0169] As described above, for example, in Figure 8-13In this process, a comparator array is used to compare the sensed voltages of the four sensors with corresponding programmable DC references. For example, DC comparators are used in both positive and negative directions to compare the amplified values ​​provided by each sensor with the references to generate overcurrent decisions. As described above, calibration circuitry is added to two of the sensors to pull a predefined current from a node of the sensor, thereby establishing a feedback loop and reducing (e.g., eliminating) DC errors. In the example described herein, a preliminary digital state machine (e.g., OI / UI state machine 824) samples, deglitches, and generates two overcurrent detection signals, and passes these two overcurrent detection signals to a subsequent digital state machine (e.g., mode control state machine 832).

[0170] Therefore, some embodiments facilitate the use of a single power inductor to manage the current and voltage supplied by a single-ended driver power stage. By cyclically limiting the peak instantaneous current through the power inductor for both positive and negative currents, some embodiments avoid performance degradation. For example, the peak instantaneous current through the power inductor is limited to a value less than the saturation current limit of the power inductor. Thus, the examples described herein avoid performance degradation that would otherwise occur when the power inductor is about to saturate.

[0171] Additionally, some embodiments reduce the DC error of overcurrent detection to less than 25 mA (e.g., DC error < ±25 mA) while supporting inductors with a wide range of saturation currents (e.g., from 2 A to 5 A). Some embodiments also support overcurrent limiting for both positive and negative currents in the three operating modes described herein (e.g., buck mode, inverting buck-boost mode, and intermediate mode). Therefore, by providing accurate overcurrent monitoring across all operating modes, some embodiments allow the current limit of the power inductor to be set very close to the saturation current limit. Furthermore, in some embodiments, overcurrent monitoring has minimal impact on the efficiency of the driver power stage and high area utilization.

[0172] Figure 14 According to embodiments of this disclosure Figure 8 A schematic diagram of the supply mode state machine 828. In Figure 14 In the example, the supply mode state machine 828 includes level shifters 1402 and 1404, which are used to downshift the drive signals of switches 202 and 204, respectively. Additionally, the supply mode state machine 828 includes example programmable delay degluing circuits 1406 and 1408, which are used to deglu the level-shifted drive signals. Figure 14 In the example, the supply mode state machine 828 includes example delay circuits 1410 and 1412, which are used to introduce delays to the level-shifted and de-glitched drive signals.

[0173] exist Figure 14In the example shown, the supply mode state machine 828 includes a first AND gate 1414 for performing a logical AND operation on the level-shifted, de-glitched, and delayed drive signal of switch 202 and the OI supply mode signal (identified as OI_SRC_COMP). Figure 14 In the example, the output of AND gate 1414 drives the clock input of first flip-flop 1416, which has a data input coupled to supply terminal 212 and a clear input coupled to the output of programmable delay deglitcher circuit 1406. The output of flip-flop 1416 drives the set input of set-reset (SR) latch 1418.

[0174] exist Figure 14 In the example shown, the supply mode state machine 828 also includes a second AND gate 1420 for performing a logical AND operation on the level-shifted, de-glitched, and delayed drive signal of switch 204 and the UI supply mode signal (identified as UI_SRC_COMP). Figure 14 In the example, the output of AND gate 1420 drives the clock input of a second flip-flop 1422, which has a data input coupled to supply terminal 212 and a clear input coupled to the output of programmable delay degluing circuit 1408. The output of flip-flop 1422 drives the reset input of SR latch 1418. Figure 14 In the example, the output of SR latch 1418 provides the supply mode OI detection signal (identified as OI_SRC_VD).

[0175] exist Figure 14 In the example shown, in response to the OI supply mode signal indicating the detection of a supply mode OI event and the closure value of the drive signal for switch 202 (e.g., indicating that switch 202 will close), the supply mode state machine 828 sets the supply mode OI detection signal to indicate that a supply mode OI event has been detected. In response to the UI supply mode signal indicating the detection of a supply mode UI event and the closure value of the drive signal for switch 204 (e.g., indicating that switch 204 will close), the supply mode state machine 828 resets the supply mode OI detection signal to indicate that the detected supply mode OI event has been cleared.

[0176] Figure 15 According to embodiments of this disclosure Figure 8 A schematic diagram of the absorption mode state machine 830. Figure 15In the example, the absorption mode state machine 830 includes example level shifters 1502, 1504, and 1506 for down-level shifting the drive signals of switches 202 and 204. For example, level shifters 1502 and 1504 down-level shift the drive signal of switch 204, and level shifter 1506 down-level shifts the drive signal of switch 202. Additionally, the absorption mode state machine 830 includes programmable delay deglitch circuits 1508, 1510, and 1512 for deglitching the level-shifted drive signals. For example, programmable delay deglitch circuits 1508 and 1510 deglitch the level-shifted drive signal of switch 204, and programmable delay deglitch circuit 1512 deglitch the level-shifted drive signal of switch 202. Figure 15 In the example, the absorption mode state machine 830 includes example delay circuits 1514, 1516, and 1518 for introducing a delay to a level-shifted and de-glitched drive signal. For example, delay circuits 1514 and 1516 delay the level-shifted and de-glitched drive signal of switch 204, and delay circuit 1518 delays the level-shifted and de-glitched drive signal of switch 202.

[0177] exist Figure 15 In the example shown, the absorption mode state machine 830 includes a first AND gate 1520 for performing a logical AND operation on the level-shifted, de-glitched, and delayed drive signal of switch 204 and the OI absorption mode signal (identified as OI_SNK_COMP). Figure 15 In the example, the output of AND gate 1520 drives the clock input of first flip-flop 1522, which has a data input coupled to supply terminal 212 and a clear input coupled to the output of programmable delay deglitcher circuit 1508. The output of flip-flop 1522 drives the set input of set-reset (SR) latch 1524.

[0178] exist Figure 15 In the example shown, the absorption mode state machine 830 also includes a second AND gate 1526 for performing a logical AND operation on the level-shifted, de-glitched, and delayed drive signal of switch 204 and the low-side UI absorption mode signal (identified as UI_SNK_COMP). Figure 15 In the example, the output of AND gate 1526 drives the clock input of a second flip-flop 1528, which has a data input coupled to supply terminal 212 and a clear input coupled to the output of programmable delay deglitcher circuit 1510. The output of flip-flop 1528 drives the first input of OR gate 1530.

[0179] exist Figure 15In the example shown, the absorption mode state machine 830 includes a third AND gate 1532 for performing a logical AND operation on the level-shifted, de-glitched, and delayed drive signal of switch 202 and the high-side UI absorption mode signal (identified as HS_UI_SNK_COMP). Figure 15 In the example, the output of AND gate 1532 drives the clock input of a third flip-flop 1534, which has a data input coupled to supply terminal 212 and a clear input coupled to the output of programmable delay degluing circuit 1512. The output of flip-flop 1534 drives the second input of OR gate 1530. Figure 15 In the example, the output of OR gate 1530 drives the reset input of SR latch 1524. Additionally, the output of SR latch 1524 provides an absorption mode OI detection signal (identified as OI_SNK_VD).

[0180] exist Figure 15 In the example shown, in response to the OI absorption mode signal indicating the detection of an absorption mode OI event and the closure value of the drive signal for switch 204 (e.g., indicating that switch 204 will close), the absorption mode state machine 830 sets the absorption mode OI detection signal to indicate that an absorption mode OI event has been detected. In response to the low-side UI absorption mode signal indicating the detection of a low-side absorption mode UI event and the closure value of the drive signal for switch 204 (e.g., indicating that switch 204 will close), the absorption mode state machine 830 resets the absorption mode OI detection signal to indicate that the detected absorption mode OI event has been cleared. Alternatively, in response to the high-side UI absorption mode signal indicating the detection of a high-side absorption mode UI event and the closure value of the drive signal for switch 202 (e.g., indicating that switch 202 will close), the absorption mode state machine 830 resets the absorption mode OI detection signal to indicate that the detected absorption mode OI event has been cleared.

[0181] Figure 16 This is a timing diagram according to an embodiment of the present disclosure, depicting the operation in supply mode during buck mode operation. Figure 2 Example UI protection and OI protection for driver power stage 104. Figure 16 In the example, the timing diagram depicts a signal corresponding to a voltage of 3.3V (e.g., AVDD = 3.3V) at supply terminal 212, where driver power stage 104 is in buck mode, supply mode OI limit is 3.45A, and supply mode UI limit is 2.75A. Additionally, Figure 16 The timing diagram depicts the signals corresponding to the output terminals of driver power stage 104 being shorted to ground (e.g., via a 5 milliohm (mΩ) resistor).

[0182] exist Figure 16In the example shown, the first row of the timing diagram depicts the current through inductor 210 (labeled IL) and a scaled version of the current through replica transistor 902 (labeled I_REP_OI_SRC). 1000). Additionally, Figure 16 The second row of the timing diagram depicts the voltage at the output of the high-side supply mode sensor 806 (labeled VSNS_OI_SRC) and the supply mode OI reference voltage (labeled VREF_OI_SRC). Figure 16 In the example, the third row of the timing diagram depicts the OI supply mode signal (identified as OI_SRC_COMP) provided by the high-side supply mode OI comparator 808.

[0183] exist Figure 16 In the example shown, the fourth row of the timing diagram depicts a scaled version of the current through inductor 210 (labeled IL) and the current through replica transistor 1102 (labeled I_REP_UI_SRC). (2000). Additionally, Figure 16 The fifth row of the timing diagram depicts the voltage at the output of the low-side supply mode sensor 810 (labeled VSNS_UI_SRC) and the supply mode UI reference voltage (labeled VREF_UI_SRC). Figure 16 In the example, the sixth row of the timing diagram depicts the UI provisioning mode signal (identified as UI_SRC_COMP) provided by the low-side provisioning mode UI comparator 812.

[0184] exist Figure 16 In the example shown, the seventh row of the timing diagram depicts the supply mode OI detection signal (identified as OI_SRC_VD) provided by the supply mode state machine 828. As described above, the supply mode state machine 828 generates the supply mode OI detection signal as a de-glitched and latched version of the OI supply mode signal and the UI supply mode signal. Figure 16 As shown, the voltage at the output of the high-side supply mode sensor 806 and the voltage at the output of the low-side supply mode sensor 810 track the current through the inductor 210 very closely.

[0185] Figure 17 This is a timing diagram according to an embodiment of the present disclosure, depicting the process during intermediate mode operation in absorption mode. Figure 2 Example UI protection and OI protection for driver power stage 104. Figure 17In the example, the timing diagram depicts a signal corresponding to a voltage of 3.3V at supply terminal 212 (e.g., AVDD = 3.3V), where driver power stage 104 is in intermediate mode, with an absorption mode OI limit of -3.45A and a high-side absorption mode UI limit of -2.75A. Additionally, Figure 17 The timing diagram depicts the signals corresponding to the output terminal of driver power stage 104 being shorted to ground (e.g., via a 5mΩ resistor).

[0186] exist Figure 17 In the example shown, the first row of the timing diagram depicts the current through inductor 210 (labeled IL) and a scaled version of the current through replica transistor 1202 (labeled I_REP_OI_SNK). Figure 17 In the example, for ease of understanding, the current through inductor 210 and the current through replica transistor 1202 are shown as having positive values. In absorption mode, the current through inductor 210 and the current through replica transistor 1202 are negative, as described above. Figure 17 In the example, the second row of the timing diagram depicts the voltage at the output of the low-side absorption mode sensor 814 (labeled VSNS_OI_SNK) and the absorption mode OI reference voltage (labeled VREF_OI_SNK). Additionally, Figure 17 The third row of the timing diagram depicts the OI absorption mode signal (labeled OI_SNK_COMP) provided by the low-side absorption mode OI comparator 816.

[0187] exist Figure 17 In the example shown, the fourth row of the timing diagram depicts a scaled version of the current through inductor 210 (labeled IL) and the current through replica transistor 1302 (labeled I_REP_UI_SNK). Figure 17 In the example, for ease of understanding, the current through inductor 210 and the current through replica transistor 1302 are shown as having positive values. In absorption mode, the current through inductor 210 and the current through replica transistor 1302 are negative, as described above. Figure 17 In the example, the fifth row of the timing diagram depicts the high-side UI absorption mode signal (identified as HS_UI_SNK_COMP) provided by the high-side absorption mode UI comparator 822. Additionally, Figure 17 The sixth row of the timing diagram depicts the voltage at the output of the high-side absorption mode sensor 820 (labeled VSNS_UI_SNK) and the high-side absorption mode UI reference voltage (labeled VREF_HS_UI_SNK).

[0188] exist Figure 17In the example shown, the seventh row of the timing diagram depicts the absorption mode OI detection signal (labeled OI_SNK_VD) provided by the absorption mode state machine 830. As described above, the absorption mode state machine 830 generates the absorption mode OI detection signal as a de-glitched and latched version of the OI absorption mode signal and the high-side UI absorption mode signal. Figure 17 As shown, the voltage at the output of the low-side absorption mode sensor 814 and the voltage at the output of the high-side absorption mode sensor 820 track the current through the inductor 210 very closely.

[0189] Figure 18 The timing diagram, according to an embodiment of the present disclosure, depicts the absorption mode during inverted buck-boost mode operation. Figure 2 Example UI protection and OI protection for driver power stage 104. Figure 18 In the example, the timing diagram depicts a signal corresponding to a voltage of 3.3V at supply terminal 212 (e.g., AVDD = 3.3V), where driver power stage 104 is in inverting buck-boost mode, with an absorption mode OI limit of -3.45A and a low-side absorption mode UI limit of -2.75A. Additionally, Figure 18 The timing diagram depicts the signals corresponding to the output terminal of driver power stage 104 being shorted to ground (e.g., via a 5mΩ resistor).

[0190] exist Figure 18 In the example shown, the first row of the timing diagram depicts the current through inductor 210 (labeled IL) and a scaled version of the current through replica transistor 1202 (labeled I_REP_OI_SNK). (2000). For example Figure 18 As shown, during inverting buck-boost mode operation, in absorption mode, the current through replica transistor 1202 is continuous. For ease of understanding, as described above, the current through inductor 210 and the current through replica transistor 1202 are shown as having positive values. In absorption mode, the current through inductor 210 and the current through replica transistor 1202 are negative, as described above. Figure 18 In the example, the second row of the timing diagram depicts the voltage at the output of the low-side absorption mode sensor 814 (labeled VSNS_OI_SNK) and the absorption mode OI reference voltage (labeled VREF_OI_SNK). Additionally, Figure 18 The third row of the timing diagram depicts the OI absorption mode signal (labeled OI_SNK_COMP) provided by the low-side absorption mode OI comparator 816.

[0191] exist Figure 18In the example shown, the fourth row of the timing diagram depicts the voltage at the output of the low-side absorption mode sensor 814 (labeled VSNS_UI_SNK) and the low-side absorption mode UI reference voltage (labeled VREF_UI_SNK). Additionally, Figure 18 The fifth row of the timing diagram depicts the low-side UI absorption mode signal (identified as UI_SNK_COMP) provided by the low-side absorption mode UI comparator 818. Figure 18 In the example, the sixth row of the timing diagram depicts the absorption mode OI detection signal (identified as OI_SNK_VD) provided by the absorption mode state machine 830. As described above, the absorption mode state machine 830 generates the absorption mode OI detection signal as a de-glitched and latched version of the OI absorption mode signal and the low-side UI absorption mode signal.

[0192] As described above, the example OI current sensor subsystem 804 (e.g., overcurrent protection circuitry) implements bidirectional cycle-by-cycle current limiting of the driver power stage 104 to seamlessly control the inductor current in the three operating modes of the driver power stage 104. Furthermore, the OI current sensor subsystem 804 is non-destructive and does not require off-chip, high-power precision resistors for current sensing. This non-destructive sensing capability of the OI current sensor subsystem 804 contributes to the driver power stage 104 achieving a peak power efficiency of >92%.

[0193] Furthermore, the example calibration described herein reduces the offset requirements of the high-side supply mode sensor 806, high-side supply mode OI comparator 808, low-side absorption mode sensor 814, and low-side absorption mode OI comparator 816, thereby enabling a more compact design. In the example described herein, by supporting higher peak currents through inductor 210, the accuracy of the OI current sensor subsystem 804 (e.g., ±25 mA or <±2.5%) helps to increase (e.g., maximize) the output power of TEC element 102. Moreover, the accuracy of the OI current sensor subsystem 804 allows the driver power stage 104 to be used with a variety of saturation current values ​​of inductor 210.

[0194] although Figure 8-15 The implementation is shown in the figure. Figure 8 The system 800 is an example of a specific configuration, but one or more of the elements, processes, and / or devices shown in Figures 8-15 may be combined, divided, rearranged, omitted, removed, and / or implemented in any other way. Furthermore, Figure 8-15 One or more of the components, processes, and / or devices can be implemented by hardware alone, or by a combination of hardware and software and / or firmware. Therefore, for example, Figure 8-15Any of the components, processes, and / or devices can be implemented by one or more programmable circuits, processor circuits, analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), vision processing units (VPUs), and / or field-programmable logic devices (FPLDs) such as FPGAs combined with machine-readable instructions (e.g., firmware or software). Furthermore, Figure 8-15 The elements, processes and / or devices may include one or more elements, processes and / or devices as Figure 8-15 The elements, processes, and apparatus shown may be supplemented or substituted for those shown, and / or may include more than one of any or all of the elements, processes, and apparatus shown.

[0195] Alternatively, or alternatively, Figure 8-15 One or more of the elements, processes, and / or devices shown can be implemented by example machine-readable instructions, which can be executed by one or more programmable circuits to implement and / or instantiate them. Figure 8-15 One or more of the elements, processes and / or devices shown herein, and / or may be implemented and / or instantiated by one or more programmable circuits. Figure 8-15 The machine-readable instructions are one or more of the elements, processes, and / or devices shown. Machine-readable instructions can be one or more executable programs or portions of one or more executable programs that are executed by one or more programmable circuits. In some examples, machine-readable instructions cause operations, tasks, etc., to be performed and / or executed automatically in the real world. In some examples, "automatic" means without human intervention.

[0196] A program may be embodied as instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media.

[0197] Although the example program is for reference Figure 8-15 The elements, processes, and / or apparatus shown are described, but many other embodiments may be used alternatively. Figure 8 The system 800 method. For example, Figure 8-15 The execution order of the components, processes, and / or devices shown may be changed, and / or Figure 8-15 Some of the components, processes, and / or devices shown may be altered, removed, or combined. Alternatively or alternatively, Figure 8-15Any or all of the elements, processes, and / or devices shown may be implemented by one or more hardware circuits (e.g., one or more processor circuits, one or more discrete analog circuits, one or more integrated analog circuits, one or more discrete digital circuits, one or more integrated digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations, without the need to execute software or firmware. The one or more programmable circuits may be distributed across different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)).

[0198] As described above, it should be understood that the example systems, devices, articles of art, and methods described include a four-switch topology that uses a single inductor and a single capacitor, saving board space and cost, and drives TEC elements in a single-ended manner, with one end of the TEC element grounded. The examples described herein include three switching modes, achieving extremely low zero-crossing glitches and high overall efficiency. Depending on the switching mode, the example four-switch topology described herein can seamlessly generate positive, negative, or both positive and negative voltages on the TEC element to ensure glitch-free zero crossings.

[0199] For example, the described four-switch topology operates in an intermediate mode with a specific switching sequence and a duty cycle of 0.5 to generate a 0V output voltage. Therefore, the example described herein avoids abrupt changes in duty cycle or switching mode near the zero-crossing point. Thus, the example described herein enables a seamless transition from a negative output to a positive output (and vice versa), achieving glitched zero crossing.

[0200] The examples described herein also include an example overcurrent protection circuit that reliably limits inductor current in both positive and negative directions without the need for an external sensing resistor. Therefore, the example overcurrent protection circuit described herein results in minimal efficiency loss and low sensing error. Furthermore, the example overcurrent protection circuit described herein handles overcurrent events (e.g., short circuits) in all three operating modes mentioned above. Additionally, by operating on a low-voltage switching node (e.g., node SW1), the example overcurrent protection circuit described herein reduces area footprint because current monitoring can utilize a relatively smaller, lower-voltage transistor compared to the example overcurrent protection circuit operating on a high-voltage switching node (e.g., node SW2).

[0201] Exemplary embodiments of this disclosure are outlined herein. Other embodiments may be understood from the entire specification and claims submitted herein.

[0202] Example 1. An electronic circuit comprising: first and second supply terminals; first and second inductor terminals; an output terminal; a first switch coupled between the first supply terminal and the first inductor terminal; a second switch coupled between the first inductor terminal and the second supply terminal; a third switch coupled between the first supply terminal and the second inductor terminal; a fourth switch coupled between the second inductor terminal and the output terminal; and a controller configured to: close the fourth switch, open the third switch, and operate the first and second switches in alternating phases when the output voltage at the output terminal is higher than the first threshold; close the second switch, open the first switch, and operate the third and fourth switches in alternating phases when the output voltage is lower than the first threshold; and operate the first and fourth switches according to the first clock signal and the second and third switches according to the second clock signal that does not overlap with the first clock signal when the output voltage is between the first and second thresholds.

[0203] Example 2. The electronic circuit according to Example 1, wherein the controller is configured to adjust the output voltage by adjusting the duty cycle of the first clock signal when the output voltage is between the first and second thresholds.

[0204] Example 3. An electronic circuit according to any one of Examples 1 or 2, wherein the controller is configured to generate a first clock signal having a fixed frequency and a second clock signal having the fixed frequency.

[0205] Example 4. An electronic circuit according to any one of Examples 1 to 3, wherein the first, second, third and fourth switches are n-channel metal-oxide-semiconductor field-effect transistors.

[0206] Example 5. An electronic circuit according to any one of Examples 1 to 4, wherein the first and third switches are p-channel metal-oxide-semiconductor field-effect transistors, and the second and fourth switches are n-channel metal-oxide-semiconductor field-effect transistors.

[0207] Example 6. An electronic circuit according to any one of Examples 1 to 5, wherein the second supply terminal is a ground terminal, wherein the first threshold is a positive voltage, and wherein the second threshold is a negative voltage.

[0208] Example 7. An electronic circuit according to any one of Examples 1 to 6, further comprising a thermoelectric cooler (TEC) element coupled between the output terminal and the second supply terminal.

[0209] Example 8. An electronic circuit according to any one of Examples 1 to 7, further comprising an inductor coupled between the first and second inductor terminals.

[0210] Example 9. An electronic circuit according to any one of Examples 1 to 8, wherein the controller has first, second, third, and fourth outputs, and: the first switch has a first current path terminal coupled to the first supply terminal, a second current path terminal coupled to the first inductor terminal, and a control terminal coupled to the first output of the controller; the second switch has a first current path terminal coupled to the first inductor terminal, a second current path terminal coupled to the second supply terminal, and a control terminal coupled to the second output of the controller; the third switch has a first current path terminal coupled to the first supply terminal, a second current path terminal coupled to the second inductor terminal, and a control terminal coupled to the third output of the controller; and the fourth switch has a first current path terminal coupled to the second inductor terminal, a second current path terminal coupled to the output terminal, and a control terminal coupled to the fourth output of the controller.

[0211] Example 10. An electronic circuit comprising: first and second supply terminals; first and second inductor terminals; an output terminal coupled to the second inductor terminal; a first transistor having a current path coupled between the first supply terminal and the first inductor terminal; a second transistor having a current path coupled between the first inductor terminal and the second supply terminal; and a current sensing circuit comprising: a third transistor having a control terminal coupled to a control terminal of the first transistor and a first current path terminal coupled to the first supply terminal; a first amplifier having a first input coupled to a second current path terminal of the third transistor and a second input coupled to the current path of the first transistor; a fourth transistor having a first current path terminal coupled to the second current path terminal of the third transistor and a control terminal coupled to an output of the first amplifier; a second amplifier having a first input coupled to the second current path terminal of the fourth transistor; and a first resistor coupled to the second current path terminal of the fourth transistor.

[0212] Example 11. An electronic circuit according to Example 10, further comprising a calibration circuit, the calibration circuit comprising: a fifth transistor having a current path coupled between the current path of the first transistor and the second input of the first amplifier, and a control terminal coupled to the control terminals of the first and third transistors; a current mirror having a first input coupled to the current path of the fifth transistor; a first switch having a first current path terminal, a second current path terminal, and a control terminal, the second current path terminal being coupled to the second input of the current mirror; a first current source having an output coupled to the first current path terminal of the first switch; a second resistor coupled between the output of the current mirror and the second supply terminal; a third resistor coupled between the output of the current mirror and the second input of the second amplifier; a second switch having a first current path terminal and a second current path terminal, the second current path terminal being coupled to the second input of the second amplifier; and a second current source having an output coupled to the first current path terminal of the second switch.

[0213] Example 12. An electronic circuit according to any one of Examples 10 or 11, wherein the third resistor is a variable resistor.

[0214] Example 13. An electronic circuit according to any one of Examples 10 to 12, wherein the resistance of the second resistor is equal to the resistance of the first resistor.

[0215] Example 14. An electronic circuit according to any one of Examples 10 to 13, further comprising a controller having an output coupled to a third input of the second amplifier.

[0216] Example 15. An electronic circuit according to any one of Examples 10 to 14, wherein the current sensing circuit is a first current sensing circuit, and the electronic circuit further includes a second current sensing circuit comprising: a fifth transistor having a first current path terminal, a second current path terminal, and a control terminal, the first current path terminal being coupled to the current path of the second transistor, and the control terminal being coupled to a control terminal of the second transistor; a sixth transistor having a first current path terminal, a second current path terminal coupled to a second supply terminal, and a control terminal coupled to the first supply terminal; a third amplifier having a first input coupled to the second current path terminal of the fifth transistor and a second input coupled to the second current path terminal of the sixth transistor; a seventh transistor having a first current path terminal coupled to the second current path terminal of the fifth transistor and a control terminal coupled to the output of the third amplifier; a fourth amplifier having a first input coupled to the second current path terminal of the seventh transistor; and a second resistor coupled to the second current path terminal of the seventh transistor.

[0217] Example 16. An electronic circuit according to any one of Examples 10 to 15, further comprising: an inductor having a first terminal coupled to a first inductor terminal and a second terminal coupled to a second inductor terminal; and an output capacitor having a terminal coupled to the second terminal of the inductor, wherein the first current sensing circuit monitors an overcurrent event associated with the first transistor, and the second current sensing circuit monitors an undercurrent event associated with the second transistor.

[0218] Example 17. An electronic circuit according to any one of Examples 10 to 16, further comprising: a fifth transistor having a current path coupled between the first supply terminal and the second inductor terminal; a sixth transistor having a current path coupled between the second inductor terminal and the output terminal; an inductor coupled between the first inductor terminal and the second inductor terminal; and a thermoelectric cooler element coupled between the output terminal and the second supply terminal.

[0219] Example 18. A method comprising: operating first and second switches at a fixed switching frequency to regulate an output voltage at an output terminal, wherein the first switch is coupled between a first supply terminal and a first inductor terminal, wherein the second switch is coupled between the first inductor terminal and a second supply terminal, wherein an inductor is coupled between the first inductor terminal and the second inductor terminal, and wherein the output terminal is coupled to the second inductor terminal; turning off the first switch and turning on the second switch in response to an inductor current through the inductor being higher than a first current threshold to initiate a first discharge phase of the inductor; maintaining the first switch off and the second switch on during the first discharge phase of the inductor; and restarting operation of the first and second switches at the fixed switching frequency in response to the inductor current dropping below a second current threshold lower than the first current threshold to exit the first discharge phase.

[0220] Example 19. The method according to Example 18 further comprises: determining the inductor current during a charging phase of the inductor based on sensing the current flowing through the first switch; and determining the inductor current during a first discharging phase of the inductor based on sensing the current flowing through the second switch.

[0221] Example 20. The method according to any one of Examples 18 or 19, further comprising, in response to the output voltage being higher than a voltage threshold: turning off a third switch and turning on a fourth switch, wherein the third switch is coupled between the first supply terminal and the second inductor terminal, wherein the fourth switch is coupled between the second inductor terminal and the output terminal; and operating the first and second switches in alternating phases.

[0222] Example 21. A method according to any one of Examples 18 to 20, further comprising: operating the first and second switches and the third and fourth switches at the fixed switching frequency to regulate the output voltage, wherein the third switch is coupled between the first supply terminal and the second inductor terminal, and wherein the fourth switch is coupled between the second inductor terminal and the output terminal; in response to the inductor current dropping below a third current threshold while the second and third switches are turned on, turning off the second and third switches and turning on the first and fourth switches to initiate a second discharge phase of the inductor; maintaining the second and third switches off and the first and fourth switches on during the second discharge phase of the inductor; and in response to the inductor current being higher than a fourth current threshold higher than the third current threshold, restarting the operation of the second and third switches at the fixed switching frequency to exit the second discharge phase.

[0223] Example 22. A method according to any one of Examples 18 to 21, further comprising: in response to the output voltage being less than a voltage threshold, turning on the second switch, turning off the first switch, and operating a third and fourth switch in alternating phases, wherein the third switch is coupled between the first supply terminal and the second inductor terminal, and wherein the fourth switch is coupled between the second inductor terminal and the output terminal; in response to the inductor current dropping below a third current threshold while the second and third switches are turned on, turning off the third switch and turning on the fourth switch to initiate a second discharge phase of the inductor; maintaining the third switch off and the second and fourth switches on during the second discharge phase of the inductor; and in response to the inductor current being higher than a fourth current threshold higher than the third current threshold, restarting the operation of the second and third switches at the fixed switching frequency and in alternating phases to exit the second discharge phase.

[0224] Example 23. A method according to any one of Examples 18 to 22, wherein sensing the current flowing through the first switch comprises: applying a voltage to a control terminal of a first transistor, the voltage being equal to the voltage applied to the control terminal of the first switch; forcing a voltage at a second current path terminal of the first transistor to be equal to the voltage at a second current path terminal of the first switch, to replicate the current flowing through the first switch at the first transistor; applying the replicated current to a first resistor to convert the replicated current into a voltage; and comparing the voltage with a reference voltage proportional to a first reference current using an amplifier.

[0225] Example 24. The method according to any one of Examples 18 to 23, wherein the size of the first transistor matches the size of the first switch.

[0226] Example 25. The method according to any one of Examples 18 to 24, further comprising calibrating the amplifier to compensate for errors introduced at least by the matching between the first transistor and the first switch, the matching between the current and the replicated current, and the amplifier.

[0227] Example 26. A method according to any one of Examples 18 to 25, wherein calibrating the first reference current comprises: turning on the first switch and the third switch to set the inductor current to zero, wherein the third switch is coupled between the first supply terminal and the second inductor terminal; turning on the calibration switch to cause a current mirror to sense a calibration current through a second transistor, thereby sampling the calibration current, the second transistor being matched with the first transistor; applying the calibration current to a second resistor to generate a reference voltage; replicating the calibration current through the first transistor; applying the replicated calibration current to the first resistor to generate a sensed voltage; comparing the reference voltage with the sensed voltage; and applying one or more trim codes to the amplifier based on the reference and the sensed voltage until the amplifier changes its output state.

[0228] Example 27. The method according to any one of Examples 18 to 26, wherein the resistance of the first resistor is equal to the resistance of the second resistor.

[0229] Example 28. The method according to any one of Examples 18 to 27, wherein the calibration switch is turned off when the first switch and the second switch are operating in normal mode.

[0230] Example 29. An electronic circuit comprising: first and second supply terminals; first and second inductor terminals; an output terminal coupled to the second inductor terminal; a first transistor having a current path coupled between the first supply terminal and the first inductor terminal; a second transistor having a current path coupled between the first inductor terminal and the second supply terminal; and a current sensing circuit comprising: a third transistor having a first current path terminal, a second current path terminal, and a control terminal coupled to a control terminal of the second transistor, the second current path terminal being coupled to the second supply terminal; a first amplifier having a first input coupled to the first current path terminal of the third transistor and a second input coupled to the current path of the second transistor; a fourth transistor having a first current path terminal coupled to the first current path terminal of the third transistor and a control terminal coupled to an output of the first amplifier; a second amplifier having a first input coupled to the second current path terminal of the fourth transistor; and a first resistor coupled to the second current path terminal of the fourth transistor.

[0231] Example 30. An electronic circuit according to Example 29, wherein the first amplifier comprises: a first n-channel metal-oxide-semiconductor (NMOS) transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal being coupled to a first current path terminal of the third transistor, and the drain terminal being coupled to the control terminal of the fourth transistor; and a second NMOS transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal being coupled to the current path of the second transistor, and the drain terminal being coupled to the gate terminals of the first NMOS transistor and the second NMOS transistor.

[0232] Example 31. An electronic circuit according to any one of Examples 29 or 30, further comprising a calibration circuit, the calibration circuit comprising: a fifth transistor having a current path coupled between the current path of the second transistor and the second input of the first amplifier and a control terminal coupled to the first supply terminal; a current mirror having a first input coupled to the current path of the fifth transistor; a first switch having a first current path terminal, a second current path terminal and a control terminal, the second current path terminal being coupled to the second input of the current mirror; a first current source having an output coupled to the first current path terminal of the first switch; a second resistor coupled between the output of the current mirror and the first supply terminal; a third resistor coupled between the output of the current mirror and the second input of the second amplifier; a second switch having a first current path terminal and a second current path terminal, the second current path terminal being coupled to the second input of the second amplifier; and a second current source having an output coupled to the first current path terminal of the second switch.

[0233] Example 32. An electronic circuit according to any one of Examples 29 to 31, wherein the resistance of the second resistor is equal to the resistance of the first resistor.

[0234] Example 33. An electronic circuit according to any one of Examples 29 to 32, wherein the current mirror comprises: a first p-channel metal-oxide-semiconductor (PMOS) transistor having a source terminal, a drain terminal, and a gate terminal, the drain terminal being coupled to a second current path terminal of the fifth transistor, the source terminal being coupled to a second resistor; and a second PMOS transistor having a source terminal, a drain terminal, and a gate terminal, the drain terminal being coupled to the second current path terminal of the first switch and the gate terminals of the first PMOS transistor and the second PMOS transistor, the source terminal being coupled to a fourth resistor.

[0235] Example 34. An electronic circuit according to any one of Examples 29 to 33, wherein the current sensing circuit is a first current sensing circuit, and the electronic circuit further includes a second current sensing circuit comprising: a fifth transistor having a first current path terminal, a second current path terminal, and a control terminal, the second current path terminal being coupled to the current path of the first transistor, and the control terminal being coupled to a control terminal of the first transistor; a third amplifier having a first input coupled to the first current path terminal of the fifth transistor and a second input coupled to the current path of the first transistor; a sixth transistor having a first current path terminal coupled to the first current path terminal of the fifth transistor and a control terminal coupled to the output of the third amplifier; a fourth amplifier having a first input coupled to the second current path terminal of the sixth transistor; and a second resistor coupled to the second current path terminal of the sixth transistor.

[0236] Example 35. An electronic circuit according to any one of Examples 29 to 34, wherein the size of the fifth transistor matches the size of the first transistor.

[0237] Example 36. An electronic circuit according to any one of Examples 29 to 35, wherein the size of the third transistor matches the size of the second transistor.

[0238] Although this disclosure has been described with reference to illustrative embodiments, this specification is not restrictive. Those skilled in the art will understand, upon referring to this specification, various modifications and combinations of the illustrative embodiments and other embodiments.

Claims

1. An electronic circuit comprising: First and second supply terminals; First and second inductor terminals; Output terminals; A first switch is coupled between the first supply terminal and the first inductor terminal; A second switch is coupled between the first inductor terminal and the second supply terminal; A third switch is coupled between the first supply terminal and the second inductor terminal; A fourth switch is coupled between the second inductor terminal and the output terminal; as well as The controller is configured as follows: When the output voltage at the output terminal is higher than the first threshold, the fourth switch is closed, the third switch is opened, and the first and second switches are operated in alternating phases. When the output voltage is lower than a second threshold that is lower than the first threshold, the second switch is closed, the first switch is opened, and the third and fourth switches are operated in alternating phases; and When the output voltage is between the first and second thresholds, the first and fourth switches are operated according to the first clock signal, and the second and third switches are operated according to the second clock signal that does not overlap with the first clock signal.

2. The electronic circuit of claim 1, wherein the controller is configured to adjust the output voltage by adjusting the duty cycle of the first clock signal when the output voltage is between the first and second thresholds.

3. The electronic circuit of claim 1, wherein the controller is configured to generate a first clock signal having a fixed frequency and a second clock signal having the fixed frequency.

4. The electronic circuit according to claim 1, wherein the first, second, third and fourth switches are n-channel metal-oxide-semiconductor field-effect transistors.

5. The electronic circuit according to claim 1, wherein the first and third switches are p-channel metal-oxide-semiconductor field-effect transistors, and the second and fourth switches are n-channel metal-oxide-semiconductor field-effect transistors.

6. The electronic circuit of claim 1, wherein the second supply terminal is a ground terminal, wherein the first threshold is a positive voltage, and wherein the second threshold is a negative voltage.

7. The electronic circuit of claim 1, further comprising a thermoelectric cooler (TEC) element coupled between the output terminal and the second supply terminal.

8. The electronic circuit of claim 1, further comprising an inductor coupled between the first and second inductor terminals.

9. The electronic circuit of claim 1, wherein the controller has first, second, third and fourth outputs, and: The first switch has a first current path terminal coupled to the first supply terminal, a second current path terminal coupled to the first inductor terminal, and a control terminal coupled to the first output of the controller; The second switch has a first current path terminal coupled to the first inductor terminal, a second current path terminal coupled to the second supply terminal, and a control terminal coupled to the second output of the controller; The third switch has a first current path terminal coupled to the first supply terminal, a second current path terminal coupled to the second inductor terminal, and a control terminal coupled to the third output of the controller; as well as The fourth switch has a first current path terminal coupled to the second inductor terminal, a second current path terminal coupled to the output terminal, and a control terminal coupled to the fourth output of the controller.

10. A method comprising: The first and second switches are operated at a fixed switching frequency to regulate the output voltage at the output terminal, wherein the first switch is coupled between a first supply terminal and a first inductor terminal, wherein the second switch is coupled between the first inductor terminal and the second supply terminal, wherein the inductor is coupled between the first inductor terminal and the second inductor terminal, and wherein the output terminal is coupled to the second inductor terminal. In response to the inductor current through the inductor being higher than a first current threshold, the first switch is turned off and the second switch is turned on to begin the first discharge phase of the inductor. During the first discharge phase of the inductor, the first switch remains off and the second switch remains on. as well as In response to the inductor current dropping below a second current threshold that is lower than the first current threshold, the first and second switches are restarted at the fixed switching frequency to exit the first discharge phase.

11. The method of claim 10, further comprising: The inductor current is determined during the charging phase of the inductor based on the sensed current flowing through the first switch. as well as The inductor current is determined during the first discharge phase of the inductor based on the sensed current flowing through the second switch.

12. The method of claim 11, wherein sensing the current flowing through the first switch comprises: A voltage is applied to the control terminal of the first transistor, the voltage being equal to the voltage applied to the control terminal of the first switch; The voltage at the second current path terminal of the first transistor is forced to be equal to the voltage at the second current path terminal of the first switch, so as to replicate the current flowing through the first switch at the first transistor; and The replicated current is applied to the first resistor to convert the replicated current into a voltage; as well as The voltage is compared with a reference voltage, which is proportional to a first reference current, using an amplifier.

13. The method of claim 12, wherein the size of the first transistor matches the size of the first switch.

14. The method of claim 12, further comprising calibrating the amplifier to compensate for errors introduced at least by the matching between the first transistor and the first switch, the matching between the current and the replicated current, and the amplifier.

15. The method of claim 14, wherein calibrating the first reference current comprises: The first switch and the third switch are turned on to set the inductor current to zero, wherein the third switch is coupled between the first supply terminal and the second inductor terminal; The calibration switch is turned on so that the current mirror senses the calibration current through the second transistor, thereby sampling the calibration current, wherein the second transistor is matched with the first transistor; The calibration current is applied to the second resistor to generate a reference voltage; The calibration current is replicated through the first transistor; The replicated calibration current is applied to the first resistor to generate the sensed voltage; Compare the reference voltage with the sensed voltage; as well as Based on the reference and the sensed voltage, one or more trim codes are applied to the amplifier until the amplifier changes its output state.

16. The method of claim 15, wherein the resistance of the first resistor is equal to the resistance of the second resistor.

17. The method of claim 15, wherein the calibration switch is turned off when the first switch and the second switch are operating in normal mode.

18. The method of claim 10, further comprising responding to the output voltage being higher than a voltage threshold: Turn off the third switch and turn on the fourth switch, wherein the third switch is coupled between the first supply terminal and the second inductor terminal, and wherein the fourth switch is coupled between the second inductor terminal and the output terminal; and The first and second switches are operated in alternating phases.

19. The method of claim 10, further comprising: The first and second switches and the third and fourth switches are operated at the fixed switching frequency to regulate the output voltage, wherein the third switch is coupled between the first supply terminal and the second inductor terminal, and wherein the fourth switch is coupled between the second inductor terminal and the output terminal; In response to the inductor current dropping below a third current threshold while the second and third switches are turned on, the second and third switches are turned off and the first and fourth switches are turned on to begin the second discharge phase of the inductor. During the second discharge phase of the inductor, the second and third switches are kept off and the first and fourth switches are kept on. as well as In response to the inductor current being higher than a fourth current threshold that is higher than the third current threshold, the second and third switches are restarted at the fixed switching frequency to exit the second discharge phase.

20. The method of claim 10, further comprising: In response to the output voltage being less than a voltage threshold, the second switch is turned on, the first switch is turned off, and the third and fourth switches are operated in alternating phases, wherein the third switch is coupled between the first supply terminal and the second inductor terminal, and wherein the fourth switch is coupled between the second inductor terminal and the output terminal; In response to the inductor current dropping below a third current threshold while the second and third switches are turned on, the third switch is turned off and the fourth switch is turned on to begin the second discharge phase of the inductor. During the second discharge phase of the inductor, the third switch remains off and the second and fourth switches remain on. as well as In response to the inductor current being higher than a fourth current threshold that is higher than the third current threshold, the second and third switches are restarted to operate at the fixed switching frequency and in alternating phases to exit the second discharge phase.

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