Level shift circuit, driving method thereof, source driving chip and display device

Abstract

A level shift circuit, a driving method thereof, a source driving chip and a display device, the level shift circuit comprising: a plurality of level shift units, at least one level shift unit comprising: an output control sub-circuit, a first output sub-circuit and a second output sub-circuit; the output control sub-circuit is configured to control signals of first and second nodes under control of signals at a signal input end, a first power supply end, a second power supply end, a first bias voltage end and a second bias voltage end; the first output sub-circuit is configured to provide a signal of a ground end or the second power supply end to a first output end under control of the signal at the first node; the second output sub-circuit is configured to provide a signal of the ground end or the second power supply end to a second output end under control of the signal at the second node; the first power supply end is a digital power supply end, and the second power supply end is an analog negative voltage power supply end.

Description

Technical Field

[0001] This article relates to semiconductor integrated circuit technology, specifically to a level shifting circuit and its driving method, a source driver chip, and a display device. Background Technology

[0002] As a mainstream flat panel display device, liquid crystal displays (LCDs) are characterized by their thinness, low power consumption, and high resolution, and are widely used in various terminal display products. An LCD device includes a timing controller, a source driver chip, a gate driver chip, and a display panel. The timing controller provides control signals to the source and gate driver chips, which then generate drive signals to drive the display panel to emit light. The control signals provided by the timing controller to the source driver chip are low-voltage control signals adapted to digital logic circuits. The source driver chip internally incorporates high-voltage components such as analog-to-digital converters, multiplexing circuits, and output buffers. These high-voltage components require high-voltage control signals to drive them. Because the voltage difference between the low-voltage and high-voltage control signals is significant, they cannot be directly interchanged. Therefore, the source driver chip integrates a level shifting circuit to perform voltage conversion. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a level shifting circuit and its driving method, a source driver chip, and a display device.

[0005] In a first aspect, this disclosure provides a level shifting circuit, comprising: a plurality of level shifting units, at least one level shifting unit comprising: an output control sub-circuit, a first output sub-circuit, and a second output sub-circuit; The output control sub-circuit is electrically connected to the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, the second bias voltage terminal, the first node, and the second node, respectively, and is configured to control the signals of the first node and the second node under the control of the signals of the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, and the second bias voltage terminal. The first output sub-circuit is electrically connected to the second power supply terminal, the ground terminal, the first output terminal and the first node respectively, and is configured to provide the ground terminal or the second power supply terminal signal to the first output terminal under the control of the signal of the first node. The second output sub-circuit is electrically connected to the second power supply terminal, the ground terminal, the second output terminal, and the second node, respectively, and is configured to provide the ground terminal or the second power supply terminal signal to the second output terminal under the control of the signal of the second node; The first power supply terminal is a digital power supply terminal, and the second power supply terminal is an analog negative voltage power supply terminal.

[0006] In an exemplary embodiment, the output control sub-circuit includes: an input sub-circuit, a first current-limiting sub-circuit, a feedback sub-circuit, and a second current-limiting sub-circuit; The input sub-circuit is electrically connected to the signal input terminal, the first power supply terminal, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the third node or the fourth node under the control of the signal from the signal input terminal. The first current limiting sub-circuit is electrically connected to the first bias voltage terminal, the first node, the second node, the third node, and the fourth node, respectively, and is configured to control the signals of the first node and the second node under the control of the signals of the first bias voltage terminal, the third node, and the fourth node. The feedback sub-circuit is electrically connected to the first node, the second node, the fifth node, and the sixth node, respectively, and is configured to provide the signal of the fifth node to the first node and the signal of the sixth node to the second node under the control of the signals of the first node and the second node. The second current-limiting sub-circuit is electrically connected to the second bias voltage terminal, the fifth node, the sixth node, and the second power supply terminal, respectively, and is configured to control the signals of the fifth node and the sixth node under the control of the signals of the second bias voltage terminal and the second power supply terminal.

[0007] In an exemplary embodiment, the input sub-circuit includes: an inverter, a first transistor, and a second transistor, wherein the inverter includes: an input terminal and an output terminal; The input terminal of the inverter is electrically connected to the signal input terminal, and the output terminal of the inverter is electrically connected to the control electrode of the first transistor. The first terminal of the first transistor is electrically connected to the first power supply terminal, and the second terminal of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the signal input terminal, the first electrode of the second transistor is electrically connected to the first power supply terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The inverter is a low-voltage inverter, and the first transistor and the second transistor are low-voltage metal-oxide-semiconductor field-effect transistors, both of which are P-type transistors.

[0008] In an exemplary embodiment, the first current-limiting sub-circuit includes: a third transistor and a fourth transistor; The control electrode of the third transistor is electrically connected to the first bias voltage terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node. The control terminal of the fourth transistor is electrically connected to the first bias voltage terminal, the first terminal of the fourth transistor is electrically connected to the fourth node, and the second terminal of the fourth transistor is electrically connected to the second node. The third transistor and the fourth transistor are medium-voltage metal-oxide-semiconductor field-effect transistors, and both are P-type transistors; The third transistor and the fourth transistor are arranged at least partially symmetrically.

[0009] In an exemplary embodiment, the third transistor is a common-gate transistor corresponding to the first transistor, and the fourth transistor is a common-gate transistor corresponding to the second transistor.

[0010] In an exemplary embodiment, the feedback sub-circuit includes a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the fifth node. The control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the sixth node. The fifth transistor and the sixth transistor are medium-voltage metal-oxide-semiconductor field-effect transistors, and both are N-type transistors; The fifth transistor and the sixth transistor are arranged at least partially symmetrically.

[0011] In an exemplary embodiment, the second current-limiting sub-circuit includes: a seventh transistor and an eighth transistor; The control terminal of the seventh transistor is electrically connected to the second bias voltage terminal, the first terminal of the seventh transistor is electrically connected to the fifth node, and the second terminal of the seventh transistor is electrically connected to the second power supply terminal. The control terminal of the eighth transistor is electrically connected to the second bias voltage terminal, the first terminal of the eighth transistor is electrically connected to the sixth node, and the second terminal of the eighth transistor is electrically connected to the second power supply terminal. The seventh and eighth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, and both are N-type transistors; The seventh transistor and the eighth transistor are arranged at least partially symmetrically.

[0012] In an exemplary embodiment, the first output sub-circuit includes: a ninth transistor and a tenth transistor; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the ground terminal, and the second electrode of the ninth transistor is electrically connected to the first output terminal. The control electrode of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the first output terminal, and the second electrode of the tenth transistor is electrically connected to the second power supply terminal. The ninth and tenth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, with the ninth transistor being a P-type transistor and the tenth transistor being an N-type transistor.

[0013] In an exemplary embodiment, the second output sub-circuit includes an eleventh transistor and a twelfth transistor; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the ground terminal, and the second electrode of the eleventh transistor is electrically connected to the second output terminal. The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the second output terminal, and the second electrode of the twelfth transistor is electrically connected to the second power supply terminal. The eleventh and twelfth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, with the eleventh transistor being a P-type transistor and the twelfth transistor being an N-type transistor.

[0014] In an exemplary embodiment, the first output sub-circuit is also electrically connected to the second bias voltage terminal, and the first output sub-circuit includes: a ninth transistor, a tenth transistor, and a thirteenth transistor; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the ground terminal, and the second electrode of the ninth transistor is electrically connected to the first output terminal. The control electrode of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the first output terminal, and the second electrode of the tenth transistor is electrically connected to the seventh node. The control terminal of the thirteenth transistor is electrically connected to the second bias voltage terminal, the first terminal of the thirteenth transistor is electrically connected to the second power supply terminal, and the second terminal of the thirteenth transistor is electrically connected to the seventh node. The ninth, tenth, and thirteenth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, with the ninth transistor being a P-type transistor and the tenth and thirteenth transistors being N-type transistors.

[0015] In an exemplary embodiment, the second output sub-circuit is also electrically connected to a second bias voltage terminal, and the second output sub-circuit includes: an eleventh transistor, a twelfth transistor, and a fourteenth transistor; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the ground terminal, and the second electrode of the eleventh transistor is electrically connected to the second output terminal. The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the second output terminal, and the second electrode of the twelfth transistor is electrically connected to the eighth node. The control terminal of the fourteenth transistor is electrically connected to the second bias voltage terminal, the first terminal of the fourteenth transistor is electrically connected to the second power supply terminal, and the second terminal of the fourteenth transistor is electrically connected to the eighth node. The eleventh, twelfth, and fourteenth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, with the eleventh transistor being a P-type transistor and the twelfth and fourteenth transistors being N-type transistors.

[0016] In an exemplary embodiment, the first bias voltage terminal connected to the plurality of level shifting units in the level shifting circuit is the same bias voltage terminal, and the second bias voltage terminal connected to the plurality of level shifting units in the level shifting circuit is the same bias voltage terminal.

[0017] In an exemplary embodiment, when the level shifting circuit is in operation, the signals at the first bias voltage terminal and the second bias voltage terminal connected to at least one level shifting unit are both valid level signals. When the level shifting circuit is not in operation, the signals at the first bias voltage terminal and the second bias voltage terminal connected to at least one level shifting unit are both invalid level signals.

[0018] Secondly, this disclosure also provides a source driver chip, including: a bias circuit and the above-mentioned level shifting circuit; The first bias voltage terminal and the second bias voltage terminal of the bias circuit are electrically connected to at least one level shifting unit in the level shifting circuit.

[0019] In an exemplary embodiment, the bias circuit includes: the fifteenth to the thirty-third transistors, a first current source, and a second current source, wherein the first current source and the second current source include: a first terminal and a second terminal; The control electrode of the fifteenth transistor is electrically connected to the first node, the first electrode of the fifteenth transistor is electrically connected to the second bias voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second node. The control electrode of the sixteenth transistor is electrically connected to the third node, the first electrode of the sixteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixteenth transistor is electrically connected to the second node. The control electrode and the second electrode of the seventeenth transistor are electrically connected to the first bias voltage terminal, respectively, and the first electrode of the seventeenth transistor is electrically connected to the fourth node. The control electrode and the second electrode of the eighteenth transistor are electrically connected to the fourth node, and the first electrode of the eighteenth transistor is electrically connected to the first power supply terminal. The control electrode of the nineteenth transistor is electrically connected to the first node, the first electrode of the nineteenth transistor is electrically connected to the fifth node, and the second electrode of the nineteenth transistor is electrically connected to the sixth node. The control electrode of the twentieth transistor is electrically connected to the third node, the first electrode of the twentieth transistor is electrically connected to the first power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the fifth node. The control electrode of the 21st transistor is electrically connected to the first node, the first electrode of the 21st transistor is electrically connected to the seventh node, and the second electrode of the 21st transistor is electrically connected to the eighth node. The control electrode of the 22nd transistor is electrically connected to the third node, the first electrode of the 22nd transistor is electrically connected to the first power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the seventh node. The control electrode of the 23rd transistor is electrically connected to the first node, the first electrode of the 23rd transistor is electrically connected to the first power supply terminal, and the second electrode of the 23rd transistor is electrically connected to the ninth node. The control electrode of the 24th transistor is electrically connected to the third node, the first electrode of the 24th transistor is electrically connected to the first power supply terminal, and the second electrode of the 24th transistor is electrically connected to the 10th node. The control electrode of the 25th transistor is electrically connected to the first node, the first electrode of the 25th transistor is electrically connected to the 10th node, and the second electrode of the 25th transistor is electrically connected to the 11th node. The control terminal of the 26th transistor is electrically connected to the first enable signal terminal, the first terminal of the 26th transistor is electrically connected to the first power supply terminal, and the second terminal of the 26th transistor is electrically connected to the first bias voltage terminal. The control electrode and the first electrode of the 27th transistor are respectively electrically connected to the second bias voltage terminal, and the second electrode of the 27th transistor is electrically connected to the second power supply terminal. The control electrode of the 28th transistor is electrically connected to the 8th node, the first electrode of the 28th transistor is electrically connected to the second power supply terminal, and the second electrode of the 28th transistor is electrically connected to the 12th node. The control electrode of the 29th transistor is electrically connected to the sixth node, the first electrode of the 29th transistor is electrically connected to the first bias voltage terminal, and the second electrode of the 29th transistor is electrically connected to the 12th node. The control electrode and the first electrode of the thirtieth transistor are electrically connected to the sixth node, and the second electrode of the thirtieth transistor is electrically connected to the second power supply terminal. The control electrode of the 31st transistor is electrically connected to the 6th node, the first electrode of the 31st transistor is electrically connected to the 8th node, and the second electrode of the 31st transistor is electrically connected to the 13th node. The control electrode of the 32nd transistor is electrically connected to the 8th node, the first electrode of the 32nd transistor is electrically connected to the second power supply terminal, and the second electrode of the 32nd transistor is electrically connected to the 13th node. The control terminal of the 33rd transistor is electrically connected to the second enable signal terminal, the first terminal of the 33rd transistor is electrically connected to the second bias voltage terminal, and the second terminal of the 33rd transistor is electrically connected to the second power supply terminal. The first end of the first current source is electrically connected to the eleventh node, and the second end of the first current source is electrically connected to the second power supply terminal. The first end of the second current source is electrically connected to the ninth node, and the second end of the second current source is electrically connected to the second power supply terminal. Transistors 16 through 26 are P-type transistors, and transistors 27 through 33 are N-type transistors.

[0020] Thirdly, this disclosure also provides a display device, including the aforementioned source driver chip.

[0021] Fourthly, this disclosure also provides a driving method for a level shifting circuit, configured to drive the aforementioned level shifting circuit, the method comprising: The output control sub-circuit controls the signals of the first node and the second node under the control of the signals at the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, and the second bias voltage terminal. Under the control of the signal from the first node, the first output sub-circuit provides a signal from the ground terminal or the second power supply terminal to the first output terminal. The second output sub-circuit, under the control of the signal from the second node, provides a ground terminal or a second power supply terminal signal to the second output terminal.

[0022] In an exemplary embodiment, the output control subcircuit includes: an input subcircuit, a first current-limiting subcircuit, a feedback subcircuit, and a second current-limiting subcircuit. Under the control of signals from the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, and the second bias voltage terminal, the output control subcircuit controls the signals of the first node and the second node, including: Under the control of the signal at the signal input terminal, the input sub-circuit provides the signal at the first power supply terminal to the third or fourth node; The first current-limiting sub-circuit controls the signals of the first node and the second node under the control of the signals of the first bias voltage terminal, the third node and the fourth node; Under the control of the signals from the first node and the second node, the feedback sub-circuit provides the signal from the fifth node to the first node and the signal from the sixth node to the second node; The second current-limiting sub-circuit controls the signals of the fifth and sixth nodes under the control of the signals at the second bias voltage terminal and the second power supply terminal.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0024] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0025] Figure 1 This is a schematic diagram of the level shifting circuit provided in this disclosure; Figure 2 This is a schematic diagram of the level shifting unit. Figure 3 The equivalent circuit diagram of the output control sub-circuit of the level shifting unit; Figure 4 The equivalent circuit diagram of the output control sub-circuit of the level shifting unit; Figure 5 Equivalent circuits of the first and second output sub-circuits of the level shifting unit Figure 1 ; Figure 6 Equivalent circuits of the first and second output sub-circuits of the level shifting unit Figure 2 ; Figure 7 Equivalent circuit of level shifting unit Figure 1 ; Figure 8 Equivalent circuit of level shifting unit Figure 2 ; Figure 9 A comparison chart of peak currents for shift units at different levels; Figure 10 A comparison chart of signal flipping speeds for different level shift units at standard process angles; Figure 11 A schematic diagram of the source driver chip provided in the embodiments of this disclosure. Figure 1 ; Figure 12 This is a schematic diagram showing the connection between the bias circuit and the level shifting circuit; Figure 13 This is the equivalent circuit diagram of the bias circuit. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs. The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0027] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0028] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0029] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0030] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0031] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0032] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0033] With the continuous development of display technology, source driver chips need to transmit more and more data, leading to increasingly higher requirements for integration. As a key circuit in source driver chips, the level shifter circuit requires both high driving capability to meet the driving requirements of the source driver chip, and low peak current to prevent excessive peak current during level shifting, which could damage the source driver chip. Existing level shifter circuits have relatively large peak currents, resulting in lower reliability of the source driver chip.

[0034] Therefore, embodiments of this disclosure provide a level shifting circuit and its driving method, a source driver chip, and a display device.

[0035] Figure 1 This is a schematic diagram of the level shifting circuit provided in this disclosure. Figure 2 This is a schematic diagram of a level shifting unit. Figure 1 and Figure 2 As shown, a level shifting circuit 10 provided in this embodiment includes: a plurality of level shifting units 100, and at least one level shifting unit 100 includes: an output control sub-circuit, a first output sub-circuit, and a second output sub-circuit.

[0036] like Figure 2As shown, the output control sub-circuit is electrically connected to the signal input terminal IN, the first power supply terminal V1, the second power supply terminal V2, the first bias voltage terminal VP, the second bias voltage terminal VN, the first node N1, and the second node N2, respectively. It is configured to control the signals of the first node N1 and the second node N2 under the control of the signals of the signal input terminal IN, the first power supply terminal V1, the second power supply terminal V2, the first bias voltage terminal VP, and the second bias voltage terminal VN, respectively. The first output sub-circuit is electrically connected to the second power supply terminal V2, the ground terminal GND, the first output terminal OUT1, and the first node N1, respectively. It is configured to provide the ground terminal GND or the second power supply terminal V2 signal to the first output terminal OUT1 under the control of the signal of the first node N1, respectively. The second output sub-circuit is electrically connected to the second power supply terminal V2, the ground terminal GND, the second output terminal OUT2, and the second node N2, respectively. It is configured to provide the ground terminal GND or the second power supply terminal V2 signal to the second output terminal OUT2 under the control of the signal of the second node N2, respectively.

[0037] In an exemplary embodiment, the first power supply terminal V1 can be a digital power supply terminal, and the second power supply terminal V2 can be an analog negative voltage power supply terminal.

[0038] This disclosure reduces the peak current of the level shift circuit and improves its reliability by electrically connecting the output control automatic circuit to the first bias voltage terminal and the second bias voltage terminal.

[0039] In an exemplary implementation, such as Figure 1 As shown, the first bias voltage terminal VP connected to the multiple level shift units in the level shift circuit is the same bias voltage terminal, and the second bias voltage terminal VN connected to the multiple level shift units in the level shift circuit is the same bias voltage terminal.

[0040] In an exemplary embodiment, when the level shifting circuit is in operation, the signals of the first bias voltage terminal VP and the second bias voltage terminal VN connected to at least one level shifting unit are both valid level signals. When the level shifting circuit is not in operation, the signals of the first bias voltage terminal VP and the second bias voltage terminal VN are both invalid level signals.

[0041] Figure 3 This is a schematic diagram of the output control sub-circuit of the level shifting unit. (Example:) Figure 3As shown, the output control subcircuit includes: an input subcircuit, a first current-limiting subcircuit, a feedback subcircuit, and a second current-limiting subcircuit. The input subcircuit is electrically connected to the signal input terminal IN, the first power supply terminal V1, the third node N3, and the fourth node N4, and is configured to provide the signal from the first power supply terminal V1 to either the third node N3 or the fourth node N4 under the control of the signal from the signal input terminal IN. The first current-limiting subcircuit is electrically connected to the first bias voltage terminal VP, the first node N1, the second node N2, the third node N3, and the fourth node N4, and is configured to control the signals from the first node N1 and the second node N2 under the control of the signals from the first bias voltage terminal, the third node N3, and the fourth node N4. The feedback sub-circuit, electrically connected to the first node N1, the second node N2, the fifth node N5, and the sixth node N6 respectively, is configured to provide the signal of the fifth node N5 to the first node N1 and the signal of the sixth node N6 to the second node N2 under the control of the signals of the first node N1 and the second node N2 respectively; the second current limiting sub-circuit, electrically connected to the second bias voltage terminal VN, the fifth node N5, the sixth node N6, and the second power supply terminal V2 respectively, is configured to control the signals of the fifth node N5 and the sixth node N6 under the control of the signals of the second bias voltage terminal VN and the second power supply terminal V2.

[0042] Figure 4 This is the equivalent circuit diagram of the output control sub-circuit of the level shifting unit. (Example:) Figure 4 As shown, the input sub-circuit includes: an inverter INV, a first transistor T1, and a second transistor T2. The inverter INV includes an input terminal and an output terminal. Specifically, the input terminal of the inverter INV is electrically connected to the signal input terminal IN, and the output terminal of the inverter INV is electrically connected to the control electrode of the first transistor T1. The first electrode of the first transistor T1 is electrically connected to the first power supply terminal V1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, and the first electrode of the second transistor T2 is electrically connected to the first power supply terminal V1. The second electrode of the second transistor T2 is also electrically connected to the fourth node N4.

[0043] In an exemplary embodiment, the first transistor T1 and the second transistor T2 are low-voltage metal-oxide-semiconductor field-effect transistors, and both are P-type transistors.

[0044] In an exemplary embodiment, since the first transistor T1 and the second transistor T2 are low-voltage metal-oxide-semiconductor field-effect transistors, the threshold voltages of the first transistor T1 and the second transistor T2 are relatively small. This not only makes the aspect ratio of the channel region of the active pattern of the first transistor T1 and the second transistor T2 smaller, reducing the area occupied by the first transistor T1 and the second transistor T2 and the area occupied by the level shift circuit, thus realizing the integration of the level shift circuit, but also makes the turn-on speed of the first transistor T1 and the second transistor T2 faster, improving the signal switching speed of the level shift circuit, and further improving the screen refresh rate of the display product where the level shift circuit is located.

[0045] In an exemplary embodiment, the signal switching speed of the level shifting circuit provided in this disclosure can reach 50MHz.

[0046] In an exemplary implementation, such as Figure 4 As shown, the first current-limiting sub-circuit includes a third transistor T3 and a fourth transistor T4. The control terminal of the third transistor T3 is electrically connected to the first bias voltage terminal VP, the first terminal of the third transistor T3 is electrically connected to the third node N3, and the second terminal of the third transistor T3 is electrically connected to the first node N1. Similarly, the control terminal of the fourth transistor T4 is electrically connected to the first bias voltage terminal VP, the first terminal of the fourth transistor T4 is electrically connected to the fourth node N4, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2.

[0047] In an exemplary embodiment, the third transistor T3 and the fourth transistor T4 are medium-voltage metal-oxide-semiconductor field-effect transistors, and both are P-type transistors.

[0048] In an exemplary embodiment, the placement of the third transistor T3 and the fourth transistor T4 can suppress peak current, reduce average current, thereby reducing power consumption, and also prevent the source driver chip where the level shift circuit is located from being damaged, which is beneficial for large-scale integration.

[0049] In an exemplary embodiment, the first transistor T1 is a common-source transistor, and the third transistor T3 is a common-gate transistor corresponding to the first transistor T1. The first transistor T1 and the third transistor T3 form a first common-gate common-source structure, and the third transistor T3 can serve as a shielding transistor for the first transistor T1.

[0050] In an exemplary embodiment, the second transistor T2 is a common-source transistor, and the fourth transistor T4 is a common-gate transistor corresponding to the second transistor T2. The second transistor T2 and the fourth transistor T4 form a second common-gate common-source structure, and the fourth transistor T4 can serve as a shielding transistor for the second transistor T2.

[0051] Since the common-gate common-source structure has a clamping effect, by setting a suitable signal at the first bias voltage terminal, it can be ensured that the maximum value of the source-drain voltage difference between the first transistor T1 and the second transistor T2 does not exceed the voltage value of the signal at the first power supply terminal.

[0052] In an exemplary embodiment, the third transistor T3 and the fourth transistor T4 are at least partially symmetrically arranged.

[0053] The third transistor T3 and the fourth transistor T4 in this disclosure are at least partially symmetrically arranged, which can improve the stability of the level shifting circuit under different process angles.

[0054] In an exemplary implementation, such as Figure 4 As shown, the feedback sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5. Similarly, the control electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the sixth node N6.

[0055] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be medium-voltage metal-oxide-semiconductor field-effect transistors, and both are N-type transistors.

[0056] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 constitute a differential pair structure. The differential pair structure is used to generate two differential drive signals with opposite phases for the first node and the second node, which can suppress common-mode noise in the circuit, reduce signal deviation caused by device mismatch at different process corners, and improve the stability and switching rate of the output signal of the level shift circuit.

[0057] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 are at least partially symmetrically arranged, which can improve the stability of the level shifting circuit under different process angles.

[0058] In an exemplary implementation, such as Figure 4 As shown, the second current-limiting sub-circuit includes a seventh transistor T7 and an eighth transistor T8. The control electrode of the seventh transistor T7 is electrically connected to the second bias voltage terminal VN, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the second power supply terminal V2. Similarly, the control electrode of the eighth transistor T8 is electrically connected to the second bias voltage terminal VN, the first electrode of the eighth transistor T8 is electrically connected to the sixth node N6, and the second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2.

[0059] In an exemplary embodiment, the seventh transistor T7 and the eighth transistor T8 are medium-voltage metal-oxide-semiconductor field-effect transistors, and both are N-type transistors.

[0060] In an exemplary embodiment, the seventh transistor T7 and the eighth transistor T8 are at least partially symmetrically arranged, which can improve the stability of the level shifting circuit under different process angles.

[0061] In an exemplary embodiment, the seventh transistor T7 and the eighth transistor T8 constitute a current source, which can not only obtain better voltage gain, but also suppress peak current, reduce average current, and thus reduce power consumption.

[0062] In an exemplary embodiment, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 constitute a load transistor, the impedance R of which satisfies: R=-2 g1 r / g2 Where g1 is the transconductance of the seventh transistor T7 and the eighth transistor T8, g2 is the transconductance of the fifth transistor T5 and the sixth transistor T6, and r is the output resistance of the seventh transistor T7 and the eighth transistor T8.

[0063] Figure 5 Equivalent circuits of the first and second output sub-circuits of the level shifting unit Figure 1 .like Figure 5 As shown, the first output sub-circuit includes a ninth transistor T9 and a tenth transistor T10. The control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the ground terminal GND, and the second electrode of the ninth transistor T9 is electrically connected to the first output terminal OUT1. Similarly, the control electrode of the tenth transistor T10 is electrically connected to the first node N1, the first electrode of the tenth transistor T10 is electrically connected to the first output terminal OUT1, and the second electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2.

[0064] In an exemplary embodiment, the ninth transistor T9 and the tenth transistor T10 are medium-voltage metal-oxide-semiconductor field-effect transistors, and the ninth transistor T9 is a P-type transistor and the tenth transistor T10 is an N-type transistor.

[0065] In an exemplary embodiment, the ninth transistor T9 and the tenth transistor T10 form an inverter, which can shape the waveform of the input signal, improve the driving capability, and set the voltage range of the signal output by the level shift circuit within the level range of the ground terminal and the second power supply terminal, so as to meet the voltage requirements for normal operation of the devices connected to the level shift circuit.

[0066] like Figure 5 As shown, the second output sub-circuit includes an eleventh transistor T11 and a twelfth transistor T12. The control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the ground terminal GND, and the second electrode of the eleventh transistor T11 is electrically connected to the second output terminal OUT2. The control electrode of the twelfth transistor T12 is electrically connected to the second node N2, the first electrode of the twelfth transistor T12 is electrically connected to the second output terminal OUT2, and the second electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2.

[0067] In an exemplary embodiment, the eleventh transistor T11 and the twelfth transistor T12 are medium-voltage metal-oxide-semiconductor field-effect transistors, and the eleventh transistor T11 is a P-type transistor and the twelfth transistor T12 is an N-type transistor.

[0068] In an exemplary embodiment, the eleventh transistor T11 and the twelfth transistor T12 form an inverter, which can shape the waveform of the input signal, improve the driving capability, and set the voltage range of the signal output by the level shift circuit within the level range of the ground terminal and the second power supply terminal, so as to meet the voltage requirements for normal operation of the devices connected to the level shift circuit.

[0069] Figure 6 Equivalent circuits of the first and second output sub-circuits of the level shifting unit Figure 2 .like Figure 6 As shown, the first output sub-circuit is also electrically connected to the second bias voltage terminal VN. The first output sub-circuit includes: a ninth transistor T9, a tenth transistor T10, and a thirteenth transistor T13. Specifically, the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the ground terminal GND, and the second electrode of the ninth transistor T9 is electrically connected to the first output terminal OUT1. The control electrode of the tenth transistor T10 is electrically connected to the first node N1, the first electrode of the tenth transistor T10 is electrically connected to the first output terminal OUT1, and the second electrode of the tenth transistor T10 is electrically connected to the seventh node N7. The control electrode of the thirteenth transistor T13 is electrically connected to the second bias voltage terminal VN, the first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal V2, and the second electrode of the thirteenth transistor T13 is electrically connected to the seventh node N7.

[0070] In an exemplary embodiment, the ninth transistor T9, the tenth transistor T10, and the thirteenth transistor T13 are medium-voltage metal-oxide-semiconductor field-effect transistors, and the ninth transistor T9 is a P-type transistor, while the tenth transistor T10 and the thirteenth transistor T13 are N-type transistors.

[0071] In an exemplary embodiment, the configuration of the thirteenth transistor T13 can further suppress peak currents, reduce average currents, and thus reduce power consumption.

[0072] like Figure 6 As shown, the second output sub-circuit is also electrically connected to the second bias voltage terminal VN. The second output sub-circuit includes: an eleventh transistor T11, a twelfth transistor T12, and a fourteenth transistor T14. Specifically, the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the ground terminal GND, and the second electrode of the eleventh transistor T11 is electrically connected to the second output terminal OUT2. The control electrode of the twelfth transistor T12 is electrically connected to the second node N2, the first electrode of the twelfth transistor T12 is electrically connected to the second output terminal OUT2, and the second electrode of the twelfth transistor T12 is electrically connected to the eighth node N8. The control electrode of the fourteenth transistor T14 is electrically connected to the second bias voltage terminal VN, the first electrode of the fourteenth transistor T14 is electrically connected to the second power supply terminal V2, and the second electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8.

[0073] In an exemplary embodiment, the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 are medium-voltage metal-oxide-semiconductor field-effect transistors, and the eleventh transistor T11 is a P-type transistor, while the twelfth transistor T12 and the fourteenth transistor T14 are N-type transistors.

[0074] In an exemplary embodiment, the configuration of the fourteenth transistor T14 can further suppress peak current, reduce average current, and thus reduce power consumption.

[0075] Figure 7 Equivalent circuit of level shifting unit Figure 1 .like Figure 7As shown, in at least one level shifting unit, the output control sub-circuit includes: first transistor T1 to eighth transistor T8 and inverter INV; the first output sub-circuit includes: ninth transistor T9 and tenth transistor T10; and the second output sub-circuit includes: eleventh transistor T11 and twelfth transistor T12. Specifically, the input terminal of inverter INV is electrically connected to the signal input terminal IN, the output terminal of inverter INV is electrically connected to the control electrode of the first transistor T1, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal V1, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, the first electrode of the second transistor T2 is electrically connected to the first power supply terminal V1, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first bias voltage terminal VP, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the first node N1; the control electrode of the fourth transistor T4 is electrically connected to the first bias voltage terminal VP, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; and there are also a fifth transistor T5 and a sixth transistor T6. Among them, the control electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the sixth node N6; the seventh transistor T7 and the eighth transistor T8.Among them, the control electrode of the seventh transistor T7 is electrically connected to the second bias voltage terminal VN, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the second power supply terminal V2; the control electrode of the eighth transistor T8 is electrically connected to the second bias voltage terminal VN, the first electrode of the eighth transistor T8 is electrically connected to the sixth node N6, and the second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the ground terminal GND, and the second electrode of the ninth transistor T9 is electrically connected to the first output terminal OUT1; the tenth transistor T... The control electrode of transistor T10 is electrically connected to the first node N1. The first electrode of transistor T10 is electrically connected to the first output terminal OUT1, and the second electrode of transistor T10 is electrically connected to the second power supply terminal V2. The control electrode of transistor T11 is electrically connected to the second node N2. The first electrode of transistor T11 is electrically connected to the ground terminal GND, and the second electrode of transistor T11 is electrically connected to the second output terminal OUT2. The control electrode of transistor T12 is electrically connected to the second node N2. The first electrode of transistor T12 is electrically connected to the second output terminal OUT2, and the second electrode of transistor T12 is electrically connected to the second power supply terminal V2.

[0076] In an exemplary embodiment Figure 8 In the provided level shifting unit, the first transistor T1 to the fourth transistor T4, the ninth transistor T9 and the eleventh transistor T11 are P-type transistors, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 and the twelfth transistor T12 are N-type transistors.

[0077] When the level shifting circuit is in operation, the signal at the first bias voltage terminal VP is a low-level signal, and the signal at the second bias voltage terminal VN is a high-level signal. Figure 7The operation of the provided level shifting unit includes: when the signal at the signal input terminal IN is a high-level signal, the first transistor T1 is turned on, the signal at the first power supply terminal V1 is written to the third node N3, the second transistor T2 is turned off, the signal at the first power supply terminal V1 cannot be written to the fourth node N4, since the signal at the first bias voltage terminal VP is a low-level signal, the third transistor T3 and the fourth transistor T4 are turned on, the signal at the first node N1 is pulled high, the signal at the second node N2 is not pulled high, the signal at the first node N1 is a high-level signal, the sixth transistor T6 is turned on, since the signal at the second bias voltage terminal VN is a high-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the low-level signal at the second power supply terminal V2 is written to the fifth node N5 and the sixth node N6, since the sixth transistor T6 is turned on, the signal at the second node N2 is pulled low by the sixth node N6, the eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, the signal at the ground terminal GND is written to the second output terminal OUT2, since the signal at the second node N2 is pulled low and the second transistor T2 is turned off, the fourth transistor T4 operates in the saturation region. As the signal at the second node N2 is pulled low, the fifth transistor T5 is turned off, accelerating the signal pull-up speed at the first node N1. The ninth transistor T9 is turned off, the tenth transistor T10 is turned on, and the signal at the second power supply terminal V2 is written to the first output terminal OUT1. When the signal at the input terminal IN is low, the second transistor T2 is turned on, and the signal at the first power supply terminal V1 is written to the fourth node N4. When the first transistor T1 is turned off, the signal at the first power supply terminal V1 cannot be written to the third node N3. Since the signal at the first bias voltage terminal VP is low, the third transistor T3 and the fourth transistor T4 are turned on, and the signal at the second node N2 is pulled high. The signal at the first node N1 is not pulled high, and the signal at the second node N2 is high. The fifth transistor T5 is turned on. Since the signal at the second bias voltage terminal VN is high, the seventh transistor T7 and the eighth transistor T8 are turned on, and the low-level signal at the second power supply terminal V2 is written to the fifth node N5 and the sixth node N6. Since the seventh transistor T7 is turned on, the signal at the first node N1 is pulled low by the fifth node N5, the ninth transistor T9 is turned on, and the tenth transistor T10 is turned off. The signal at the ground terminal GND is written to the first output terminal OUT1. Because the signal at the first node N1 is pulled low and the first transistor T1 is turned off, the third transistor T3 operates in the saturation region. As the signal of the first node N1 is pulled low, the sixth transistor T6 is turned off, which accelerates the signal of the second node N2 from being pulled high. The eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, and the signal of the second power supply terminal V2 is written to the second output terminal OUT2.

[0078] When the level shifting circuit is not in operation, the signal at the first bias voltage terminal VP is a high-level signal, and the signal at the second bias voltage terminal VN is a low-level signal. The third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are disconnected, and the signals at the first node N1 and the second node N2 are floating. This prevents the signals at the first power supply terminal V1 and the second power supply terminal V2 from being written, thus saving power consumption of the level shifting circuit.

[0079] Figure 8 Equivalent circuit of level shifting unit Figure 2 .like Figure 8As shown, in at least one level shifting unit, the output control sub-circuit includes: first transistor T1 to eighth transistor T8 and inverter INV; the first output sub-circuit includes: ninth transistor T9, tenth transistor T10 and thirteenth transistor T13; and the second output sub-circuit includes: eleventh transistor T11, twelfth transistor T12 and fourteenth transistor T14. Specifically, the input terminal of inverter INV is electrically connected to the signal input terminal IN, the output terminal of inverter INV is electrically connected to the control electrode of the first transistor T1, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal V1, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, the first electrode of the second transistor T2 is electrically connected to the first power supply terminal V1, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first bias voltage terminal VP, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the first node N1; the control electrode of the fourth transistor T4 is electrically connected to the first bias voltage terminal VP, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; and there are also a fifth transistor T5 and a sixth transistor T6. Among them, the control electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the sixth node N6; the seventh transistor T7 and the eighth transistor T8.Specifically, the control electrode of the seventh transistor T7 is electrically connected to the second bias voltage terminal VN, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the second power supply terminal V2; the control electrode of the eighth transistor T8 is electrically connected to the second bias voltage terminal VN, the first electrode of the eighth transistor T8 is electrically connected to the sixth node N6, and the second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the ground terminal GND, and the second electrode of the ninth transistor T9 is electrically connected to the first output terminal OUT1; the control electrode of the tenth transistor T10 is electrically connected to the first node N1, the first electrode of the tenth transistor T10 is electrically connected to the first output terminal OUT1, and the second electrode of the tenth transistor T10 is electrically connected to the seventh node N7; the eleventh transistor T11... The control electrode of the eleventh transistor T11 is electrically connected to the second node N2; the first electrode of the eleventh transistor T11 is electrically connected to the ground terminal GND; and the second electrode of the eleventh transistor T11 is electrically connected to the second output terminal OUT2. The control electrode of the twelfth transistor T12 is electrically connected to the second node N2; the first electrode of the twelfth transistor T12 is electrically connected to the second output terminal OUT2; and the second electrode of the twelfth transistor T12 is electrically connected to the eighth node N8. The control electrode of the thirteenth transistor T13 is electrically connected to the second bias voltage terminal VN; the first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal V2; and the second electrode of the thirteenth transistor T13 is electrically connected to the seventh node N7. The control electrode of the fourteenth transistor T14 is electrically connected to the second bias voltage terminal VN; the first electrode of the fourteenth transistor T14 is electrically connected to the second power supply terminal V2; and the second electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8.

[0080] In an exemplary embodiment Figure 8 In the provided level shifting unit, the first transistor T1 to the fourth transistor T4, the ninth transistor T9, the eleventh transistor T11 and the thirteenth transistor T13 are P-type transistors, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12 and the fourteenth transistor T14 are N-type transistors.

[0081] When the level shifting circuit is in operation, the signal at the first bias voltage terminal VP is a low-level signal, and the signal at the second bias voltage terminal VN is a high-level signal. Figure 8The operation of the provided level shifting unit includes: When the signal at the signal input terminal IN is a high-level signal, the first transistor T1 is turned on, and the signal at the first power supply terminal V1 is written to the third node N3. When the second transistor T2 is turned off, the signal at the first power supply terminal V1 cannot be written to the fourth node N4. Since the signal at the first bias voltage terminal VP is a low-level signal, the third transistor T3 and the fourth transistor T4 are turned on, and the signal at the first node N1 is pulled high. The signal at the second node N2 is not pulled high. When the signal at the first node N1 is a high-level signal, the sixth transistor T6 is turned on. Since the signal at the second bias voltage terminal VN is high... With the voltage level signal activated, transistors T7 (seventh), T8 (eighth), T13 (thirteenth), and T14 (fourteenth) are turned on. The low-level signal at the second power supply terminal V2 is written to nodes N5 (fifth), N6 (sixth), N7 (seventh), and N8 (eighth). Because transistor T6 is turned on, the signal at node N2 is pulled low. Transistor T11 (eleventh) is turned on, and transistor T12 (twelfth) is turned off. The signal at ground terminal GND is written to the second output terminal OUT2. Because the signal at node N2 is pulled low and transistor T2 is turned off, transistor T4 operates in the saturation region. Because the signal at node N2 is pulled low, transistor T5 is turned off, accelerating the rise of the signal at node N1. Transistor T9 is turned off, and transistor T10 is turned on. The signal at the second power supply terminal V2 is written to the first output terminal OUT1. When the signal at the input terminal IN is low, the second transistor T2 is turned on, and the signal at the first power supply terminal V1 is written to the fourth node N4. When the first transistor T1 is turned off, the signal at the first power supply terminal V1 cannot be written to the third node N3. Since the signal at the first bias voltage terminal VP is low, the third transistor T3 and the fourth transistor T4 are turned on, and the signal at the second node N2 is pulled high. The signal at the first node N1 is not pulled high. The signal at the second node N2 is high, and the fifth transistor T5 is turned on. Since the signal at the second bias voltage terminal VN is high, the seventh... Transistors T7, T8, T13, and T14 are turned on, and the low-level signal at the second power supply terminal V2 is written to nodes N5, N6, N7, and N8. Because transistor T7 is turned on, the signal at node N1 is pulled low by node N5. Transistor T9 is turned on, and transistor T10 is turned off. The signal at ground terminal GND is written to the first output terminal OUT1. Because the signal at node N1 is pulled low and transistor T1 is turned off, transistor T3 operates in the saturation region. Because the signal at node N1 is pulled low, transistor T6 is turned off, accelerating the rise of the signal at node N2. Transistor T11 is turned off, and transistor T12 is turned on. The signal at the second power supply terminal V2 is written to the second output terminal OUT2.

[0082] When the level shifting circuit is not in operation, the signal at the first bias voltage terminal VP is a high-level signal, and the signal at the second bias voltage terminal VN is a low-level signal. The third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the thirteenth transistor T13, and the fourteenth transistor T14 are disconnected. The signals at the first node N1 and the second node N2 are floating, preventing the writing of signals at the first power supply terminal V1 and the second power supply terminal V2, thus saving power consumption of the level shifting circuit.

[0083] Figure 9 This is a comparison chart of the peak currents of shift units at different levels. (Example) Figure 9 As shown, level shifting unit one is Figure 7 The provided level shifting unit, level shifting unit two is Figure 8 The provided level shifting unit has a maximum peak current of level shifting unit 2 that is less than the maximum peak current of level shifting unit 1, and the maximum peak current of level shifting unit 1 is less than the maximum peak current of existing level shifting units.

[0084] Figure 10 This is a comparison graph showing the signal switching speed of different level shift units at a standard process angle. (Example:) Figure 10 As shown, level shifting unit one is Figure 7 The provided level shifting unit, level shifting unit two is Figure 8 The provided level shifting units, specifically level shifting unit one and level shifting unit two, exhibit excellent stability at different process angles, with symmetrical rise and fall times. Existing level shifting units risk signal failure to flip at standard process angles.

[0085] Table 1 Table 1 is a comparison of the average current of different level shift units at different process angles. 1 represents... Figure 7 The provided level shifting unit, 2 is Figure 8 The provided level shifting units are as follows: SS_25 is a double slow process angle at 25 degrees Celsius; FF_25 is a double fast process angle at 25 degrees Celsius; TT_25 is a standard process angle at 25 degrees Celsius; SS_120 is a double slow process angle at 120 degrees Celsius; FF_120 is a double fast process angle at 120 degrees Celsius; TT_120 is a standard process angle at 120 degrees Celsius; SS_-40 is a double slow process angle at -40 degrees Celsius; FF_-40 is a double fast process angle at -40 degrees Celsius; TT_-40 is a standard process angle at -40 degrees Celsius. As shown in Table 1, for the same process angle at different temperatures... Figure 8 The average current of the provided level shifting units is less than Figure 7 The average current of the provided level shifter unit, Figure 7 The average current of the provided level shift unit is less than the average current of existing level shift units, and Figure 7 The average current of the provided level shift unit is reduced by more than 50% compared to the average current of existing level shift units.

[0086] This disclosure also provides a driving method for a level shifting circuit, configured to drive the level shifting circuit provided in any of the foregoing embodiments. The driving method for the level shifting circuit provided in this disclosure may include the following steps: Step 100: The output control sub-circuit controls the signals of the first node and the second node under the control of the signals at the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, and the second bias voltage terminal.

[0087] Step 200: Under the control of the signal from the first node, the first output sub-circuit provides a signal from the ground terminal or the second power supply terminal to the first output terminal.

[0088] Step 300: Under the control of the signal from the second node, the second output sub-circuit provides a signal from the ground terminal or the second power supply terminal to the second output terminal.

[0089] In an exemplary embodiment, the output control subcircuit includes: an input subcircuit, a first current-limiting subcircuit, a feedback subcircuit, and a second current-limiting subcircuit.

[0090] Step 100 may include the following steps: Step 110: Under the control of the signal at the signal input terminal, the input sub-circuit provides the signal at the first power supply terminal to the third or fourth node.

[0091] Step 120: The first current limiting sub-circuit controls the signals of the first node and the second node under the control of the signals of the first bias voltage terminal, the third node and the fourth node.

[0092] Step 130: Under the control of the signals from the first node and the second node, the feedback sub-circuit provides the signal from the fifth node to the first node and the signal from the sixth node to the second node.

[0093] Step 140: The second current limiting sub-circuit controls the signals of the fifth node and the sixth node under the control of the signals at the second bias voltage terminal and the second power supply terminal.

[0094] Figure 11 A schematic diagram of the source driver chip provided in the embodiments of this disclosure. Figure 1 , Figure 12 This is a schematic diagram showing the connection between the bias circuit and the level shifting circuit. (Example:) Figure 11 and Figure 12As shown, the source driver chip provided in this embodiment includes a bias circuit 20 and a level shifting circuit 10. The bias circuit 20 is electrically connected to a first bias voltage terminal VP and a second bias voltage terminal VN, which are connected to at least one level shifting unit 100 in the level shifting circuit 10.

[0095] like Figure 11 As shown, the source driver chip also includes: interface circuit 30, data processor 40, shift register 50, data latch circuit 60, digital-to-analog converter circuit 70, gating circuit 80, and output buffer circuit 90.

[0096] In an exemplary embodiment, the display device in which the source driver chip is located further includes: a timing controller, a grayscale controller, and a display panel. The display panel includes: multiple sub-pixels and multiple data signal lines. The source driver chip is electrically connected to the timing controller, the grayscale controller, and the display panel, respectively, and the sub-pixels are electrically connected to the data signal lines.

[0097] In an exemplary embodiment, the grayscale controller is used to output a gamma signal to the source driver chip based on the grayscale data of subpixels in the display image from the timing controller.

[0098] In an exemplary embodiment, the interface circuit 30 is electrically connected to the data processor 40. The interface circuit 30 is used to convert received image data from the timing controller into digital image data and output it to the data processor 40.

[0099] In an exemplary embodiment, there are multiple interface circuits 30, and all of them have the same structure. The image data received by each of the multiple interface circuits 30 can be adjusted according to the position of the sub-pixels in the display panel, which is not limited herein.

[0100] In an exemplary embodiment, the interface circuit may include a miniature low-voltage differential signal interface or a point-to-point interface, and this disclosure does not impose any limitations on it.

[0101] In an exemplary embodiment, the data processor 40 is electrically connected to the shift register 50. The data processor 40 is configured to preprocess digitized image data before transferring it to the shift register 50.

[0102] In an exemplary embodiment, the shift register 50 includes multiple shift register units cascaded in sequence; in two adjacent shift registers, the last shift register unit in the preceding shift register is electrically connected to the first shift register unit in the following shift register.

[0103] In an exemplary embodiment, the shift register 50 is also electrically connected to the data latch circuit 60. The data latch circuit 60 corresponds one-to-one with the shift register, and is configured to store digitized image data output from its corresponding shift register 50, and output to the level shift circuit 10 under the control of the drive control signal.

[0104] In an exemplary embodiment, the level conversion circuit 10 is electrically connected to the digital-to-analog converter circuit 70. The level conversion circuit 10 is configured to convert low-level digitized image data from the data latch circuit 60 into high-level digitized image data and output it to the digital-to-analog converter circuit 70 corresponding to the shift register. The digital-to-analog converter circuit 70 corresponds one-to-one with the shift register 50.

[0105] In an exemplary embodiment, the digital-to-analog converter circuit 70 is electrically connected to the gating circuit 80. The digital-to-analog converter circuit 70 is configured to combine a gamma signal from the grayscale controller, convert the high-level digitized image data received from the corresponding shift register of the corresponding digital-to-analog converter circuit 70 into an analog grayscale signal, and output it to the gating circuit.

[0106] In an exemplary embodiment, the gating circuit 80 is electrically connected to the output buffer circuit 90. The gating circuit 80 is configured to output an analog grayscale signal to the output buffer circuit 90.

[0107] In an exemplary embodiment, an output buffer circuit 90 is electrically connected to the data signal line. The output buffer circuit 90 is configured to provide a data signal to the data signal line.

[0108] In an exemplary embodiment, the output buffer circuit 90 is electrically connected to the output terminal of the gating circuit 80, and there is a one-to-one correspondence between the output buffer circuit 90 and the digital-to-analog converter circuit 70. It is understood that the number of output buffer circuits 90 and digital-to-analog converter circuits 70 is the same, and the output terminal of one output buffer circuit 90 is electrically connected to one data signal line. Figure 13 This is the equivalent circuit diagram of the bias circuit. (For example...) Figure 13As shown, the bias circuit includes: transistors 15 to 33 (T15 to T33) and a first current source I1 and a second current source I2. The first current source I1 and the second current source I2 each have a first terminal and a second terminal. Specifically, the control electrode of transistor 15 (T15) is electrically connected to the first node ND1, the first terminal of transistor 15 (T15) is electrically connected to the second bias voltage terminal VN, and the second terminal of transistor 15 (T15) is electrically connected to the second node ND2. The control electrode of transistor 16 (T16) is electrically connected to the third node ND3, the first terminal of transistor 16 (T16) is electrically connected to the first power supply terminal V1, and the second terminal of transistor 16 (T16) is electrically connected to the second node ND2. The control electrode and the second terminal of transistor 17 (T17) are respectively electrically connected to the first bias voltage terminal VP, and the first terminal of transistor 17 (T17) is electrically connected to the fourth node ND4. The control electrode of transistor 18 (T18) is... The control electrode and the second electrode are respectively electrically connected to the fourth node ND4. The first electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1. The control electrode of the nineteenth transistor T19 is electrically connected to the first node ND1. The first electrode of the nineteenth transistor T19 is electrically connected to the fifth node ND5. The second electrode of the nineteenth transistor T19 is electrically connected to the sixth node ND6. The control electrode of the twentieth transistor T20 is electrically connected to the third node ND3. The first electrode of the twentieth transistor T20 is electrically connected to the first power supply terminal V1. The second electrode of the twentieth transistor T20 is electrically connected to the fifth node ND5. The control electrode of the twenty-first transistor T21 is electrically connected to the first node ND1. The first terminal of transistor T21 is electrically connected to the seventh node ND7; the second terminal of transistor T21 is electrically connected to the eighth node ND8; the control terminal of transistor T22 is electrically connected to the third node ND3, the first terminal of transistor T22 is electrically connected to the first power supply terminal V1, and the second terminal of transistor T22 is electrically connected to the seventh node ND7; the control terminal of transistor T23 is electrically connected to the first node ND1, the first terminal of transistor T23 is electrically connected to the first power supply terminal V1, and the second terminal of transistor T23 is electrically connected to the ninth node ND9; the control terminal of transistor T24 is electrically connected to the third node ND8. ND3 is electrically connected; the first terminal of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal V1; the second terminal of the twenty-fourth transistor T24 is electrically connected to the tenth node ND10; the control terminal of the twenty-fifth transistor T25 is electrically connected to the first node ND1; the first terminal of the twenty-fifth transistor T25 is electrically connected to the tenth node ND10; the second terminal of the twenty-fifth transistor T25 is electrically connected to the eleventh node ND11; the control terminal of the twenty-sixth transistor T26 is electrically connected to the first enable signal terminal EN1; the first terminal of the twenty-sixth transistor T26 is electrically connected to the first power supply terminal V1; the second terminal of the twenty-sixth transistor T26 is electrically connected to the first bias voltage terminal VP.The control electrode and first electrode of the 27th transistor T27 are electrically connected to the second bias voltage terminal VN, and the second electrode of the 27th transistor T27 is electrically connected to the second power supply terminal V2; the control electrode of the 28th transistor T28 is electrically connected to the eighth node ND8, the first electrode of the 28th transistor T28 is electrically connected to the second power supply terminal V2, and the second electrode of the 28th transistor T28 is electrically connected to the twelfth node ND12; the control electrode of the 29th transistor T29 is electrically connected to the sixth node ND6, the first electrode of the 29th transistor T29 is electrically connected to the first bias voltage terminal VP, and the second electrode of the 29th transistor T29 is electrically connected to the twelfth node ND12; the control electrode and first electrode of the 30th transistor T30 are electrically connected to the sixth node ND6, and the second electrode of the 30th transistor T30 is electrically connected to the second power supply terminal V2; the control electrode of the 31st transistor T31 is electrically connected to the sixth node ND6, and the 30th transistor T30 is electrically connected to the second power supply terminal V2; The first terminal of transistor T31 is electrically connected to the eighth node ND8; the second terminal of transistor T31 is electrically connected to the thirteenth node ND13; the control terminal of transistor T32 is electrically connected to the eighth node ND8; the first terminal of transistor T32 is electrically connected to the second power supply terminal V2; the second terminal of transistor T32 is electrically connected to the thirteenth node ND13; the control terminal of transistor T33 is electrically connected to the second enable signal terminal EN2; the first terminal of transistor T33 is electrically connected to the second bias voltage terminal VN; the second terminal of transistor T33 is electrically connected to the second power supply terminal V2; the first terminal of the first current source I1 is electrically connected to the eleventh node ND11; the second terminal of the first current source I1 is electrically connected to the second power supply terminal V2; the first terminal of the second current source I2 is electrically connected to the ninth node ND9; the second terminal of the second current source I2 is electrically connected to the second power supply terminal V2.

[0109] In an exemplary embodiment, the sixteenth transistor T16 to the twenty-sixth transistor T26 are P-type transistors, and the twenty-seventh transistor T27 to the thirty-third transistor T33 are N-type transistors.

[0110] The operation of the bias circuit includes: When the signals at the first node N1 and the third node N3 are low, the fifteenth transistor T15 and the sixteenth transistor T16 are turned on, and the high-level signal at the first power supply terminal V1 is written to the second bias voltage terminal VN. Then, the nineteenth transistor T19 and the twentieth transistor T20 are turned on, and the high-level signal at the first power supply terminal V1 is written to the fifth node ND5 and the sixth node ND6. Finally, the twenty-ninth transistor T29, the thirtieth transistor T30, and the thirty-first transistor T31 are turned on, pulling the signal at the sixth node ND6 low. Then, the twentieth transistor T21 and the twenty-second transistor T22 are turned on, and the high-level signal at the first power supply terminal V1 is written to... At nodes 7 (ND7) and 8 (ND8), transistors 28 (T28) and 32 (T32) are turned on. The signal at node 8 (ND8) is pulled low. The signal at the second power supply terminal V2 is written to the first bias voltage terminal VP through the turned-on transistors 28 (T28) and 29 (T29). The signal at the second enable signal terminal ENN is low. Transistor 33 (T33) is turned off, and the signal at the second bias voltage terminal VN is high. Although transistor 27 (T27) is turned off, the signal at the second bias voltage terminal VN remains high because it is continuously pulled high by the signal at the first power supply terminal V1. Transistors 23 (T23), 24 (T24), and 25 (T25) are turned on. The signal at the first power supply terminal V1 is written to nodes 9 (ND9) and 11 (ND11), forming the signals at the first terminals of the first current source I1 and the second current source I2, thus creating a current path between them.

[0111] The bias circuit provided in this disclosure is connected to the same power supply terminal (including: the first power supply terminal V1 and the second power supply terminal V2) as the level shift circuit is connected to the same power supply terminal (including: the first power supply terminal V1 and the second power supply terminal V2), which can perfectly match this level shift circuit.

[0112] Although a bias circuit has been added in this disclosure, one bias circuit corresponds to multiple level shifting units, and the increased area is negligible when spread across a single level shifting unit.

[0113] The first enable signal terminal ENP and the second enable signal terminal ENN provided in this disclosure can be electrically connected to a timing controller, or they can also be electrically connected to one of the structures in the source driver chip. This disclosure does not limit them in any way.

[0114] This disclosure also provides a display device, including: the source driver chip provided in any of the foregoing embodiments.

[0115] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0116] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0117] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0118] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A level shifting circuit, characterized in that, include: Multiple level shifting units, at least one level shifting unit includes: an output control sub-circuit, a first output sub-circuit, and a second output sub-circuit; The output control sub-circuit is electrically connected to the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, the second bias voltage terminal, the first node, and the second node, respectively, and is configured to control the signals of the first node and the second node under the control of the signals of the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, and the second bias voltage terminal. The first output sub-circuit is electrically connected to the second power supply terminal, the ground terminal, the first output terminal and the first node respectively, and is configured to provide the ground terminal or the second power supply terminal signal to the first output terminal under the control of the signal of the first node. The second output sub-circuit is electrically connected to the second power supply terminal, the ground terminal, the second output terminal, and the second node, respectively, and is configured to provide the ground terminal or the second power supply terminal signal to the second output terminal under the control of the signal of the second node; The first power supply terminal is a digital power supply terminal, and the second power supply terminal is an analog negative voltage power supply terminal.

2. The level shifting circuit according to claim 1, characterized in that, The output control sub-circuit includes: an input sub-circuit, a first current limiting sub-circuit, a feedback sub-circuit, and a second current limiting sub-circuit; The input sub-circuit is electrically connected to the signal input terminal, the first power supply terminal, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the third node or the fourth node under the control of the signal from the signal input terminal. The first current limiting sub-circuit is electrically connected to the first bias voltage terminal, the first node, the second node, the third node, and the fourth node, respectively, and is configured to control the signals of the first node and the second node under the control of the signals of the first bias voltage terminal, the third node, and the fourth node. The feedback sub-circuit is electrically connected to the first node, the second node, the fifth node, and the sixth node, respectively, and is configured to provide the signal of the fifth node to the first node and the signal of the sixth node to the second node under the control of the signals of the first node and the second node. The second current-limiting sub-circuit is electrically connected to the second bias voltage terminal, the fifth node, the sixth node, and the second power supply terminal, respectively, and is configured to control the signals of the fifth node and the sixth node under the control of the signals of the second bias voltage terminal and the second power supply terminal.

3. The level shifting circuit according to claim 2, characterized in that, The input sub-circuit includes: an inverter, a first transistor, and a second transistor; the inverter includes: an input terminal and an output terminal. The input terminal of the inverter is electrically connected to the signal input terminal, the output terminal of the inverter is electrically connected to the control electrode of the first transistor, the first electrode of the first transistor is electrically connected to the first power supply terminal, the second electrode of the first transistor is electrically connected to the third node, the control electrode of the second transistor is electrically connected to the signal input terminal, the first electrode of the second transistor is electrically connected to the first power supply terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The inverter is a low-voltage inverter, and the first transistor and the second transistor are low-voltage metal-oxide-semiconductor field-effect transistors, both of which are P-type transistors.

4. The level shifting circuit according to claim 3, characterized in that, The first current-limiting sub-circuit includes: a third transistor and a fourth transistor; The control electrode of the third transistor is electrically connected to the first bias voltage terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node. The control terminal of the fourth transistor is electrically connected to the first bias voltage terminal, the first terminal of the fourth transistor is electrically connected to the fourth node, and the second terminal of the fourth transistor is electrically connected to the second node. The third transistor and the fourth transistor are medium-voltage metal-oxide-semiconductor field-effect transistors, and both are P-type transistors; The third transistor and the fourth transistor are arranged at least partially symmetrically.

5. The level shifting circuit according to claim 4, characterized in that, The third transistor is a common-gate transistor corresponding to the first transistor, and the fourth transistor is a common-gate transistor corresponding to the second transistor.

6. The level shifting circuit according to claim 4, characterized in that, The feedback sub-circuit includes: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the fifth node. The control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the sixth node. The fifth transistor and the sixth transistor are medium-voltage metal-oxide-semiconductor field-effect transistors, and both are N-type transistors; The fifth transistor and the sixth transistor are arranged at least partially symmetrically.

7. The level shifting circuit according to claim 6, characterized in that, The second current-limiting sub-circuit includes: a seventh transistor and an eighth transistor; The control terminal of the seventh transistor is electrically connected to the second bias voltage terminal, the first terminal of the seventh transistor is electrically connected to the fifth node, and the second terminal of the seventh transistor is electrically connected to the second power supply terminal. The control terminal of the eighth transistor is electrically connected to the second bias voltage terminal, the first terminal of the eighth transistor is electrically connected to the sixth node, and the second terminal of the eighth transistor is electrically connected to the second power supply terminal. The seventh and eighth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, and both are N-type transistors; The seventh transistor and the eighth transistor are arranged at least partially symmetrically.

8. The level shifting circuit according to claim 1, characterized in that, The first output sub-circuit includes: a ninth transistor and a tenth transistor; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the ground terminal, and the second electrode of the ninth transistor is electrically connected to the first output terminal. The control electrode of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the first output terminal, and the second electrode of the tenth transistor is electrically connected to the second power supply terminal. The ninth and tenth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, with the ninth transistor being a P-type transistor and the tenth transistor being an N-type transistor.

9. The level shifting circuit according to claim 1, characterized in that, The second output sub-circuit includes: an eleventh transistor and a twelfth transistor; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the ground terminal, and the second electrode of the eleventh transistor is electrically connected to the second output terminal. The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the second output terminal, and the second electrode of the twelfth transistor is electrically connected to the second power supply terminal. The eleventh and twelfth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, with the eleventh transistor being a P-type transistor and the twelfth transistor being an N-type transistor.

10. The level shifting circuit according to claim 1, characterized in that, The first output sub-circuit is also electrically connected to the second bias voltage terminal. The first output sub-circuit includes: a ninth transistor, a tenth transistor, and a thirteenth transistor. The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the ground terminal, and the second electrode of the ninth transistor is electrically connected to the first output terminal. The control electrode of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the first output terminal, and the second electrode of the tenth transistor is electrically connected to the seventh node. The control terminal of the thirteenth transistor is electrically connected to the second bias voltage terminal, the first terminal of the thirteenth transistor is electrically connected to the second power supply terminal, and the second terminal of the thirteenth transistor is electrically connected to the seventh node. The ninth, tenth, and thirteenth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, with the ninth transistor being a P-type transistor and the tenth and thirteenth transistors being N-type transistors.

11. The level shifting circuit according to claim 1, characterized in that, The second output sub-circuit is also electrically connected to the second bias voltage terminal. The second output sub-circuit includes: an eleventh transistor, a twelfth transistor, and a fourteenth transistor. The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the ground terminal, and the second electrode of the eleventh transistor is electrically connected to the second output terminal. The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the second output terminal, and the second electrode of the twelfth transistor is electrically connected to the eighth node. The control terminal of the fourteenth transistor is electrically connected to the second bias voltage terminal, the first terminal of the fourteenth transistor is electrically connected to the second power supply terminal, and the second terminal of the fourteenth transistor is electrically connected to the eighth node. The eleventh, twelfth, and fourteenth transistors are medium-voltage metal-oxide-semiconductor field-effect transistors, with the eleventh transistor being a P-type transistor and the twelfth and fourteenth transistors being N-type transistors.

12. The level shifting circuit according to claim 1, characterized in that, The multiple level shifting units in the level shifting circuit are connected to the same first bias voltage terminal, and the multiple level shifting units in the level shifting circuit are connected to the same second bias voltage terminal.

13. The level shifting circuit according to claim 12, characterized in that, When the level shifting circuit is in operation, the signals at the first bias voltage terminal and the second bias voltage terminal connected to at least one level shifting unit are both valid level signals. When the level shifting circuit is not in operation, the signals at the first bias voltage terminal and the second bias voltage terminal connected to at least one level shifting unit are both invalid level signals.

14. A source driver chip, characterized in that, include: The level shifting circuit as described in any one of claims 1 to 13.

15. The source driver chip according to claim 14, characterized in that, Also includes: Bias circuit; The first bias voltage terminal and the second bias voltage terminal of the bias circuit are electrically connected to at least one level shifting unit in the level shifting circuit.

16. The source driver chip according to claim 15, characterized in that, The bias circuit includes: the fifteenth to the thirty-third transistors, a first current source and a second current source, wherein the first current source and the second current source include: a first terminal and a second terminal; The control electrode of the fifteenth transistor is electrically connected to the first node, the first electrode of the fifteenth transistor is electrically connected to the second bias voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second node. The control electrode of the sixteenth transistor is electrically connected to the third node, the first electrode of the sixteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixteenth transistor is electrically connected to the second node. The control electrode and the second electrode of the seventeenth transistor are electrically connected to the first bias voltage terminal, respectively, and the first electrode of the seventeenth transistor is electrically connected to the fourth node. The control electrode and the second electrode of the eighteenth transistor are electrically connected to the fourth node, and the first electrode of the eighteenth transistor is electrically connected to the first power supply terminal. The control electrode of the nineteenth transistor is electrically connected to the first node, the first electrode of the nineteenth transistor is electrically connected to the fifth node, and the second electrode of the nineteenth transistor is electrically connected to the sixth node. The control electrode of the twentieth transistor is electrically connected to the third node, the first electrode of the twentieth transistor is electrically connected to the first power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the fifth node. The control electrode of the 21st transistor is electrically connected to the first node, the first electrode of the 21st transistor is electrically connected to the seventh node, and the second electrode of the 21st transistor is electrically connected to the eighth node. The control electrode of the 22nd transistor is electrically connected to the third node, the first electrode of the 22nd transistor is electrically connected to the first power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the seventh node. The control electrode of the 23rd transistor is electrically connected to the first node, the first electrode of the 23rd transistor is electrically connected to the first power supply terminal, and the second electrode of the 23rd transistor is electrically connected to the ninth node. The control electrode of the 24th transistor is electrically connected to the third node, the first electrode of the 24th transistor is electrically connected to the first power supply terminal, and the second electrode of the 24th transistor is electrically connected to the 10th node. The control electrode of the 25th transistor is electrically connected to the first node, the first electrode of the 25th transistor is electrically connected to the 10th node, and the second electrode of the 25th transistor is electrically connected to the 11th node. The control terminal of the 26th transistor is electrically connected to the first enable signal terminal, the first terminal of the 26th transistor is electrically connected to the first power supply terminal, and the second terminal of the 26th transistor is electrically connected to the first bias voltage terminal. The control electrode and the first electrode of the 27th transistor are respectively electrically connected to the second bias voltage terminal, and the second electrode of the 27th transistor is electrically connected to the second power supply terminal. The control electrode of the 28th transistor is electrically connected to the 8th node, the first electrode of the 28th transistor is electrically connected to the second power supply terminal, and the second electrode of the 28th transistor is electrically connected to the 12th node. The control electrode of the 29th transistor is electrically connected to the sixth node, the first electrode of the 29th transistor is electrically connected to the first bias voltage terminal, and the second electrode of the 29th transistor is electrically connected to the 12th node. The control electrode and the first electrode of the thirtieth transistor are electrically connected to the sixth node, and the second electrode of the thirtieth transistor is electrically connected to the second power supply terminal. The control electrode of the 31st transistor is electrically connected to the 6th node, the first electrode of the 31st transistor is electrically connected to the 8th node, and the second electrode of the 31st transistor is electrically connected to the 13th node. The control electrode of the 32nd transistor is electrically connected to the 8th node, the first electrode of the 32nd transistor is electrically connected to the second power supply terminal, and the second electrode of the 32nd transistor is electrically connected to the 13th node. The control terminal of the 33rd transistor is electrically connected to the second enable signal terminal, the first terminal of the 33rd transistor is electrically connected to the second bias voltage terminal, and the second terminal of the 33rd transistor is electrically connected to the second power supply terminal. The first end of the first current source is electrically connected to the eleventh node, and the second end of the first current source is electrically connected to the second power supply terminal. The first end of the second current source is electrically connected to the ninth node, and the second end of the second current source is electrically connected to the second power supply terminal. Transistors 16 through 26 are P-type transistors, and transistors 27 through 33 are N-type transistors.

17. A display device, characterized in that, include: The source driver chip as described in any one of claims 14 to 16.

18. A driving method for a level shifting circuit, characterized in that, The method, configured to drive a level shifting circuit as described in any one of claims 1 to 13, comprises: The output control sub-circuit controls the signals of the first node and the second node under the control of the signals at the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, and the second bias voltage terminal. Under the control of the signal from the first node, the first output sub-circuit provides a signal from the ground terminal or the second power supply terminal to the first output terminal. The second output sub-circuit, under the control of the signal from the second node, provides a ground terminal or a second power supply terminal signal to the second output terminal.

19. The method according to claim 18, characterized in that, The output control subcircuit includes: an input subcircuit, a first current-limiting subcircuit, a feedback subcircuit, and a second current-limiting subcircuit. Under the control of signals from the signal input terminal, the first power supply terminal, the second power supply terminal, the first bias voltage terminal, and the second bias voltage terminal, the output control subcircuit controls the signals of the first node and the second node, including: Under the control of the signal at the signal input terminal, the input sub-circuit provides the signal at the first power supply terminal to the third or fourth node; The first current-limiting sub-circuit controls the signals of the first node and the second node under the control of the signals of the first bias voltage terminal, the third node and the fourth node; Under the control of the signals from the first node and the second node, the feedback sub-circuit provides the signal from the fifth node to the first node and the signal from the sixth node to the second node; The second current-limiting sub-circuit controls the signals of the fifth and sixth nodes under the control of the signals at the second bias voltage terminal and the second power supply terminal.

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