Optimized internal integrated circuit communication output driver

Abstract

The present disclosure relates to an optimized internal integrated circuit communication output driver. An example I2C output driver, an electronic system including the I2C output driver, and a method for generating an I2C output signal based on a logic output signal are provided. The I2C output driver includes an output control transistor, gate pre-charge circuitry, and gate drive circuitry. The output control transistor includes a drain terminal electrically connected to an I2C output, a gate terminal that receives a gate output control signal, and a grounded source terminal. The gate pre-charge circuitry generates a pre-charge signal in a logic low state of the logic output signal. The gate output control signal is composed of the pre-charge signal and an output transistor gate control signal. Wherein, a falling time of the I2C output signal transmitted on the I2C output line is controlled based on the pre-charge signal, the output transistor gate control signal, and a gate-drain capacitance.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to internal integrated circuit (I2C) communication output drivers, and more specifically, to improved circuit designs for I2C communication output drivers. Background Technology

[0002] The Interconnect-by-Concept (I2C) communication protocol enables simple communication between multiple devices using only two signals: a clock signal and a data signal. I2C is a serial protocol widely used in microcontrollers, memory, computer monitors, sensors, and many other interconnected devices. I2C is a half-duplex communication system where only a single controller or target device is configured to transmit data to or from the target device using the data signal on the I2C data bus. Therefore, the I2C protocol uses a clock signal to synchronize communication between devices. Electronic devices use I2C output drivers to send I2C communication signals on the I2C data bus. The I2C protocol is widely used due to its simplicity and power efficiency.

[0003] The applicant has identified numerous technical challenges and difficulties associated with the circuitry of I2C output drivers. Through applied effort, ingenuity, and innovation, the applicant has solved the problems associated with the circuitry of I2C output drivers by developing the solutions implemented in this disclosure, which are described in detail below. Summary of the Invention

[0004] Various embodiments relate to an example I2C output driver, an electronic system including an I2C output driver, and a method for generating an I2C output signal based on a logic output signal.

[0005] An example I2C output driver configured to receive a logic output signal is provided. The example I2C output driver includes an output control transistor, a gate precharge circuitry system, and a gate drive circuitry system. The output control transistor includes: a drain terminal electrically connected to the I2C output line; a gate terminal configured to receive a gate output control signal; a source terminal electrically connected to electrical ground; and a gate-drain capacitance based on the geometry of the drain terminal and the gate terminal. The gate precharge circuitry system is configured to generate a precharge signal in a logic low state of the logic output signal. The gate drive circuitry system is configured to generate an output transistor gate control signal based on the logic output signal. The gate output control signal includes the precharge signal and the output transistor gate control signal. The fall time of the I2C output signal transmitted on the I2C output line is controlled based on the precharge signal, the output transistor gate control signal, and the gate-drain capacitance.

[0006] In some embodiments, the I2C output signal is one of a serial data line and a serial clock line.

[0007] In some embodiments, the fall time of the I2C output signal depends on the gate-drain capacitance, the precharge signal, and the output transistor gate control signal.

[0008] In some embodiments, the fall time of the I2C output signal is greater than 5.8 nanoseconds and less than 120 nanoseconds.

[0009] In some embodiments, the gate-drain overlap between the gate terminal and the drain terminal of the output control transistor is greater than the gate-source overlap between the gate terminal and the source terminal of the output control transistor.

[0010] In some embodiments, the output control transistor includes a high-voltage transistor, which has a rated voltage of at least 5.5 volts.

[0011] In some embodiments, the gate drive circuit system includes a first transistor, a current source, and a second transistor connected in series, wherein the first transistor and the second transistor have opposite channel types, and wherein the first transistor and the second transistor are configured to receive a logic output signal.

[0012] In some embodiments, the gate precharge circuit system includes a third transistor connected in series, a plurality of diode-connected transistors, and a fourth transistor, wherein a precharge control signal is generated between the third transistor and the plurality of diode-connected transistors.

[0013] In some embodiments, the gate precharge circuit system further includes a fifth transistor configured to generate a precharge signal based on a precharge control signal when the logic output signal transitions from logic high to logic low.

[0014] In some embodiments, the I2C output driver further includes a latch-up protection circuit system, wherein the latch-up protection circuit system reduces the voltage of the gate output control signal when the gate output control signal approaches a threshold voltage.

[0015] In some embodiments, the latch-up protection circuit system includes a sixth transistor, which is connected in series with a fourth transistor between the gate terminal of the output control transistor and electrical ground, wherein the sixth transistor and the fourth transistor have opposite channel types.

[0016] An example electronic system is also provided. In some embodiments, the example electronic system includes a data generator circuit system and an I2C output driver. The data generator circuit system is configured to generate one or more data output signals. The I2C output driver includes an output control transistor, a gate precharge circuit system, and a gate drive circuit system. The output control transistor includes a drain terminal, a gate terminal, a source terminal, and a gate-drain capacitance. The drain terminal is electrically connected to the I2C data line. The gate terminal is configured to receive a gate output control signal. The source terminal is electrically connected to electrical ground. The gate-drain capacitance is based on the geometry of the drain terminal and the gate terminal. The gate precharge circuit system is configured to generate a precharge signal in a logic low state of the logic output signal. The gate drive circuit system is configured to generate an output transistor gate control signal based on the data output signal. The gate output control signal includes a precharge signal and an output transistor gate control signal; and the fall time of the I2C data signal transmitted on the I2C data line is controlled based on the precharge signal, the output transistor gate control signal, and the gate-drain capacitance.

[0017] In some embodiments, the fall time of the I2C data signal depends on the gate-drain capacitance, the precharge signal, and the output transistor gate control signal.

[0018] In some embodiments, the fall time of the I2C data signal is greater than 5.8 nanoseconds and less than 120 nanoseconds.

[0019] In some embodiments, the gate-drain overlap between the gate terminal and the drain terminal of the output control transistor is greater than the gate-source overlap between the gate terminal and the source terminal of the output control transistor.

[0020] In some embodiments, the gate drive circuit system includes a first transistor, a current source, and a second transistor connected in series, wherein the first transistor and the second transistor have opposite channel types, and wherein the first transistor and the second transistor are configured to receive a logic output signal.

[0021] In some embodiments, the gate precharge circuit system includes: a third transistor connected in series, a plurality of diode-connected transistors and a fourth transistor, wherein a precharge control signal is generated between the third transistor and the plurality of diode-connected transistors; and a fifth transistor configured to generate a precharge signal based on the precharge control signal when a logic output signal transitions from logic high to logic low.

[0022] In some embodiments, the I2C output driver further includes a latch-up protection circuit system, wherein the latch-up protection circuit system reduces the voltage of the gate output control signal when the gate output control signal approaches a threshold voltage.

[0023] In some embodiments, the latch-up protection circuit system includes a sixth transistor, which is connected in series with a fourth transistor between the gate terminal of the output control transistor and electrical ground, wherein the sixth transistor and the fourth transistor have opposite channel types.

[0024] A method for generating an I2C output signal based on a logic output signal is also provided. In some embodiments, the method includes: receiving a logic output signal at a gate drive circuitry of an I2C output driver; generating an output transistor gate control signal based on the logic output signal at the gate drive circuitry; receiving the logic output signal at a gate precharge circuitry of the I2C output driver; generating a precharge signal at the gate precharge circuitry during a logic low state of the logic output signal; and receiving a gate output control signal at the gate terminal of an output control transistor of the I2C output driver, wherein the gate output control signal includes the precharge signal and the output transistor gate control signal, and the output control transistor includes: a drain terminal electrically connected to an I2C output line; a gate terminal; a source terminal electrically connected to electrical ground; and a gate-drain capacitor based on the geometry of the drain terminal and the gate terminal. The method further includes generating an I2C output signal on the I2C output line, wherein the fall time of the I2C output signal is controlled based on the precharge signal, the output transistor gate control signal, and the gate-drain capacitor. Attached Figure Description

[0025] Referring now to the accompanying drawings. In some embodiments described herein, the components illustrated in the drawings may or may not be present. According to exemplary embodiments of this disclosure, some embodiments may include fewer (or more) components than those shown in the drawings.

[0026] Figure 1 An example block diagram of an I2C output driver according to an exemplary embodiment of the present disclosure is shown.

[0027] Figure 2 An example circuit diagram of an I2C output driver including a gate precharge circuit system block according to an exemplary embodiment of the present disclosure is shown.

[0028] Figure 3 A cross-section of an example modified logic transistor according to an exemplary embodiment of the present disclosure is depicted.

[0029] Figure 4 A cross-section of an example high-voltage transistor according to an example embodiment of the present disclosure is depicted.

[0030] Figures 5A to 5CAn example schematic diagram of an I2C output driver is depicted, illustrating various circuit systems according to example embodiments of the present disclosure.

[0031] Figures 6 to 9 An example timing diagram associated with an I2C output driver according to an example embodiment of the present disclosure is depicted.

[0032] Figure 10 A block diagram of an example electronic system including an I2C output driver according to an example embodiment of the present disclosure is depicted.

[0033] Figure 11 An example flowchart depicts a process for generating an I2C output signal based on a logic output signal according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0034] Hereinafter, exemplary embodiments will be described more fully with reference to the accompanying drawings, which illustrate some, but not all, embodiments of the invention disclosed herein. In fact, embodiments of this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Similar reference numerals always refer to similar elements.

[0035] In various embodiments, digital signals may be described with reference to this embodiment. Typically, a digital signal may occupy one of two states. Throughout the specification, these two states may be described as a logic high state or a logic low state. A digital signal is in a logic high state when its electrical characteristics are above a logic threshold. For example, the voltage of the digital signal exceeds the logic threshold voltage. A digital signal is in a logic low state when its electrical characteristics are below a logic threshold. For example, the voltage of the digital signal is below the logic threshold voltage. The logic state of a digital signal may also be indicated by 0 (e.g., logic low state) and 1 (e.g., logic high state), and 0 and 1 are always used interchangeably.

[0036] When referring to digital signals, the term "set" refers to the logical state of a digital signal when it is active. An active high digital signal is set when the digital signal is in a logical high state and deset when the digital signal is in a logical low state. An active low digital signal is set when the digital signal is in a logical low state and deset when the digital signal is in a logical high state.

[0037] A digital signal can transition from one logic state to another. The transition from a logic low state to a logic high state can be called the rising edge of a digital signal. The transition from a logic high state to a logic low state can be called the falling edge of a digital signal.

[0038] Overview

[0039] The various example embodiments address technical problems associated with I2C output drivers. As those skilled in the art to which this disclosure pertains will understand, there are numerous example scenarios in which systems can benefit from improvements in I2C output driver design.

[0040] For example, the Interconnect-to-Consumer (I2C) communication protocol enables simple communication between multiple devices using only two signals (clock and data). I2C is a serial protocol widely used in microcontrollers, memory, computer monitors, sensors, and many other interconnected devices. I2C is a half-duplex communication system where only a single controller or target device is configured to transmit data to or from the target device using the data signal on the I2C data bus. Therefore, the I2C protocol uses a clock signal to synchronize communication between devices. Electronic devices use I2C output drivers to send I2C communication signals on the I2C data bus. The I2C protocol is widely used due to its simplicity and power efficiency.

[0041] Typically, I2C output drivers, in addition to transmitting data, utilize data signal transitions to indicate data transitions (e.g., the start and stop of a transmission). I2C lines (e.g., I2C clock lines, I2C data lines) are held high by pull-up resistors or other circuitry associated with the I2C bus. Thus, I2C output drivers can pull down I2C lines (e.g., toward electrical ground) and release them (e.g., to return them to a high state) to transmit data. Timing the transitions of I2C output signals transmitted on the I2C lines may require precise timing. Therefore, the I2C protocol specification establishes various timing characteristics for I2C output signals (e.g., I2C clock signals, I2C data signals). I2C output drivers need to meet these timing characteristics to ensure accurate communication. One such timing characteristic is the signal fall time. The signal fall time is the duration for an I2C output signal to transition from a high to a low state.

[0042] The I2C protocol specification can establish minimum and / or maximum signal fall times. For example, in Standard mode, the specification can establish a maximum signal fall time of 300 nanoseconds for both the I2C data and I2C clock signals. In Fast mode, the specification can establish the minimum signal fall time based on the positive supply voltage of the I2C output driver. For example, the minimum signal fall time in nanoseconds can be twenty times the quotient of the positive supply voltage divided by 5.5 (e.g., at a positive supply voltage of 1.6 volts, the minimum signal fall time is 5.82 nanoseconds). The maximum signal fall time for both the I2C data and I2C clock signals in Fast mode can be established as 300 nanoseconds. In Fast mode+, the specification can similarly establish the minimum signal fall time based on the positive supply voltage of the I2C output driver, for example, twenty times the quotient of the positive supply voltage divided by 5.5. The maximum signal fall time for both the I2C data and I2C clock signals in Fast mode can be established as 120 nanoseconds. Therefore, the I2C output driver must adjust the signal fall time of the I2C output signal to conform to the I2C communication protocol.

[0043] In some examples, a feedback capacitor is combined with the output control transistor to control the descent slope of the I2C output signal. For example, an external feedback capacitor can be electrically connected between the I2C line and the gate terminal of the output control transistor. The resulting current, proportional to the slope of the I2C output signal, is injected into a resistor connected to the positive supply voltage, or into a current source connected to the positive supply voltage, causing a drop in the gate voltage at the output control transistor. This closed-loop feedback controls the descent slope of the I2C output signal, making it independent of the I2C line. The resistor allows the transition time to be independent of the positive supply voltage (e.g., the higher the positive supply voltage, the steeper the slope), while the current source allows the slope of the I2C output signal to be independent of the positive supply voltage (e.g., the lower the positive supply voltage, the shorter the transition). However, using an additional external capacitor between the I2C line and the gate terminal of the output control transistor has several disadvantages. For example, the external capacitor requires additional area, consumes additional power, and increases the capacitance at the I2C output line pins. Therefore, the I2C output driver circuit system needs to reduce the overall size of the I2C output driver, reduce the power consumption of the I2C output driver, and reduce the capacitance at the I2C output line pins.

[0044] The various example embodiments described herein utilize various techniques to reduce the size, power consumption, and output line pin capacitance of the I2C output driver. For example, in some embodiments, the external feedback capacitor electrically connected between the I2C line and the gate terminal of the output control transistor is removed. Removing the external feedback capacitor reduces the overall footprint and power consumption of the I2C output driver. Additionally, the capacitance of the I2C output line pin is reduced. Alternatively, parasitic capacitance within the output control transistor, such as gate-drain capacitance, is used to control the fall time of the I2C output signal. Gate-drain capacitance is the internal capacitance (e.g., Miller capacitance) between the doped drain region of the output control transistor and the gate of the output control transistor.

[0045] In some embodiments, the internal gate-drain capacitance of the output control transistor may be smaller than that of the external capacitor. For example, the internal gate-drain capacitance may be equal to or close to 0.05 picofarads, while the capacitance of a conventional feedback capacitor is equal to or close to 1 picofarad. To compensate for the reduced capacitance at the output control transistor, the current generated by the current source supplying the gate control signal to the gate of the output control transistor must be reduced to maintain the same voltage variation of the I2C output signal. However, the reduction in the current supplied to the gate of the output control transistor may increase the time required for the gate voltage of the output control transistor to rise above the threshold voltage. In other words, the turn-on delay of the output control transistor increases. The increased turn-on delay may violate the I2C communication protocol standard.

[0046] To compensate for the low current source and prolonged turn-on delay at the gate of the output control transistor, a gate precharge circuit system can be used. When the logic output signal supplied to the I2C driver transitions from a logic high to a logic low state, the gate precharge circuit system increases the current at the gate of the output control transistor. Therefore, the output control transistor can turn on more quickly, thereby connecting the I2C line to electrical ground.

[0047] Additionally, in some embodiments, the geometry of the output control transistor can be modified to increase the gate-drain capacitance within the output control transistor. For example, the overlap between the gate and the doped drain region of the output control transistor can be increased (e.g., gate-drain overlap), thus increasing the gate-drain capacitance. In some embodiments, this gate-drain overlap can be used to create a high-voltage transistor with a higher gate-drain capacitance than a standard transistor. The increased gate-drain capacitance allows for an increase in the current supplied to the gate control signal of the output transistor.

[0048] As a result of the exemplary embodiments described herein, the area occupied by the I2C output driver can be significantly reduced. Furthermore, removing the external feedback capacitor reduces the power consumption of the I2C output driver. Additionally, removing the feedback capacitor reduces the capacitance at the I2C output line pins.

[0049] Now refer to Figure 1 A block diagram of an example I2C output driver is provided. Figure 1 As depicted, the example I2C output driver is configured to receive a logic output signal 110. The logic output signal 110 is transmitted to a gate drive circuit system 108, a gate precharge circuit system 104, and a latch-up protection circuit system 106. The gate drive circuit system 108 is configured to generate an output transistor gate control signal 114 based at least partially on the logic output signal 110. The gate precharge circuit system 104 is configured to generate a precharge signal 112 based at least partially on the logic output signal 110. Additionally, the latch-up protection circuit 106 is configured to receive a latch-up control signal. Figure 1 As further described, the gate output control signal 116 is derived from a combination of the precharge signal 112, the output transistor gate control signal 114, and the latch control signal 118. The gate output control signal 116 is transmitted to the output control circuitry system 102 to generate an I2C output signal 120 on the I2C line 122.

[0050] like Figure 1 As depicted, the I2C output driver 100 is configured to receive a logic output signal 110. The logic output signal 110 includes any signal type configured to represent data using discrete values ​​(e.g., logic high state, logic low state). The logic output signal 110 can be generated by an electronic system (e.g., for...). Figure 10 The described electronic system 1000 generates data for transmission on the I2C output driver 100. For example, the electronic system may use discrete values ​​to represent various data and provide these discrete values ​​to the I2C output driver 100 via a logic output signal 110. The I2C output driver 100 can then transmit the logic output signal 110 according to the I2C communication protocol.

[0051] like Figure 1 As further described, the I2C output driver 100 is configured to generate an I2C output signal 120 on the I2C line 120. Typically, the I2C output signal 120 follows the logic output signal 110 after a delay.

[0052] like Figure 1As further described, the I2C output driver 100 includes a gate drive circuitry system 108. The gate drive circuitry system 108 includes any circuitry system, comprising hardware and / or software, configured to receive a logic output signal 110 and generate an output transistor gate control signal 114 based on the logic output signal 110, such that the I2C output signal 120 corresponds to the logic output signal 110. For example, in some embodiments, the gate drive circuitry system 108 may include an inverter such that the logic state of the output transistor gate control signal 114 is opposite to that of the logic output signal 110. In such embodiments, the output transistor gate control signal 114 may control an output control transistor, for example, the output control transistor pulling the I2C output signal 120 to electrical ground when the output control transistor is enabled.

[0053] The output transistor gate control signal 114 can operate as an analog signal under the control of the output control transistor in the output control circuit system 102. For example, the output transistor gate control signal 114 can be configured to turn off or turn on the output control transistor. However, when the output transistor gate control signal 114 turns on the output control transistor (e.g., the voltage level is higher than the threshold of the output control transistor), the voltage level of the output transistor gate control signal is not fixed. For example, the voltage level varies according to the fall time control based on a tradeoff between the current provided by the gate precharge circuit system 104 (e.g., the gate precharge signal 112) and the feedback capacitance of the output control transistor.

[0054] In some embodiments, the output transistor gate control signal 114 may include current, voltage, or other characteristics that conform to the operating criteria of the output control circuitry system 102. For example, the gate drive circuitry system 108 may include a current source that generates current according to the ratings of the output control circuitry system 102.

[0055] like Figure 1 As further described, the I2C output driver 100 includes an output control circuitry system 102. The output control circuitry system 102 includes any circuitry system, including hardware and / or software, configured to control the I2C output signal 120 on the I2C line 122 based on a gate output control signal 116. Typically, the I2C line 122 is an open-drain line. Thus, by default, the I2C output signal 120 on the I2C line 122 is pulled high by the circuitry system associated with the I2C bus. The output control circuitry system 102 can pull the output signal 120 to a logic low state by enabling the circuitry system to electrically connect the I2C line 122 to electrical ground.

[0056] Therefore, the output control circuitry 102 can be configured according to the I2C communication protocol to electrically connect the I2C line 122 to electrical ground to transmit a logic low state and disconnect the I2C line 122 from electrical ground to transmit a logic high state. Thus, in some embodiments, the output control circuitry may include an output control transistor (e.g., for...). Figure 2 (The output control transistor 206 is described further.) In such an embodiment, when the output control transistor is enabled, the I2C line 122 is electrically connected to ground. Furthermore, when the output control transistor is disabled, the I2C line 122 is disconnected from ground and pulled high by the I2C bus circuitry. In some embodiments, the gate output control signal 116 can control the state of the output control transistor. When low, the output control signal 116 applied to the gate of the output control transistor is typically at ground voltage. However, when high, the output control signal 116 is not at a fixed, defined level. When high, the output control signal 116 is typically above the threshold voltage of the output control transistor up to the supply voltage to turn on the output control transistor. However, unlike common logic signals, the high level of the output control signal is not fixed. In fact, the voltage of the output control signal 116 determines the fall time of the I2C output signal 120. For example, the higher the voltage of the output control signal 116, the faster the fall time of the I2C output signal 120. The output control signal may include the output transistor gate control signal 114 and the precharge signal 112. When the latch-up protection circuit system 106 is enabled, the latch-up control signal 118 may decrease the gate output control signal 116.

[0057] like Figure 1 As further described herein, the I2C output driver 100 includes a gate precharge circuitry system 104. The gate precharge circuitry system 104 includes any circuitry system, including hardware and / or software, configured to generate a precharge signal 112 based on a logic output signal 110 transitioning from a logic high state to a logic low state. As described herein, the output control circuitry system 102 can enable a transistor (e.g., an output control transistor) to electrically connect the I2C line 122 to electrical ground based on a gate output control signal 116. In some embodiments, the output transistor gate control signal 114 generated by the gate drive circuitry system 108 may include a relatively low current (e.g., 5 microamps). Receiving a relatively low current at the output control circuitry system 102 (particularly at the gate of the output control transistor) may increase the time required for the gate voltage of the output control transistor to rise above the transistor's threshold voltage. Therefore, the turn-on delay of the output control transistor increases. This increased turn-on delay may violate the I2C communication protocol standard.

[0058] Thus, the gate precharge circuit system 104 can be configured to generate a precharge signal 112 when the logic output signal 110 transitions from a logic high state to a logic low state. The precharge signal 112 can increase the voltage change at the gate terminal of the output control transistor, thereby reducing the turn-on delay of the output control circuit system 102.

[0059] like Figure 1 As further described, the I2C output driver 100 may include a latch-up protection circuitry system 106. The latch-up protection circuitry system 106 includes any circuitry system, including hardware and / or software, configured to reduce the charge at the output control circuitry system 102 when the voltage of the gate output control signal 116 received at the output control circuitry 102 approaches or exceeds a threshold voltage (e.g., the rated voltage of the output control transistor). In some embodiments, the latch-up protection circuitry system 106 may enable an electrical connection between the input terminals of the output control circuitry system 102 and electrical ground. Enabling an electrical connection between the input terminals of the output control circuitry system 102 and electrical ground may cause the latch-up control signal 118 to flow from the output control circuitry system 102 to electrical ground, thereby reducing the voltage at the output control circuitry system 102.

[0060] Now refer to Figure 2 A sample I2C output driver 200 is provided. Figure 2 As depicted, the example I2C output driver 200 includes a gate drive circuitry system 108 configured to receive a logic output signal 110 and generate an output transistor gate control signal 114. Figure 2 As further described, the I2C output driver 200 includes a gate precharge circuit system 104 configured to receive a logic output signal 110 and generate a precharge signal 112. An output control circuit system 102 is configured to receive a gate output control signal 116 including an output transistor gate control signal 114 and the precharge signal 112, and generate an I2C output signal 120.

[0061] like Figure 2The gate drive circuit system 108, as depicted, includes a first p-channel metal-oxide-semiconductor (PMOS) 202, a current source 212, and a first n-channel metal-oxide-semiconductor (NMOS) 204. The first PMOS 202, current source 212, and NMOS 204 are connected in series in an inverter configuration. Therefore, when the logic output signal 110 is in a logic high state, the first PMOS 202 is disabled and the first NMOS is enabled, thereby electrically connecting the dot 208 to electrical ground and pulling the output transistor gate control signal 114 to a logic low state. In this case, the output control transistor 206 is disabled, and the I2C output signal 120 on the I2C line 122 remains in a logic high state. When the logic output signal 110 is in a logic low state, the first PMOS 202 is enabled and the first NMOS is disabled, thereby electrically connecting the dot 208 to the power supply voltage via the current source 212, and generating the output transistor gate control signal 114 in the logic high state. This output transistor gate control signal includes a characteristic current based on the current source 212. In this case, the output control transistor 206 is enabled and the I2C line 122 is electrically connected to ground, thereby pulling the I2C output signal 120 into a logic low state.

[0062] like Figure 2 As further described, the output control circuit system 102 includes an output control transistor 206. Figure 2 The output control transistor 206 includes a drain terminal electrically connected to I2C line 122, a gate terminal electrically connected to network point 208 and configured to receive a gate output control signal 116 including an output transistor gate control signal 114 and a precharge signal 112, and a source terminal electrically connected to electrical ground. Figure 2 As depicted, the output control transistor 206 includes an NMOS transistor. Therefore, when the voltage of the gate output control signal 116 exceeds the threshold voltage of the output control transistor 206, the output control transistor 206 is enabled and the I2C line 122 is electrically connected to electrical ground, thereby pulling the logic state of the I2C output signal 120 to a logic low state.

[0063] like Figure 2 As further illustrated, the output control transistor 206 includes a gate-drain capacitance 210. The gate-drain capacitance 210 includes the parasitic capacitance between the gate region and the drain region of the transistor. This parasitic capacitance between the gate region and the drain region of the transistor can be referred to as Miller capacitance. The gate-drain capacitance 210 is generated due to the geometry of the gate region and the drain region of the transistor. For example, the gate-drain capacitance 210 may correspond to the overlap of the gate region and the drain region of the transistor. Such parasitic capacitance can be formed by an oxide layer between the gate region and the drain region, which acts as a dielectric between the two conductive regions.

[0064] As described herein, when the output control transistor 206 is enabled, the I2C output driver 200 can use the gate-drain capacitance 210 of the output control transistor 206 to control the fall time of the I2C output signal 122. The fall time of the I2C output signal 122 is related to the duration required for the voltage of the I2C output signal 122 to fall from above a logic high state threshold to below a logic low state threshold. For example, in some embodiments, the fall time of the I2C output signal 122 is the time from 70% of the positive supply voltage (Vdd) on the I2C bus to 30% of the positive supply voltage on the I2C bus. The current of the gate output control signal 116 can be selected based on the gate-drain capacitance 210 such that the fall time of the I2C output signal 122 is within the parameters specified in the I2C communication protocol specification. In some embodiments, the fall time of the I2C output signal 122 can be between 0 nanoseconds and 300 nanoseconds; more preferably between 5.8 nanoseconds and 300 nanoseconds; and most preferably between 5.8 nanoseconds and 120 nanoseconds. In some embodiments, the fall time may depend on the positive power supply voltage of the I2C bus.

[0065] In some embodiments, the geometry of the output control transistor 206 can be modified to change the gate-drain capacitance 210 of the output control transistor 206. For example, the overlap between the gate and drain regions of the output control transistor 206 can be increased to increase the gate-drain capacitance 210 without adding additional capacitor components external to the output control transistor 206. Figure 3 An example of a modified transistor is described. In some embodiments, the output control transistor may include a high-voltage transistor. The high-voltage transistor may include a transistor configured with a rated voltage equal to or greater than 5.5 volts. For Figure 4 An example high-voltage transistor is further described.

[0066] like Figure 2 As further described, the I2C output driver 200 may include a gate precharge circuit system 104 configured to receive a logic output signal 110 and generate a precharge signal 112 based on the logic state of the logic output signal 110. For example, the gate precharge circuit system 104 may be configured to generate a current (e.g., the precharge signal 112) when the logic output signal 110 transitions from a logic high state to a logic low state. The precharge signal 112 may increase the voltage change at the gate terminal of the output control transistor 206. By increasing the voltage at the gate terminal of the output control transistor 206, the turn-on delay of the output control transistor 206 can be reduced. Figure 5B The example gate precharge circuit system 104 is further described.

[0067] Now refer to Figure 3 A cross-section of an example modified logic transistor 300 is provided. For example... Figure 3 The example modified logic transistor 300 depicted includes a source terminal 304 electrically connected to a doped source region 314, a gate terminal 306, and a drain terminal 308 electrically connected to a doped drain region 316. Figure 3 As further depicted, gate 306 and source region 314 overlap via gate-source overlap 310. Additionally, gate 306 and drain region 316 overlap via gate-source overlap 310. (As shown...) Figure 3 As illustrated, a first parasitic capacitance (e.g., gate-drain capacitance 210) is formed between the gate 306 and the drain region 316, and a second parasitic capacitance (e.g., gate-channel capacitance 318) is formed between the gate 306 of the modified logic transistor 300 and the substrate channel.

[0068] As described herein, the capacitance value of the parasitic capacitance formed within the modified logic transistor 300 can vary depending on the geometry of the modified logic transistor 300. For example, the parasitic capacitance between the gate 306 and the source region 314 can vary based on the gate-source overlap 310. Similarly, the gate-drain capacitance 210 can vary based on the gate-drain overlap 312. In some embodiments, the gate-drain overlap 312 can be increased to increase the gate-drain capacitance 210. Figure 3 As further described, in some embodiments, the gate-drain overlap 312 can be greater than the gate-source overlap 310. In this case, the gate-drain capacitance 210 can be greater than the parasitic capacitance between the gate 306 and the source region 314.

[0069] When used as an output control transistor, the gate-source capacitance (not depicted) is negligible compared to the gate-drain capacitance 210. Therefore, the fall time of the I2C output signal 120 can depend on the ratio of the gate-drain capacitance 210 to the gate-channel capacitance 318.

[0070] Now refer to Figure 4 A cross-section of an example high-voltage transistor 400 is provided. (Example:) Figure 4 The example high-voltage transistor 400 depicted includes a source terminal 404 electrically connected to a doped source region 414, a first gate 406, and a drain terminal 408 electrically connected to a doped gate region 416. Additionally, Figure 4 The high-voltage transistor 400 includes a second gate 418 disposed between the gate 406 and the substrate. For example... Figure 4As further depicted, gate 406 surrounds at least a portion of second gate 418 such that gate 406 overlaps with source region 414 via gate-source overlap 410, and gate 406 overlaps with drain region 416 via gate-drain overlap 412.

[0071] Figure 4 The transistor structure depicted can be derived from the EEPROM of a flash memory bit cell, where the transistor structure utilizes two stacked polysilicon gates (polysilicon gate 406, polysilicon gate 418). In the bit cell, the polysilicon gates are typically self-aligned (e.g., gate edges aligned, both gates etched simultaneously). However, as... Figure 4 As depicted, the high-voltage transistor 400 can be designed such that the two gates 406, 418 are not self-aligned. In such an embodiment, the two gates 406, 418 are short-circuited at one or both of their ends. Below gate 418 is a high-voltage gate oxide. Between gate 418 and gate 406 is an isolation oxide. The isolation oxide is commonly referred to as ONO (SiO2 / Si3N4 / SiO2 stack); where "O" represents oxide and "N" represents nitride.

[0072] like Figure 4 As depicted, the gate-source capacitance 422 is a result of an oxide capacitance region formed at the source terminal 404 below the portion of the polysilicon gate 406 that does not overlap with the second polysilicon gate 418. Similarly, the gate-drain capacitance 210 is a result of an oxide capacitance region formed at the drain terminal 408 below the portion of the polysilicon gate 406 that does not overlap with the second polysilicon gate 418. Because the gate-source overlap 410 and the gate-drain overlap 412 are defined by the drain extension of the gate 406 beyond the gate 418, the overlap may be asymmetrical in some embodiments. In some embodiments, the high-voltage transistor may be designed such that the gate-source capacitance 422 is not equal to the gate-drain capacitance. For example, the gate-drain capacitance 210 may be significantly larger than the gate-source capacitance 422.

[0073] Utilizing this principle, in some embodiments, due to, for example, an increase in gate-drain overlap 412, the gate-drain capacitance 210 between the gate 406 and drain region 416 of the high-voltage transistor 400 can be increased compared to a standard logic transistor. This increases the output control transistor (e.g., as...). Figure 2 The gate-drain capacitance 210 at the output control transistor 406 (described in the figure) can increase the current supplied to the gate 406 of the output control transistor to maintain the same fall time.

[0074] like Figure 4As further described, a parasitic capacitance (e.g., oxide-channel capacitance 420) is formed between the second gate 418 and the channel of the high-voltage transistor 400.

[0075] When the high-voltage capacitor 400 is used as the output control transistor, the fall time of the I2C output signal 120 can depend on the ratio of the gate-drain capacitance 210 to the sum of the oxide-channel capacitance 420 and the gate-source capacitance 422.

[0076] Now refer to Figures 5A to 5C This describes an example I2C output driver 500. (Example...) Figures 5A to 5C As depicted, the example I2C output driver 500 includes a PMOS transistor 502 (e.g., a first transistor) that includes a source terminal, a gate terminal, and a drain terminal. The source terminal is electrically connected to a positive voltage source. The gate terminal is electrically connected to a logic output signal 110. The drain terminal is electrically connected to a dot 524.

[0077] like Figures 5A to 5C As depicted, the example I2C output driver 500 includes a current source 508 comprising a PMOS transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is electrically connected to point 524. The gate terminal is electrically connected to a positive reference voltage 522. The drain terminal is electrically connected to point 208.

[0078] like Figure 5A As depicted, the positive reference voltage 522 is generated by a PMOS transistor 534, which is a diode-connected transistor, meaning that the PMOS transistor 534 operates in saturation mode. A reference current 536 is injected through the PMOS transistor 534 from a reference current source 538, which is typically a functional sub-block of the I2C circuit and can be used for several analog purposes, not limited to the I2C output driver 500.

[0079] The positive reference voltage 522 is approximately equal to the supply voltage minus the absolute value of the threshold voltage of the PMOS transistor 534. For example, if the supply voltage is 5 volts and the threshold voltage of the PMOS transistor 534 is -0.8V, then the net positive reference voltage 522 will be 5 volts minus 0.8 volts, or 4.2 volts. Any PMOS transistor whose source is at the supply voltage potential and whose gate is at the positive reference voltage 522 will form a mirror image of the current flowing through the PMOS transistor 534. This is the case for PMOS transistors 510 and 508. Figures 5A to 5CAs depicted, the example I2C output driver 500 includes an NMOS transistor 504 (e.g., a second transistor) that includes a source terminal, a gate terminal, and a drain terminal. The source terminal is electrically connected to electrical ground, and the gate terminal is electrically connected to a logic output signal 110. The drain terminal is electrically connected to a dot 208.

[0080] like Figures 5A to 5C As further depicted, the example I2C output driver 500 includes an NMOS output control transistor 206. The NMOS output control transistor 206 includes a source terminal, a gate terminal, and a drain terminal. The drain terminal is electrically connected to I2C line 122. The gate terminal is electrically connected to a resistor 532, wherein the resistor 532 is electrically connected between the gate terminal of the NMOS output control transistor 206 and a dot 208. The source terminal is electrically connected to electrical ground.

[0081] like Figures 5A to 5C As further depicted, the example I2C output driver 500 includes a PMOS transistor 510 (e.g., a third transistor) comprising a source terminal, a gate terminal, and a drain terminal. The source terminal is electrically connected to a positive voltage source. The gate terminal is electrically connected to a positive reference voltage 522. The drain terminal is electrically connected to a dot 528.

[0082] like Figures 5A to 5C As further described, the example I2C output driver 500 includes a first diode-connected NMOS transistor 512 and a second diode-connected PMOS transistor 514, both of which include a source terminal, a gate terminal, and a drain terminal. The drain terminal of the first diode-connected NMOS transistor 512 is electrically connected to point 528 and the gate terminal of the first diode-connected NMOS transistor 512. The source terminal of the first diode-connected NMOS transistor 512 is electrically connected to the drain terminal of the second diode-connected NMOS transistor 514. The drain terminal of the second diode-connected NMOS transistor 514 is also electrically connected to the gate terminal of the second diode-connected NMOS transistor 514. The source terminal of the second diode-connected NMOS transistor 514 is electrically connected to point 526.

[0083] like Figures 5A to 5C As further depicted, the example I2C output driver 500 includes an NMOS transistor 516 (e.g., a fourth transistor) that includes a source terminal, a gate terminal, and a drain terminal. The drain terminal is electrically connected to a dot 526. The gate terminal is electrically connected to the output of an inverter 530, wherein the inverter 530 is configured to receive a logic output signal 110. The source terminal is electrically connected to electrical ground.

[0084] like Figures 5A to 5C As further depicted, the example I2C output driver 500 includes an NMOS transistor 518 (e.g., a fifth transistor) that includes a source terminal, a gate terminal, and a drain terminal. The drain terminal is electrically connected to point 524. The source terminal is electrically connected to point 528. The drain terminal is electrically connected to point 208.

[0085] like Figures 5A to 5C As further depicted, the example I2C output driver 500 includes a PMOS transistor 520 (e.g., a sixth transistor) comprising a source terminal, a gate terminal, and a drain terminal. The source terminal is electrically connected to point 208. The gate terminal is electrically connected to a positive reference voltage 522. The drain terminal is electrically connected to point 526.

[0086] refer to Figure 5A This indicates the electrical components of the I2C output driver 500 associated with the example gate drive circuitry 108. (e.g.) Figure 5A The example gate drive circuit system 108 depicted includes a PMOS transistor 502, a current source 508, and an NMOS transistor 504 connected in series between a positive voltage source and electrical ground.

[0087] When logic output signal 110 transitions from a logic low state to a logic high state, NMOS transistor 504 is enabled and PMOS transistor 502 is disabled. Therefore, the gate terminal of output control transistor 206 is electrically connected to ground via NMOS transistor 504, and output control transistor 206 is disabled. In this situation, I2C output signal 102 is pulled high via I2C bus logic.

[0088] When the logic output signal 110 transitions from a logic high state to a logic low state, the NMOS transistor 504 is disabled and the PMOS transistor 502 is enabled. Therefore, the gate drive circuitry 108 generates an output transistor gate control signal 114 that includes a current based on the current source 508. A gate output control signal 116, based on the output transistor gate control signal 114 and the pre-charge signal 112, enables the output control transistor 206. With the output control transistor enabled, the I2C line 122 is electrically connected to ground. As described herein, the fall time of the I2C output signal 120 depends on the current of the gate output control signal 116 and the parasitic capacitance of the output control transistor 206.

[0089] refer to Figure 5B This indicates the electrical components of the I2C output driver 500 associated with the example gate precharge circuit system 104. For example... Figure 5BThe example gate precharge circuit system 104 depicted includes a PMOS transistor 502, an NMOS transistor 518, a PMOS transistor 510, a diode-connected NMOS transistor 512, a diode-connected NMOS transistor 514, and an NMOS transistor 516.

[0090] The gate precharge circuit system 104 is configured to inject a precharge signal 112 into the gate output control signal 116 when the logic output signal 110 transitions from a logic high state to a logic low state. Therefore, when the logic output signal 110 transitions from a logic high state to a logic low state, both the NMOS transistor 516 and the PMOS transistor 502 are enabled. Thus, the series-connected NMOS transistors 512, 514, and 516 pull the voltage at the gate terminal of the NMOS transistor 518 to the sum of the threshold voltage of the NMOS transistor 512 and the threshold voltage of the NMOS transistor 514. Additionally, the drain of the NMOS transistor 518 is pulled to the value of a positive voltage source by the PMOS transistor 502. Furthermore, when the NMOS transistor 504 is disabled, the source of the NMOS transistor 518 rises to the sum of the threshold voltage of the NMOS transistor 514 and the threshold voltage of the NMOS transistor 512 minus the threshold voltage of the NMOS transistor 518. In some embodiments, when the logic output signal 110 transitions from a logic high state to a logic low state, the source voltage of the NMOS transistor 518 can be approximated by the threshold voltage of the NMOS transistor 514, provided that the NMOS transistors 512 and 518 have similar threshold voltages.

[0091] When NMOS transistor 514 and output control transistor 206 have similar threshold voltages, the precharge signal 112 generated by the gate precharge circuit system 104 quickly pulls the dot 208 to the threshold voltage of the output control transistor 206 because, in addition to the low current path provided by the PMOS transistor associated with current source 508, NMOS transistor 518 also provides a highly conductive path from the positive supply voltage through PMOS transistor 502 and NMOS transistor 518.

[0092] The gate precharge circuit system 104 enables the gate voltage at the output control transistor 206 to rise quickly to the threshold voltage of the output control transistor 206, thereby avoiding the long delay that would have existed when the gate voltage depended only on the low current from the current source 508.

[0093] refer to Figure 5CThis indicates the electrical components of the I2C output driver 500 associated with the example latch-up protection circuit system 106. When the logic output signal 110 is in a logic low state, the latch-up protection circuit 106 prevents the voltage at point 208 (e.g., the gate of the output control transistor 206) from exceeding a threshold voltage. Exceeding the threshold voltage can cause numerous problems. For example, exceeding the threshold voltage may trigger a bipolar effect in a PMOS transistor. Similarly, a drop below electrically ground may trigger a bipolar effect in an NMOS transistor.

[0094] like Figure 5C The example latch-up protection circuit system 106 depicted includes a PMOS transistor 520 and an NMOS transistor 516. There is a potential risk of latch-up when the logic output signal 110 is low and the I2C line 122 is driven low by the on-state output control transistor 206. In this situation, the I2C output signal 120 is low, and the voltage at point 208 is high, for example, at the positive reference voltage. If the I2C bus forces a rising edge on I2C line 122 to create a current conflict on the output control resistor 206, the capacitive drain-gate coupling in the output control resistor 206 will tend to raise the potential of point 208 above the positive reference voltage. If the level at point 208 exceeds the positive reference voltage +0.6V, the parasitic drain-body diode of the PMOS transistor 508 can turn on and trigger latch-up (e.g., a parasitic bipolar PNPN structure, also known as a parasitic SCR or parasitic thyristor, inherent in common CMOS processes). Once the potential at point 208 exceeds the positive supply voltage, the PMOS transistor 520 prevents such latch-up by driving current to ground. When the voltage at point 208 exceeds the positive supply voltage, resistor 532 limits the current injected into the source terminal of the PMOS transistor 520, thereby helping to reduce the voltage at point 208. In some embodiments, the threshold voltage at point 208 may include the positive supply voltage + 0.6 volts. Once the voltage at point 208 exceeds the positive supply voltage, the PMOS transistor 520 begins to drive current to ground, and its dimensions are determined such that (based on its impedance) the maximum voltage at point 208 never reaches the positive supply voltage + 0.6V.

[0095] When logic output signal 110 is in a logic low state and the voltage amplitude at point 208 is close to the threshold voltage, PMOS transistor 520 is enabled, and current flows from point 208 through PMOS transistor 520 and through NMOS transistor 516 to electrical ground. Therefore, the voltage at point 208 can be kept below the positive voltage source. The threshold voltage can be defined based on a positive reference voltage 522. For example, as... Figure 5CAs depicted, the gate of PMOS transistor 520 receives a positive reference voltage 522. When the drain terminal of PMOS transistor 520 is electrically grounded (e.g., logic output signal 110 is low, NMOS transistor 516 is on, and point 208 is high), the source terminal of PMOS transistor 520 drives current to ground when the voltage at the source terminal (e.g., point 208) is higher than the absolute value of the gate terminal voltage (e.g., positive reference voltage 522) plus the threshold voltage of PMOS transistor 520 (approximately a positive voltage source).

[0096] Now refer to Figure 6 Example timing diagram 600 is provided. Figure 6 The diagram illustrates the I2C output signal 120 and gate output control signal 116 in two example I2C output drivers. Signal diagram 602 illustrates the I2C output signal 120 and gate output control signal 116 in an I2C output driver without a gate precharge circuitry system (e.g., gate precharge circuitry system 104). Signal diagram 604 illustrates the I2C output signal 120 and gate output control signal 116 in an I2C output driver with a gate precharge circuitry system (e.g., I2C output drivers 100, 200, 500).

[0097] like Figure 6 As depicted, at time t0, the logic output signal 110 transitions from a logic low state to a logic high state. In both signal diagrams 602 and 604, the gate output control signal 116 becomes 0, and the I2C output signal 120 begins to rise. Because the rise of the I2C output signal 120 is controlled by the I2C bus, the rise is the same in both circuits.

[0098] At time t2, logic output signal 110 transitions from a logic high state to a logic low state. In response, gate output control signal 116 begins to rise. Figure 6 As depicted in the diagram, based on an I2C output driver including a gate precharge circuit system, the gate output control signal 116 rises much faster in signal diagram 604.

[0099] At time t3, the voltage at the gate terminal of the output control transistor reaches the threshold voltage of the output control transistor, and the output control transistor begins to conduct. As the output control transistor conducts, the voltage of the I2C output signal begins to decrease. The voltage at the gate terminal of the output control transistor continues to increase until, at time t4, the current from current source 508 equals the capacitor feedback current. The I2C output signal decreases linearly until it reaches a stable low level at time t5. The capacitor feedback current returns to 0. The voltage at the gate terminal of the output control transistor continues to increase until it reaches the threshold voltage at time t6.

[0100] Now refer to Figure 7 Example timing diagram 700 is depicted, which depicts the rise and fall times of an I2C output signal (e.g., I2C output signal 120) generated using an I2C output driver (e.g., I2C output driver 100, 200, 500).

[0101] Timing diagram 702 depicts a logic output signal 110a at a high voltage (e.g., 5.5 volts) and a logic output signal 110b at a low voltage (e.g., 1.6 volts).

[0102] Timing diagram 704 depicts the response of I2C output signals 120a and 120b to variations in logic output signals 110a and 110b. As depicted in timing diagram 704, the rise times of I2C output signals 120a and 120b are controlled by the I2C bus. However, the fall times of I2C output signals 120a and 120b are controlled by the output control transistor of the I2C driver (e.g., output control transistor 206). As shown in timing diagram 704, the fall slopes of I2C output signals 120a and 120b are almost constant.

[0103] Timing diagram 706 depicts gate control signals 116a and 116b in response to changes in logic output signals 110a and 110b. As depicted in timing diagram 706, both gate control signals 116a and 116b initially rise rapidly with the assistance of gate precharge circuit system 104.

[0104] Now refer to Figure 8 Example timing diagram 800 is provided. Example timing diagram 800 compares the fall time in an I2C output driver (e.g., I2C output driver 100, 200, 500) with the fall time in an I2C output driver without a gate precharge circuit system 104 at a low voltage.

[0105] Timing diagram 802 depicts a logic output signal 110b at a low voltage (e.g., 1.6 volts).

[0106] Timing diagram 804 compares the fall times of I2C output signals 120c and 120d in response to changes in logic output signal 110b. I2C output signal 120c depicts the fall time of an I2C output driver with gate precharge circuitry system 104, while I2C output signal 120d depicts the fall time of an I2C output driver without gate precharge circuitry system 104. As depicted in timing diagram 804, the fall of I2C output signal 120c occurs approximately 15 nanoseconds earlier than the fall of I2C output signal 120d due to the precharge signal (e.g., precharge signal 112) provided by the gate precharge circuitry system (e.g., gate precharge circuitry system 104).

[0107] Timing diagram 806 depicts the corresponding gate output control signals 116c and 116d. Gate output control signal 116c depicts the gate output control signal of the I2C output driver with gate precharge circuitry system 104, while gate output control signal 116d depicts the gate output control signal of the I2C output driver without gate precharge circuitry system 104. As depicted in timing diagram 806, gate output control signal 116c with gate precharge circuitry system 104 rises faster than gate output control signal 116d.

[0108] Now refer to Figure 9 Example timing diagram 900 is provided. Example timing diagram 900 compares the fall time in an I2C output driver (e.g., I2C output driver 100, 200, 500) with the fall time in an I2C output driver without a gate precharge circuit system 104 at a high voltage.

[0109] Timing diagram 902 depicts a logic output signal 110a at a high voltage (e.g., 5.5 volts).

[0110] Timing diagram 904 compares the fall times of I2C output signals 120e and 120f in response to changes in logic output signal 110a. I2C output signal 120e depicts the fall time of an I2C output driver with gate precharge circuitry system 104, while I2C output signal 120f depicts the fall time of an I2C output driver without gate precharge circuitry system 104. As depicted in timing diagram 904, the fall of I2C output signal 120e occurs approximately 36 nanoseconds earlier than the fall of I2C output signal 120f due to the precharge signal (e.g., precharge signal 112) provided by the gate precharge circuitry system (e.g., gate precharge circuitry system 104).

[0111] Timing diagram 906 depicts the corresponding gate output control signals 116e and 116f. Gate output control signal 116e depicts the gate output control signal of the I2C output driver with gate precharge circuitry system 104, while gate output control signal 116f depicts the gate output control signal of the I2C input driver without gate precharge circuitry system 104. As depicted in timing diagram 906, gate output control signal 116e with gate precharge circuitry system 104 rises faster than gate output control signal 116f.

[0112] Now refer to Figure 10 A block diagram of an example electronic system 1000 is provided. For example... Figure 10 As depicted, the electronic system 1000 includes a data generator circuit system 1002 configured to generate a data output signal 1010. The data generator circuit system 1002 includes any circuit system containing hardware and / or software configured to generate digitally encoded data according to a communication protocol. For example, the data generator circuit system 1002 may be configured to encode data into digital signals (e.g., data output signal 1010) based on data transmission on I2C data line 1022.

[0113] like Figure 10 As further described herein, the data generator circuitry 1002 is configured to provide a data output signal 1010 (e.g., logic output signal 110) to an I2C output driver (e.g., I2C output driver 100, 200, 500) configured according to this disclosure. The I2C output driver is configured to generate an I2C data signal 1020 (e.g., I2C output signal 120) on the I2C data line 1022 according to the I2C communication protocol.

[0114] In some embodiments, the electronic system 1000 may include an I2C communication slave device.

[0115] Now refer to Figure 11 An example flowchart is provided, depicting a process 1100 of generating I2C output signals (e.g., I2C output signal 120, I2C data signal 1020) based on logic output signals (e.g., logic output signal 110, data output signal 1010) according to the I2C communication protocol. At block 1102, the logic output signals are received at the gate drive circuitry system (e.g., gate drive circuitry system 108) of the I2C output drivers (e.g., I2C output drivers 100, 200, 500). As described herein, the logic output signals may include digitally encoded data and / or clock signals intended for transmission on I2C lines (e.g., I2C data lines or I2C block lines) according to the I2C communication protocol.

[0116] In block 1104, the gate drive circuitry of the I2C output driver generates an output transistor gate control signal (e.g., output transistor gate control signal 114) based on a logic output signal. In some embodiments, the output transistor gate control signal may include an inverted signal of the logic output signal. Additionally, in some embodiments, the output transistor gate control signal may be generated including a current and / or voltage configured to drive an output control circuitry (e.g., output control circuitry 102) according to the I2C communication protocol.

[0117] In block 1106, a logic output signal is received at the gate precharge circuitry system (e.g., gate precharge circuitry system 104) of the I2C output driver.

[0118] In block 1108, the gate precharge circuitry generates a precharge signal (e.g., precharge signal 112) when the logic output signal is in a logic low state. As described herein, the gate precharge circuitry can be configured to inject current at the gate of the output control transistor to reduce the on-time of the output control transistor. In some embodiments, the current of the precharge signal can be based on the parasitic capacitance of the output control transistor.

[0119] In block 1110, a gate output control signal (e.g., gate output control signal 116) is received at the gate terminal of the output control transistor (e.g., output control transistor 206) of the I2C output driver, wherein the gate output signal includes a precharge signal and an output transistor gate control signal. The output control transistor includes: a drain terminal electrically connected to the I2C output line; a gate terminal; a source terminal electrically connected to electrical ground; and a gate-drain capacitor based on the geometry of the drain terminal and the gate terminal. As described herein, when the voltage at the gate terminal of the output control transistor exceeds the threshold voltage of the output control transistor, the output control transistor is enabled and the I2C line is electrically connected to ground, thereby pulling the I2C output signal to electrical ground.

[0120] In block 1112, an I2C output signal is generated on the I2C output line, wherein the fall time of the I2C output signal is controlled based on a precharge signal, an output transistor gate control signal, and a gate-drain capacitance. As described herein, the precharge signal and the output transistor gate control signal are combined at the gate terminal of the output control transistor. The on-time of the output control transistor is based on the current of the gate output control signal, which includes the precharge signal and the output transistor gate control signal. The gate-drain capacitance of the output control transistor, along with other parasitic capacitances in the output control transistor, determines the fall time of the I2C output signal.

[0121] While this detailed description has illustrated some embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments, according to various modifications and improvements. For example, those skilled in the art will recognize that such principles can be applied to any electronic device that communicates over an I2C line using an I2C driver. For example, electronic devices that implement one or more I2C master devices and / or one or more I2C slave devices. Such devices may include microcontrollers, memories, computer monitors, sensors, and many other interconnect devices.

[0122] In the appended claims, unless the specific terms “means for…” or “steps for…” are used in a given claim, they are not intended to be interpreted in accordance with paragraph 6 of 35 USC 112.

[0123] The use of broader terms such as “comprising,” “including,” and “having” should be understood to support narrower terms such as “consisting of,” “essentially consisting of,” and “substantially consisting of.” The use of terms such as “optionally,” “may,” “possibly,” “possibly,” etc., relating to any element of the embodiments means that the element is not required, or alternatively, that the element is required, both of which are within the scope of the embodiments. Furthermore, references to examples are provided merely for illustrative purposes and are not intended to be exclusive.

Claims

1. An internal integrated circuit I2C output driver configured to receive a logic output signal, the I2C output driver comprising: Output control transistor, the output control transistor comprising: Drain terminal, which is electrically connected to the I2C output line; A gate terminal configured to receive a gate output control signal; The source terminal is electrically connected to electrical ground; and Gate-drain capacitance, the gate-drain capacitance being based on the geometry of the drain terminal and the gate terminal; A gate precharge circuit system configured to generate a precharge signal when the logic output signal is at a logic low state; and A gate drive circuit system configured to generate an output transistor gate control signal based on the logic output signal; The gate output control signal includes the precharge signal and the output transistor gate control signal; and The fall time of the I2C output signal transmitted on the I2C output line is controlled based on the pre-charge signal, the output transistor gate control signal, and the gate-drain capacitance.

2. The I2C output driver according to claim 1, wherein, The I2C output signal is either a serial data line or a serial clock line.

3. The I2C output driver according to claim 2, wherein, The fall time of the I2C output signal depends on the gate-drain capacitance, the precharge signal, and the output transistor gate control signal.

4. The I2C output driver according to claim 3, wherein, The fall time of the I2C output signal is greater than 5.8 nanoseconds and less than 120 nanoseconds.

5. The I2C output driver according to claim 1, wherein, The gate terminal of the output control transistor overlaps with the gate-drain terminal of the output control transistor more than the gate terminal overlaps with the gate-source terminal of the output control transistor.

6. The I2C output driver according to claim 1, wherein, The output control transistor includes a high-voltage transistor, which has a rated voltage of at least 5.5 volts.

7. The I2C output driver according to claim 1, wherein, The gate drive circuit system includes a first transistor, a current source, and a second transistor connected in series, wherein the first transistor and the second transistor have opposite channel types, and wherein the first transistor and the second transistor are configured to receive the logic output signal.

8. The I2C output driver according to claim 1, wherein, The gate precharge circuit system includes: A third transistor, a plurality of diode-connected transistors, and a fourth transistor are connected in series, wherein a precharge control signal is generated between the third transistor and the plurality of diode-connected transistors.

9. The I2C output driver according to claim 8, wherein, The gate precharge circuit system also includes: A fifth transistor is configured to generate the precharge signal based on the precharge control signal when the logic output signal transitions from logic high to logic low.

10. The I2C output driver according to claim 9, further comprising a latch-up protection circuit system, wherein, When the gate output control signal approaches the threshold voltage, the latch-up protection circuit system reduces the voltage of the gate output control signal.

11. The I2C output driver according to claim 10, wherein, The latch-up protection circuit system includes a sixth transistor connected in series with the fourth transistor between the gate terminal of the output control transistor and the electrical ground, wherein the sixth transistor and the fourth transistor have opposite channel types.

12. An electronic system comprising: A data generator circuit system configured to generate one or more data output signals; and I2C output driver, the I2C output driver comprising: Output control transistor, the output control transistor comprising: Drain terminal, which is electrically connected to the I2C data line; A gate terminal configured to receive a gate output control signal; The source terminal is electrically connected to electrical ground; and Gate-drain capacitance, the gate-drain capacitance being based on the geometry of the drain terminal and the gate terminal; A gate precharge circuit system configured to generate a precharge signal when the logic output signal is at a logic low state; and A gate drive circuit system configured to generate an output transistor gate control signal based on the data output signal; The gate output control signal includes the precharge signal and the output transistor gate control signal; and The fall time of the I2C data signal transmitted on the I2C data line is controlled based on the pre-charge signal, the output transistor gate control signal, and the gate-drain capacitance.

13. The electronic system according to claim 12, wherein, The fall time of the I2C data signal depends on the gate-drain capacitance, the precharge signal, and the output transistor gate control signal.

14. The electronic system according to claim 13, wherein, The fall time of the I2C data signal is greater than 5.8 nanoseconds and less than 120 nanoseconds.

15. The electronic system according to claim 12, wherein, The gate terminal of the output control transistor overlaps with the gate-drain terminal of the output control transistor more than the gate terminal overlaps with the gate-source terminal of the output control transistor.

16. The electronic system according to claim 12, wherein, The gate drive circuit system includes a first transistor, a current source, and a second transistor connected in series, wherein the first transistor and the second transistor have opposite channel types, and wherein the first transistor and the second transistor are configured to receive the logic output signal.

17. The electronic system according to claim 12, wherein, The gate precharge circuit system includes: A third transistor, a plurality of diode-connected transistors, and a fourth transistor are connected in series, wherein a precharge control signal is generated between the third transistor and the plurality of diode-connected transistors; and A fifth transistor is configured to generate the precharge signal based on the precharge control signal when the logic output signal transitions from logic high to logic low.

18. The electronic system of claim 17, wherein the I2C output driver further comprises a latch-up protection circuit system, wherein, When the gate output control signal approaches the threshold voltage, the latch-up protection circuit system reduces the voltage of the gate output control signal.

19. The electronic system according to claim 18, wherein, The latch-up protection circuit system includes a sixth transistor connected in series with the fourth transistor between the gate terminal of the output control transistor and the electrical ground, wherein the sixth transistor and the fourth transistor have opposite channel types.

20. A method for generating an I2C output signal based on a logic output signal, the method comprising: The logic output signal is received at the gate drive circuit system of the I2C output driver; At the gate drive circuit system, an output transistor gate control signal is generated based on the logic output signal; The logic output signal is received at the gate precharge circuit system of the I2C output driver; In the gate precharge circuit system, a precharge signal is generated when the logic output signal is in a logic low state; At the gate terminal of the output control transistor of the I2C output driver, a gate output control signal is received, wherein the gate output control signal includes the precharge signal and the output transistor gate control signal, and the output control transistor includes: Drain terminal, which is electrically connected to the I2C output line; Gate terminal; The source terminal is electrically connected to electrical ground; and Gate-drain capacitance, the gate-drain capacitance being based on the geometry of the drain terminal and the gate terminal; The I2C output signal is generated on the I2C output line, wherein the fall time of the I2C output signal is controlled based on the precharge signal, the output transistor gate control signal, and the gate-drain capacitance.

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