phase locked loop circuit

Abstract

A phase-locked loop circuit includes a digitally controlled oscillator for generating an output clock signal based on at least one control code generated using at least one phase error signal; and a phase detector for generating the at least one phase error signal based on a rising edge difference between a rising edge of a first clock signal and a corresponding edge of a edge-aligned correction feedback signal and a rising edge lead-lag relationship; wherein the edge-aligned correction feedback signal is generated based on the output clock signal.

Description

Technical Field

[0001] This application relates to a phase-locked loop circuit, and more particularly to a phase-locked loop circuit that digitally implements an analog phase-locked loop circuit. Background Technology

[0002] In the display technology field, analog phase-locked loop (PLL) circuits or digital counting frequency sensing circuits are commonly used to generate the required high-precision clocks. An analog PLL circuit includes a phase frequency detector, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider to provide an output clock aligned with a reference clock. However, the need to redesign analog PLL circuits for different specifications leads to longer development timelines. For example, the resistor and capacitor values ​​of the loop filter need to be redesigned to change the bandwidth for different lock times. Alternatively, the VCO and frequency divider need to be redesigned for different output and reference clocks.

[0003] Digital counting frequency sensing circuits comprise a digital counter circuit and a digital voltage-controlled oscillator (VCO) to provide an output clock correlated with a reference clock. Compared to analog phase-locked loop (PLL) circuits, digital counting frequency sensing circuits offer the advantage of rapid implementation by digital circuits. However, digital counting frequency sensing circuits have the following limitations: the output clock and reference clock are not phase-aligned; the output clock has high noise; and the lock-in time is relatively long. Therefore, combining the advantages of analog PLL circuits and digital counting frequency sensing circuits has become a goal for the industry. Summary of the Invention

[0004] Therefore, one objective of this application is to provide a digital phase-locked loop circuit for providing an output clock. This helps to combine the advantages of analog phase-locked loop circuits and digital counting frequency detection circuits.

[0005] This application provides a phase-locked loop circuit, comprising a digitally controlled oscillator for generating an output clock signal based on at least one control code generated using at least one phase error signal; and a phase detector for generating the at least one phase error signal based on a rising edge difference and a rising edge lead-lag relationship between a rising edge of a first clock signal and a corresponding edge of an edge alignment correction feedback signal; wherein the edge alignment correction feedback signal is generated based on the output clock signal.

[0006] This application provides a phase detector for a phase-locked loop circuit, comprising: a counter for generating an edge alignment correction feedback signal based on an output clock signal of the phase-locked loop circuit; an edge sampler for generating a first sample signal corresponding to the rising edge of the first clock signal of the phase-locked loop circuit, and a second sample signal corresponding to the rising edge lead-lag relationship between the rising edge of the first clock signal and a corresponding edge of the edge alignment correction feedback signal, based on the first clock signal and the output clock signal; and a phase quantization circuit coupled to the counter and the edge sampler for generating at least one phase error signal based on the first sample signal, the second sample signal, and the edge alignment correction feedback signal. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a phase-locked loop circuit according to an embodiment of this application.

[0008] Figure 2 This is a schematic diagram of a phase detector according to an embodiment of this application.

[0009] Figure 3 This is a schematic diagram of an edge sampler according to an embodiment of this application.

[0010] Figure 4 The waveform diagram shows a first clock signal, a first sampling signal, and an edge alignment correction feedback signal according to an embodiment of this application.

[0011] Figure 5 This is a schematic diagram of an edge sampler according to another embodiment of this application.

[0012] Figure 6 This is a schematic diagram of a phase-locked loop circuit according to another embodiment of this application.

[0013] Figure 7 The waveform diagrams are of at least one first phase error code and at least one second phase error code according to an embodiment of this application.

[0014] Figure 8 This is a schematic diagram of a digitally controlled oscillator according to an embodiment of this application.

[0015] Figure 9 This is a schematic diagram of a phase-locked loop circuit according to another embodiment of this application.

[0016] The reference numerals in the attached figures are explained as follows: Detailed Implementation

[0017] Certain terms are used in this specification and subsequent claims to refer to specific components. It will be understood by those skilled in the art that hardware manufacturers may use different names to refer to the same component. This specification and subsequent claims do not distinguish components by differences in name, but by differences in function. The term "comprising" as used throughout this specification and subsequent claims is an open-ended term and should be interpreted as "including but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0018] Please refer to Figure 1 . Figure 1 This is a schematic diagram of a phase-locked loop circuit 1 according to an embodiment of this application. The phase-locked loop circuit 1 includes a phase detector 10, a loop filter 20, and a digitally controlled oscillator 30. The digitally controlled oscillator 30 is used to adjust the phase based on at least one phase error signal PD. er At least one control code DCO generated code Generate output clock signal CLK out Phase detector 10 is used to detect a first clock signal CLK. Ref The rise edge difference and rise edge lead / lag relationship between a rise edge and a corresponding edge of an edge alignment correction feedback signal generate at least one phase error signal PD. er It should be noted that the edge alignment correction feedback signal is based on the output clock signal CLK. out This is generated. In one embodiment, the loop filter 20 is coupled between the phase detector 10 and the digitally controlled oscillator 30 to generate based on at least one phase error signal PD. er Generate at least one first phase error code as at least one control code DCO code .

[0019] Please refer to Figure 2 . Figure 2 This is a schematic diagram of one embodiment of a phase detector 10. The phase detector 10 includes an edge sampler 101, a counter 102, and a phase quantization circuit 103. The edge sampler 101 is used to measure the phase based on a first clock signal CLK. Ref and output clock signal CLK out A first sampled signal Ref_trig corresponding to the rising edge and a second sampled signal Ref_lag corresponding to the rising edge lead-lag relationship are generated. Please refer to [reference needed]. Figure 3 , Figure 3This is a schematic diagram of one embodiment of the edge sampler 101. The edge sampler 101 includes D-type flip-flop circuits DFF1 to DFF6, an inverter (NOTgate) circuit, an XOR gate circuit, a NAND gate circuit, and a decision circuit 1011. The two input terminals of the XOR circuit respectively receive the first clock signal CLK. Ref And a switching signal INV, used to switch the phase detector 10 to detect the first clock signal CLK. Ref The rising edge or a falling edge. Specifically, when the switching signal INV=0, the phase detector 10 can detect the first clock signal CLK. Ref The rising edge; conversely, when the switching signal INV=1, the phase detector 10 can detect the first clock signal CLK. Ref The falling edge. It should be noted that, for ease of explanation, the following examples will use the switching signal INV=0. Furthermore, the operating principles of D-type flip-flops, inverters, mutual exclusion gates, and reverse gates are well-known in the art and will not be elaborated upon here.

[0020] In edge sampler 101, each clock signal terminal of DFF1 to DFF3 of the DFF circuit receives the output clock signal CLK. out The data input terminal of DFF1 is coupled to the output terminal of the XOR circuit, the data input terminal of DFF2 is coupled to the data output terminal of DFF1, and the data input terminal of DFF3 is coupled to the data output terminal of DFF2. The two input terminals of the judgment circuit 1011 are coupled to the data output terminals of DFF2 and DFF3, respectively. In this way, the judgment circuit 1011 can determine the first clock signal CLK. Ref The phase of the rising edge is determined, and the first sampled signal Ref_trig is output accordingly. Please refer to... Figure 4 , Figure 4 The first clock signal CLK in an embodiment of this application Ref The waveforms of the first sampled signal Ref_trig and the edge alignment correction feedback signal div are shown below. Figure 4 As shown, the first sampling signal Ref_trig=1 represents the first clock signal CLK. Ref The phase of the rising edge.

[0021] Furthermore, the clock signal terminal of the DFF4 circuit receives the output clock signal CLK through an inverter circuit. out The clock signal terminals of DFF5 to DFF6 in the DFF circuit respectively receive the output clock signal CLK. outThe data input terminal of DFF4 in the DFF circuit is coupled to the output terminal of the XOR circuit. The data input terminal of DFF5 in the DFF circuit is coupled to the data output terminal of DFF4 in the DFF circuit. The data input terminal of DFF6 in the DFF circuit is coupled to the data output terminal of DFF5 in the DFF circuit. The two input terminals of the inverted gate circuit are coupled to the output terminal of the judgment circuit 1011 and the data output terminal of DFF6 in the DFF circuit, respectively. In this way, the inverted gate circuit can determine the first clock signal CLK. Ref The phase of the rising edge and the output clock signal CLK out The rising edge lead-lag relationship of the corresponding rising edge phase is determined, and the second sampling signal Ref_lag is output accordingly. For example, when the second sampling signal Ref_lag=1, the first clock signal CLK... Ref The rising edge phase leads the output clock signal CLK out The phase corresponding to the rising edge; conversely, when the second sampled signal Ref_lag=0, the first clock signal CLK... Ref The rising edge phase lags behind the output clock signal CLK out The phase of the corresponding rising edge.

[0022] Please continue to refer to this. Figure 2 Counter 102 is used to determine the output clock signal CLK. out An edge alignment correction feedback signal div is generated. A phase quantization circuit 103, coupled to a counter 102 and an edge sampler 101, is used to generate at least one phase error signal PD based on a first sampled signal Ref_trig, a second sampled signal Ref_lag, and the edge alignment correction feedback signal div. er Specifically, the phase quantization circuit 103 can record the rising edge value of the edge alignment correction feedback signal div when the first sampled signal Ref_trig=1, and calculate the first clock signal CLK based on the rising edge value and the second sampled signal Ref_lag. Ref The output clock signal CLK after frequency division out At least one phase error signal PD er It should be noted that, by using the rising edge lead-lag relationship represented by the second sampled signal Ref_lag, the phase quantization circuit 103 can obtain at least one phase error signal PD with better resolution. er Please continue to refer to this. Figure 4 The edge alignment correction feedback signal div=0 represents the output clock signal CLK. out The phase of the corresponding rising edge. Furthermore, the difference between the rising edge value and 0 of the edge alignment correction feedback signal div corresponding to the first sampled signal Ref_trig=1 represents the first clock signal CLK. Ref The output clock signal CLK after frequency division outThe phase difference.

[0023] It should be noted that, Figure 3 This is merely an embodiment of this application, and those skilled in the art can make appropriate adjustments according to system requirements. For example, please refer to... Figure 5 , Figure 5 This is a schematic diagram of an edge sampler 101 according to another embodiment of this application. In one embodiment, the digitally controlled oscillator 30 can generate a four-phase output clock signal CLK. out1 ~CLK out4 The edge sampler 101 can determine the first clock signal CLK based on this. Ref The phase of the rising edge. And the edge sampler 101 can determine the phase of the first clock signal CLK. Ref The phase of the rising edge and multiple output clock signals CLK out1 ~CLK out4 The phase quantization circuit 103 calculates the rising edge lead-lag relationship of the corresponding rising edge phase and outputs multiple second sampled signals Ref_lag1 to Ref_lag3 accordingly. In this way, by using the rising edge lead-lag relationship represented by the multiple second sampled signals Ref_lag1 to Ref_lag3, the phase quantization circuit 103 can obtain at least one phase error signal PD with better resolution. er .

[0024] Furthermore, the loop filter 20 will filter at least one phase error signal PD. er Convert to at least one control code DCO code The digital control oscillator 30 is used to generate the output clock signal CLK. out Specifically, the loop filter 20 can be implemented digitally using s-domain to z-domain conversion methods such as a bilinear transformation method or a pulse-invariant method, but is not limited to this. It should be noted that the working principles of the bilinear transformation method or the pulse-invariant method are well known in the art and will not be elaborated here.

[0025] Please note Figure 1 This is merely an embodiment of this application, and those skilled in the art can make appropriate adjustments according to system requirements. To improve the noise immunity of the phase-locked loop circuit of this application, the phase-locked loop circuit may selectively include a frequency stabilization circuit and / or an integral-derivative modulation (Sigma-Delta Modulation) circuit. It should be noted that the following phase-locked loop circuit is derived from phase-locked loop circuit 1, therefore, the same components are represented by the same symbols. Please refer to... Figure 6 , Figure 6This is a schematic diagram of a phase-locked loop circuit 2 according to an embodiment of this application. The difference between phase-locked loop circuit 2 and phase-locked loop circuit 1 lies in the frequency stabilization circuit 40 and the integral-differential modulation circuit 50. In this embodiment, phase-locked loop circuit 2 can control the control terminals SEL1 and SEL of multiplexers MUX1 and MUX2, so that the digitally controlled oscillator 30 is directly or through one or more of the frequency stabilization circuit 40 and the integral-differential modulation circuit 50 coupled to the loop filter 20.

[0026] In one embodiment, the digitally controlled oscillator 30 is coupled to the loop filter 20 via a frequency stabilization circuit 40. The frequency stabilization circuit 40 can filter or integrate at least one first phase error code and output at least one second phase error code as at least one control code (DCO). code Please refer to this. Figure 7 , Figure 7 The image shows waveforms of at least one first phase error code and at least one second phase error code according to an embodiment of this application. Figure 7 As shown, compared to at least one first phase error code DCO code1 At least one second phase error code DCO code2 The waveform changes relatively smoothly. In this way, at least one second phase error code (DCO) is obtained. code2 As at least one control code DCO code The digital control oscillator 30 generates the output clock signal CLK. out This allows the phase-locked loop circuit 2 to have better noise immunity.

[0027] In another embodiment, the digital controlled oscillator 30 is coupled to the loop filter 20 via an integrator-differential modulation circuit 50. The integrator-differential modulation circuit 50 can convert the quantization error of at least one first phase error code to the high-frequency band and output at least one third phase error code as at least one control code (DCO). code In other words, the quantization noise in the low-frequency band is reduced, and the output clock signal CLK... out The frequency will not deviate from the target frequency for an extended period. It should be noted that, in this embodiment, such as... Figure 8 As shown, the digital-controlled oscillator 30 may include a current-to-digital-to-analog converter 301, a low-pass filter 302, and a current-controlled oscillator 303. The current-to-digital-to-analog converter 301 is used to convert the current as at least one control code (DCO) into a digital-to-analog converter. code At least one third phase error code is converted into at least one control current. A low-pass filter 302 is coupled between a current digital-to-analog converter 301 and a current-controlled oscillator 303 to filter out quantization errors in the high-frequency band of the at least one control current, and thereby drives the current-controlled oscillator 303 to generate an output clock signal CLK. outIt should be noted that the filtering or integration processing of the frequency stabilization circuit 40 and the working principle of the integral-differential modulation circuit 50 are well known in the art and will not be described in detail here.

[0028] Furthermore, the phase detector 10, loop filter 20, frequency stabilization circuit 40, and integral-differential modulation circuit 50 of the phase-locked loop circuit 2 of this application are all implemented using digital circuits. Therefore, the phase-locked loop circuit 2 can utilize the advantages of rapid adjustment of digital circuits to control the phase-locked loop circuit 2 to meet different requirements and specifications. Please refer to... Figure 9 , Figure 9 This is a schematic diagram of a phase-locked loop (PLL) circuit 3 according to an embodiment of this application. The difference between PLL circuit 3 and PLL circuit 2 is that PLL circuit 3 also includes a state control circuit 60. State control circuit 60 is coupled to phase detector 10, loop filter 20, frequency stabilization circuit 40, and integral-derivative modulation circuit 50, and is used to control the output of phase detector 10 according to different requirements, or to adjust the parameter settings of loop filter 20, frequency stabilization circuit 40, and integral-derivative modulation circuit 50.

[0029] In one embodiment, when the first clock signal CLK Ref In the event of a failure, the state control circuit 60 can control the phase detector 10, loop filter 20, frequency stabilization circuit 40, and integral-derivative modulation circuit 50 to continue outputting the corresponding signals, so that the phase-locked loop circuit 3 can continue to output the output clock signal CLK. out In another embodiment, when the phase-locked loop circuit 3 has entered the locked state, the state control circuit 60 can control the deactivation of the first clock signal CLK. Ref It also controls the phase detector 10, loop filter 20, frequency stabilization circuit 40, and integral-differential modulation circuit 50 to continue outputting the corresponding signals, so that the phase-locked loop circuit 3 can continue to output the output clock signal CLK. out In another embodiment, when the first clock signal CLK Ref In the event of excessive noise or sudden phase change, the state control circuit 60 can control the phase detector 10, loop filter 20, frequency stabilization circuit 40, and integral-differential modulation circuit 50 to continue outputting the corresponding signal (e.g., the signal from the previous cycle in the locked state), so that the phase-locked loop circuit 3 can continue to output the output clock signal CLK. out .

[0030] In another embodiment, when the requirements specify that the phase-locked loop circuit 3 should enter a fast locking mode, the state control circuit 60 can adjust the parameters of the loop filter 20 to increase the bandwidth and reduce the locking time of the phase-locked loop circuit 3. After the phase-locked loop circuit 3 enters the locked state, the state control circuit 60 can adjust the parameters of the loop filter 20 to reduce the bandwidth and decrease the first clock signal CLK. Ref The jitter affects the phase-locked loop circuit 3. In another embodiment, the state control circuit 60 can record the lock output clock signal CLK when the phase-locked loop circuit 3 enters the locked state. out At least one control code DCO corresponding to the target frequency code When the phase-locked loop circuit 3 starts operating, the state control circuit 60 can adjust the parameters of the loop filter 20, the frequency stabilization circuit 40, and the integral-derivative modulation circuit 50, so that the initial at least one control code DCO is generated. code At least one control code DCO close to the target frequency code In this way, the locking time of phase-locked loop circuit 3 can be significantly reduced.

[0031] In summary, the phase-locked loop circuit of this application implements the architecture of a traditional analog phase-locked loop circuit using digital circuitry. In this way, the phase-locked loop circuit can obtain an output clock signal aligned with the reference clock signal, while also taking advantage of the rapid adjustment and implementation capabilities of digital circuitry.

[0032] The foregoing has outlined the features of several embodiments to enable those skilled in the art to fully understand various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A phase-locked loop circuit, characterized in that, Include: A digitally controlled oscillator for generating an output clock signal based on at least one control code generated using at least one phase error signal; and A phase detector is used to generate the at least one phase error signal based on a rising edge difference and a rising edge lead-lag relationship between a rising edge of a first clock signal and a corresponding edge of an edge alignment correction feedback signal. The edge alignment correction feedback signal is generated based on the output clock signal.

2. The phase-locked loop circuit as described in claim 1, characterized in that, The phase detector includes: A counter is used to generate the edge alignment correction feedback signal based on the output clock signal; An edge sampler is configured to generate a first sampled signal corresponding to the rising edge and a second sampled signal corresponding to the lead-lag relationship of the rising edge, based on the first clock signal and the output clock signal; and A phase quantization circuit, coupled to the counter and the edge sampler, is used to generate the at least one phase error signal based on the first sample signal, the second sample signal and the edge alignment correction feedback signal.

3. The phase-locked loop circuit as described in claim 2, characterized in that, The edge sampler includes: A first type D flip-flop includes a first clock input, a first data input, and a first data output. A second D-type flip-flop includes a second clock input, a second data input, and a second data output. A third type D flip-flop includes a third clock input, a third data input, and a third data output. The first clock input terminal, the second clock input terminal, and the third clock input terminal are used to receive the output clock signal. The first data input terminal is used to receive the first clock signal. The first data output terminal is used to output a first data output signal to the second data input terminal. The second data output terminal is used to output a second data output signal to the third data input terminal. The third data output terminal is used to output a third data output signal. A judgment circuit is used to receive the second data output signal and the third data output signal to generate the first sampling signal; An inverter circuit is used to receive the output clock signal and generate an inverted output clock signal; A fourth D-type flip-flop, comprising a fourth clock input, a fourth data input, and a fourth data output; A fifth type D flip-flop includes a fifth clock input, a fifth data input, and a fifth data output. A sixth type D flip-flop, comprising a sixth clock input, a sixth data input, and a sixth data output; The fourth clock input terminal is used to receive the inverted output clock signal; the fifth and sixth clock input terminals are used to receive the output clock signal; the fourth data input terminal is used to receive the first clock signal; the fourth data output terminal is used to output a fourth data output signal to the fifth data input terminal; the fifth data output terminal is used to output a fifth data output signal to the sixth data input terminal; and the sixth data output terminal is used to output a sixth data output signal. An inverting and gate circuit is used to receive the first sampling signal and the sixth data output signal to generate the second sampling signal.

4. The phase-locked loop circuit as described in claim 2, characterized in that, Also includes: A loop filter, coupled between the phase detector and the digitally controlled oscillator, is used to generate a first phase error code based on the at least one phase error signal.

5. The phase-locked loop circuit as described in claim 4, characterized in that, Also includes: A frequency stabilizing circuit, coupled between the loop filter and the digitally controlled oscillator, is used to generate the at least one control code based on the first phase error code.

6. The phase-locked loop circuit as described in claim 4, characterized in that, Also includes: An integrator-derivative modulation circuit, coupled between the loop filter and the digitally controlled oscillator, is used to generate at least one control code based on the first phase error code.

7. The phase-locked loop circuit as described in claim 6, characterized in that, This digitally controlled oscillator includes: A current-to-digital-to-analog converter is used to convert the at least one control code into at least one control current; A low-pass filter is coupled to the current-to-digital-to-analog converter; and A current-controlled oscillator is used to be driven by the low-pass filter and to generate the output clock signal according to the at least one control current.

8. A phase detector for a phase-locked loop circuit, characterized in that, Include: A counter is used to generate an edge alignment correction feedback signal based on an output clock signal of the phase-locked loop circuit; An edge sampler is configured to generate, based on the first clock signal and the output clock signal, a first sample signal corresponding to the rising edge of the first clock signal of the phase-locked loop circuit, and a second sample signal corresponding to the rising edge lead-lag relationship between the rising edge of the first clock signal and a corresponding edge of the edge alignment correction feedback signal; and A phase quantization circuit, coupled to the counter and the edge sampler, is used to generate at least one phase error signal based on the first sample signal, the second sample signal and the edge alignment correction feedback signal.

9. The phase detector as claimed in claim 8, characterized in that, The edge sampler includes: A first type D flip-flop includes a first clock input, a first data input, and a first data output. A second D-type flip-flop includes a second clock input, a second data input, and a second data output. A third type D flip-flop includes a third clock input, a third data input, and a third data output. The first clock input terminal, the second clock input terminal, and the third clock input terminal are used to receive the output clock signal. The first data input terminal is used to receive the first clock signal. The first data output terminal is used to output a first data output signal to the second data input terminal. The second data output terminal is used to output a second data output signal to the third data input terminal. The third data output terminal is used to output a third data output signal. A judgment circuit is used to receive the second data output signal and the third data output signal to generate the first sampling signal; An inverter circuit is used to receive the output clock signal and generate an inverted output clock signal; A fourth D-type flip-flop, comprising a fourth clock input, a fourth data input, and a fourth data output; A fifth type D flip-flop includes a fifth clock input, a fifth data input, and a fifth data output. A sixth type D flip-flop, comprising a sixth clock input, a sixth data input, and a sixth data output; The fourth clock input terminal is used to receive the inverted output clock signal; the fifth and sixth clock input terminals are used to receive the output clock signal; the fourth data input terminal is used to receive the first clock signal; the fourth data output terminal is used to output a fourth data output signal to the fifth data input terminal; the fifth data output terminal is used to output a fifth data output signal to the sixth data input terminal; and the sixth data output terminal is used to output a sixth data output signal. An inverting and gate circuit is used to receive the first sampling signal and the sixth data output signal to generate the second sampling signal.

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