Successive approximation analog-to-digital converter

Abstract

The application discloses a gradually approaching analog-to-digital converter, comprising a first and a second capacitor array, a comparator, a conversion logic and a digital weight average module; the positive and negative phase input terminals of the comparator are coupled with a pair of differential input voltages through sampling switches respectively, and each outputs a pair of complementary n-bit comparison results in a conversion stage; the conversion logic encodes and converts the n-bit comparison results of the outputs of the comparator into 2 n -1 bit values; the digital weight average module generates a next beat pointer according to the n-bit comparison results and the current beat pointer, and generates a control signal for controlling the conversion switches of the plurality of capacitors in the first and second capacitor arrays according to the 2 n -1 bit values, wherein the switching states of the conversion switches of the plurality of capacitors in the first and second capacitor arrays are opposite. The application realizes effective average of capacitor mismatch error while keeping the comparator input common-mode voltage stable.

Description

Technical Field

[0001] This application relates to the field of digital-to-analog converter technology, and in particular to a successive approximation analog-to-digital converter. Background Technology

[0002] This invention relates to the field of analog-to-digital converter (ADC) technology, and more particularly to a successive approximation register analog-to-digital converter (SAR ADC). With the development of integrated circuit technology, SAR ADCs, due to their advantages of low power consumption, simple structure, fast conversion speed, and ease of digital implementation, are widely used in high-speed, high-precision data acquisition systems. SAR ADCs typically use capacitors and switch arrays to complete sampling and successive approximation conversion, where the matching accuracy of each capacitor directly determines the conversion accuracy and linearity of the ADC.

[0003] However, due to unavoidable process deviations in integrated circuit manufacturing, capacitor mismatch is inevitable. When the actual capacitor value deviates from the design value, the corresponding capacitor weights will be incorrect, causing the output voltage to deviate from the ideal value. This leads to a deterioration in the ADC's integral nonlinearity (INL) and differential nonlinearity (DNL), reducing the accuracy of analog-to-digital conversion. Especially for high-weight capacitors, due to their larger weights, even a small relative mismatch can cause a large absolute error, significantly impacting the overall ADC performance. Therefore, high-weight capacitor mismatch has become one of the important factors limiting the performance of high-resolution SAR ADCs.

[0004] To reduce the impact of capacitor mismatch on ADC performance, existing technologies typically employ Data Weighted Averaging (DWA). DWA works by cyclically distributing weights across multiple unit capacitors, averaging the mismatch error, which was originally concentrated on a single capacitor, over multiple conversion cycles. This transforms the deterministic error caused by mismatch into random noise, reducing the impact of capacitor mismatch on ADC linearity and conversion accuracy, and improving overall system performance.

[0005] On the other hand, to reduce the impact of comparator input common-mode voltage variations during successive approximation on comparator offset, capacitor nonlinearity, and conversion accuracy, existing SAR ADCs typically employ a capacitor-switching architecture based on common-mode voltage (VCM). This architecture, through a well-designed switching method for the capacitor array, keeps the common-mode voltage at the comparator input essentially constant during successive approximation, thereby reducing comparator input common-mode ripple and improving comparator decision accuracy. Therefore, the VCM-based capacitor switching method has become one of the mainstream architectures in medium-to-high resolution SAR ADCs.

[0006] To apply DWA technology to VCM-Based SAR ADCs, existing solutions typically split the high-order binary weighted capacitance into a thermometer coding structure. For example, the highest three bits are converted to thermometer code, and the highest two bits are grouped according to an averaging principle, connecting the initial state to the reference voltage and ground potential respectively to maintain a relatively constant common-mode voltage at the comparator input. Simultaneously, to ensure the DWA algorithm can continuously and cyclically allocate unit capacitance, the original 3-bit effective output needs to be expanded to a 4-bit output to meet the requirements of thermometer coding and cyclic scheduling.

[0007] However, the existing technologies still have the following shortcomings: On the one hand, since the highest two bits of the digital code cover most of the code values ​​in the entire conversion range, their output code accounts for about three-quarters of all output codes. Therefore, even with the splitting and averaging grouping method, the high-order capacitors will still cause a certain change in the comparator input common-mode voltage at different conversion stages, making it difficult to achieve a completely constant common-mode voltage throughout the entire successive approximation process, thus affecting the comparator's decision accuracy and the overall linearity of the ADC. On the other hand, after splitting the highest three bits into thermometer codes, in order to balance the common-mode hold and DWA cyclic averaging functions, the existing scheme needs to extend the original three-step high-order conversion to a four-step conversion, that is, add a comparison and capacitor switching operation, which increases the successive approximation period of the SAR ADC, prolongs the conversion time, and reduces the conversion rate, which is not conducive to the realization of high-speed SAR ADCs.

[0008] Existing DWA (Digital Wave Approach) solutions are mainly designed for ΣΔ ADCs or conventional SAR ADCs. For VCM-Based SAR ADCs, traditional DWA solutions are difficult to apply directly because the comparator input common-mode voltage needs to be kept constant. Therefore, how to effectively average capacitor mismatch errors in VCM-Based SAR ADCs while maintaining stable comparator input common-mode voltage and avoiding increased successive approximation steps and reduced conversion speed due to thermometer encoding extension has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0009] The purpose of this application is to provide a successive approximation analog-to-digital converter that effectively averages capacitor mismatch error while maintaining stable comparator input common-mode voltage and avoiding increased successive approximation steps and reduced conversion speed due to thermometer encoding extension.

[0010] In a first aspect, the present invention provides a successive approximation analog-to-digital converter, comprising a first capacitor array, a second capacitor array, a comparator, conversion logic, and a digital weight averaging module; The first capacitor array and the second capacitor array are respectively coupled to the positive and negative input terminals of the comparator and each includes multiple unit capacitors. One end of each unit capacitor in the first capacitor array is coupled to the positive input terminal of the comparator, and the other end is coupled to a common-mode voltage via a sampling switch. Furthermore, the other end of each unit capacitor in the first capacitor array is coupled to a reference voltage via a switching switch. Similarly, one end of each unit capacitor in the second capacitor array is coupled to the negative input terminal of the comparator, and the other end is coupled to the common-mode voltage via a sampling switch. Furthermore, the other end of each unit capacitor in the second capacitor array is coupled to the reference voltage via a switching switch. The number of unit capacitors is 2. n -1 item; The positive and negative input terminals of the comparator are coupled to a pair of differential input voltages through sampling switches, and during the conversion phase, the positive and negative output terminals of the comparator each output a pair of complementary n-bit comparison results. The conversion logic encodes the n-bit comparison result output from the positive or negative output of the comparator into 2... n -1 bit value; The digital weight averaging module controls the switching states of multiple unit capacitors in the first and second capacitor arrays. The digital weight averaging module generates a pointer for the next cycle based on the comparison result between the pointer of the current cycle and the n-bit value, and then uses the pointer of the current cycle and the 2-bit value as the basis for its calculation. n The -1 bit value generates a control signal for the switching of multiple capacitors in the first and second capacitor arrays in the next step, wherein the switching state of the switching of multiple capacitors in the first capacitor array is the opposite of the switching state of the switching of multiple capacitors in the second capacitor array.

[0011] In a preferred embodiment, the digital weight averaging module includes n groups of 2 n -1 two-to-one logic module, with corresponding connections between adjacent groups of two-to-one logic modules, and the value of the pointer of the current step is coupled to the first to nth groups of 2 modules in ascending order. n -1 of the two-to-one logic modules; for the nth group of 2 n-1 two-to-one logic modules, whose coupled pointer values ​​are 0, the 2 n The -1 bit value is correspondingly coupled to the nth group 2. n -1 two-to-one logic module, when its coupled pointer value is 1, the 2 n -1 bit value cyclically shifted by 2 n-1 Subsequently coupled to the nth group 2 n -1 binary-to-one logic module; for the k-th group 2 n -1 two-to-one logic modules, where when the coupled pointer value is 0, the first group of 2... n The output value of one of the two-to-one logic modules is correspondingly coupled to the two... n -1 two-to-one logic modules, where when the coupled pointer value is 1, the first group of 2... n -1 cyclically shifts the output value of a 2-to-1 multiplexer logic module by 2. k-1 Post-coupling of the 2 n -1 binary multiplexer logic modules, where k ranges from 1 to n-1.

[0012] In a preferred embodiment, the value of n is 3, the number of unit capacitors is 7, the comparator outputs a 3-bit comparison result, the conversion module encodes the 3-bit comparison result into a 7-bit value, and the pointer is 3 bits. The digital weight averaging module includes three groups of seven 2-to-1 logic modules. Adjacent groups of seven 2-to-1 logic modules are connected accordingly. The first bit of the pointer is coupled to each of the seven 2-to-1 logic modules in the first group, the second bit is coupled to each of the seven 2-to-1 logic modules in the second group, and the third bit is coupled to each of the seven 2-to-1 logic modules in the third group. When the third bit of the pointer is 0, the seven bits are coupled to the seven 2-to-1 logic modules in the third group. When the third bit of the pointer is 1, the seven bits are cyclically shifted by 4 and then coupled to the seven 2-to-1 logic modules in the third group. A logic module; when the second bit of the pointer is 0, the output values ​​of the 7 multiplexers in the 3rd group are coupled to the 7 multiplexers in the 2nd group; when the second bit of the pointer is 1, the output values ​​of the 7 multiplexers in the 3rd group are cyclically shifted by 2 and then coupled to the 7 multiplexers in the 2nd group; when the first bit of the pointer is 0, the output values ​​of the 7 multiplexers in the 2nd group are coupled to the 7 multiplexers in the 1st group; when the first bit of the pointer is 1, the output values ​​of the 7 multiplexers in the 2nd group are cyclically shifted by 1 and then coupled to the 7 multiplexers in the 1st group.

[0013] In a preferred embodiment, the pointer for the next beat is generated based on the comparison result between the pointer of the current beat and the n bits using the following formula: Dout+P i +Ri-1 =P i _new; where Dout is the value of the i-th bit of the n-bit comparison result, P i R is the value of the i-th bit in the pointer of the current shot. i-1 For Dout and P i Carry at the (i-1)th bit.

[0014] In a preferred embodiment, the value of n is 3, and the positive output of the comparator outputs a 3-bit comparison result Doutp<2:0>, where: Doutp <0> +P0+R2=P0_new; Doutp <1> +P1+R0=P1_new; Doutp <2> +P2+R1=P2_new; Where P0 to P2 are the values ​​of each bit in the pointer of the current beat, P0_new to P2_new are the values ​​of each bit in the pointer of the next beat, and R0 is Doutp. <1> With the carry-in of P1 at bit 0, R1 is Doutp <2> With the carry-in of P2 in the first bit, R2 is Doutp <0> The carry-over of P0 in the second position.

[0015] In a preferred embodiment, the n-bit comparison result output from the positive output terminal is encoded into 2... n -1 bit value includes: the n-bit comparison result increases by 1 for each bit from the least significant bit to the most significant bit, the 2 n The -1 bit value changes from 0 to 1 sequentially from the least significant bit to the most significant bit.

[0016] In a preferred embodiment, the value of n is 3, the number of unit capacitors is 7, and the positive output terminal of the comparator outputs a 3-bit comparison result; In the order from the least significant bit 000 to the most significant bit 111, the 3-bit comparison results are as follows: 000 corresponds to 0000000, 001 corresponds to 0000001, 010 corresponds to 0000011, 011 corresponds to 0000111, 100 corresponds to 0001111, 101 corresponds to 0011111, 110 corresponds to 0111111, and 111 corresponds to 1111111.

[0017] In a preferred embodiment, the negative output terminal outputs an n-bit comparison result encoding conversion of 2 n -1 bit value includes: the n-bit comparison result decreases by 1 from the least significant bit to the most significant bit, the 2 n The -1 bit value changes from 1 to 0 sequentially from the least significant bit to the most significant bit.

[0018] In a preferred embodiment, the value of n is 3, the number of unit capacitors is 7, and the negative output terminal of the comparator outputs a 3-bit comparison result; In the order from the least significant bit 111 to the most significant bit 000, the 3-bit comparison results are as follows: 111 corresponds to 1111111, 110 corresponds to 0111111, 101 corresponds to 0011111, 100 corresponds to 0001111, 011 corresponds to 0000111, 010 corresponds to 0000011, 001 corresponds to 0000001, and 000 corresponds to 0000000.

[0019] In a preferred embodiment, the initial value of each bit of the pointer is set to 0.

[0020] It should be understood that, within the scope of this invention, the above-described technical features of this invention and the technical features specifically described below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be described in detail here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. It should be understood that the accompanying drawings described below are merely some implementation examples of the present invention, and those skilled in the art can obtain other implementation examples based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a successive approximation analog-to-digital converter according to one embodiment of this application.

[0023] Figure 2 A schematic diagram of a 3-bit capacitor array is shown.

[0024] Figure 3 This is a schematic diagram of a successive approximation analog-to-digital converter according to one embodiment of this application, wherein the capacitor array has 3 conversion bits.

[0025] Figure 4 This is a logic diagram for generating a changeover switch control signal according to one embodiment of this application.

[0026] Figure 5 Simulation results using a 3-bit capacitor array and a 7-bit unit capacitor in this embodiment are shown. Detailed Implementation

[0027] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] Through extensive and in-depth research, the inventors have proposed a successive approximation analog-to-digital converter with capacitor mismatch calibration, which splits the n-bit binary capacitors in the capacitor array into 2... n -1 bit unit capacitance, during the conversion stage, the n-bit comparison result of the comparator is encoded into 2. n -1 bit value, based on the pointer of the current beat and 2 n -1 bit value generation control capacitor array 2 n The switching state of the -1 bit unit capacitor switching switch is used to effectively average the capacitor mismatch error, improve the linearity and accuracy of the analog-to-digital converter, and at the same time keep the comparator input common-mode voltage stable.

[0029] This application has at least the following beneficial effects and advantages: (1) Using a VCM-based SAR ADC can keep the common mode of the comparator input constant, which reduces the design difficulty of the comparator; (2) The pointer to the next loop can be generated by using the conversion output of each loop and the pointer of the current loop; (3) The pointer of the digital weight averaging module can be reused in the fully differential SAR ADC, which can reduce the logic complexity of the digital weight averaging module.

[0030] (4) A ring-type shift logic is used to connect the comparator output and the pointer to realize the function of the digital weight averaging module; (5) The use of digital weighted averaging (DWA) technology can effectively improve the accuracy of the ADC. When DWA is turned off, the low-frequency spectrum is -20dB, while when DWA is turned on, the low-frequency noise is -40dB. Overall, the performance is significantly improved by nearly 3 bits.

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0032] One embodiment of this application relates to a successive approximation analog-to-digital converter (SAR ADC), the block diagram of which is shown below. Figure 1As shown, the approximation analog-to-digital converter includes a first capacitor array 101, a second capacitor array 102, a comparator 103, conversion logic 104, and a digital weighted averaging (DWA) module 105. It should be noted that the approximation analog-to-digital converter of this application also includes a clock generation circuit (not shown in the figure), which generates a clock signal CLK for the comparator 103.

[0033] The first capacitor array 101 is coupled to the non-inverting input terminal VP of the comparator 103 and includes multiple unit capacitors. One end of each unit capacitor in the first capacitor array 101 is coupled to the non-inverting input terminal VP of the comparator 103, and the other end is coupled to the common-mode voltage VCM through a sampling switch (not shown in the figure). Furthermore, the other end of each unit capacitor in the first capacitor array 101 is also coupled to a reference voltage, such as a positive reference voltage Vrefp or a negative reference voltage Vrefn, through a switching switch (not shown in the figure). The second capacitor array 102 is coupled to the non-inverting input terminal VN of the comparator 103 and includes multiple unit capacitors. One end of each unit capacitor in the second capacitor array 102 is coupled to the non-inverting input terminal VN of the comparator 103, and the other end is coupled to the common-mode voltage VCM through a sampling switch. Furthermore, the other end of each unit capacitor in the second capacitor array 102 is also coupled to a reference voltage, such as a positive reference voltage Vrefp or a negative reference voltage Vrefn, through a switching switch (not shown in the figure). The number of unit capacitors in the second capacitor array 102 of the first capacitor array 101 is 2. n -1. Here, n is the number of bits in the digital-to-analog converter of the capacitor array. For example, n can be 3 or higher, such as 3 to 8, and the specific value is set according to the actual scenario. It should be noted that unit capacitance refers to a capacitor with a capacitance value of one unit C. The positive input terminal VP and the negative input terminal VN of comparator 103 are coupled to a pair of differential input voltages through sampling switches. The positive input voltage VIP is coupled to the positive input terminal VP, and the negative input voltage VIN is coupled to the negative input terminal VN. During the sampling phase, the sampling switch is closed and the switching switch is open. One end of each unit capacitor in the first capacitor array 101 is coupled to the positive input voltage VIP, and one end of each unit capacitor in the second capacitor array 102 is coupled to the negative input voltage VIN. The other end of each unit capacitor in the first capacitor array 101 and the second capacitor array 102 is coupled to the common-mode voltage VCM. The capacitor array completes the sampling of the input voltage. After sampling, the sampling switch is opened, and the sampled charge is retained in the capacitor array. Then, the switching phase begins. The control capacitor array switches the connection relationship between each capacitor and the reference voltage sequentially from the most significant bit to the least significant bit. By changing the redistribution of the charge generated by the capacitor array, the output voltage of the capacitor array is successively approximated. After each capacitor switching, the comparator compares the input signal with the output voltage of the capacitor array and determines the current bit code based on the comparison result. Repeat the above process until all bits have been converted, and finally output the digital code.

[0034] During the conversion phase, the positive and negative outputs of comparator 103 each output a pair of complementary n-bit comparison results, which are Doutp respectively. <n-1:0>and Douton <n-1:0>To simplify the diagram, Dout is used uniformly. <n-1:0>The conversion logic 104 encodes the n-bit comparison result output from the positive or negative output of comparator 103 into 2... n -1 bit value. In one embodiment, the n-bit comparison result output from the positive output is encoded into 2. n -1 bit value includes: n bits. The comparison result increases by 1 or 2 bits from the least significant bit to the most significant bit. n The -1 bit value changes sequentially from 0 to 1 from the least significant bit to the most significant bit. The negative output terminal outputs the n-bit comparison result encoded in 2. n -1 bit value includes: n bits. The comparison result decreases by 1 or 2 bits from the least significant bit to the most significant bit. n The -1 bit value changes from 1 to 0 sequentially from the least significant bit to the most significant bit.

[0035] The digital weight averaging module 105 controls the switching states of multiple unit capacitors in the first capacitor array 101 and the second capacitor array 102. Specifically, the digital weight averaging module 105 generates the pointer for the next frame based on the comparison result between the pointer of the current frame and n bits, and calculates the pointer for the next frame based on the comparison result between the pointer of the current frame and 2 bits. n The -1 bit value generates the control signal for the switching of multiple capacitors in the first capacitor array 101 and the second capacitor array 102 in the next cycle. The switching states of the multiple capacitors in the first capacitor array 101 are opposite to those of the multiple capacitors in the second capacitor array 102. In this embodiment, the conversion logic 104 and the digital weight averaging module 105 can obtain the control signal for the switching of the first capacitor array 101 or the second capacitor array 102 based on the positive or negative output of the comparator 103, and then invert the switching signal to obtain the control signal for the switching of the other capacitor array. It is understood that in other embodiments, two conversion logics and two digital weight averaging modules may be included. One conversion logic converts and encodes the positive output of the comparator 103 and controls the switching of the first capacitor array 101 through one of the digital weight averaging modules; the other conversion logic converts and encodes the negative output of the comparator 103 and controls the switching of the second capacitor array 102 through another digital weight averaging module.

[0036] In one embodiment, the pointer for the next clock cycle is generated based on the comparison result between the pointer of the current clock cycle and n bits using the following formula: Dout + P i +R i-1 =P i _new; where Dout is the value of the i-th bit of the n-bit comparison result, P i R is the value of the i-th bit in the pointer of the current shot. i-1 For Dout and P i The carry at the (i-1)th bit. In this embodiment, the initial value of the pointer is set to 0 for each bit.

[0037] Furthermore, the digital weight averaging module 105 includes n groups of 2 n -1 MUX2T1 (two-to-one) logic module, with corresponding connections between adjacent groups of two-to-one logic modules, that is, the nth group 2 n -1 two-to-one logic module and the (n-1)th group of 2 n -1 two-to-one multiplexer logic modules are connected one-to-one, and the (n-1)th group 2 n -1 binary multiplex logic module and the (n-2)th group of 2 n - One binary-to-one multiplexer logic module is connected in a one-to-one correspondence, and so on. The value of the pointer of the current step is coupled to the first to nth groups of 2 in ascending order. n Each of the -1 binary multiplexer logic modules, for example, the 0th bit of the pointer to the current beat is coupled to the first group of 2. n In each of the -1 two-to-one logic modules, the first bit is coupled to the second group of 2. n -1 for each of the two-to-one multiplexer logic modules, and so on. For the nth group of 2 n -1 2-to-1 multiplexer logic module, whose coupled pointer value is 0, the conversion logic output is 2. n The -1 bit value is correspondingly coupled to the nth group 2. n -1 2-to-1 logic module, whose coupled pointer value is 1, 2 n -1 bit value cyclically shifted by 2 n-1 Subsequently coupled to the nth group 2 n -1 binary multiplexer logic module. For the k-th group 2 n -1 two-to-one logic modules, where when the coupled pointer value is 0, the first group of 2... n The output value of one 2-to-1 multiplexer logic module is correspondingly coupled to two... n -1 two-to-one logic modules, where when the coupled pointer value is 1, the first group of 2... n -1 cyclically shifts the output value of a 2-to-1 multiplexer logic module by 2. k-1 Post-coupling 2 n -1 two-to-one logic module, where k ranges from 1 to n-1. In this embodiment, the two-to-one logic module uses a ring shift logic connection to the comparator output of 2 n -1 bit value and pointer.

[0038] This invention splits an n-bit binary capacitor into 2 n -1 bit unit capacitance, combined with comparison result encoding and pointer cyclic update, realizes dynamic rotation of unit capacitance, while maintaining the stability of VCM-Based SAR ADC comparator input common mode, and realizes high-bit capacitance mismatch averaging without increasing the number of comparisons.

[0039] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0040] This article uses an example with n=3 as an example. The following explanation uses the high 3 bits of a fully differential SAR ADC as an example. Using standard binary weights as an example, the original circuit is as follows: Figure 2 As shown, the capacitors corresponding to the three bits are 4C, 2C, and C, respectively. During sampling, the sampling switch Φs is turned on, and the input voltages VP and VN are connected to the input terminals VIP and VIN of comparator 103, respectively, for the first comparison. From the start of the conversion, the mismatch of the capacitors in each bit will cause weighting errors, especially the higher bits which have larger weights and are prone to causing larger errors, resulting in a loss of accuracy. To solve this problem, this invention splits the capacitors of the higher 3 bits into... Figure 3 The capacitor array shown.

[0041] like Figure 3 As shown, Figure 2 The three-bit capacitors 4C, 2C, and C are split into seven-bit capacitors, all with a capacitance value of C. Similarly, the number of switching switches increases from s1a / s1b, s2a / s2b, s3a / s3b to Φ1a / Φ1b, Φ2a / Φ2b, Φ3a / Φ3b, Φ4a / Φ4b, Φ5a / Φ5b, Φ6a / Φ6b, and Φ7a / Φ7b. In this example, with n equal to 3 and seven unit capacitors, comparator 103 outputs a 3-bit comparison result, which the conversion module encodes into a 7-bit value.

[0042] After disassembling the capacitors and switches, DWA conversion can be implemented in several ways. One method is to use a 7-bit thermometer code for DWA conversion. Another method, without increasing conversion time, involves grouping the seven unit capacitors (C) and their corresponding switches to achieve 4C, 2C, and C conversions. This case study uses the grouping method for illustration. Since the seven unit capacitors form 4C, 2C, and 1C combinations, the total capacitance weight for each conversion state remains consistent with the original 3-bit binary weight. Only the physical location of the unit capacitors is changed, thus not affecting the ideal conversion relationship of the capacitor array, and achieving unit capacitance mismatch averaging.

[0043] for Figures 2 to 3 The main purpose is to split the capacitors at the higher positions. Figures 2 to 3 The conversion logic 104 and the digital weight averaging module 105 are also added, which are the core points of this invention. First, a 3-bit rotatable pointer is generated by the following expressions (1)-(3).

[0044] Doutp <0> +P0+R2=P0_new (1) Doutp <1> +P1+R0=P1_new (2) Doutp <2> +P2+R1=P2_new(3) Where P2, P1, and P0 are the values ​​of each bit in the pointer of the current beat, PP2_new, P1_new, and P0_new are the values ​​of each bit in the pointer of the next beat, and R0 is Doutp. <1> With the carry-in of P1 at bit 0, R1 is Doutp <2> With the carry-in of P2 in the first bit, R2 is Doutp <0> And the carry-in of P0 in the second bit. In this embodiment, the truth table can be listed as shown in Table 1 below. In the table, Doutp<2:0> is the 3-bit output of the current SAR ADC. Note that the pointer at the first conversion when the SAR ADC is enabled each time needs to be fixed to a fixed value (e.g., 000). Table 1 Then, in this embodiment, it is necessary to select which four unit capacitors C form the highest-order capacitor 4C, which two unit capacitors C form the capacitor 2C, and which unit capacitor C is a single C capacitor. The capacitor switches are selected and encoded by the high 3 bits of the comparator 103 output. The output Doutp<2:0> of the comparator 103 can be encoded as Voutp<7:1>, as shown in Table 2 below. Table 2 The positive output of comparator 103 outputs the 7-bit value Voutp<7:1> converted from the 3-bit comparison result Doutp<2:0>. In order from the low bit 000 to the high bit 111, the 3-bit comparison result is encoded as follows: 000 corresponds to 0000000, 001 corresponds to 0000001, 010 corresponds to 0000011, 011 corresponds to 0000111, 100 corresponds to 0001111, 101 corresponds to 0011111, 110 corresponds to 0111111, and 111 corresponds to 1111111.

[0045] In order for the negative input to share the pointer of the positive input, and for the switch of the negative input to be completely opposite to that of the positive input when switching, the output of the negative input can be encoded as shown in Table 3 below. The output of comparator 103, Doutn<2:0>, can be encoded as Voutn<7:1>. Table 3 Specifically, the negative output of comparator 103 outputs the 7-bit value Voutn<7:1> converted from the 3-bit comparison result Doutn<2:0>. In order from the low bit 111 to the high bit 000, the 111 in the 3-bit comparison result is encoded as 1111111, 110 is encoded as 0111111, 101 is encoded as 0011111, 100 is encoded as 0001111, 011 is encoded as 0000111, 010 is encoded as 0000011, 001 is encoded as 0000001, and 000 is encoded as 0000000.

[0046] Then determine the connection between the current pointer and the current result. For example... Figure 4 As shown, VOUT<7:1> is the output of comparator 103, P2, P1, and P0 are pointers for the current phase, MUX2T1 is a 2-to-1 multiplexer, and the outputs Φ7, Φ6, Φ5, Φ4, Φ3, Φ2, and Φ1 are the control signals for the switching switches. Note that this example uses VOUT<7:1> as the output of the positive input of comparator 103; Φ7, Φ6, Φ5, Φ4, Φ3, Φ2, and Φ1 are the control signals for the switching switches corresponding to each unit capacitor in the first capacitor array. The positive and negative outputs of the fully differential SAR ADC need to be added separately. Figure 4 The logic units generate logic switches that control the upper and lower symmetrical sides respectively.

[0047] The digital weight averaging module 105 includes three groups of seven 2-to-1 logic modules. The seven 2-to-1 logic modules in adjacent groups are connected accordingly. The first bit of the pointer is coupled to each of the seven 2-to-1 logic modules in the first group, the second bit is coupled to each of the seven 2-to-1 logic modules in the second group, and the third bit is coupled to each of the seven 2-to-1 logic modules in the third group. When the third bit of the pointer is 0, the seven bits are coupled to the corresponding seven 2-to-1 logic modules in the third group; when the third bit of the pointer is 1, the seven bits are cyclically shifted by 4 and then coupled to the corresponding seven 2-to-1 logic modules in the third group. When the second bit of the pointer is 0, the output values ​​of the 7 multiplexers in the 3rd group are coupled to the 7 multiplexers in the 2nd group. When the second bit of the pointer is 1, the output values ​​of the 7 multiplexers in the 3rd group are cyclically shifted by 2 and then coupled to the 7 multiplexers in the 2nd group. When the first bit of the pointer is 0, the output values ​​of the 7 multiplexers in the 2nd group are coupled to the 7 multiplexers in the 1st group. When the first bit of the pointer is 1, the output values ​​of the 7 multiplexers in the 2nd group are cyclically shifted by 1 and then coupled to the 7 multiplexers in the 1st group.

[0048] Simulation results of DWA effect based on noise-shaping SAR ADC are as follows: Figure 5 As shown. Figure 5 The left image shows the effect of disabling DWA, while the right image shows the effect of enabling DWA. It's clear that enabling DWA significantly reduces low-frequency noise. Precision has been improved from 10.16 bits to 13.11 bits.

[0049] The term "coupled to" and its derivatives may be used in this document. "Coupled" can mean two or more elements in direct physical or electrical contact. However, "coupled" can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.

[0050] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded.

[0051] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A successive approximation analog-to-digital converter, characterized in that, It includes a first capacitor array, a second capacitor array, a comparator, conversion logic, and a digital weight averaging module; The first capacitor array and the second capacitor array are respectively coupled to the positive and negative input terminals of the comparator and each includes multiple unit capacitors. One end of each unit capacitor in the first capacitor array is coupled to the positive input terminal of the comparator, and the other end is coupled to a common-mode voltage via a sampling switch. Furthermore, the other end of each unit capacitor in the first capacitor array is coupled to a reference voltage via a switching switch. Similarly, one end of each unit capacitor in the second capacitor array is coupled to the negative input terminal of the comparator, and the other end is coupled to the common-mode voltage via a sampling switch. Furthermore, the other end of each unit capacitor in the second capacitor array is coupled to the reference voltage via a switching switch. The number of unit capacitors is 2. n -1 item; The positive and negative input terminals of the comparator are coupled to a pair of differential input voltages through sampling switches, and during the conversion phase, the positive and negative output terminals of the comparator each output a pair of complementary n-bit comparison results. The conversion logic encodes the n-bit comparison result output from the positive or negative output of the comparator into 2... n -1 bit value; The digital weight averaging module controls the switching states of multiple unit capacitors in the first and second capacitor arrays. The digital weight averaging module generates a pointer for the next cycle based on the comparison result between the pointer of the current cycle and the n-bit value, and then uses the pointer of the current cycle and the 2-bit value as the basis for its calculation. n The -1 bit value generates a control signal for the switching of multiple capacitors in the first and second capacitor arrays in the next step, wherein the switching state of the switching of multiple capacitors in the first capacitor array is the opposite of the switching state of the switching of multiple capacitors in the second capacitor array.

2. The analog-to-digital converter as described in claim 1, characterized in that, The digital weight averaging module includes n groups 2 n -1 two-to-one logic module, with corresponding connections between adjacent groups of two-to-one logic modules, and the value of the pointer of the current step is coupled to the first to nth groups of 2 modules in ascending order. n -1 of the two-to-one logic modules; for the nth group of 2 n -1 two-to-one logic modules, whose coupled pointer values ​​are 0, the 2 n The -1 bit value is correspondingly coupled to the nth group 2. n -1 two-to-one logic module, when its coupled pointer value is 1, the 2 n -1 bit value cyclically shifted by 2 n-1 Subsequently coupled to the nth group 2 n -1 binary-to-one logic module; for the k-th group 2 n -1 two-to-one logic modules, where when the coupled pointer value is 0, the first group of 2... n The output value of one of the two-to-one logic modules is correspondingly coupled to the two... n -1 two-to-one logic modules, where when the coupled pointer value is 1, the first group of 2... n -1 cyclically shifts the output value of a 2-to-1 multiplexer logic module by 2. k-1 Post-coupling of the 2 n -1 binary multiplexer logic modules, where k ranges from 1 to n-1.

3. The analog-to-digital converter as described in claim 2, characterized in that, The value of n is 3, the number of unit capacitors is 7, the comparator outputs a 3-bit comparison result, the conversion module encodes the 3-bit comparison result into a 7-bit value, and the pointer is 3 bits. The digital weight averaging module includes three groups of seven 2-to-1 logic modules. Adjacent groups of seven 2-to-1 logic modules are connected accordingly. The first bit of the pointer is coupled to each of the seven 2-to-1 logic modules in the first group, the second bit is coupled to each of the seven 2-to-1 logic modules in the second group, and the third bit is coupled to each of the seven 2-to-1 logic modules in the third group. When the third bit of the pointer is 0, the seven bits are coupled to the seven 2-to-1 logic modules in the third group. When the third bit of the pointer is 1, the seven bits are cyclically shifted by 4 and then coupled to the seven 2-to-1 logic modules in the third group. A logic module; when the second bit of the pointer is 0, the output values ​​of the 7 multiplexers in the 3rd group are coupled to the 7 multiplexers in the 2nd group; when the second bit of the pointer is 1, the output values ​​of the 7 multiplexers in the 3rd group are cyclically shifted by 2 and then coupled to the 7 multiplexers in the 2nd group; when the first bit of the pointer is 0, the output values ​​of the 7 multiplexers in the 2nd group are coupled to the 7 multiplexers in the 1st group; when the first bit of the pointer is 1, the output values ​​of the 7 multiplexers in the 2nd group are cyclically shifted by 1 and then coupled to the 7 multiplexers in the 1st group.

4. The analog-to-digital converter as described in claim 1, characterized in that, The pointer for the next beat is generated based on the comparison result between the pointer of the current beat and the n bits using the following formula: Dout+P i +R i-1 =P i _new; where Dout is the value of the i-th bit of the n-bit comparison result, P i R is the value of the i-th bit in the pointer of the current shot. i-1 For Dout and P i Carry at the (i-1)th bit.

5. The analog-to-digital converter as described in claim 4, characterized in that, The value of n is 3, and the positive output of the comparator outputs a 3-bit comparison result Doutp<2:0>, where: Doutp <0> +P0+R2=P0_new; Doutp <1> +P1+R0=P1_new; Doutp <2> +P2+R1=P2_new; Where P0 to P2 are the values ​​of each bit in the pointer of the current beat, P0_new to P2_new are the values ​​of each bit in the pointer of the next beat, and R0 is Doutp. <1> With the carry-in of P1 at bit 0, R1 is Doutp <2> With the carry-in of P2 in the first bit, R2 is Doutp <0> The carry-over of P0 in the second position.

6. The analog-to-digital converter as described in claim 1, characterized in that, The n-bit comparison result output from the positive output terminal is encoded and converted into 2. n -1 bit value includes: the n-bit comparison result increases by 1 for each bit from the least significant bit to the most significant bit, the 2 n The -1 bit value changes from 0 to 1 sequentially from the least significant bit to the most significant bit.

7. The analog-to-digital converter as described in claim 6, characterized in that, The value of n is 3, the number of unit capacitors is 7, and the positive output of the comparator outputs a 3-bit comparison result; In the order from the least significant bit 000 to the most significant bit 111, the 3-bit comparison results are as follows: 000 corresponds to 0000000, 001 corresponds to 0000001, 010 corresponds to 0000011, 011 corresponds to 0000111, 100 corresponds to 0001111, 101 corresponds to 0011111, 110 corresponds to 0111111, and 111 corresponds to 1111111.

8. The analog-to-digital converter as described in claim 1, characterized in that, The negative output terminal outputs an n-bit comparison result encoding conversion 2. n -1 bit value includes: the n-bit comparison result decreases by 1 from the least significant bit to the most significant bit, the 2 n The -1 bit value changes from 1 to 0 sequentially from the least significant bit to the most significant bit.

9. The analog-to-digital converter as described in claim 8, characterized in that, The value of n is 3, the number of unit capacitors is 7, and the negative output terminal of the comparator outputs a 3-bit comparison result; In the order from the least significant bit 111 to the most significant bit 000, the 3-bit comparison results are as follows: 111 corresponds to 1111111, 110 corresponds to 0111111, 101 corresponds to 0011111, 100 corresponds to 0001111, 011 corresponds to 0000111, 010 corresponds to 0000011, 001 corresponds to 0000001, and 000 corresponds to 0000000.

10. The analog-to-digital converter as claimed in claim 1, characterized in that, Each bit of the pointer is initially set to 0.

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