Precharge circuit with differential input and output

Abstract

The present disclosure relates to a pre-charge circuit with differential input and output. An electronic circuit is described herein. In one embodiment, the circuit includes a differential input including a first input node and a second input node and coupled to an input capacitor during operation, a differential output including a first output node and a second output node and coupled to an output capacitor during operation, a first switch coupled between the first input node and the first output node, a pre-charge circuit configured to inject charge at the first output node, and a control circuit configured to turn on and off the first switch and to control the pre-charge circuit to inject charge at the first output node when the first switch is off. The circuit can be used to pre-charge an input capacitance of another circuit coupled to the differential output.

Description

Technical Field

[0001] This invention relates to the field of voltage measurement, and in particular to voltage monitoring using analog-to-digital converters (ADCs). Background Technology

[0002] Voltage measurement has several requirements besides accuracy. One challenge is electromagnetic interference (EMI), which can distort voltage measurements. This problem is typically addressed by providing filters to suppress high-frequency interference. In the case of switched-capacitor ADCs (such as successive approximation ADCs, SAR ADCs), sampling is accomplished using one or more buffer capacitors (hereinafter referred to as sampling capacitors) and a switch. When using a switched-capacitor ADC, a capacitive current (displacement current) is generated during the sampling phase. This capacitive current depends on the size of the sampling capacitor, the voltage difference between the input voltage and the voltage across the sampling capacitor at the start of the sampling process, and the sampling frequency.

[0003] To avoid unwanted aliasing and suppress interference (e.g., caused by electromagnetic interference), a filter can be implemented before the sampling capacitor and the switch. This filter can be placed on the chip or implemented as external circuitry and typically includes a filter capacitor. External filters generally result in additional cost for external components and additional space on the printed circuit board (PCB). Furthermore, the capacitance of the external filter must be large enough to minimize the error introduced during the sampling phase by charging the sampling capacitor, as charge is transferred from the filter capacitor to the sampling capacitor during the sampling phase. Internal (on-chip) filters need to maintain a small area, thus requiring a small filter capacitor. A buffer can be placed after the filter to prevent charge from being drawn from the filter capacitor to charge the sampling capacitor. Buffers need to meet sampling speed requirements and consume power and chip area. They can also introduce offset and noise and reduce measurement accuracy.

[0004] A technique is needed that allows for small (internal) filters while maintaining full measurement accuracy, without the aforementioned drawbacks. Summary of the Invention

[0005] This document describes an electronic circuit. In one embodiment, the circuit includes: a differential input, including a first input node and a second input node, and coupled to an input capacitor during operation; a differential output, including a first output node and a second output node, and coupled to an output capacitor during operation; a first switch coupled between the first input node and the first output node; a pre-charge circuit configured to inject charge at the first output node; and a control circuit configured to turn the first switch on and off, and to control the pre-charge circuit to inject charge at the first output node when the first switch is off. This circuit can be used to pre-charge the input capacitor of another circuit coupled to the differential output.

[0006] According to one embodiment, a corresponding pre-charging method includes: turning on and off a first switch coupled between a first input node and a first output node, wherein the first input node and the second input node form a differential input coupled to an input capacitor, and wherein the first output node and the second output node form a differential output coupled to an output capacitor. The method further includes controlling a pre-charging circuit to inject charge at the first output node when the first switch is off. Attached Figure Description

[0007] The embodiments described herein can be better understood in conjunction with the following description and accompanying drawings. The components in the drawings are not necessarily drawn to scale, but rather are intended to illustrate the principles of the embodiments. Furthermore, in the drawings, the same reference numerals denote corresponding parts. In the drawings:

[0008] Figure 1 The diagram illustrates the basic structure of an electronic circuit used to sample an input voltage, including a circuit for pre-charging the sampling capacitor (pre-charging circuit).

[0009] Figure 2 An embodiment of an electronic circuit with a first charge pump and logic control circuitry is illustrated.

[0010] Figure 3 The diagram shows Figure 2 The switching scheme of the circuit and the corresponding voltage signal curve.

[0011] Figure 4 A more detailed illustration is provided. Figure 2 Examples.

[0012] Figure 5 The diagram shows Figure 2 Modification of the example.

[0013] Figure 6 The diagram shows Figure 5 The switching scheme of the circuit and the corresponding voltage signal curve.

[0014] Figure 7The diagram shows Figure 5 The circuit provides alternative switching schemes and corresponding voltage signal curves.

[0015] Figure 8 The diagram shows Figure 5 Modification of the example.

[0016] Figure 9 The diagram shows Figure 1 Modification of the example.

[0017] Figure 10 This is a flowchart illustrating a method that can be used to precharge a capacitor. Detailed Implementation

[0018] A switched-capacitor ADC includes a sample-and-hold circuit with a sampling capacitor and a switch. At the beginning of the sampling phase, the sampling capacitor is coupled (via the switch) to the input node that provides the input voltage. If the input voltage is provided by a filter with a filter capacitor (i.e., if the input node of the sample-and-hold circuit is connected to the filter output), charge may transfer from the filter capacitor to the sampling capacitor during the sampling phase, which will affect the measurement. To prevent or reduce this charge transfer, the sampling capacitor can be pre-charged before the sampling phase. For this purpose, a pre-charge buffer can provide charge to the sampling capacitor in the first phase, and then in the second phase, the sampling capacitor is coupled to the input node. In the second phase, the filter capacitor only needs to provide a much smaller amount of charge to the sampling capacitor (ideally zero).

[0019] In many applications, differential voltage measurements are required. For example, when measuring the voltage drop across a high-side power transistor, it is necessary to measure a relatively low differential voltage (e.g., less than 1 V), while the common-mode voltage may be relatively large (e.g., -20 V to 60 V).

[0020] Figure 1 The diagram illustrates the basic structure of an electronic circuit 10, including a pre-charge circuit 100. The electronic circuit 10 includes a differential input formed by a first input node INP and a second input node INN. In this context, "differential input" means that the two input nodes INP and INN are floating (ungrounded) input nodes. The information sought is the differential input voltage V. INP -V INN The common-mode voltage (e.g., defined as (V)) INP +V INN (2) This could be much larger (on the order of magnitude) than the differential voltage and vary considerably. The differential input can be coupled to filter 50, which can be composed of a filter with an input resistance R. F and filter capacitor C FThe filter 50 is composed of an RC circuit. The input of filter 50 can be coupled to an electronic component, such as MOSFET T. In the depicted example, filter 50 is coupled to the load path of MOSFET T; therefore, the drain-source voltage V... DS This is the (differential) input voltage "seen" by filter 50. Therefore, in this example, the filtered input voltage is the differential input voltage applied to the differential inputs (nodes INP, INN) of electronic circuit 10. It should be understood that the concepts described herein are not limited to MOSFETs or other types of electronic switches such as bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), or junction field-effect transistors (JEFTs). In practice, transistor T can also be replaced by other electronic components, such as (shunt) resistors.

[0021] Electronic circuit 10 also includes a differential output formed by a first output node OUTP and a second output node OUTN. In this context, "differential output" means that the two output nodes OUTP and OUTN are floating (ungrounded) output nodes. In the example described herein, the second input node INN and the second output node OUTN can be connected by a low-impedance line. The first input node INP and the first output node OUTP can be connected via a first switch SW. S Coupling, first switch SW S This can be implemented, for example, by a MOSFET. The differential output of electronic circuit 10 is coupled to an output capacitor, which, in the depicted example, is a first output capacitor C coupled to the first output node OUTP. SP and the second output capacitor C coupled to the second output node OUTN SN Formation. Another switch SW can be provided between the first output node OUTP and the second output node OUTN. C (Hereinafter referred to as the changeover switch). First output capacitor C SP Second output capacitor C SN and changeover switch SW C It can be part of an analog-to-digital converter (ADC). Where the first and / or second output capacitor C... SP and C SN It forms the input capacitor of the analog-to-digital converter (and is also the output capacitor of the electronic circuit 10).

[0022] Figure 1 The electronic circuit 10 depicted also includes a pre-charge circuit 100 coupled to a first input node INP and a first output node OUTP. The pre-charge circuit 100 is configured to provide a charging current i to the first output node OUTP. CH (Thus injecting charge into it). Figure 1The electronic circuit 10 also includes a control circuit 300, which is configured to control the switch SW. S And the operation of the pre-charge circuit 100. The control circuit 300 is configured to operate via the first control signal P. SWS Turning the first switch SW on and off S First switch SW S It can be a transistor (e.g., a MOSFET), and may require suitable driver circuitry to turn the first switch SW on and off. S The same applies to the other switches described later in this document. It should be understood that driver circuitry may also be required for these switches to reliably turn them on and off. Since suitable driver circuitry is known in itself, it will not be discussed in detail here. Control circuitry 300 is also configured to operate via a second control signal P. LC Control the pre-charge circuit 100 to provide charging current i to the first output node OUTP CH (That is, injecting charge into it). The control circuit 300 can also be configured to be controlled via a third control signal P. SWC On / off selector switch SW C .

[0023] In one example, control circuitry 300 can be implemented as a state machine with dedicated logic elements, configured to perform the functions described above. In some examples, control circuitry 300 can be implemented using one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuitry, and any combination of these components. In some examples, the controller may include memory, which may be random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, including executable instructions for causing one or more processors to perform actions attributed to them. Therefore, the functionality provided by control circuitry 300 can be implemented using hardware, software, or a combination thereof. Control circuitry 300 or a portion thereof may also be part of the control unit of the ADC.

[0024] Figure 2 The circuit is basically the same as Figure 1 The same, but in more detail, example of the pre-charge circuit 100 is shown. For simplicity of illustration, Figure 2 The control circuit 300 is not shown. Figure 2 The pre-charge circuit 100 depicted includes a first charge pump 20, a control logic circuit 30, and a second switch SW. CH The first charge pump 20 can be connected via the second switch SW. CHThe first charge pump 20 is coupled to the first output node OUTP. It is also coupled to the second input node INN and has a clock input for receiving the clock signal CLK. The clock signal CLK can be provided by an external circuit device. Control logic circuitry 30 is coupled to the first input node INP and the first output node OUTP. Furthermore, control logic circuitry 30 is configured to communicate via a fourth control signal P. SWCH To turn the second switch SW on and off CH When the second switch SW CH When closed, the first charge pump 20 can inject charge at the first output node OUTP in each cycle of the clock signal CLK. In other words, the second switch SW CH The first charge pump 20 is activated or deactivated. The control logic circuit 30 is also configured to receive a second control signal P. LC This signal triggers the pre-charge process (see...) Figure 3 In an alternative example, charge pump 20 is activated and deactivated by enabling and disabling the clock signal CLK it receives. In this case, switch SW may not be required. CH The control logic circuit 30 can also be part of the control circuit 300, but... Figure 2 For ease of understanding, they are depicted as individual elements.

[0025] When using a switched capacitor ADC to measure differential voltage (e.g., V), INP -V INN When performing the measurement, it is done in two stages. First, in the sampling stage, the sampling capacitor (e.g., C) is used. SP C SN The differential voltage is sampled (using a sampling switch), meaning that the differential voltage is "held" (stored) at the sampling moment by means of a sampling capacitor (hence the name sample and hold circuit). Next, in the conversion phase, the sampled differential voltage is converted into a digital signal representing that sampled differential voltage. Figure 2 In the example, during the sampling phase, the first input voltage V at the first input node INP is... INP via the first output capacitor C SP The sampled second input voltage V at the second input node INN INN via the second output capacitor C SN Sampled. Essentially, the differential voltage V INP -V INN From capacitor C SP and C SN Storage. During the sampling phase, the first switch SW S Close so that the first output capacitor C SP Connect to the first input node INP to receive the first input voltage V INPHowever, because the switch SW is closed immediately at the start of the sampling phase... S Measurement errors will be introduced due to the above reasons, therefore, in the first output capacitor C SP The first switch SW may not close until pre-charging is complete. S At the start of the transition phase, the first switch SW... S Disconnect, changeover switch SW C The circuit closes, and analog-to-digital conversion begins. It should be noted that various analog-to-digital conversion techniques are known in themselves, and therefore will not be discussed further in this paper. As mentioned earlier, the pre-charge concept described in this paper may be useful, at least when used in conjunction with analog-to-digital converters having input capacitors that store the voltage to be digitized (differential). However, the pre-charge concept can also be used in other applications, such as, for example, switched-capacitor amplifiers, where deriving digital values ​​is not required.

[0026] Figure 3 The diagram shows Figure 2 The switching scheme of electronic circuit 10. The first (top) figure depicts the first output voltage V at the first output node OUTP. OUTP The (multiple) signal curves. The second, third, and fourth figures respectively show the signal curves used for the switch SW. CH SW S and SW C The switch signal P SWCH P SWS and P SWC Before time t0, the first output voltage V OUTP Equal to the second input voltage V present at the second input node INN INN Because in the previous conversion cycle, the changeover switch SW C Short-circuit nodes OUTP and OUTN (and therefore also OUTP and INN). At time t0, the second switch SW... CH By the fourth control signal P SWCH The circuit is switched on, thereby connecting the first charge pump 20 to the first output node OUTP. Therefore, the first charge pump 20 injects charge at the first output node OUTP and charges the first output capacitor C. SP (Pre)charging. This results in a voltage V at the first output node OUTP. OUTP rise.

[0027] At time t1, the first output voltage V OUTP The first input voltage V at the first input node INP is reached. INP The voltage level. At this moment, control logic circuit 30 turns off the second switch SW. CHThis deactivates the charge pump and stops charge injection at node OUTP. Furthermore, at time t1, control circuit 300 turns on the first switch SW. S Understandably, the first switch SW S Second switch SW CH They don't necessarily switch at the same time, but when the second switch SW is turned off... CH Connect the first switch SW S There may be brief pauses between them. This also applies at other times when the two switches are toggled. Understandably, at those times, there may also be brief pauses between the two toggling operations of the two corresponding switches. Due to the second switch SW... CH Only at the first output voltage V OUTP (Approximately) reaching the first input voltage V INP It is only turned off at a certain time. Due to the delay of the logic control circuit 30, there may be a first output voltage V. OUTP A slight overshoot. However, in the first switch SW S After being switched on, the first output node OUTP is connected to the first input node INP, and the first output voltage V... OUTP In fact, it is equal to the first input voltage V. INP .

[0028] Control logic circuit 30 does not necessarily have to keep the second switch SW open. CH Turn on until the first output voltage V OUTP Reaching the first input voltage V INP In some embodiments, the control logic circuit 30 may also be configured to operate at a first output voltage V. OUTP Reaching threshold V THR (exist Figure 3 In the example, it occurs at time t th Then turn off the second switch SW. CH Threshold V THR It may be slightly lower than the first input voltage V. INP For example, the first input voltage V INP 80%. Figure 3 The dotted line diagram shown illustrates the signal curve of voltage VOUTP and P in this case. SWCH and P SWS The switching signal.

[0029] In switch SW S Once connected, the sampling phase begins, and the first output capacitor C... SP For the first input voltage V INP Sampling is performed. At time t2, when sampling is complete, the output capacitor C... SP Maintain the first input voltage V INPThe conversion phase can then begin. For this purpose, the control circuit 300 can be configured to operate via a first control signal P. SWS Turn off the first switch SW S And via the third control signal P SWC Turn on the changeover switch SW C At the changeover switch SW C Once connected, the first output node OUTP is coupled to the second output node OUTN, and the first output voltage V... OUTP Equal to the second output voltage V OUTN During the conversion phase, the ADC converts the sampled differential voltage into a digital value representing that sampled differential voltage. After the conversion is complete, the control circuit 300 turns off the switch SW at time t3. C A new cycle can then begin, repeating the process described above.

[0030] Figure 4 The circuit is basically the same as Figure 2 The same, but more detailed, example of the first charge pump 20 and control logic circuitry 30 is shown. The first charge pump 20 may include a diode bridge rectifier consisting of diodes D1–D4. The anodes of diodes D1 and D2 are coupled to the second input node INN, and the cathodes of diodes D3 and D4 are connected via a second switch SW. CH Coupled to the first output node OUTP. The input of the first inverter INV1 is configured to receive the clock signal CLK, and the output of the first inverter INV1 is connected to the first pump capacitor C. P1 The first inverter INV2 is coupled to the anode of diode D3 and the cathode of diode D1. The input of the second inverter INV2 is coupled to the output of the first inverter INV1, and the output of the second inverter INV2 is connected via the second pump capacitor C. P2 Coupled to the anode of diode D4 and the cathode of diode D2. During the operation of the first charge pump 20, as described above, the second switch SW... CH Close, and switch SW S and SW C disconnect.

[0031] When the output of the first inverter INV1 provides a high signal level (e.g., 5 V), the first pump capacitor C... P1 Increase the voltage at the common circuit node of diodes D1 and D3. Diode D3 becomes forward biased, and current can flow from capacitor C. P1 The flow is directed to the first output node OUTP (thus affecting capacitor C). SP(Pre-charge). Subsequently, when the output of the first inverter INV1 provides a low signal level (e.g., 0 V), diode D3 becomes reverse biased again. When the output of the first inverter INV1 provides a low signal level, the output of the second inverter INV2 provides a high signal level (e.g., 5 V), and the second pump capacitor C... P2 Increase the voltage at the common circuit node of diodes D2 and D4. Diode D4 becomes forward biased, and current can flow from capacitor C. P2 The current flows to the first output node OUTP for further processing of capacitor C. SP (Pre)charge. Subsequently, when the output of the second inverter INV2 provides a low signal level (e.g., 0 V), diode D4 becomes reverse biased again, and a new cycle begins. Cycle repeats, the first output capacitor C... SP It is gradually charged, and therefore the first output voltage V OUTP The corresponding increase. First pump capacitor C P1 Second pump capacitor C P2 The voltage domain of the second input node INN is also isolated from the inverter and clock. Furthermore, in some embodiments, the second switch SW... CH Alternatively, it can be placed before the input of the first inverter INV1, instead of between the cathodes of diodes D3 and D4 and the first output node OUTP. Then the second switch SW CH Connecting or disconnecting the clock signal CLK from the input of the first inverter INV1 deactivates or activates the charge pump.

[0032] according to Figure 4 For example, control logic circuit 30 may include comparator 40 and switch SW. L The non-inverting input of comparator 40 is coupled to the first input node INP, and the inverting input of comparator 40 is coupled to the first output node OUTP. The output of comparator 40 provides the fourth control signal P. SWCH And via logic switch SW L Coupled to the second switch SW CH As long as the first output voltage V OUTP Below the first input voltage V INP Comparator 40 then outputs a fourth control signal P with a high level. SWCH To turn on the second switch SW CH The output of comparator 40 is compared with the second switch SW. CH The switch SW between L By the second control signal P LC Control. Only when logic switch SW is active. L When closed, the fourth control signal P SWCH Only then will the second switch SW be turned on. CHIn other words, the second control signal P LC Control the fourth control signal P SWCH Whether it is forwarded or not, so that the first charge pump 20 can be controlled according to the above functions. Therefore, the second control signal P LC Activate or deactivate the precharge circuit 100.

[0033] Figure 5 The circuit is basically the same as Figure 2 The same applies, but an additional second charge pump 21 and a third switch SW are provided in the pre-charge circuit 100. DISCH The second charge pump 21 is connected to the third switch SW. DISCH The first charge pump 20 is coupled to the first output node OUTP. The second charge pump 21 is also coupled to the second input node INN and (like the first charge pump 20) receives the clock signal CLK. The control logic circuit 30 is configured to receive the clock signal CLK via the fifth control signal P. SWDISCH To control the third switch SW DISCH When the third switch SW DISCH When closed, the second charge pump 21 can draw charge from the first output node OUTP according to the clock signal CLK. In other words, the third switch SW DISCH Activate or deactivate the second charge pump 21. The charge pump configured to extract charge is known in itself, and therefore will not be discussed in detail here.

[0034] Figure 6 The diagram shows Figure 5 The switching scheme of electronic circuit 10. The first (top) figure depicts the first output voltage V at the first output node OUTP. OUTP The signal curves of switch SW are shown in Figures 2, 3, 4, and 5. CH SW DISCH SW S and SW C control signal P SWCH P SWDISCH P SWS and P SWC Before time t0', the first output voltage V OUTP Essentially equal to the second output voltage V present at the second output node OUTN. OUTN At time t0', via the fourth control signal P SWCH Turn on the second switch SW CH The first charge pump 20 is connected to the second switch SW CH Connect to the first output node OUTP. Then, the first charge pump 20 injects charge at the first output node OUTP and to the first output capacitor C. SP Charging. Therefore, the first output voltage V OUTPThe first output voltage V rises. At time t1', the first output voltage V... OUTP The first input voltage V at the first input node INP is reached. INP The level. Due to the second switch SW CH Only at the first output voltage V OUTP Reaching the first input voltage V INP It is then turned off. Due to the delay of the logic control circuit 30, there may be a first output voltage V. OUTP Overshoot. To compensate for this, a second charge pump 21 can be provided. At time t1', the control logic circuit 30 turns off the second switch SW. CH And turn on the third switch SW DISCH Since the second charge pump 21 is configured to draw charge from the first output node OUTP, capacitor C SP Discharged, and the first output voltage V OUTP The second charge pump 21 can be configured to provide a smaller current than the first charge pump 20, meaning that the rate at which charge is drawn from the second charge pump 21 may be less than the rate at which charge is injected from the first charge pump 20. In other words, the first charge pump 20 can be configured to inject more charge at the first output node OUTP in equal time intervals than the second charge pump 21 can be configured to draw from the first output node OUTP.

[0035] At time t2', the first output voltage V OUTP Drop to the first input voltage V INP Below. This time, due to the delay of the logic control circuit 30, the first output voltage V... OUTP A slight undershoot may occur. Due to the difference in strength between the first charge pump 20 and the second charge pump 21, the undershoot at time t2' is smaller than the overshoot at time t1'. This causes the first output capacitor C... SP It is pre-charged more accurately. At time t2', via the fifth control signal P SWDISCH Turn off the third switch SW DISCH Furthermore, at time t2', the control circuit 300 is configured to turn on the first switch SW. S (Sampling switch). At switch SW S Once connected, the sampling phase begins, and the first output capacitor C... SP For the first input voltage V INP Sampling is performed. From this point onward, the switching scheme is basically the same as... Figure 3 The same applies, so it will not be repeated here. It should be understood that... Figure 4The example control logic circuit 30 depicted is not applicable to this switching scheme. Logic control circuits providing the above functionality can be implemented with additional logic elements, but these are not discussed in more detail herein. Those skilled in the art will be able to design such circuits as provided in the reference. Figure 6 The control logic for the described function.

[0036] Figure 7 The diagram shows Figure 5 An alternative switching scheme for electronic circuit 10. The first (top) figure depicts the first output voltage V at the first output node OUTP. OUTP The signal curves of switch SW are shown in the second, third, fourth, and fifth figures. CH SW DISCH SW S and SW C The switch signal P SWCH P SWDISCH P SWS and P SWC Before time t0'', the first output voltage V OUTP Equal to the second input voltage V present at the second input node INN INN At time t0'', via the fourth control signal P SWCH Turn on the second switch SW CH And the first charge pump 20 is connected to the second switch SW CH Connected to the first output node OUTP. The first charge pump 20 injects charge at the first output node OUTP and to the first output capacitor C. SP Charging. Therefore, the first output voltage V OUTP Rise. First output capacitor C SP It can be charged until the first output voltage V OUTP The target voltage V is reached at time t1''. TARGET Target voltage V TARGET It can be higher than the first input voltage V INP At time t1'', ​​control logic circuit 30 can turn off the second switch SW. CH .

[0037] When the target voltage V is reached TARGET Subsequently, at time t2'', the control logic circuit 30 can be configured to control via the fifth control signal P SWDISCH Turn on the third switch SW DISCH Time t2'' can also be the same as time t1'', ​​but... Figure 7 In the example depicted, there is a pause between time t1'' and time t2''. At the third switch SW... DISCHAfter being switched on, the second charge pump 21 draws charge from the first output node OUTP, therefore capacitor C SP Discharge, first output voltage V OUTP The voltage drops. At time t3'', when the first output voltage V... OUTP Reaching V INP At that time, the control logic circuit 30 can turn off the third switch SW. DISCH .

[0038] Furthermore, at time t3'', logic circuit 300 can be controlled via the first control signal P SWS Turn on the first switch SW S (Sampling switch). At switch SW S Once the circuit is switched on, the sampling phase begins, and the first output capacitor C... SP For the first input voltage V INP Sampling is performed. From this point onward, the switching scheme is basically the same as... Figure 3 The same applies, so it will not be elaborated upon here. It should be understood that to achieve [the desired outcome]... Figure 7 In the switching timing scheme, the second charge pump 21 does not necessarily need to be weaker than the first charge pump 20 (i.e., have a smaller output current), because in this case it is not used for overshoot. Furthermore, the control logic circuit 30 can be configured to turn off the third switch SW at a time different from time t3''. DISCH Furthermore, logic circuit 300 can be configured to turn on the first switch SW at a time different from time t3''. S For example, when the first output voltage V OUTP The value drops to a predefined threshold (e.g., V). INP When the value is 110%, the control logic circuit 30 can turn off the third switch SW. DISCH Furthermore, logic circuit 300 can connect the first switch SW. S .

[0039] Figure 8 The circuit is basically the same as Figure 5 Similar to the previous circuit, but with an additional third charge pump 22 provided in the pre-charge circuit 100. The third charge pump 22 is coupled to the control logic circuit 30 and the control circuit 300. The third charge pump 22 is also coupled to the second input node INN and the clock signal CLK. The third charge pump 22 may have the same characteristics as... Figure 4 The first charge pump 20 shown has a similar structure. The third charge pump 22 can be configured to provide a power supply voltage V to the control logic circuit 30 and the control circuit 300. SUP Due to (partial) logic circuits (such as the second switch SW) CH and the third switch SW DISCH It may be necessary to operate in a floating voltage domain, therefore a supply voltage V should be provided in the same voltage domain.SUP This avoids the need for complex additional power supply circuitry. It should be understood that, in addition to the third charge pump 22, a current source can also be used. The same applies to the first charge pump 20 and the second charge pump 21, which can also be replaced by current sources, respectively. Various implementations of current sources are known in themselves and will not be discussed further here.

[0040] Figure 9 Basically with Figure 1 The same, but a modification to filter 50 is shown. For simplicity of illustration, Figure 9 The control circuit 300 is not shown. Filter 50 and... Figure 1 Similarly, including those with input resistance R F and input capacitor C F The filter 50 includes an RC circuit (for the filter capacitor). Additionally, the filter 50 also includes a first common-mode capacitor C. CMP Second common-mode capacitor C CMN Differential filter capacitor C DIFF and the first resistor R CMP Second resistor R CMN First resistor R CMP Coupled at the drain node of MOSFET T to the differential filter capacitor C DIFF Filter resistor R F and the first common-mode capacitor C CMP Between the common circuit nodes. Second resistor R CMN Coupled at the source node of MOSFET T to the differential filter capacitor C DIFF Second common-mode capacitor C CMN Between the common circuit node of the second input node INN and the first common-mode capacitor C. CMP Second common-mode capacitor C CMN It is also coupled to a reference node, such as ground. Figure 9 In the example, filter 50 is implemented as a fully differential filter. Resistor R CMP and capacitor C CMP and resistor R CMN and capacitor C CMN This forms two passive RC filter stages with respect to the common-mode voltage. Resistor R CMP and R CMN and capacitor C DIFF An RC filter stage is formed for the differential input voltage. The filtered input voltage is applied to the differential input (nodes INP, INN) of electronic circuit 10.

[0041] The concepts described in this article also refer to Figure 10 The flowchart illustrates a method that can be used for capacitors (e.g., C).SP A pre-charging method. In the depicted example, the method includes turning on and off a first switch SW coupled between a first input node INP and a first output node OUTP. S (See Figure 10 (Block S1). The first input node INP and the second input node INN can be coupled to the input capacitor C. F The differential inputs, and the first output node OUTP and the second output node OUTN can be coupled to the output capacitor C. SP Differential output (see also) Figure 1 The method also includes a first switch SW. S When disconnected, the control pre-charge circuit 100 injects charge at the first output node OUTP (see...). Figure 10 Box S2; see also Figure 1 and Figure 4 ).

[0042] Although the invention has been illustrated and described with reference to one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, the terminology used to describe such components (including references to “device”) is intended to correspond—unless otherwise stated—to any component or structure that performs the specified function of said component (e.g., is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs that function in the exemplary embodiments shown herein.

Claims

1. An electronic circuit (10), comprising: The differential input includes a first input node (INP) and a second input node (INN), and is coupled to an input capacitor (C) during operation. F ); The differential output includes a first output node (OUTP) and a second output node (OUTN), and is coupled to an output capacitor (C) during operation. SP C SN ); First switch (SW) S ), coupled between the first input node (INP) and the first output node (OUTP); The pre-charge circuit (100) is configured to inject charge at the first output node (OUTP); as well as The control circuit (300) is configured as follows: Turning the first switch (SW) on and off S );as well as In the first switch (SW) S When the circuit is disconnected, the pre-charge circuit (100) is controlled to inject charge (i) at the first output node (OUTP). CH ).

2. The electronic circuit (10) according to claim 1. in, The second input node (INN) and the second output node (OUTN) are connected by a low-impedance line.

3. The electronic circuit (10) according to claim 1 or 2. in, The control circuit (300) is configured such that as long as the differential input voltage (V) remains constant... INP -V INN ) lower than the differential output voltage (V OUTP -V OUTN The pre-charge circuit (100) is controlled to inject charge at the first output node (OUTP).

4. The electronic circuit (10) according to claim 1 or 2. in, The control circuit (300) is configured such that as long as the differential output voltage (V) remains constant... OUTP -V INN If the value is below a predetermined threshold, the pre-charge circuit (100) is controlled to inject charge at the first output node (OUTP).

5. The electronic circuit (10) according to any one of claims 1 to 4. in, The pre-charge circuit (100) includes a first charge pump (20) coupled to the first output node (OUTP) and configured to inject charge at the first output node (OUTP).

6. The electronic circuit according to claim 5, in, The control circuits (300, 30) are configured to operate based on the voltage (V) at the first input node (INP). INP ) and the voltage (V) at the first output node (OUTP) OUTP ) to activate and deactivate the charge pump (20).

7. The electronic circuit according to claim 6, in, The control circuits (300, 30) are configured to operate by means of a second switch (SW). CH The charge pump (20) is connected to the first output node (OUTP) and the charge pump (20) is disconnected from the first output node (OUTP) accordingly, thereby activating and deactivating the charge pump (20).

8. The electronic circuit (10) according to any one of claims 5 to 7. in, The control circuits (300, 30) are configured to activate the first charge pump (20) at a first time (t0) and deactivate the first charge pump (20) at a second time (t1). At the second time (t1), the voltage (V) at the first output node (OUTP) is... OUTP The voltage (V) at the first input node (INP) is reached. INP ).

9. The electronic circuit (10) according to any one of claims 5 to 7. in, The control circuits (300, 30) are configured to activate the first charge pump (20) at a first time (t0) and at a threshold time (t... th Deactivate the first charge pump (20) at the threshold time (t) th At the first output node (OUTP), the voltage (V) OUTP () Reaching the specified threshold.

10. The electronic circuit according to any one of claims 5 to 9, in, The pre-charge circuit includes a comparator (40) configured to detect the second time point (t1).

11. The electronic circuit according to any one of claims 5 to 10, in, The pre-charge circuit (100) includes a second charge pump (21) coupled to the first output node (OUTP) and configured to draw charge from the first output node (OUTP).

12. The electronic circuit according to claim 11, in, The control circuits (300, 30) are configured to activate the second charge pump (21) after the first charge pump (20) is deactivated to compensate for the voltage (V) at the first output node (OUTP). OUTP Overshoot.

13. The electronic circuit (10) according to any one of claims 5 to 12. in, The control circuit (300) includes a control logic circuit (30), and The pre-charging circuit (100) further includes a third charge pump (22), which is configured to provide a power supply voltage (V) to the control logic circuit (30). SUP ).

14. The electronic circuit according to claim 13, in, The control circuits (300, 30) are referenced to ground level, and the control logic circuit (30) is floating and referenced to the potential present at the first input node (INP).

15. A system comprising: The electronic circuit (100) according to any one of claims 1 to 14. An analog-to-digital converter having a differential input coupled to the differential output of the electronic circuit (100), Among them, the output capacitor (C) of the electronic circuit (100) SP C SN It is formed by the input capacitance of the analog-to-digital converter.

16. A method comprising: The first switch (SW) is used to connect and disconnect the first input node (INP) and the first output node (OUTP). S ), wherein the first input node (INP) and the second input node (INN) form a coupling to the input capacitor (C). F The differential input of the capacitor (C) and the first output node (OUTP) and the second output node (OUTN) are coupled to the output capacitor (C). SP C SN The differential output of ) In the first switch (SW) S When the circuit is disconnected, the control pre-charge circuit (100) injects charge at the first output node (OUTP).

17. The method according to claim 16, in, Injecting charge at the first output node (OUTP) includes injecting current into the first output node (OUTP) to charge the output capacitor (C). SP Charge until the first output voltage (V) at the first output node (OUTP) is reached. OUTP () Reached the threshold.

18. The method according to claim 17, in, The threshold is equal to or lower than the first input voltage (V) at the first input node (INP). INP ).

19. The method according to claim 17 or 18, in, Injecting charge at the first output node (OUTP) also includes drawing current from the first output node (OUTP) to charge the output capacitor (C). SP Discharge, and compensate the first output voltage (V) OUTP Overshoot.

20. The method according to claim 16, in, Injecting charge at the first output node (OUTP) includes: Injecting current into the first output node (OUTP) to the output capacitor (C) SP Charge until the first output voltage (V) at the first output node (OUTP) is reached. OUTP The target value is reached, which is greater than the first input voltage (V) at the first input node (INP). INP );as well as Current is drawn from the first output node (OUTP) to the output capacitor (C). SP Discharge until the first output voltage (V) is reached. OUTP () Reached the threshold.

21. The method according to claim 20, in, The threshold is essentially equal to the first input voltage (V). INP ).

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