Analog-to-digital converter and determination method of sampling time thereof, storage medium and integrated circuit

Abstract

The application discloses an analog-to-digital converter and a method for determining a sampling time of the analog-to-digital converter, a storage medium and an integrated circuit. The method comprises the following steps: step 1, setting an initial value of the sampling time under the condition that the working voltage of a channel remains unchanged; step 2, switching to the channel after presetting an internal sampling capacitor to a reference voltage, sampling and converting at a preset sampling time to obtain a current digital result; step 3, controlling the preset sampling time to increase by a preset step length, and repeating step 2 to update the current digital result; step 4, comparing the current digital result before updating with the current digital result after updating, if the two are equal, taking the current digital result after updating as a measured voltage, and taking the preset sampling time corresponding to the current digital result after updating as a measured time, otherwise returning to step 3; and step 5, determining a target sampling time required by the channel according to the measured voltage, the measured time, a full-scale voltage of the analog-to-digital converter and a preset voltage error.

Description

Technical Field

[0001] This invention relates to the fields of IC design and application technology, and in particular to an analog-to-digital converter and a method for determining its sampling time, a storage medium, and an integrated circuit. Background Technology

[0002] Successive approximation analog-to-digital converters (ADCs) are widely used in integrated circuits to convert analog voltages into digital quantities. Their operation includes a sampling phase and a conversion phase. The sampling phase requires sufficient time to ensure that the internal sampling capacitor is fully charged or discharged to match the input voltage; otherwise, the conversion result will be inaccurate.

[0003] In multi-channel analog-to-digital converter (ADC) applications, the sampling time required for each channel varies due to differences in external sensor impedance, internal trace resistance, and capacitance. Insufficient sampling time leads to decreased conversion accuracy; excessive sampling time reduces the overall sampling rate of the ADC. Common methods for configuring sampling time include: first, performing impedance calculations for each channel individually, a tedious process reliant on the designer's experience; second, classifying channels based on estimated impedance ranges and using conservative sampling times, sacrificing sampling rates for some channels; and third, directly selecting the maximum sampling time, suitable only for applications where speed is not critical. All of these methods require manual processing and are inefficient. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the first objective of this invention is to propose a method for determining the sampling time of an analog-to-digital converter, which enables fully automatic matching of sampling times, accurately calculating the target sampling time required for each channel without manual calculation of channel impedance, while balancing sampling accuracy and sampling rate.

[0005] A second objective of this invention is to provide a computer-readable storage medium.

[0006] The third objective of this invention is to provide an analog-to-digital converter.

[0007] The fourth objective of this invention is to provide an integrated circuit.

[0008] To achieve the above objectives, a first aspect of the present invention provides a method for determining the sampling time of an analog-to-digital converter (ADC), wherein the ADC has at least one channel to be matched, and the method includes: Step 1, setting an initial value for a preset sampling time while keeping the operating voltage of the channel to be matched constant; Step 2, switching to the channel to be matched after setting the sampling capacitor inside the ADC to a reference voltage, and sampling and converting at the currently set preset sampling time to obtain a current digital result; Step 3, controlling the preset sampling time to increase by a preset step size, and repeating Step 2 to update the current digital result; Step 4, comparing the current digital result before and after the update, if they are equal, then taking the updated current digital result as the measured voltage, and taking the preset sampling time corresponding to the updated current digital result as the measured time, otherwise returning to Step 3; Step 5, determining the target sampling time required for the channel to be matched based on the measured voltage, the measured time, the full-scale voltage of the ADC, and a preset voltage error.

[0009] According to the method for determining the sampling time of the analog-to-digital converter of the present invention, the sampling time is gradually increased from the initial value by preset sampling time, and the sampling stability is determined by comparing the results of two adjacent digital results. In this way, the optimal sampling time required for each channel can be automatically matched without manual intervention, and the sampling accuracy and sampling rate are improved.

[0010] In addition, the method for determining the sampling time of an analog-to-digital converter according to the above embodiments of the present invention may further include the following additional technical features: According to one embodiment of the present invention, the reference voltage includes a reference low voltage and a reference high voltage.

[0011] According to one embodiment of the present invention, when the reference voltage is a reference low voltage, the calculation formula for the target sampling time is as follows:

[0012] in, Indicates the target sampling time. This indicates the actual measured time. This represents the full-scale voltage. This indicates the preset voltage error. This indicates the measured voltage.

[0013] According to one embodiment of the present invention, when the reference voltage is a reference high voltage, the calculation formula for the target sampling time is as follows:

[0014] in, Indicates the target sampling time. This indicates the actual measured time. This represents the full-scale voltage. This indicates the preset voltage error. This indicates the measured voltage.

[0015] According to an embodiment of the present invention, the method further includes: executing a test procedure when the reference voltage is a reference low voltage and a test procedure when the reference voltage is a reference high voltage respectively, and obtaining a first target sampling time and a second target sampling time accordingly; and taking the maximum value of the first target sampling time and the second target sampling time as the final target sampling time.

[0016] According to one embodiment of the present invention, the initial value of the preset sampling time and the step size are both one clock cycle of the analog-to-digital converter.

[0017] According to one embodiment of the present invention, the preset voltage error is equal to the voltage value corresponding to the least significant bit of the analog-to-digital converter.

[0018] According to an embodiment of the present invention, when the analog-to-digital converter has multiple channels to be matched, the method further includes: after determining the target sampling time of the current channel to be matched, repeating steps 1 to 5 sequentially for the remaining channels to be matched until the target sampling time of all channels to be matched is determined.

[0019] According to an embodiment of the present invention, the method further includes: when a change in the condition affecting the impedance characteristics of the channel to be matched is detected, automatically re-execute steps 1 to 5 to update the target sampling time of the channel to be matched.

[0020] According to one embodiment of the present invention, the change in the condition affecting the impedance characteristics of the channel to be matched includes system timer timeout, chip temperature change exceeding a preset threshold, or power supply voltage fluctuation exceeding a preset threshold.

[0021] To achieve the above objectives, a second aspect of the present invention provides a computer-readable storage medium storing a program for determining the sampling time of an analog-to-digital converter (ADC), wherein the ADC sampling time determination program, when executed by a processor, implements the ADC sampling time determination method described in the aforementioned embodiments of the present invention.

[0022] According to an embodiment of the present invention, the computer-readable storage medium storing the analog-to-digital converter sampling time determination program thereon, when executed by a processor, increases the preset sampling time from an initial value one by one, and determines whether the sampling is stable by comparing the results of two adjacent digital results. This allows the optimal sampling time required for each channel to be automatically matched without manual intervention, thereby improving sampling accuracy and sampling rate.

[0023] To achieve the above objectives, a third aspect of the present invention provides an analog-to-digital converter, comprising: a memory, a processor, and a computer program stored in the memory, wherein when the computer program is executed by the processor, it implements the method for determining the sampling time of the analog-to-digital converter as described in the preceding embodiment of the present invention.

[0024] According to the embodiment of the present invention, the analog-to-digital converter gradually increases the preset sampling time from the initial value and determines whether the sampling is stable by comparing the results of two adjacent digital results. In this way, the optimal sampling time required for each channel can be automatically matched without manual intervention, thereby improving the sampling accuracy and sampling rate.

[0025] To achieve the above objectives, a fourth aspect of the present invention provides an integrated circuit, which includes an analog-to-digital converter as described in the foregoing embodiments of the present invention.

[0026] According to the integrated circuit of the present invention, the computer program stored in the memory is executed by the processor inside the circuit. The sampling time is incremented sequentially from the initial value by a preset sampling time, and the sampling stability is determined by comparing the results of two adjacent digital results. In this way, the optimal sampling time required for each channel can be automatically matched without manual intervention, and the sampling accuracy and sampling rate are improved.

[0027] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] Figure 1 This is a flowchart illustrating a method for determining the sampling time of an analog-to-digital converter according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating a method for determining the sampling time of an analog-to-digital converter according to another embodiment of the present invention; Figure 3 This is a block diagram of an analog-to-digital converter according to an embodiment of the present invention; Figure 4 This is a block diagram of an integrated circuit according to an embodiment of the present invention. Detailed Implementation

[0029] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0030] The following description, with reference to the accompanying drawings, describes an analog-to-digital converter, a method for determining its sampling time, a storage medium, and an integrated circuit according to embodiments of the present invention.

[0031] Figure 1 This is a flowchart illustrating a method for determining the sampling time of an analog-to-digital converter according to an embodiment of the present invention.

[0032] Specifically, in some embodiments of the present invention, such as Figure 1 As shown, the analog-to-digital converter has at least one channel to be matched, and the method for determining the sampling time of the analog-to-digital converter includes: S101, Step 1: Set the initial value of the preset sampling time while keeping the operating voltage of the channel to be matched constant.

[0033] Specifically, in this embodiment, the control unit first triggers an automatic matching process, selecting the currently configured channel in the analog-to-digital converter (ADC) as the matching channel. Before starting the test, it is necessary to ensure that the input voltage provided by the external sensor or other voltage source connected to the matching channel remains stable throughout the entire test cycle. This is a prerequisite for ensuring the comparability of subsequent adjacent conversion results and the validity of the charge-discharge stability criterion. Subsequently, an initial value is set for the preset sampling time. This initial value can be configured as one clock cycle of the ADC to start the test from the shortest time. Of course, those skilled in the art can also flexibly adjust the size of this initial value according to the specific application scenario and the operating clock frequency of the ADC, as long as the initial value is less than or equal to the minimum possible stabilization time of the channel. This step provides a starting benchmark for subsequently incrementally increasing the sampling time and judging sampling stability.

[0034] S102, Step 2: After setting the sampling capacitor inside the analog-to-digital converter to the reference voltage, switch to the channel to be matched, and sample and convert using the currently set preset sampling time to obtain the current digital result.

[0035] Specifically, in this embodiment, the analog-to-digital converter (ADC) internally includes a sampling capacitor and a corresponding input channel selection switch. The control unit first controls the input channel selection switch to switch to the reference voltage terminal, connecting the sampling capacitor to the reference voltage source. This reference voltage can be selected as a low reference voltage or a high reference voltage depending on the test mode. While connected to this reference voltage source, the sampling capacitor is fully charged to the high reference voltage or fully discharged to the low reference voltage, thus placing it in a known and defined charge state. After completing the preset operation, the control unit immediately switches the input channel selection switch from the reference voltage terminal back to the channel to be matched. At this time, the sampling capacitor is connected to the external input voltage of the channel to be matched, and a charge transfer process occurs between them due to the voltage difference. Simultaneously with the switch switching, the control unit starts a timer, using the currently set preset sampling time as the waiting period. At the end of this waiting period, an analog voltage value approximating the input voltage of the channel to be matched has been established on the sampling capacitor. Subsequently, the ADC immediately performs a complete analog-to-digital conversion operation on this analog voltage value, converting it into the corresponding digital code. This digital code is the current digital result obtained in this operation. This numerical result reflects the digital code of the voltage across the sampling capacitor after analog-to-digital conversion at the end of the current sampling time. When this step is executed for the first time, the currently set preset sampling time is the initial value set in step S101.

[0036] S103, Step 3: Control the preset sampling time to increase by a preset step size, and repeat Step 2 to update the current digital result.

[0037] Specifically, in this embodiment, after completing one sampling and conversion operation in step S102, if the stability determination condition defined in step S104 has not yet been met, the control unit increments the preset sampling time, that is, increases the current preset sampling time by a preset step size. In some embodiments of the present invention, this step size is preferably set to one clock cycle of the analog-to-digital converter. After the adjustment is completed, the entire operation of step S102 is returned and repeated: the sampling capacitor is preset to the reference voltage again, the channel to be matched is switched again, the sampled capacitor waits for charge transfer with the updated sampling time, the analog-to-digital conversion is performed again, and a new digital result is obtained. This new digital result logically replaces the previous result and becomes the current digital result for the new round, thereby realizing the update of the current digital result. Through the above-mentioned loop mechanism, the preset sampling time starts from the initial value and increases by one step size in each round. The sampling capacitor can be charged or discharged more fully during the waiting time after each increment, and the residual voltage on it gradually approaches the real input voltage of the channel to be matched. Correspondingly, the digital result obtained from each conversion also gradually converges to the real digital code corresponding to the channel voltage. This series of digital results obtained at different sampling times provides a continuous and progressive data foundation for determining whether the sampling has reached stability in the subsequent step S104 by comparing adjacent results. The incremental process terminates when the stability condition defined in step S104 is met.

[0038] S104, Step 4: Compare the current digital results before and after the update. If they are equal, use the updated current digital result as the measured voltage and the preset sampling time corresponding to the updated current digital result as the measured time. Otherwise, return to Step 3.

[0039] Specifically, in this embodiment, after obtaining a new digital result each time through step S103, the control unit compares the new result (i.e., the updated current digital result) with the digital result obtained and saved in the previous cycle (i.e., the current digital result before the update). If the comparison finds that the two are equal, it indicates that the charging and discharging of the sampling capacitor has reached a stable state that sufficiently approximates the channel voltage at the current sampling time. At this time, the control unit records this equal digital result as the measured voltage and records the preset sampling time corresponding to the generation of this stable result as the measured time, for use in the subsequent step S105 to calculate the target sampling time. If two adjacent results are not equal, it indicates that the sampling is not yet sufficient. The control unit saves the current digital result for the next round of comparison and automatically returns to step S103, continuing to increment the preset sampling time by one step and starting a new round of preset, switching, waiting, and conversion operations until the above-mentioned stability determination condition is met.

[0040] S105, Step 5: Determine the target sampling time required for the channel to be matched based on the measured voltage, measured time, full-scale voltage of the analog-to-digital converter, and preset voltage error.

[0041] Specifically, in this embodiment, after obtaining the measured voltage and measured time t1 in step S104, the control unit further combines the full-scale voltage of the analog-to-digital converter and the preset voltage error to calculate the target sampling time actually required by the channel to be matched within the full range. Since step S104 is the settling time t1 measured under the current actual input voltage condition of the channel to be matched, this time only reflects the time required for the sampling capacitor to charge and discharge from the reference voltage to the current specific voltage. However, in practical applications, the input voltage of the channel to be matched may vary at any level between zero and full scale. If t1 is directly configured as the sampling time of the channel, when the input voltage is close to full scale, the charging and discharging time required by the sampling capacitor will be longer than t1, which may lead to insufficient sampling. Therefore, it is necessary to convert t1 into a target sampling time that meets the same error requirement under full-scale conditions according to the corresponding conversion relationship of the charging mode or discharging mode, so as to ensure that the channel can obtain accurate conversion results when receiving input voltage of any amplitude. This conversion process is based on a preset voltage error value, which can be pre-set according to accuracy requirements. For example, in some embodiments of this invention, it is set to the voltage value corresponding to the least significant bit of the analog-to-digital converter. The full-scale voltage is an inherent parameter of the analog-to-digital converter itself, determined by a reference voltage source. The control unit substitutes the above-mentioned known quantities into the calculation formula corresponding to the current test mode to obtain the target sampling time. This target sampling time is the parameter finally written into the sampling time configuration register and used for all subsequent normal sampling operations of this channel.

[0042] Furthermore, in some embodiments of the present invention, the reference voltage includes a reference low voltage and a reference high voltage.

[0043] Specifically, in this embodiment, the analog-to-digital converter (ADC) internally provides two selectable reference voltage nodes, defined as a low reference voltage and a high reference voltage. The low reference voltage is typically ground potential or the negative reference voltage terminal of the ADC. During preset operations, the control unit switches the sampling capacitor to this node, completely releasing the charge on the capacitor to achieve a charge-free state. The high reference voltage is typically the full-scale voltage of the ADC or the positive reference voltage terminal. The control unit switches the sampling capacitor to this node, fully charging the capacitor to achieve a full charge state. By setting two different reference voltage levels, this method can perform charging mode testing and discharging mode testing respectively. In charging mode, the sampling capacitor starts from the low reference voltage and charges the input voltage of the channel to be matched; in discharging mode, the sampling capacitor starts from the high reference voltage and discharges the input voltage of the channel to be matched. The two modes correspond to different initial charge states that the sampling capacitor may face in practical applications, which can more comprehensively reflect the charging and discharging characteristics of the channel. This provides a hardware basis for subsequently calculating the target sampling time under the charging and discharging paths and providing the larger value as the final configuration parameter.

[0044] Furthermore, in some embodiments of the present invention, when the reference voltage is a low reference voltage, the formula for calculating the target sampling time is as follows:

[0045] in, Indicates the target sampling time. Indicates the actual measurement time. This represents the full-scale voltage. Indicates the preset voltage error. This indicates the measured voltage.

[0046] Furthermore, in some embodiments of the present invention, when the reference voltage is a reference high voltage, the calculation formula for the target sampling time is as follows:

[0047] in, Indicates the target sampling time. Indicates the actual measurement time. This represents the full-scale voltage. Indicates the preset voltage error. This indicates the measured voltage.

[0048] Furthermore, in some embodiments of the present invention, such as Figure 2 As shown, the method also includes: S201, execute the test procedure when the reference voltage is the reference low voltage and the test procedure when the reference voltage is the reference high voltage respectively, and obtain the first target sampling time and the second target sampling time accordingly.

[0049] Specifically, in this embodiment, for the same channel to be matched, the control unit executes a complete automatic matching process twice. The first time, the reference voltage is set to a low reference voltage, and a charging mode test is performed according to steps S101 to S105 to obtain a first target sampling time; the second time, the reference voltage is set to a high reference voltage, and a discharging mode test is performed according to steps S101 to S105 to obtain a second target sampling time.

[0050] S202, take the maximum value between the first target sampling time and the second target sampling time as the final target sampling time.

[0051] Specifically, in this embodiment, the control unit compares the first target sampling time and the second target sampling time, selects the larger value as the final target sampling time for the channel to be matched, and writes it into the sampling time configuration register corresponding to that channel. By testing the two paths separately and taking the larger value, the sampling accuracy of the channel under various operating conditions can be ensured.

[0052] Furthermore, in some embodiments of the present invention, the initial value and step size of the preset sampling time are both one clock cycle of the analog-to-digital converter.

[0053] Specifically, in this embodiment, the initial value of the preset sampling time is one clock cycle of the analog-to-digital converter, and the increment step is also one clock cycle. The clock cycle is determined by the ADC's system clock and is the smallest time unit in the ADC's operating timing. Setting both the initial value and the step size to one clock cycle allows the sampling time to increase gradually from the minimum value with the finest granularity, ensuring that the found stable sampling time is optimal and avoiding the defects of wasted sampling time or insufficient sampling caused by skipping the optimal sampling point due to an excessively large step size.

[0054] Furthermore, in some embodiments of the present invention, the preset voltage error is equal to the voltage value corresponding to the least significant bit of the analog-to-digital converter.

[0055] Specifically, in this embodiment, the preset voltage error is set to the voltage value corresponding to one least significant bit (1LSB) of the analog-to-digital converter. 1LSB is the smallest voltage change that the ADC can distinguish. Using 1LSB as the error tolerance standard ensures that the sampling accuracy meets the ADC's quantization requirements while avoiding the problem of needing infinite sampling time in pursuit of absolute accuracy, thus achieving a reasonable balance between accuracy and efficiency.

[0056] Furthermore, in some embodiments of the present invention, when the analog-to-digital converter has multiple channels to be matched, the method further includes: after determining the target sampling time of the current channel to be matched, repeating steps 1 to 5 sequentially for the remaining channels to be matched until the target sampling time of all channels to be matched is determined.

[0057] Specifically, in this embodiment, the control unit automatically determines the sampling time for each channel to be matched according to a preset channel order or a user-specified channel list. After the target sampling time for the current channel is calculated and written to the corresponding configuration register, the control unit switches the channel selection switch to the next channel to be matched, repeating the entire testing and calculation process until all channels in the list are configured. The entire multi-channel matching process is completed automatically by the control unit without manual intervention. Users can choose to automatically match all channels according to their actual application needs, or they can specify only some channels for matching, while the remaining channels maintain the default sampling time or the sampling time manually configured by the user.

[0058] Furthermore, in some embodiments of the present invention, the method further includes: when a change in the condition affecting the impedance characteristics of the channel to be matched is detected, steps 1 to 5 are automatically re-executed to update the target sampling time of the channel to be matched.

[0059] Specifically, in this embodiment, after completing the initial sampling time configuration, the control unit continuously monitors for triggering events that affect the channel impedance characteristics. Once such an event is detected, the control unit automatically restarts the matching process for the affected channel, sequentially executing steps S101 to S105 to redetermine and update the target sampling time configuration for that channel. The detection of triggering events can be achieved through periodic triggering by a timer, monitoring chip temperature changes by a temperature sensor, or detecting supply voltage fluctuations by a power supply voltage monitoring circuit. This automatic reconfiguration mechanism allows the analog-to-digital converter to autonomously recalibrate the sampling time without manual intervention when the operating environment changes, ensuring that sampling accuracy and sampling rate are always maintained at their optimal levels.

[0060] Furthermore, in some embodiments of the present invention, changes in the conditions affecting the impedance characteristics of the channel to be matched include system timer timeout, chip temperature change exceeding a preset threshold, or power supply voltage fluctuation exceeding a preset threshold.

[0061] Specifically, in this embodiment, the control unit detects trigger conditions through one or more of the following methods: timing via a system timer, generating a trigger signal when the timer expires to achieve periodic automatic recalibration; real-time monitoring of the chip temperature via an on-chip temperature sensor, generating a trigger signal when the temperature change exceeds a preset threshold; and real-time monitoring of the supply voltage via a power supply voltage monitoring circuit, generating a trigger signal when the voltage fluctuation exceeds a preset threshold. These trigger conditions can be selected and configured by the user according to the actual application scenario, and each preset threshold can also be adjusted independently to achieve a balance between power consumption and performance; no specific limitations are imposed here.

[0062] In summary, according to the method for determining the sampling time of the analog-to-digital converter of the present invention, the sampling time is gradually increased from the initial value by preset sampling time, and the stability of sampling is determined by comparing the results of two adjacent digital results. Thus, the optimal sampling time required for each channel can be automatically matched without manual intervention, and the sampling accuracy and sampling rate are improved.

[0063] Based on the method for determining the sampling time of an analog-to-digital converter (ADC) proposed in the foregoing embodiments of the present invention, the present invention also proposes a computer-readable storage medium storing a program for determining the sampling time of an ADC. When the program for determining the sampling time of an ADC is executed by a processor, it implements the method for determining the sampling time of an ADC as described in the embodiments of the present invention.

[0064] According to an embodiment of the present invention, the computer-readable storage medium storing the analog-to-digital converter sampling time determination program thereon, when executed by a processor, increases the preset sampling time from an initial value one by one, and determines whether the sampling is stable by comparing the results of two adjacent digital results. This allows the optimal sampling time required for each channel to be automatically matched without manual intervention, thereby improving sampling accuracy and sampling rate.

[0065] Figure 3 This is a block diagram of an analog-to-digital converter according to an embodiment of the present invention.

[0066] like Figure 3 As shown, the analog-to-digital converter 100 includes: a memory 10, a processor 20, and a computer program stored on the memory 10. When the computer program is executed by the processor 20, it implements the method for determining the sampling time of the analog-to-digital converter according to the above-described embodiment of the present invention.

[0067] According to the present invention, the analog-to-digital converter executes a computer program stored in the memory through its internal processor, and gradually increases the preset sampling time from the initial value. It also determines whether the sampling is stable by comparing the results of two adjacent digital results. In this way, it can automatically match the optimal sampling time required for each channel without manual intervention, and improves the sampling accuracy and sampling rate.

[0068] Figure 4 This is a block diagram of an integrated circuit according to an embodiment of the present invention.

[0069] like Figure 4 As shown, the integrated circuit 1000 includes an analog-to-digital converter 100 as described in the above embodiment of the present invention.

[0070] According to the integrated circuit of the present invention, by employing the analog-to-digital converter of the above embodiments of the present invention, the sampling time is gradually increased from the initial value by preset sampling time, and the sampling stability is determined by comparing the results of two adjacent digital results. Thus, the optimal sampling time required for each channel can be automatically matched without manual intervention, and the sampling accuracy and sampling rate are improved.

[0071] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0072] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0073] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0074] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0076] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0077] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0078] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for determining the sampling time of an analog-to-digital converter, characterized in that, The analog-to-digital converter has at least one channel to be matched, and the method includes: Step 1: Under the condition that the operating voltage of the channel to be matched remains unchanged, set the initial value of the preset sampling time; Step 2: After setting the sampling capacitor inside the analog-to-digital converter to the reference voltage, switch to the channel to be matched, and sample and convert using the currently set preset sampling time to obtain the current digital result; Step 3: Increase the preset sampling time by a preset step size and repeat Step 2 to update the current digital result; Step 4: Compare the current digital results before and after the update. If they are equal, the updated current digital result is taken as the measured voltage, and the preset sampling time corresponding to the updated current digital result is taken as the measured time. Otherwise, return to step 3. Step 5: Determine the target sampling time required for the channel to be matched based on the measured voltage, the measured time, the full-scale voltage of the analog-to-digital converter, and the preset voltage error.

2. The method for determining the sampling time of an analog-to-digital converter according to claim 1, characterized in that, The reference voltage includes a reference low voltage and a reference high voltage.

3. The method for determining the sampling time of an analog-to-digital converter according to claim 2, characterized in that, When the reference voltage is a low reference voltage, the calculation formula for the target sampling time is as follows: in, Indicates the target sampling time. This indicates the measured time. This represents the full-scale voltage. This indicates the preset voltage error. This indicates the measured voltage.

4. The method for determining the sampling time of an analog-to-digital converter according to claim 2, characterized in that, When the reference voltage is a high reference voltage, the calculation formula for the target sampling time is as follows: in, Indicates the target sampling time. This indicates the measured time. This represents the full-scale voltage. This indicates the preset voltage error. This indicates the measured voltage.

5. The method for determining the sampling time of an analog-to-digital converter according to any one of claims 1-4, characterized in that, The method further includes: The test procedures when the reference voltage is a low reference voltage and the test procedures when the reference voltage is a high reference voltage are executed respectively to obtain the first target sampling time and the second target sampling time accordingly. The maximum value between the first target sampling time and the second target sampling time is taken as the final target sampling time.

6. The method for determining the sampling time of an analog-to-digital converter according to claim 1, characterized in that, The initial value of the preset sampling time and the step size are both one clock cycle of the analog-to-digital converter.

7. The method for determining the sampling time of an analog-to-digital converter according to claim 1, characterized in that, The preset voltage error is equal to the voltage value corresponding to the least significant bit of the analog-to-digital converter.

8. The method for determining the sampling time of an analog-to-digital converter according to claim 1, characterized in that, When the analog-to-digital converter has multiple channels to be matched, the method further includes: After determining the target sampling time for the current channel to be matched, repeat steps 1 to 5 for the remaining channels to be matched in sequence until the target sampling time for all channels to be matched has been determined.

9. The method for determining the sampling time of an analog-to-digital converter according to claim 1, characterized in that, The method further includes: When a change in the condition affecting the impedance characteristics of the channel to be matched is detected, steps 1 to 5 are automatically re-executed to update the target sampling time of the channel to be matched.

10. The method for determining the sampling time of an analog-to-digital converter according to claim 9, characterized in that, The conditions affecting the impedance characteristics of the channel to be matched change, including system timer timeout, chip temperature change exceeding a preset threshold, or power supply voltage fluctuation exceeding a preset threshold.

11. A computer-readable storage medium storing thereon a program for determining the sampling time of an analog-to-digital converter, wherein the program for determining the sampling time of an analog-to-digital converter, when executed by a processor, implements the method for determining the sampling time of an analog-to-digital converter according to any one of claims 1-10.

12. An analog-to-digital converter, characterized in that, include: A memory, a processor, and a computer program stored in the memory, wherein the computer program, when executed by the processor, implements the method for determining the sampling time of an analog-to-digital converter according to any one of claims 1-10.

13. An integrated circuit, characterized in that, Includes the analog-to-digital converter as described in claim 12.

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