An in-line adjustable reference analog-to-digital converter

Abstract

The embodiment of the application discloses an embedded adjustable reference ADC, which comprises a reference voltage source, an operational amplifier, a reference voltage selection circuit, a reference current circuit, an IDAC, an RDAC, a CDAC and a comparator; wherein the reference voltage source is connected with the inverting input end of the operational amplifier, the first end of the reference voltage selection circuit is connected with the non-inverting input end of the operational amplifier, the output end of the operational amplifier is connected with the input end of the reference current circuit, the first, second and third output ends of the reference current circuit are respectively connected with the input end of the IDAC, the second end of the reference voltage selection circuit and a power supply, the output end of the IDAC is connected with the input end of the RDAC, the first and second output ends of the RDAC are respectively connected with the ground and the input end of the CDAC, and the output end of the CDAC is connected with the input end of the comparator. By using the embodiment of the application, more unit elements can be arranged on the same chip area, and the power consumption is lower when realizing the same number of analog-to-digital conversion.

Description

Technical Field

[0001] This invention relates to the field of application-specific integrated circuits and logic chips, and in particular to an embedded adjustable reference analog-to-digital converter. Background Technology

[0002] An analog-to-digital converter (ADC) is a device that converts analog signals into digital signals and is widely used in digital circuits. Using digital signal processing in digital circuits can improve the circuit's noise immunity and make data processing methods more flexible. However, at the input and output ends, the feedback signal and the control quantity of the controlled object may still be analog signals. Analog input quantities can be converted into digital signals by an ADC, and a digital-to-analog converter (DAC) is used at the output end. C It converts digital signals back into analog signals.

[0003] In existing technologies, the reference voltage is typically generated by an internal bandgap voltage source, which is usually 1.2V and cannot be adjusted. If the ADC requires a different reference voltage, an additional reference voltage conversion circuit is needed to boost or buck the reference voltage, and then a reference voltage buffer is used to drive the capacitor or resistor network inside the ADC. This additional circuitry consumes a significant amount of chip area and power, increasing cost, especially in analog-to-digital conversion systems that require multiple reference voltages. Summary of the Invention

[0004] This application provides an embedded adjustable reference analog-to-digital converter that can arrange more unit components on the same chip area, while consuming less power to achieve the same number of bits of analog-to-digital conversion.

[0005] A first aspect of this application provides an embedded adjustable reference analog-to-digital converter (ADC). The embedded adjustable reference ADC includes a reference voltage source, an operational amplifier, a reference voltage selection circuit, a reference current circuit, a current-to-analog converter (DAC), a resistor-to-analog converter (DAC), a capacitor-to-analog converter (DAC), and a comparator. The reference voltage source is connected to the inverting input of the operational amplifier. The first terminal of the reference voltage selection circuit is connected to the non-inverting input of the operational amplifier. The output of the operational amplifier is connected to the input of the reference current circuit. The first output of the reference current circuit is connected to the input of the current-to-analog converter (DAC). The second output of the reference current circuit is connected to the second terminal of the reference voltage selection circuit. The third terminal of the reference voltage selection circuit is grounded. The output of the current-to-analog converter is connected to the input of the resistor-to-analog converter (DAC). The first output of the resistor-to-analog converter is grounded. The second output of the resistor-to-analog converter is connected to the input of the capacitor-to-analog converter (DAC). The output of the capacitor-to-analog converter (DAC) is connected to the input of the comparator.

[0006] Optionally, the reference voltage selection circuit includes a plurality of first resistors connected in series and a plurality of first switches. Each of the two ends of each first resistor is connected to one end of a first switch. The other ends of the plurality of first switches are connected to the non-inverting input of the operational amplifier. One end of the plurality of first resistors connected in series is connected to the second output of the reference current circuit, and the other end of the plurality of first resistors connected in series is grounded.

[0007] Optionally, the reference current circuit includes two cascaded first MOS transistors, one of which has its gate connected to the output of the operational amplifier, and the other has its gate connected to a fixed bias voltage source. The source of one of the first MOS transistors is connected to a power supply, the drain of one of the first MOS transistors is connected to the source of the other first MOS transistor, and the drain of the other first MOS transistor is connected to the second terminal of the reference voltage selection circuit.

[0008] Optionally, the current-to-analog converter includes multiple sets of MOSFET units and multiple second switches. Each set of MOSFET units includes two cascaded second MOSFETs. The gate of one of the second MOSFETs in each set of MOSFET units is connected to the gate of one of the first MOSFETs. The gate of the other second MOSFET in each set of MOSFET units is connected to the gate of the other first MOSFET. The source of one of the second MOSFETs in each set of MOSFET units is connected to a power supply. The drain of one of the second MOSFETs in each set of MOSFET units is connected to the source of the other second MOSFET. The drains of the other second MOSFETs in each set of MOSFET units are interconnected through a second switch.

[0009] Optionally, the resistor-to-analog converter includes a coarse-adjustment voltage divider module, which includes multiple second resistors connected in series and multiple third switches. One end of each of the multiple second resistors is connected to the output terminal of the current-to-analog converter, and each of the two ends of each second resistor is connected to one end of a third switch. The other end of the multiple third switches is connected to the input terminal of the capacitor-to-analog converter.

[0010] Optionally, the resistor-to-analog converter further includes a fine-tuning voltage divider module, which includes multiple third resistors connected in series, multiple fourth switches, and a fourth resistor. Each of the three third resistors is connected to one end of a fourth switch at each end. The other ends of the multiple fourth switches are connected to the fourth resistor and the input terminal of the capacitor-to-analog converter. One end of the multiple third resistors connected in series is connected to the other end of the multiple second resistors connected in series.

[0011] Optionally, the resistor-to-analog converter further includes a common module, which includes a plurality of parallel fifth resistors, one end of which is connected to the other end of a plurality of series-connected third resistors, the other end of which is connected to the other end of a plurality of third switches and grounded.

[0012] Optionally, the capacitor-to-analog converter includes a positive sampling module and a negative sampling module. The positive sampling module includes multiple fifth switches and multiple first capacitors, with each first capacitor corresponding to one of the fifth switches. The upper plate of one of the first capacitors is connected to the output terminal or the positive-phase analog input terminal of the coarse adjustment voltage divider module through the corresponding fifth switch. The upper plates of the other first capacitors (excluding one of the first capacitors) are connected to one of the positive-phase analog input terminal, the reference voltage terminal, or the low-level reference voltage terminal through the corresponding fifth switches. The lower plates of the multiple first capacitors are interconnected. The negative sampling module includes multiple sixth switches and multiple second capacitors, with each second capacitor corresponding to one of the sixth switches; the upper plate of one of the second capacitors is connected to the output terminal or the inverting analog input terminal of the fine-tuning voltage divider module through the corresponding sixth switch, and the upper plates of the other second capacitors are connected to one of the inverting analog input terminal, the reference voltage terminal, or the low-level reference voltage terminal through the corresponding sixth switches; the lower plates of the multiple second capacitors are interconnected.

[0013] Optionally, the non-inverting input of the comparator is connected to the lower plate of a plurality of first capacitors, and the inverting input of the comparator is connected to the lower plate of a plurality of second capacitors.

[0014] Optionally, the embedded adjustable reference analog-to-digital converter further includes a seventh switch and an eighth switch, wherein the common-mode reference voltage terminal is connected to the non-inverting input terminal of the comparator through the seventh switch, and the common-mode reference voltage terminal is connected to the inverting input terminal of the comparator through the eighth switch.

[0015] This application employs a design combining a current DAC, a resistor DAC, and a capacitor DAC. This design uses fewer resistive components and achieves lower power consumption while maintaining constant impedance and current load at the output of the reference buffer. This simplifies the design complexity of the reference buffer and effectively reduces noise introduced by DAC impedance and current load switching compared to existing DACs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of an analog-to-digital conversion system provided in one embodiment of the prior art is shown; Figure 2 It shows Figure 1 A schematic diagram of the ADC structure in the embodiment; Figure 3 A schematic diagram of an embedded adjustable reference analog-to-digital converter provided in one embodiment of this application is shown; Figure 4 A schematic diagram of an embedded adjustable reference analog-to-digital converter system provided in one embodiment of this application is shown. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] Please refer to Figure 1 This diagram illustrates a schematic of an analog-to-digital conversion (ADC) system provided in an embodiment of the prior art. The ADC system includes a reference voltage generation circuit, a reference voltage conversion circuit, a reference voltage buffer, an ADC, a comparator, a successive approximation register, and logic control circuitry. The reference voltage generation circuit provides a stable reference voltage that determines the full-scale value of the ADC input range. In the prior art, this reference voltage is typically provided by an internal bandgap reference voltage source, which is generally 1.2V, stable but not adjustable. If the ADC requires different reference voltages, such as 1.5V, 2.5V, or 5V, the 1.2V bandgap reference voltage cannot be used directly; an additional reference voltage conversion circuit is needed to boost or buck the bandgap reference voltage. The buffer is used for the capacitor or resistor network inside the ADC to provide sufficient current. The ADC converts the analog input signal into a digital output signal. The comparator converts the input analog signal V... in The input voltage is compared with the guessed voltage generated by the ADC, and the output is high or low. The successive approximation register approximates the true input voltage value step by step according to the comparator's result, following a binary search logic (try half, then a quarter, and so on). The logic control circuit coordinates the clock signal and controls the timing of the SAR register to ensure that each conversion step is performed in an orderly manner.

[0020] Please refer to Figure 2 It shows Figure 1 The schematic diagram of the ADC in the embodiment is shown in the figure. It is a 5-8 bit successive approximation register (SAR) ADC, mainly composed of a 5-bit most significant bit (MSB) capacitive digital-to-analog converter (CDAC) and an 8-bit least significant bit (LSB) resistor digital-to-analog converter (RDAC).

[0021] The least significant bit (LSB) resistor-series digital-to-analog converter (DAC) uses a resistor divider, typically consisting of a series of resistors of equal value (e.g., R) connected in series to form a voltage divider. For a K-bit LSB DAC, 2... K A resistor is used to provide all voltage levels from 0 to the reference voltage. An 8-bit LSB RDAC requires 256 resistors, as shown in the diagram. These 256 resistors are connected in series, with one end connected to the low-level reference voltage terminal VRB and the other end connected to the high-level reference voltage terminal VRT. The input voltages of VRB and VRT are determined by the reference voltage VFRE. A digital encoder controls a set of switches, selecting the corresponding voltage from each tap of the resistor string as the DAC's output voltage. As shown in the diagram, each resistor is connected to one end of a switch, and the other ends of these switches serve as the RDAC's output, connected to the CDAC. Therefore, an LSBRDAC also includes 256 switches.

[0022] The Most Significant Bit (LSB) capacitive digital-to-analog converter (DAC) consists of a binary-weighted capacitor array that converts digital codes into analog voltages through successive approximations for comparison with the input signal. It is coupled to the LSB RDAC via a series capacitor. As shown in the figure, the MSB CDAC includes a positive sampling module and a negative sampling module. The positive and negative sampling modules are similar; here, we take the negative sampling module as an example.

[0023] The negative sampling module includes six capacitors connected in parallel, one of which is a coupling capacitor, and the other five are weighting capacitors. The coupling capacitor is designed with a capacitance of 1C, and the capacitance values ​​of the five weighting capacitors are designed according to a binary weight ratio (1, 2, 4, 8, 16), resulting in a total capacitance of 32C for the negative sampling module. Each capacitor is connected to multiple ports through a set of switches, requiring 32 switches. Specifically, the upper plate of the coupling capacitor is connected to the inverting analog input terminal AINP or the output terminal of the RDAC via a switch, and the upper plate of the weighting capacitors is connected to the inverting analog input terminal AINP, the high-level reference voltage terminal VRT, and the low-level reference voltage terminal VRB via switches. The lower plates of the coupling capacitor and the weighting capacitors are interconnected.

[0024] The positive sampling module is identical to the negative sampling module, except that the upper plate of the coupling capacitor is connected to either the positive analog input terminal AIMN or the high-level reference voltage terminal VRT. in Sure.

[0025] In summary, it can be seen that a reference voltage conversion circuit and a reference voltage buffer are required in the analog-to-digital converter system; in the analog-to-digital converter, the LSB RDAC requires 256 resistors and 256 switches, and the MSB CDAC requires 64 capacitors and 64 switches.

[0026] Please refer to Figure 3 and Figure 4 , Figure 3 This illustration shows a schematic diagram of an embedded adjustable reference analog-to-digital converter provided in one embodiment of this application. Figure 4 A schematic diagram of an embedded adjustable reference analog-to-digital converter (ADC) system according to an embodiment of this application is shown. The embedded adjustable reference ADC includes a reference voltage source, an operational amplifier, a reference voltage selection circuit, a reference current circuit, a current digital-to-analog converter (IDAC), a resistor-to-analog converter (RDAC), a capacitor-to-analog converter (CDAC), and a comparator. The reference voltage source is connected to the inverting input of the operational amplifier; the first terminal of the reference voltage selection circuit is connected to the non-inverting input of the operational amplifier; the output of the operational amplifier is connected to the input of the reference current circuit; the first output of the reference current circuit is connected to the input of the current ADC; the second output of the reference current circuit is connected to the second terminal of the reference voltage selection circuit; the third terminal of the reference voltage selection circuit is grounded; the output of the current ADC is connected to the input of the resistor-to-analog converter; the first output of the resistor-to-analog converter is grounded; the second output of the resistor-to-analog converter is connected to the input of the capacitor-to-analog converter; and the output of the capacitor-to-analog converter is connected to the input of the comparator.

[0027] The reference voltage source provides a stable reference voltage that determines the full-scale value of the ADC input range. In the prior art, this reference voltage is typically provided by an internal bandgap reference voltage source, which is generally 1.2V, very stable, but not adjustable.

[0028] The reference voltage selection circuit is used to select different reference voltages. In a specific embodiment provided in this application, the reference voltage selection circuit includes multiple first resistors connected in series and multiple first switches. Each first resistor has two ends connected to one end of a first switch. The other ends of the multiple first switches are connected to the non-inverting input terminal of the operational amplifier. One end of the multiple series-connected first resistors is connected to the second output terminal of the reference current circuit, and the other end of the multiple series-connected first resistors is grounded. Figure 3As shown, the control terminals of multiple first switches are used to receive reference voltage selection signals to select different voltage divider nodes to output reference voltages corresponding to the ranges. These reference voltage selection signals can be generated by logic control circuits.

[0029] The first terminal of the reference voltage selection circuit is the other terminal of the plurality of first switches, the second terminal of the reference voltage selection circuit is one terminal of the plurality of first resistors connected in series, and the third terminal of the reference voltage selection circuit is the other terminal of the plurality of first resistors connected in series.

[0030] The reference current circuit converts the control voltage output by the operational amplifier into a stable and accurate reference current, which is then distributed as a current source to all subsequent branches requiring current. In a specific embodiment provided in this application, the reference current circuit includes two cascaded first MOS transistors. The gate of one first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the other first MOS transistor is connected to a fixed bias voltage source. The source of one first MOS transistor is connected to a power supply, the drain of one first MOS transistor is connected to the source of the other first MOS transistor, and the drain of the other first MOS transistor is connected to the second terminal of the reference voltage selection circuit.

[0031] The input terminal of the reference current circuit is the gate of the two first MOS transistors and the source of one of the first MOS transistors. The gate of one of the first MOS transistors is connected to the output terminal of the operational amplifier, the gate of the other first MOS transistor is connected to a fixed bias voltage source, and the source of the other first MOS transistor is connected to the power supply. The first output terminal of the reference current circuit is the gate of the two first MOS transistors, and the second output terminal of the reference current circuit is the drain of the other first MOS transistor.

[0032] In the embodiments of this application, the reference current circuit adopts a current mirror structure, which consists of two cascaded MOS transistors. The gates and sources of the two MOS transistors are connected in the same way. As long as the turn-on control voltage of the MOS transistors is the same, the drain current will be the same.

[0033] The system comprises a reference voltage source, an operational amplifier, a reference voltage selection circuit, and a reference current circuit. Figure 4 The voltage reference circuit in the circuit.

[0034] The most basic building block of an IDAC is the current switching unit. Each current switching unit typically contains two core components: a current source that provides the base current and a pair of switches connected to the current source. The switches can also be controlled by control signals generated by logic control circuits. The on / off state of the switches determines the direction of current flow from each current source to a specific output terminal, and the analog current output of the IDAC is the sum of the total current flowing from all current sources to that specific output terminal.

[0035] Furthermore, IDAC can be... Figure 4 The logic control circuitry in an IDAC is controlled through Dynamic Element Matching (DEM). Ideally, every unit component in a DAC (such as a unit capacitor, unit resistor, or unit current source) should be perfectly identical. However, in actual manufacturing, due to process variations, these components will always have slight differences. If the multiple unit current sources constituting the IDAC are not exactly equal in size, then a nonlinear step error will occur when outputting analog currents corresponding to different digital codes. This will lead to a deterioration in the differential nonlinearity of the ADC, and even code loss. DEM technology uses algorithms to randomize or rotate these error-prone components, "averaging" the originally fixed, deterministic nonlinear error into random white noise. Although the total error energy may not change, it no longer manifests as specific harmonic distortion, thereby significantly improving the signal-to-noise ratio and spurious-free dynamic range.

[0036] In a specific embodiment provided in this application, the current-to-analog converter includes multiple sets of MOSFET units and multiple second switches. Each set of MOSFET units includes two cascaded second MOSFETs. The gate of one of the second MOSFETs in each set of MOSFET units is connected to the gate of one of the first MOSFETs. The gate of the other second MOSFET in each set of MOSFET units is connected to the gate of the other first MOSFET. The source of one of the second MOSFETs in each set of MOSFET units is connected to a power supply. The drain of one of the second MOSFETs in each set of MOSFET units is connected to the source of the other second MOSFET. The drains of the other second MOSFETs in each set of MOSFET units are interconnected through a second switch.

[0037] The number of MOS transistor groups is related to the number of bits converted by the analog-to-digital converter (ADC). For example, to achieve an n-bit conversion, a linearly weighted IDAC would require 2... n The circuit uses a MOSFET unit. This embodiment employs a current-controlled DAC, where the PMOS current source array is placed at the top of the circuit near the power supply, while the switch is placed at the bottom. Other practical methods are also possible and are not specifically limited.

[0038] In this circuit, the input terminal of the IDAC is the gate of the second MOSFET, and the output terminal of the current-to-analog converter is the drain of another second MOSFET.

[0039] RDAC is an important type of DAC. Its core principle is to use the voltage divider or current divider characteristics of a precision resistor network to convert the input digital signal into a corresponding analog voltage or current signal. Its specific structure can be... Figure 2 The structure shown in the embodiment can also have other implementation structures.

[0040] In one specific embodiment provided in this application, the resistor digital-to-analog converter includes a coarse adjustment voltage divider module, which includes a plurality of second resistors connected in series and a plurality of third switches. One end of the plurality of second resistors connected in series is connected to the output terminal of the current digital-to-analog converter, and each end of each second resistor is connected to one end of a third switch. The other end of the plurality of third switches is connected to the input terminal of the capacitor digital-to-analog converter.

[0041] In this context, the input terminal VRT of the resistor-to-analog converter is one end of a series of second resistors.

[0042] like Figure 3 As shown, the coarse voltage divider module includes seven second resistors (R_2~R_8) connected in series and multiple third switches. Each second resistor is connected to one end of a third switch. If no third switches are connected to either side of R_2 and R_8, six third switches are required; if only one third switch is connected to either side of R_2 and R_8, seven third switches are required; if both sides of R_2 and R_8 are connected to third switches, eight third switches are required. The configuration can be adjusted according to specific needs.

[0043] Furthermore, the resistor-to-digital converter also includes a fine-tuning voltage divider module, which includes multiple third resistors connected in series, multiple fourth switches, and a fourth resistor. Each of the three third resistors is connected to one end of a fourth switch at each end. The other ends of the multiple fourth switches are connected to the fourth resistor and the input terminal of the capacitor-to-digital converter. One end of the multiple series-connected third resistors is connected to the other end of the multiple series-connected second resistors.

[0044] like Figure 3 As shown, the fine-tuning voltage divider module includes seven third resistors connected in series, each with a resistance value of 1 / 8 of the second resistor's value. Similarly, each third resistor is connected to one end of a fourth switch. If no fourth switches are connected to either side of the 7 / 8 R and 1 / 8 R resistors, six third switches are required; if only one fourth switch is connected to either side of the 7 / 8 R and 1 / 8 R resistors, seven fourth switches are required; if both sides of the 7 / 8 R and 1 / 8 R resistors are connected to fourth switches, eight fourth switches are required. This can be configured according to specific needs.

[0045] The coarse voltage divider module is used to determine the first preset bit in the low-order bits based on the first residual analog input signal, and the fine voltage divider module is used to determine the last preset bit in the low-order bits based on the second residual analog signal. The number of bits in the first preset bit is determined according to the number of resistors connected in series in the coarse voltage divider module, and the number of bits in the last preset bit is determined according to the number of resistors connected in series in the fine voltage divider module.

[0046] The first residual analog input signal is the analog input signal remaining after the high-order bits are determined by the high-order bits from the analog input signal by the high-order bits digital-to-analog converter. The second residual analog input signal is the analog input signal remaining after the high-order bits are determined by the coarse adjustment voltage divider module based on the first residual analog input signal. The number of bits in both the pre-set and post-set bits is determined by taking the logarithm of 2 with respect to the number of series resistors.

[0047] Furthermore, the resistor-to-analog converter also includes a common module, which includes multiple parallel fifth resistors, one end of which is connected to the other end of multiple series-connected third resistors, the other end of which is connected to the other end of multiple third switches and grounded.

[0048] like Figure 3 As shown, the common module includes eight parallel fifth resistors. The other end of the eight parallel fifth resistors is the input terminal of the common resistor module, which is connected to the other end of multiple third switches and the low-level reference voltage terminal VRB. In this application, VRB is grounded. One end of the eight parallel fifth resistors is the output terminal of the common resistor module, and the input terminal of the fine-tuning voltage divider module is the other end of multiple fourth switches.

[0049] As can be seen, the resistor-to-digital converter includes 7 second resistors connected in series, 7 third resistors connected in series, 1 fourth resistor, and 8 fifth resistors connected in parallel, thus comprising a total of 23 resistors. The resistor-to-digital converter also includes 8 third switches and 8 fourth switches, for a total of 16 switches.

[0050] A CDAC is a circuit that primarily utilizes the charging and discharging characteristics of capacitors and charge redistribution to convert digital signals into analog signals. Because its core structure is easily implemented in standard CMOS processes and it consumes relatively little power, it occupies a central position in modern integrated circuits, especially successive approximation analog-to-digital converters (SAR ADCs).

[0051] In one specific embodiment provided in this application, the capacitor-to-analog converter includes a positive sampling module and a negative sampling module. The positive sampling module includes multiple fifth switches and multiple first capacitors, with each first capacitor corresponding to one of the fifth switches. The upper plate of one of the first capacitors is connected to the output terminal or the positive-phase analog input terminal of the coarse adjustment voltage divider module through the corresponding fifth switch. The upper plates of the other first capacitors (excluding one of the first capacitors) are connected to one of the positive-phase analog input terminal, the reference voltage terminal, or the low-level reference voltage terminal through the corresponding fifth switches. The lower plates of the multiple first capacitors are interconnected. The negative sampling module includes multiple sixth switches and multiple second capacitors, with each second capacitor corresponding to one of the sixth switches; the upper plate of one of the second capacitors is connected to the output terminal or the inverting analog input terminal of the fine-tuning voltage divider module through the corresponding sixth switch, and the upper plates of the other second capacitors are connected to one of the inverting analog input terminal, the reference voltage terminal, or the low-level reference voltage terminal through the corresponding sixth switches; the lower plates of the multiple second capacitors are interconnected.

[0052] like Figure 3 As shown, the positive sampling module includes six capacitors connected in parallel, one of which is a coupling capacitor, and the other five are weighting capacitors. The coupling capacitor is designed with a capacitance value of 1C, and the capacitance values ​​of the five weighting capacitors are designed according to a binary weight ratio (1, 2, 4, 8, 16), so the positive sampling module has a capacitance of 32C. Each capacitor is connected to multiple ports through a set of switches, so 32 switches are required. Specifically, the upper plate of the coupling capacitor is connected to the inverting analog input terminal AIMN or the output terminal of the RDAC through a switch, and the upper plate of the weighting capacitor is connected to the inverting analog input terminal AIMN, the low-level reference voltage terminal VRB, and the reference voltage terminal VREF through a switch. The lower plates of the coupling capacitor and the weighting capacitors are connected to each other.

[0053] Symmetrically, the negative sampling module also includes six capacitors in parallel, one of which is a coupling capacitor, and the other five are weighting capacitors. The coupling capacitor is designed with a capacitance of 1C, and the capacitance values ​​of the five weighting capacitors are designed according to a binary weight ratio (1, 2, 4, 8, 16), so the positive sampling module includes 32C capacitors. Each capacitor is connected to multiple ports through a set of switches, requiring 32 switches. Specifically, the upper plate of the coupling capacitor is connected to the inverting analog input terminal AINP or the output terminal of the RDAC through a switch, and the upper plate of the weighting capacitor is connected to the inverting analog input terminal AINP, the low-level reference voltage terminal VRB, and the reference voltage terminal VREF through a switch. The lower plates of the coupling capacitor and the weighting capacitor are interconnected.

[0054] In one specific embodiment provided in this application, the non-inverting input terminal of the comparator is connected to the lower plate of a plurality of first capacitors, and the inverting input terminal of the comparator is connected to the lower plate of a plurality of second capacitors.

[0055] In one specific embodiment provided in this application, the embedded adjustable reference analog-to-digital converter further includes a seventh switch and an eighth switch. The common-mode reference voltage terminal is connected to the non-inverting input terminal of the comparator through the seventh switch, and the common-mode reference voltage terminal is connected to the inverting input terminal of the comparator through the eighth switch.

[0056] In single-ended input SAR ADCs, although the signal is only input from one end (such as AINP), AIMN is often fixedly connected to a reference level (such as AVDD / 2 or GND) to form a pseudo-differential input structure in order to match the internal differential structure and improve anti-interference capability. This design helps to suppress common-mode noise, improve the signal-to-noise ratio, and make the comparator operate in the optimal linear region.

[0057] The embedded adjustable reference analog-to-digital converter is a single-ended embedded adjustable reference analog-to-digital converter, which allows sampling of the analog input signal to be converted using either the positive sampling module or the negative sampling module; wherein, if the negative sampling module is used to sample the analog input signal to be converted, then: During the sampling phase: The embedded adjustable reference analog-to-digital converter is used to receive the analog input signal to be converted, the analog input signal including an inverted analog input signal; The logic control circuit controls the seventh switch to close to connect with the common-mode reference voltage terminal; and controls the sixth switch to connect with the inverting analog input terminal to sample the inverting analog input signal through the negative sampling module; During the holding and pre-setting phase: The logic control circuit controls the seventh switch to open and controls the sixth switch to connect to the reference voltage terminal; In the successive approximation stage: The successive approximation register starts from the most significant bit and guesses whether each bit is 0 or 1 in turn. The logic control circuit controls the switches to close or open based on the result of the successive approximation register guess, so as to obtain the node voltage output by the embedded adjustable reference analog-to-digital converter. The switches include the first switch to the eighth switch. The comparator compares the node voltage with half of the common-mode reference voltage output from the common-mode reference voltage terminal to obtain the comparison result; The successive approximation register determines whether the current bit is 1 or 0 based on the comparison result, and the logic control circuit switches the switch based on the comparison result, and then guesses whether the next bit is 1 or 0.

[0058] Specifically, the successive approximation stage includes a high-level successive approximation stage; wherein, in the high-level successive approximation stage: The successive approximation register starts from the most significant bit and guesses whether each bit is 0 or 1 in turn. If the guess result of the current bit is 1, the logic control circuit controls the sixth switch to connect the lower plate of the second capacitor corresponding to the current bit to the reference voltage terminal, the lower plate of the second capacitor corresponding to the other undetermined bits is connected to the low-level reference voltage terminal, and the connection state of the lower plate of the second capacitor corresponding to the determined bit remains unchanged, so as to obtain the node voltage output by the embedded adjustable reference analog-to-digital converter. The comparator compares the node voltage with half of the common-mode reference voltage output from the common-mode reference voltage terminal to obtain the comparison result; If the comparison result indicates that the node voltage is less than 1 / 2 of the common-mode reference voltage output by the common-mode reference voltage terminal, then the successive approximation register determines the current bit to be 1 and maintains the connection state of the lower plate of the second capacitor corresponding to the current bit. If the comparison result indicates that the node voltage is greater than 1 / 2 of the common-mode reference voltage output by the common-mode reference voltage terminal, then the successive approximation register determines that the current bit is 0, and the logic control circuit connects the lower plate of the second capacitor corresponding to the current bit to the low-level reference voltage terminal by controlling the sixth switch. The successive approximation register guesses whether the next bit is 0 or 1.

[0059] Specifically, the successive approximation stage further includes a low-level fine-tuning successive approximation stage; wherein, in the low-level fine-tuning successive approximation stage: The logic control circuit starts from the second resistor corresponding to the highest bit, sequentially closes the third switch corresponding to the second resistor, opens the third switch corresponding to the remaining undetermined bits, and keeps the connection state of the third switch corresponding to the determined bits unchanged, so as to obtain the node voltage output by the embedded adjustable reference analog-to-digital converter. The comparator compares the node voltage with half of the common-mode reference voltage output from the common-mode reference voltage terminal to obtain the comparison result; If the comparison result indicates that the node voltage is less than 1 / 2 of the common-mode reference voltage output by the common-mode reference voltage terminal, then the successive approximation register determines the current bit to be 1 and maintains the connection state of the third switch corresponding to the current bit. If the comparison result indicates that the node voltage is greater than 1 / 2 of the common-mode reference voltage output by the common-mode reference voltage terminal, then the successive approximation register determines that the current bit is 0, and the logic control circuit disconnects the third switch corresponding to the current bit; The successive approximation register guesses whether the next bit is 0 or 1.

[0060] It should be noted that the specific process of sampling the analog input signal to be converted using the positive sampling module is similar to that using the negative sampling module, and can be referred to accordingly. Additionally, IDAC can be used in the median successive approximation stage, but will not be detailed here.

[0061] The embedded adjustable reference analog-to-digital converter system provided in this application adopts a design scheme combining capacitor DAC, resistor DAC, and current DAC. Figure 1 Compared to existing analog-to-digital conversion systems, this system does not require a reference voltage conversion circuit and a buffer; simultaneously, Figure 2 The LSB RDAC in the analog-to-digital converter provided in the prior art includes 256 resistors and 256 switches. This application... Figure 3 The provided embedded adjustable reference analog-to-digital converter includes 23 resistors and 16 switches. This solution uses fewer resistive components and achieves lower power consumption while keeping the output impedance and current load of the reference buffer constant. This simplifies the design complexity of the reference buffer and effectively reduces the noise introduced by the switching of DAC impedance and current load compared to the R-2R DAC.

[0062] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0063] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0064] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0065] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0067] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0068] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0069] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0070] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. An embedded adjustable reference analog-to-digital converter, characterized in that, The embedded adjustable reference analog-to-digital converter includes a reference voltage source, an operational amplifier, a reference voltage selection circuit, a reference current circuit, a current-to-analog converter, a resistor-to-analog converter, a capacitor-to-analog converter, and a comparator. The reference voltage source is connected to the inverting input of the operational amplifier; the first terminal of the reference voltage selection circuit is connected to the non-inverting input of the operational amplifier; the output of the operational amplifier is connected to the input of the reference current circuit; the first output of the reference current circuit is connected to the input of the current-to-analog converter; the second output of the reference current circuit is connected to the second terminal of the reference voltage selection circuit; the third terminal of the reference voltage selection circuit is grounded; the output of the current-to-analog converter is connected to the input of the resistor-to-analog converter; the first output of the resistor-to-analog converter is grounded; the second output of the resistor-to-analog converter is connected to the input of the capacitor-to-analog converter; and the output of the capacitor-to-analog converter is connected to the input of the comparator.

2. The embedded adjustable reference analog-to-digital converter according to claim 1, characterized in that, The reference voltage selection circuit includes multiple first resistors connected in series and multiple first switches. Each of the two ends of each first resistor is connected to one end of a first switch. The other ends of the multiple first switches are connected to the non-inverting input of the operational amplifier. One end of the multiple first resistors connected in series is connected to the second output of the reference current circuit, and the other end of the multiple first resistors connected in series is grounded.

3. The embedded adjustable reference analog-to-digital converter according to claim 1, characterized in that, The reference current circuit includes two cascaded first MOS transistors. The gate of one first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the other first MOS transistor is connected to a fixed bias voltage source. The source of one first MOS transistor is connected to a power supply, the drain of one first MOS transistor is connected to the source of the other first MOS transistor, and the drain of the other first MOS transistor is connected to the second terminal of the reference voltage selection circuit.

4. The embedded adjustable reference analog-to-digital converter according to claim 2, characterized in that, The current-to-analog converter includes multiple sets of MOSFET units and multiple second switches. Each set of MOSFET units includes two cascaded second MOSFETs. The gate of one of the second MOSFETs in each set of MOSFET units is connected to the gate of one of the first MOSFETs. The gate of the other second MOSFET in each set of MOSFET units is connected to the gate of the other first MOSFET. The source of one of the second MOSFETs in each set of MOSFET units is connected to a power supply. The drain of one of the second MOSFETs in each set of MOSFET units is connected to the source of the other second MOSFET. The drains of the other second MOSFETs in each set of MOSFET units are interconnected through a second switch.

5. The embedded adjustable reference analog-to-digital converter according to claim 1, characterized in that, The resistor-to-analog converter includes a coarse-adjustment voltage divider module, which includes multiple second resistors connected in series and multiple third switches. One end of each of the multiple second resistors is connected to the output terminal of the current-to-analog converter, and each of the two ends of each second resistor is connected to one end of a third switch. The other end of the multiple third switches is connected to the input terminal of the capacitor-to-analog converter.

6. The embedded adjustable reference analog-to-digital converter according to claim 5, characterized in that, The resistor-to-digital converter also includes a fine-tuning voltage divider module, which includes multiple third resistors connected in series, multiple fourth switches, and a fourth resistor. Each of the three third resistors is connected to one end of a fourth switch at each end. The other ends of the multiple fourth switches are connected to the fourth resistor and the input terminal of the capacitor-to-digital converter. One end of the multiple third resistors connected in series is connected to the other end of the multiple second resistors connected in series.

7. The embedded adjustable reference analog-to-digital converter according to claim 6, characterized in that, The resistor-to-analog converter also includes a common module, which includes multiple parallel fifth resistors, one end of which is connected to the other end of multiple series-connected third resistors, and the other end of which is connected to the other end of multiple third switches and grounded.

8. The embedded adjustable reference analog-to-digital converter according to claim 1, characterized in that, The capacitor-to-analog converter includes a positive sampling module and a negative sampling module. The positive sampling module includes multiple fifth switches and multiple first capacitors, with each first capacitor corresponding to one of the fifth switches. The upper plate of one of the first capacitors is connected to the output terminal or the positive-phase analog input terminal of the coarse adjustment voltage divider module through the corresponding fifth switch. The upper plates of the other first capacitors are connected to one of the positive-phase analog input terminal, the reference voltage terminal, or the low-level reference voltage terminal through the corresponding fifth switches. The lower plates of the multiple first capacitors are interconnected. The negative sampling module includes multiple sixth switches and multiple second capacitors, with each second capacitor corresponding to one of the sixth switches; the upper plate of one of the second capacitors is connected to the output terminal or the inverting analog input terminal of the fine-tuning voltage divider module through the corresponding sixth switch, and the upper plates of the other second capacitors are connected to one of the inverting analog input terminal, the reference voltage terminal, or the low-level reference voltage terminal through the corresponding sixth switches; the lower plates of the multiple second capacitors are interconnected.

9. The embedded adjustable reference analog-to-digital converter according to claim 1, characterized in that, The non-inverting input of the comparator is connected to the lower plate of a plurality of first capacitors, and the inverting input of the comparator is connected to the lower plate of a plurality of second capacitors.

10. The embedded adjustable reference analog-to-digital converter according to claim 9, characterized in that, The embedded adjustable reference analog-to-digital converter also includes a seventh switch and an eighth switch. The common-mode reference voltage terminal is connected to the non-inverting input terminal of the comparator through the seventh switch, and the common-mode reference voltage terminal is connected to the inverting input terminal of the comparator through the eighth switch.

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