A 2 bit / cycle SAR ADC based on jump switching

Abstract

The present application belongs to the technical field of analog-digital conversion, and particularly relates to a 2 bit / cycle SAR ADC based on jump switching. The present application obtains 4-bit interval code words by operating 6-bit complementary outputs generated by three comparators, and each group of interval code words is a complementary code word, and each group can use only one latch to latch; the hardware overhead required for complete latching of six-bit comparison code words and subsequent decoding in the structure of a traditional 2 bit / cycle successive approximation analog-digital converter is reduced; the reverse combination of high-bit capacitors and low-bit capacitors is switched and reconstructed into only net value switching of low-bit capacitors by jump switching control logic, so that invalid capacitor switching actions are saved, and dynamic switching energy consumption of the capacitor array is reduced; the present application does not change the normal binary weight CDAC structure, and the LATCH latched code words directly drive the capacitor array, so that the present application can be compatible with traditional SAR ADC capacitor array design, matching design and layout implementation.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital conversion technology, specifically relating to a 2-bit / cycle SAR ADC based on jump switching. Background Technology

[0002] Successive approximation analog-to-digital converters (SAR ADCs) are widely used in medium-resolution and medium-to-high-speed analog-to-digital conversion scenarios due to their advantages such as low power consumption, small area, and simple structure. Traditional SAR ADCs output only 1 bit of quantized digital code value per comparison cycle, which limits the conversion speed. To improve speed, 2-bit / cycle SAR ADCs typically use three comparators to divide the current quantization range into four intervals, and can output 2 bits of quantized digital code value per comparison cycle.

[0003] In traditional 2-bit / cycle SAR ADCs, three comparators output six complementary quantized digital code values, which must first be latched and then decoded by decoding logic into four-bit binary code values ​​to control capacitor array switching. This results in significant hardware overhead for the latches and decoding logic, as well as high dynamic power consumption. Furthermore, in traditional 2-bit / cycle SAR ADCs, capacitor array switching obtains the target weight through inverse combinations of high-order and low-order capacitors, but this process generates unnecessary switching energy waste. For high-speed, low-power SAR ADCs, the aforementioned logic power consumption and capacitor array switching power consumption significantly reduce overall energy efficiency. Therefore, it is necessary to propose a SAR ADC circuit structure with low hardware overhead and low switching power consumption. Summary of the Invention

[0004] To address the aforementioned problems and shortcomings, and to resolve the issues of high hardware overhead and high dynamic power consumption in existing high-speed, low-power SAR ADCs, this invention provides a 2-bit / cycle SAR ADC based on skip switching. This invention simplifies the six-bit comparator output to four bits using logic gates, ultimately requiring only two latches for latching, reducing the six latching circuits needed to latch the three comparator output codewords in a 2-bit / cycle SAR ADC. Secondly, skip switching control logic is introduced in the comparator output and switching control stages. When the target capacitor array switching net value can be equivalently achieved by a single small-weighted capacitor, only the actual small capacitor switching is performed, eliminating the need for the reverse combination switching of high-bit and low-bit capacitors in traditional schemes, thereby reducing capacitor array switching power consumption.

[0005] A 2-bit / cycle SAR ADC based on jump switching includes: a sampling circuit module, a comparator module, a capacitor array module, and a jump switching control logic module.

[0006] The sampling circuit module is responsible for sampling the continuously changing input signal. When the sampling signal CLKS is pulled high, it samples and holds the instantaneous voltage of the signal on the capacitor array module, and maintains the sampling voltage unaffected by the input signal throughout the entire subsequent conversion cycle.

[0007] The capacitor array module is a charge redistribution type digital-to-analog converter, including a set of SIG_DAC and a set of REF_DAC. By switching the connection level of the lower plate of each capacitor, it generates an analog voltage corresponding to the control code value at the output terminal using the charge redistribution principle. SIG_DAC is a sampling capacitor array, and REF_DAC is a reference capacitor array.

[0008] The comparator module consists of three comparators that compare the voltage on SIG_DAC with the voltage on REF_DAC to determine the signal amplitude range, generate three comparison result codewords and three complementary codewords, forming a total of six comparator output codewords C1, C1B, C2, C2B, C3, and C3B, and transmit the comparison results to the jump switching control logic module.

[0009] The jump switching control logic module is the core of this invention. Based on a successive approximation state machine, it first directly generates four-bit interval valid codewords K0, K1, K2, and K3 based on the outputs of the three comparators and their complementary outputs. These four-bit codewords are used to represent the four quantization intervals where the current input signal is located. Then, based on the interval valid codewords K0, K1, K2, and K3 and the current SIG_DAC state, it determines the actual net weight change in the switching path SIG_DAC. Subsequently, it reconstructs the high and low capacitor combination switching of SIG_DAC into low capacitor net value switching and latches the control signal. The latched control signal directly drives the SIG_DAC switching.

[0010] Furthermore, the four-bit interval valid codewords K0, K1, K2, and K3 in the jump switching control logic module are implemented using four NOR gate operations.

[0011] Furthermore, the method for determining the actual net weight change in the switching path based on the valid codeword of the interval and the current switching state of the capacitor array is as follows: For adjacent high and low bit binary weight capacitors with corresponding voltage change weights of 2X and X, when the target capacitor voltage change is +X: after identifying the net change, the capacitor with weight X is directly controlled to switch in the forward direction, so that the SIG_DAC voltage output produces the same +X net change; similarly, when the target capacitor voltage change is -X, the capacitor with weight X is directly controlled to switch in the reverse direction.

[0012] Furthermore, the specific workflow of the aforementioned 2-bit / cycle SAR ADC based on skip switching is as follows:

[0013] Sampling phase: At the start of the conversion cycle, the sampling clock is valid, the sampling switch is turned on, and SIG_DAC samples the input signal. After sampling is completed, the sampling switch is turned off, and the upper plate of SIG_DAC retains the input charge.

[0014] Comparison: The jump switching control logic module controls the lower plate of SIG_DAC to switch, and at the same time controls REF_DAC to generate two different comparison voltages. The total comparison range is divided into four regions by the three comparison voltages generated by SIG_DAC and REF_DAC. Then, the comparator control clock CLKC becomes active, and the three comparators generate three comparison result codewords and three complementary codewords, forming a total of six comparator output codewords. After calculation, four-bit effective codewords of K0, K1, K2, and K3 are obtained, which represent the quantization range of the current input signal.

[0015] Equivalent net weight judgment: The jump switching control logic module determines the corresponding net change in capacitor voltage based on the valid codewords K0, K1, K2, K3 of the interval and the current SIG_DAC switch state, generates the minimum necessary capacitor switching control codeword with the same net change in capacitor voltage, and passes the control codeword into SIG_DAC.

[0016] Capacitor array switching: After receiving the control codeword, SIG_DAC switches the corresponding weighted capacitors.

[0017] Repeated comparisons, equivalent net weight judgments, and capacitor array switching generate code values ​​D2 and D1 for each round; the final digital codeword is output after the conversion cycle ends.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. This invention does not change the normal binary weighted CDAC structure, and the LATCH codeword of this invention directly drives the capacitor array, which is compatible with the traditional SAR ADC capacitor array design, matching design and layout implementation.

[0020] 2. In a traditional 2-bit / cycle SAR ADC, three comparators output six quantized digital code values ​​(C1, C1B, C2, C2B, C3, C3B). These six codewords must first be latched using six latches, and then the decoding logic decodes the four-bit binary capacitor switching control code value. The capacitor switching control uses an absolute state mapping method based on the target code value. When the transition between adjacent quantization intervals involves an inverse combination of high-order and low-order capacitor switching, the traditional control logic executes the state flipping of each capacitor separately, failing to directly identify the equivalent net weight change corresponding to this combination switch. Directly omitting the high-order or low-order switching will result in an inconsistency between the total weight of the capacitor array and the target quantization state. Without refactoring the traditional decoding and capacitor control logic, the traditional structure cannot directly achieve jump switching.

[0021] This invention calculates a 4-bit interval codeword by operating on the 6-bit complementary outputs generated by three comparators. The interval codewords are paired into complementary codewords, and each pair can be latched using only one latch. That is, only two latches are needed to latch K0, K1, K2, and K3. This reduces the hardware overhead required for complete latching of the six-bit comparison codeword and subsequent decoding in the traditional 2-bit / cycle successive approximation analog-to-digital converter structure.

[0022] 3. This invention reconstructs the reverse combination switching of high-order capacitors and low-order capacitors into a switching of only the net value of the low-order capacitors by using jump switching control logic, thereby eliminating invalid capacitor switching actions and reducing the energy consumption of dynamic switching of capacitor arrays. It is especially suitable for scenarios in high-speed 2-bit / cycle SAR ADCs where intermediate code value switching occurs frequently. Attached Figure Description

[0023] Figure 1 The circuit diagram of a 2-bit / cycle SAR ADC based on skip switching is shown in the example.

[0024] Figure 2 This is a schematic diagram of the jump switching logic latch of the present invention;

[0025] Figure 3 This is a schematic diagram of a latch codeword direct-drive capacitor array as an example.

[0026] Figure 4 This diagram compares examples of switching between traditional switching logic and the jump switching logic of this invention. Detailed Implementation

[0027] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0028] In this embodiment, a 2-bit / cycle SAR ADC based on skip-switching is used, such as... Figure 1As shown in the diagram. The specific implementation employs four NOR gates and a jump-switching control logic circuit. The outputs of the three comparators are C1, C1B, C2, C2B, C3, and C3B. The four NOR gates are used to directly generate four-bit interval valid codewords K0, K1, K2, and K3 based on the complementary outputs of the three comparators. These four codewords represent the four quantization intervals of the current input signal. Compared to a typical 2-bit / cycle SAR ADC, it eliminates the need to first fully latch six complementary comparison codewords, reducing latching circuitry and eliminating the need for a complex decoder.

[0029] In this embodiment, the logical relationships of the four NOR gates are as follows: K0 = NOR(C1, C3); K1 = NOR(C2, GND); K2 = NOR(C2B, GND); K3 = NOR(C1B, C3B).

[0030] The jump switching control logic determines the actual net weight change in the switching path based on the valid codeword of the interval and the current switching state of the capacitor array. Taking adjacent binary weight capacitors 2X and X as an example, when the target capacitor change is +X, the traditional method generates a +2X change through the high-order capacitor and a -X change through the low-order capacitor, so that the two are superimposed to obtain a net change of +X. After identifying the net change, this invention no longer drives the high-order capacitor to perform a +2X switch, nor drives the low-order capacitor to perform a -X switch. Instead, it directly controls the small capacitor with weight X to switch in the forward direction, so that the capacitor array output produces the same net change of +X. Similarly, when the target capacitor change is -X, this invention directly controls the small capacitor with weight X to switch in the reverse direction, instead of performing the reverse combination switch of -2X and +X.

[0031] In this embodiment, the specific workflow of the 2-bit / cycle SAR ADC based on skip-switching is as follows:

[0032] Sampling phase: At the start of the conversion cycle, the sampling clock is valid, the sampling switch is turned on, the SIG_DAC module samples the input signal, and after sampling is completed, the sampling switch is turned off, and the upper plate of the SIG_DAC capacitor array retains the input charge.

[0033] Comparison: The jump switching control logic module controls the lower plate of the SIG_DAC capacitor array to switch, and at the same time controls the REF_DAC to generate two different comparison voltages. The three comparison voltages divide the total comparison range into four regions. Then, the comparator control clock CLKC becomes active, and the three comparators generate three comparison result codewords and three complementary codewords, forming a total of six comparator output codewords. After NOR gate logic operations, four-bit effective codewords of the K0, K1, K2, and K3 ranges are obtained, representing one of the four quantization ranges of the current input signal.

[0034] Equivalent Net Weight Judgment: The jump switching control logic module determines the net change in capacitor voltage corresponding to the traditional binary switching path based on the valid codewords K0, K1, K2, K3 and the current SIG_DAC state, and then transmits the control codeword to the capacitor array. As shown in Table 1, when the traditional control method requires reverse combination switching of high-order and low-order capacitors to obtain a certain net change, this invention shields the redundant actions in the reverse combination switching, retaining only the minimum necessary capacitor switching that can produce the same net change. Furthermore, the final jump switching control logic output control codeword only needs to be latched by two latches.

[0035] Table 1: Comparator Output Capacitor Switching Correspondence Table for Low Hardware Overhead Latching and Skip Switching Techniques

[0036]

[0037] Capacitor array switching: After receiving the control codeword, the SIG_DAC capacitor array switches the corresponding weighted capacitors. The 2-bit / cycle SAR ADC divides the quantization range into four intervals within each comparison cycle. If the signal falls within (1 / 2*Vref, 3 / 4*Vref), then... Figure 4 Traditional switching logic requires reversing the high-order capacitor (-2X) and reversing the low-order capacitor (+X) to obtain the target voltage (-X). Under the same conditions, the present invention does not switch the high-order capacitor, but reverses the low-order capacitor (-X), and the capacitor array ultimately obtains the same target voltage (-X).

[0038] Repeated comparisons, equivalent net weight determinations, and capacitor array switching generate code values ​​D2 and D1 for each round. The final digital codeword is output after the conversion cycle ends.

[0039] While maintaining the functionality of a traditional 2-bit / cycle successive approximation analog-to-digital converter (ADC), the power consumption reduction of this invention comes from two parts. First, it avoids the complete latching and complex decoding logic circuitry of the complementary output codewords of six comparators in the traditional structure, thus reducing the power consumption of dynamic switching in the control logic. Second, in a normal binary weighted capacitor array, when the traditional switching path obtains a net voltage change through the inverse combination of high-order and low-order capacitors, this invention directly switches the low-order capacitor required to generate the net change, reducing the number of charge-discharge cycles between the lower plate of the capacitor and the reference voltage. These two factors combined improve the energy efficiency of the 2-bit / cycle successive approximation ADC.

[0040] It should be noted that, yes, this invention includes... Figure 1The example provided illustrates a 2-bit / cycle SARADC structure implemented using a combination of REF DAC and SIG DAC. This example is solely for explaining the implementation process of the switching method of this invention and does not constitute a limitation on the applicable structure of this invention. Any SAR ADC structure that employs a multi-bit / cycle successive approximation conversion mechanism and can apply the switching logic described in this invention during comparison, sampling, capacitor array reallocation, or DAC switching processes is applicable to this invention. For example, a 2-bit / cycle SAR ADC composed of two SIG DACs or a multi-bit / cycle SAR ADC implemented using other equivalent capacitor arrays and comparison paths, as long as the switching process has the same or equivalent technical features in terms of function, timing, or implementation effect as the technical solution described in this invention, should fall within the protection scope of this invention.

Claims

1. A 2-bit / cycle SAR ADC based on skip switching, characterized in that, include: The module includes a sampling circuit module, a capacitor array module, a comparator module, and a jump switching control logic module. The sampling circuit module is responsible for sampling the continuously changing input signal. When the sampling signal CLKS is pulled high, the instantaneous voltage of the signal is sampled and held on the capacitor array module, and the sampling voltage is kept unaffected by the input signal throughout the entire subsequent conversion cycle. The capacitor array module is a charge redistribution type digital-to-analog converter, including a set of SIG_DAC and a set of REF_DAC. By switching the connection level of the lower plate of each capacitor, it generates an analog voltage corresponding to the control code value at the output terminal using the charge redistribution principle; SIG_DAC is a sampling capacitor array, and REF_DAC is a reference capacitor array. The comparator module consists of three comparators that compare the voltage on SIG_DAC with the voltage on REF_DAC, determine the signal amplitude range, generate three comparison result codewords and three complementary codewords, forming a total of six comparator output codewords C1, C1B, C2, C2B, C3, and C3B, and transmit the comparison results to the jump switching control logic module. The jump switching control logic module is based on a successive approximation state machine. It first generates four-bit effective codewords K0, K1, K2, and K3 directly based on the outputs of the three comparators and their complementary outputs. The four-bit codewords are used to represent the four quantization intervals in which the current input signal is located. Based on the valid codewords K0, K1, K2, K3 in the interval and the current SIG_DAC state, the actual net weight change in the switching path SIG_DAC is determined. Then, the high and low capacitor combination switching of SIG_DAC is reconstructed into low capacitor net value switching, and the control signal is latched. The latched control signal directly drives the SIG_DAC switching.

2. The 2-bit / cycle SAR ADC based on skip switching as described in claim 1, characterized in that: The four-bit interval valid codewords K0, K1, K2, and K3 in the jump switching control logic module are implemented using four NOR gate operations.

3. The 2-bit / cycle SAR ADC based on skip switching as described in claim 1, characterized in that, The method for determining the actual net weight change in the switching path based on the valid codewords in the interval and the current SIG_DAC state is as follows: For adjacent high and low binary weighted capacitors, the corresponding voltage change weights are 2X and X. When the target capacitor voltage change is +X: after identifying the net change, the capacitor with weight X is directly controlled to switch in the positive direction, so that the SIG_DAC voltage produces the same +X net change; similarly, when the target capacitor voltage change is -X, the capacitor with weight X is directly controlled to switch in the reverse direction.

4. The 2-bit / cycle SAR ADC based on skip switching as described in claim 1, characterized in that, The specific workflow is as follows: Sampling phase: At the start of the conversion cycle, the sampling clock is valid, the sampling switch is turned on, the SIG_DAC samples the input signal, and after sampling is completed, the sampling switch is turned off, and the upper plate of the SIG_DAC retains the input charge; Comparison: The jump switching control logic module controls the lower plate of SIG_DAC to switch, and at the same time controls REF_DAC to generate two different comparison voltages. The total comparison range is divided into four regions by the three comparison voltages generated by SIG_DAC and REF_DAC. Then, the comparator control clock CLKC becomes active, and the three comparators generate three comparison result codewords and three complementary codewords, forming a total of six comparator output codewords. After calculation, four-bit effective codewords of K0, K1, K2, and K3 are obtained, which represent the quantization range of the current input signal. Equivalent net weight judgment: The jump switching control logic module determines the corresponding net change in capacitor voltage based on the valid codewords K0, K1, K2, K3 in the interval and the current SIG_DAC state, generates the minimum necessary capacitor switching control codeword with the same net change in capacitor voltage, and passes the control codeword into SIG_DAC. Capacitor array switching: After receiving the control codeword, SIG_DAC switches the corresponding weighted capacitors; Repeated comparisons, equivalent net weight judgments, and capacitor array switching generate code values ​​D2 and D1 for each round; the final digital codeword is output after the conversion cycle ends.

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