Multirate sigma-delta ADC

Abstract

Multi-rate sigma-delta ADCs are disclosed. A sigma-delta ADC for processing an analog input signal and generating a sampled digital representation of the input signal, comprising: a continuous-time sub-circuit comprising an input integrator that receives the analog input signal and generates a first signal; a fast discrete-time sub-circuit operating at a first clock rate, receiving the first signal and generating a second signal; a slow-speed discrete-time sub-circuit operating at a second clock rate slower than the first clock rate, the slow-speed discrete-time sub-circuit comprising a quantizer that converts the second signal to a digital signal and a DAC that generates an analog feedback signal.

Description

Technical Field

[0001] This invention relates to the field of hybrid analog and digital electronic circuits, and more particularly to a low-power architecture that uses a Σ-Δ modulator to convert analog signals into digital representations. Background Technology

[0002] Many electronic applications involve converting analog signals into time series of digital samples. Compared to analog signal processing techniques and architectures, digital signal processing techniques and architectures typically offer better results at a lower cost, or consume less power and silicon surface area. A circuit specifically configured to accept analog signals as input and generate corresponding digital output signals is called an analog-to-digital converter (ADC). ADCs are used in countless electronic circuits and applications.

[0003] One important application of ADCs is in radio receivers, where they affect overall performance, sensitivity, and power consumption. ADCs are commonly used for signal recording and processing, including audio and video signals, and are essential for most measurement techniques.

[0004] Σ-Δ ADCs achieve this by applying Σ-Δ modulation to the input signal. This is an oversampling process that encodes the input signal into a low-bit digital signal (possibly a 1-bit signal) at a sampling frequency much higher than the Nyquist rate. Oversampling improves the signal-to-noise ratio (SNR). Σ-Δ converters use noise shaping techniques, which shift the spectral distribution of quantization noise to higher frequencies outside the region of interest. These methods result in even higher SNRs. Σ-Δ modulated signals can be used and processed as is, or converted into lower-rate code-modulated signals using known digital signal processing techniques such as decimation and filtering.

[0005] Continuous-time (CT) and discrete-time (DT) structures are known to be used in Σ-Δ converters and modulators, the latter typically employing switched-capacitor circuits.

[0006] EP 3104530 B1 and WO 2023 / 225655 A1 disclose two examples of Σ-Δ type digital modulators and converters. J. Gerardo Garcia-Sánchez and José M. de La Rosa, “Multirate Downsampling Hybrid CT / DT Cascade Sigma-Delta Modulators”, IEEE Transactions on Circuits and Systems, Vol. 59, No. 2, February 2012, pp. 285-294, disclose a hybrid cascaded CT / DT Σ-Δ type modulator in which the front-end stage operates at the highest rate. Summary of the Invention

[0007] The purpose of this invention is to provide a Σ-Δ ADC that combines the advantages of continuous-time Σ-Δ modulators with the advantages of discrete-time implementation, provides an inherent anti-aliasing filter, and overcomes other disadvantages and limitations of the prior art.

[0008] According to the invention, these objectives are achieved by the object of the appended claims, and in particular by a Σ-Δ type ADC for processing analog input signals and generating a sampled digital representation of the input signals, comprising: a continuous-time subcircuit including an input integrator that receives the analog input signal and generates a first signal; a fast discrete-time subcircuit that operates at a first clock rate, receives the first signal and generates a second signal; and a slow discrete-time subcircuit that operates according to a second clock rate slower than the first clock rate, the slow discrete-time subcircuit including a quantizer that converts the second signal into a digital signal and a DAC that generates an analog feedback signal.

[0009] Preferably, the fast discrete-time subcircuit includes at least one integrator and a block of switched capacitors timing at a first clock rate. One of the switched capacitor blocks samples and holds the signal provided to the integrator, which thus operates at a fast clock rate in discrete time. The combination of the first continuous-time input integrator followed by the discrete-time integrator produces a second-order Σ-Δ modulator, but this is not a limitation of the invention and also allows for higher-order implementations.

[0010] The ADC of the present invention can have a CRFB (cascaded feedback resonators) configuration, a CIFF (cascaded integrators with feedforward) configuration, or any other suitable topology.

[0011] Preferably, the second clock rate is derived from the first clock rate, or conversely, the ratio between the second clock rate and the first clock rate is fixed and determined. The slow clock can be generated by dividing the fast clock by an integer or fractional factor. In a typical example, the fast clock has a frequency of 32 MHz, and the slow clock is obtained by dividing (scaling) the fast clock by factors of 2, 4, 8, or more.

[0012] According to any one of the preceding claims, the Σ-Δ type ADC, wherein the fast discrete-time subcircuit includes a switched capacitor block timing at the first clock rate and the slow discrete-time subcircuit includes a switched capacitor block timing at the second clock rate.

[0013] The ADC of the invention can be configured to process single-ended or differential input signals. In the latter case, the associated analog signal is preferably differential. This can include a first signal generated by a first integrator stage and a second signal provided to a quantizer.

[0014] The ADC of the present invention is applicable to numerous applications, including digital radio receivers, comprising an antenna, a mixer that converts radio signals into lower frequency signals, the ADC, followed by decimation circuitry and a digital demodulator.

[0015] Compared to what is known in the art, this invention offers advantageous reductions in power consumption and complexity, as well as inherent anti-aliasing characteristics. The digital circuitry following the ADC operates at a reduced rate because the ADC output is timed by a slower clock; therefore, their power requirements and complexity are also reduced. Another advantage is that the ADC can be easily reconfigured as needed, for example, by changing the fast clock frequency and / or the scaling ratio between the fast and slow clocks. Attached Figure Description

[0016] Exemplary embodiments of the present invention are disclosed in the specification and illustrated in the accompanying drawings, in which: Figure 1 An example of an ADC with a CRFB (Refeedback Resonator Cascade) topology according to the present invention is illustrated schematically. Figure 2 This is a simplified schematic diagram of an ADC with a CIFF (cascaded integrator with feedforward) topology according to the present invention.

[0017] Figure 3 An ADC of the invention is shown for use in a digital radio receiver.

[0018] Figure 4 The differential implementation of the CRFB ADC of the present invention is illustrated schematically.

[0019] Prominent elements in the accompanying drawings are identified by the reference numerals used in the following written description. Identical, similar, or functionally equivalent elements may be identified by the same reference numerals. When a drawing contains several identical, similar, or functionally equivalent elements, some reference numerals may be omitted for clarity. Detailed Implementation

[0020] Figure 1 An example of a Σ-Δ ADC 200 with a second-order CRFB topology according to the present invention is shown. The invention is not limited to this particular implementation and can be extended to higher-order and other types of Σ / Δ topologies, such as CIFF, CIFB (cascaded feedback integrator), etc. The input stage 100 of the ADC is an integrator operating in continuous time, including an integrator stage 40. This configuration inherently provides useful filtering of the input signal.

[0021] The signal 151 generated by the first integrator is provided to the discrete-time sub-circuit 120, which is synchronized by a clock CK, the frequency of which will be determined by the application requirements. For example, it could be 32 MHz. The clock CK will be referred to as a "fast" clock in this disclosure, relative to the "slow" clock CK2, which will be described later. The labels "first" and "second" will also be used to designate clocks CK and CK2.

[0022] In the fast sub-circuit 120, the second integrator 65 of the ADC operates in discrete time according to a fast clock CK applied to the switched capacitor block 107. Unit 107 introduces a scaling factor "a" into the signal applied to the second integrator stage 65.

[0023] The ADC200 also includes two additional switched capacitor blocks 115 and 116, which operate at the same rate as capacitor block 107 and are preferably timed by the same clock signal. They respectively feed the output of the second integrator to the summing node before the first and second integrators. The scaling factor introduced by the switched capacitor blocks... g and- g 2 The definitions of the signal transfer function and noise transfer function that affect the ADC, especially the definition of its zeros, will be explained below. These values ​​also depend on the in-band noise suppression required for a given decimation rate.

[0024] The output of the second integrator is applied to the quantizer 80. Importantly, the quantizer 80 operates in discrete time with a slow clock CK2, characterized by a frequency lower than that of the fast clock CK. The second clock signal CK2 can be obtained from the first clock signal through simple integer or fractional division. The clock frequency CK2 of the quantizer can be modified based on the signal bandwidth and dynamic characteristics required by the target application.

[0025] The quantizer 80 may have, for example, a successive approximation architecture (SAR) and a bit depth of 8 to 11 bits, but these are not essential requirements of the present invention. Preferably, to improve system linearity, the quantizer 80 preferably has a second auxiliary input to accept dithering code D added to the quantizer input at a reduced rate CK2. The dithering code is a pseudo-random code with the same bit width as the quantizer output. The purpose is to improve the linearity of the ADC by utilizing different parts of the ADC.

[0026] The digital signal generated by the quantizer is also converted back to the analog feedback signal 155 by the DAC unit 85, which also operates in discrete time with the same reduced clock CK2 as the quantizer 80. The resulting analog signal is also fed back to the inputs of the first and second integrators via two switched capacitor blocks 101 and 102, which are also timed by the reduced clock CK2. These blocks introduce scaling factors -1 and -b, respectively. These factors contribute to the definition of the noise and signal transfer function, which will be discussed later. The invention is not limited to this choice of coefficients, and the factor associated with block 101 can be different from -1 if desired.

[0027] It is worth noting that the scaling factor g,g 2 ,b,1 Implemented by switched capacitor blocks 115, 116, 102, and 101, the gains of integrating amplifiers 40 and 65 are also determined by the capacitance of their respective feedback networks (not shown in the figure). Therefore, the transfer function of the invented ADC is primarily determined by the capacitance ratio, which is highly insensitive to process variations. Consequently, the ADC of this invention requires little or no calibration / fine-tuning to operate at the intended specifications. Preferably, for the same purpose, the DAC85 also uses capacitors (it is a capacitive DAC or CDAC).

[0028] It is important to note that the device of the present invention has different blocks operating at different rates. The figure identifies a continuous-time sub-circuit 100, a fast discrete-time sub-circuit 120 synchronized with a fast clock signal CK, and a slow discrete-time sub-circuit 140 synchronized with a slow clock signal CK2. The continuous-time input stage 100 inherently provides an anti-aliasing filter, as in a continuous-time Σ-Δ modulator. Furthermore, the second integrator operates at a much higher rate than the quantizer and feedback DAC85, and this oversampling also helps reduce aliasing of out-of-band signal components. Moreover, because the first integrator operates in continuous time while the second integrator operates at a higher clock frequency than the quantizer, the anti-aliasing characteristics are well maintained.

[0029] Assuming the second integrator operating at a higher rate than the quantizer can be considered a continuous-time integrator with respect to quantization noise, the noise transfer function of the proposed device can be analyzed. The noise transfer function (NTF) can be expressed as given by the following equation. in z This corresponds to the sampling rate CK2.

[0030] Applying the Laplace transform ( s domain) and z Relationship between transformations The signal transfer function (STF) can be written as in z 1 This corresponds to the full sampling rate CK of the fast discrete-time subcircuit 120. It should be noted that if the slow clock CK2 is derived from the fast clock, the integer divided by the quotient... N ,So .

[0031] STF uses continuous-time variables corresponding to the contributions of continuous-time sub-circuit 100. s Discrete variables of the contribution of the second integrator z 1 Discrete variables of slow discrete-time sub-circuit 140 z This is represented by the novel feature of the device, which has reaction loops operating at different rates.

[0032] As described above, the present invention is not limited to the CRFB architecture. Figure 2 A CIFF (cascaded integrator with feedforward) implementation of the present invention is shown. Input stage 100 is a time-continuous integrator, as in the previous example, but using a feedforward loop to synthesize the desired NTF and STF. In this example, the fast discrete-time subcircuit 120 includes a second discrete-time integrator implemented with switched capacitor block 107 and integrator 65. Its output is combined with the input signal by block 122 and with the first integration signal by block 124 before being presented to quantizer 80, which operates at a reduced clock rate CK2 in slow discrete-time subcircuit 140, similar to SDAC85 and switched capacitor block 101. As in the previous example, this embodiment has two integration stages; however, the present invention also allows for higher-order implementations.

[0033] Figure 4 This is another schematic representation of the CRFB ADC according to the present invention, showing a differential architecture. Integrating amplifiers 40 and 65 are implemented by fully differential operational amplifiers with feedback capacitors, and switched capacitor blocks 101, 102, 115, 116, and 107 are also drawn as examples of internal circuitry. However, other methods of implementing these functions are also available.

[0034] Figure 3The possible use of the invented ADC 200 in a radio receiver is illustrated. The radio signal received by antenna 210 and amplified by low-noise amplifier 220 is converted into a lower-frequency signal in mixer 230 and digitized by ADC 200. Advantageously, ADC 200 inherently implements analog anti-aliasing. Its output is provided to digital receiver stage 280, where samples from ADC 200 can be digitally decimated and / or filtered in block 240 and demodulated. Since the output of ADC 200 is already timed at a rate CK2 that is considerably lower than the internal rate CK, the power consumption of digital block 280 is significantly reduced.

[0035] Reference symbols in the attached figure 40 Integrator 65 Integrator 80 quantizer 85 CDAC 100 continuous-time sub-circuit 101 Switched Capacitor Block 102 Switched Capacitor Block 107 Switching Capacitor Block 115 Switching Capacitor Block 116 Switched Capacitor Block 118 Switching Capacitor Block 120 Fast Discrete-Time Subcircuit 122 Switched Capacitor Block 124 switched capacitor block 140 slow discrete-time sub-circuits 151 First Signal 152 Second Signal 155 Feedback Signal 200 ADC 210 antenna 220 Low Noise Amplifier 230 mixer 240 Decimation Filter 258 demodulation 280 digital receiving unit.

Claims

1. A multi-rate continuous-time and discrete-time Σ-Δ ADC for processing analog input signals and generating sampled digital representations of the input signals, comprising: - A continuous-time sub-circuit, including an input integrator that receives an analog input signal and generates a first signal. - A fast discrete-time subcircuit that operates at a first clock rate, receives a first signal, and generates a second signal. - A slow discrete-time sub-circuit operating at a second clock rate slower than the first clock rate, the slow discrete-time sub-circuit including... - A quantizer converts the second signal into a digital signal. - DAC, generates analog feedback signals.

2. The Σ-Δ ADC according to claim 1, comprising a switched capacitor block, operating at a second clock rate, and feeding back an analog feedback signal to an input integrator.

3. The Σ-Δ ADC according to claim 1, wherein the fast discrete-time sub-circuit includes at least one integrator.

4. The Σ-Δ ADC according to claim 1, configured with CRFB or CIFF.

5. The Σ-Δ type ADC according to claim 1, wherein the input signal, the first signal, and the second signal are differential signals.

6. The Σ-Δ ADC of claim 1, wherein the second clock rate is derived from the first clock rate, or conversely, such that the ratio between the second clock rate and the first clock rate is fixed and determined.

7. The Σ-Δ ADC of claim 1, wherein the fast discrete-time subcircuit includes a switched capacitor block timing at a first clock rate, and the slow discrete-time subcircuit includes a switched capacitor block timing at a second clock rate.

8. A digital radio receiver, comprising an antenna, a mixer for converting radio signals into lower frequency signals, an ADC according to any one of the preceding claims, a decimation circuit, and a digital demodulator.

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