Multi-bit parallel encoder based on superconducting junction switch and switching encoding method thereof

Abstract

The application discloses a kind of multi-bit parallel encoders based on superconducting junction switch and switching encoding method, belong to superconducting integrated circuit technical field;The encoder includes bias signal generation module, signal input module to be measured, the superconducting encoding array consisting of multiple Josephson junctions with gradient critical current threshold, and RL transmission filter module and SQUID reading module;System utilizes square wave bias current to control the working state of Josephson junction, when the total current superimposed with the analog signal to be measured exceeds the critical current of a branch Josephson junction, the junction flips to voltage state, and the current is shunted to RL transmission filter module;RL module utilizes its low-pass filter characteristics, attenuates the high-frequency oscillation noise generated by Josephson junction by more than 40dB, and drives SQUID to output corresponding digital logic level;The application realizes in-situ analog-digital conversion in low-temperature environment, with the characteristics of high integration, low power consumption and high signal-to-noise ratio.

Description

Technical Field

[0001] This invention belongs to the field of superconducting electronics and integrated circuit technology, and relates to a multi-bit parallel encoder based on superconducting junction switching and its switching encoding method. Specifically, it relates to a device and its switching and encoding methods for realizing analog signal digital encoding (ADC) using the nonlinear switching characteristics of Josephson junction (JJ). Background Technology

[0002] In the fields of superconducting quantum computing, radio astronomy observation, and ultra-low temperature precision measurement, signal readout and processing are typically performed in ultra-low temperature environments (mK temperature range). To achieve data acquisition, traditional methods usually transmit the analog signal acquired at the cryogenic end to the room temperature end via a long cable for analog-to-digital conversion (ADC).

[0003] However, analog signals are inherently less resistant to interference. During long-distance transmission across temperature zones, they are highly susceptible to coupling and interference from environmental electromagnetic noise, leading to a severe deterioration in the signal-to-noise ratio. In contrast, digital signals possess naturally strong anti-interference capabilities and high stability. If digitization can be completed directly at low temperatures, high-fidelity data transmission can be achieved with an extremely low bit error rate.

[0004] Unfortunately, existing room-temperature digitization solutions rely heavily on coaxial cables to transmit fragile analog signals, which not only introduces persistent noise interference but also incurs significant heat loads and wiring complexity. Therefore, given the limitations of analog transmission, it is necessary to further investigate how to achieve small-area, high-speed, low-power, and low-noise superconducting switches to advance cryogenic in-situ ADC technology.

[0005] Therefore, developing a superconducting ADC chip capable of operating directly in low-temperature environments with low power consumption and high speed is particularly important. Existing superconducting digital circuit technologies (such as RSFQ), while fast, have high static power consumption, making large-scale integration difficult. Traditional SQUID-based interferometric switches, while low in power consumption, have large loop areas, limiting device integration density. By utilizing the Josephson junction's critical current characteristics as a natural threshold comparator, combined with the filtering function of an RL circuit, a compact, fast-responding, and extremely low-noise multi-bit parallel encoder can be constructed.

[0006] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a multi-bit parallel encoder based on a superconducting junction switch and a switching and encoding method to solve the problems of large size, high power consumption and difficulty in suppressing high-frequency noise in existing low-temperature readout technology.

[0008] To achieve the above objectives, this invention provides a multi-position parallel encoder based on a superconducting junction switch, comprising: a bias signal generation module, a test signal input module, a superconducting encoding array, an RL transmission filter module, a SQUID readout module, and a signal processing module. The superconducting encoding array consists of k parallel encoding branches (k≥1). The core of each encoding branch is a Josephson junction unit with a specific critical current value. The square wave bias current generated by the bias signal generation module is connected to all encoding branches as the system's clock signal. The test signal input module introduces an analog signal current into the encoding array. The RL transmission filter module is connected in parallel with the Josephson junction and consists of a series transmission resistor Rin and a transmission coil Lin.

[0009] To solve the above-mentioned technical problems and achieve the above-mentioned and other related objectives, the present invention provides a technical solution for a multi-bit parallel encoder based on a superconducting junction switch as follows:

[0010] A multi-bit parallel encoder based on a superconducting junction switch is characterized by comprising: a bias signal generation module, a signal input module, a superconducting encoding array, an RL transmission filter module, a SQUID readout module, and a signal processing module; wherein the superconducting encoding array consists of k parallel encoding branches, where k is a natural number greater than or equal to 1.

[0011] The k Josephson junction units in the superconducting coded array are configured with a gradient-distributed critical current threshold. And satisfy This allows for the formation of a multi-level quantization ladder targeting the amplitude of the analog current signal under test.

[0012] The bias signal generation module is connected to the input terminal of the superconducting coding array and outputs a square wave bias current to control the working state of the Josephson junction unit in the superconducting coding array.

[0013] The signal input module is connected in parallel with the superconducting encoding array to input the analog current signal to be measured into the superconducting encoding array;

[0014] Each coding branch of the superconducting coding array contains a Josephson junction unit that serves as a threshold comparator.

[0015] The SQUID readout module contains k SQUID devices corresponding to the number of encoded branches. Each SQUID device is connected to its corresponding transmission coil L via mutual inductance. in coupling;

[0016] The output of the SQUID readout module is connected to the signal processing module to convert the sensed magnetic flux signal into a digital logic level output.

[0017] A further technical solution of the multi-bit parallel encoder based on a superconducting junction switch of the present invention is as follows:

[0018] Furthermore, the k Josephson junction units in the superconducting coded array are configured with a gradient-distributed critical current threshold. And satisfy When the amplitude of the simulated current signal under test superimposed on the square wave bias current changes, the Josephson junctions of different branches successively flip from the zero-resistance superconducting state to the finite-resistance voltage state, forming a multi-level quantization ladder for the signal amplitude.

[0019] Furthermore, the RL transmission filtering module constitutes a first-order low-pass filter with a cutoff frequency of Due to the transmission resistance R in and transmission coil L in Decision, satisfaction The cutoff frequency It is configured to be much smaller than the characteristic oscillation frequency of the Josephson junction element in the finite resistance voltage state. ( ),satisfy This ensures that the attenuation of the AC Josephson high-frequency oscillation noise in the readout circuit is greater than 40dB.

[0020] Furthermore, the Josephson junction unit and the RL transmission filter module are integrated on the same substrate; the Josephson junction adopts an Nb / Al-AlOx / Nb or Al / Al-AlOx / Al stacked structure; the transmission resistance R... in Pd or Mo metal thin film resistors are used.

[0021] Furthermore, the Josephson junction unit and the RL transmission filter module adopt a common substrate vertical integration structure, which includes a Si substrate layer and a SiO2 film layer from bottom to top; on one side of the SiO2 film layer, a Josephson junction bottom electrode, an Al-AlOx barrier layer, and a Josephson junction top electrode are stacked sequentially, and on the other side, a transmission resistor R is formed by a metal resistance film layer. in A superconducting wiring layer is also prepared above the SiO2 film to form a transmission coil L. in The interconnections between modules and the insulation isolation layers between functional layers are also provided.

[0022] To solve the above technical problems, the technical solution of the switching and encoding method for the multi-bit parallel encoder based on superconducting junction switches of the present invention is as follows:

[0023] The signal switching and encoding method performed by the multi-bit parallel encoder is characterized in that the method comprises: in the sampling phase, the square-wave bias current is at a high level: if the total current obtained by superimposing the analog current signal to be measured in a certain encoding branch exceeds the critical current of the Josephson junction unit in this branch , the Josephson junction unit instantaneously switches to a finite-resistance voltage state, the analog current signal to be measured is shunted into the parallel RL transmission filtering module, and drives the corresponding SQUID device to output a logic high level; in the reset phase, the square-wave bias current is at a low level: the Josephson junction units of all encoding branches recover to the zero-resistance superconducting state, the analog current signal to be measured is short-circuited by the Josephson junction units, the current in the RL transmission filtering module decays to zero, and the corresponding SQUID device outputs a logic low level.

[0024] A further technical solution of the switching and encoding method for the multi-bit parallel superconducting encoder based on superconducting junction switches of the present invention is as follows:

[0025] Further, in the sampling phase, when the Josephson junction unit is in the finite-resistance voltage state, that is, when the dynamic resistance is present, the effective signal current flowing through the RL transmission filtering module and coupled to the SQUID device has a transfer function of ; where, is the analog current signal to be measured, is the signal angular frequency, and j is the imaginary unit.

[0026] The encoding mechanism of the present invention can be analogous to a full-parallel (Flash) analog-to-digital converter in classical semiconductor electronics. In a classical Flash ADC, a resistor voltage dividing network is typically used to generate a series of gradient-distributed reference voltages, and the input voltage is compared in parallel with these reference voltages through a plurality of comparators. Correspondingly, the present invention innovatively uses the critical current characteristic of the Josephson junction to replace the reference voltage in classical circuits. Each Josephson junction in the superconducting encoding array serves as both a sampling switch and a high-sensitivity current threshold comparator. By setting gradient-distributed critical current thresholds (I_c1<I_c2<⋯<I_ck), the system can directly perform "Thermometer Code" type parallel quantization on analog signals in the current domain without requiring a complex voltage reference source, thereby significantly reducing the complexity and power consumption of the circuit.

[0027] The working principle of the present invention is as follows: Josephson junctions with different critical currents (I_c1<I_c2<⋯<I_ck) are used to form a gradient threshold array. After the input analog signal is superimposed with the bias current, according to the magnitude of the total current, the Josephson junctions in different branches will sequentially switch from the zero-resistance superconducting state to the finite-resistance voltage state. The junction in the voltage state will "squeeze" the current into the parallel RL transmission filtering module, which is coupled to the SQUID through the transmission coil, thereby outputting a digital code representing the signal amplitude. At the same time, the RL module utilizes its low-pass filtering characteristic to filter out high-frequency oscillation noise generated when the Josephson junction switches.

[0028] The present invention provides a multi-bit parallel superconducting encoder based on superconducting junction switches, and a switching and encoding method. Compared with the prior art, the present invention has the following features and beneficial effects:

[0029] 1. The present invention uses a single micro-nano scale Josephson junction as a comparator. Compared with the traditional SQUID comparator, the area is greatly reduced, which is beneficial to realize large-scale integration of multi-bit parallel encoding.

[0030] 2. The RL transmission filtering module of the present invention effectively attenuates the quantum oscillation noise of the Josephson junction up to hundreds of GHz by more than 40dB, ensuring a high signal-to-noise ratio of the output digital signal.

[0031] 3. The Josephson junction of the present invention has a picosecond-level switching speed, supporting a sampling rate above GHz; and it is in a superconducting state in the non-switching state, with extremely low static power consumption. Brief Description of the Drawings

[0032] Figure 1 is an overall structural block diagram of a multi-bit parallel superconducting encoder according to an embodiment of the present invention.

[0033] Figure 2 is the principle diagram (left) and the switching operation mode diagram (right) of the Josephson junction switching unit in the embodiment of the present invention.

[0034] Figure 3 is a detailed circuit schematic diagram (left) and a switching operation mode diagram (right) of a 3-bit parallel superconducting encoder based on a gradient threshold according to an embodiment of the present invention.

[0035] Figure 4 is a longitudinal cross-sectional structural diagram of an integrated Josephson junction and RL transmission filtering module in an embodiment of the present invention.

[0036] Figure 5 is a schematic diagram of signal timing logic according to an embodiment of the present invention.

[0037] The parts indicated by the reference numerals in each figure are as follows:

[0038] 11 Bias signal generation module 12 Josephson knot 120 Si substrate 121 <![CDATA[SiO₂ film layer]]> 122 bottom layer 123 <![CDATA[Al-AlO x Layers 124 Top floor 125 Wiring layer 126 isolation layer 13 Input module of signal under test 14 RL transmission module 140 Pd resistive film <![CDATA[R in ]]> Transmission resistance <![CDATA[L in ]]> Transmission coil 15 SQUID magnification module 16 Signal processing module 17 coaxial cable 18 Low-temperature superconducting cables Detailed Implementation

[0039] The present invention will be further described in detail below with reference to the accompanying drawings.

[0040] This invention relates to a multi-bit parallel encoder based on a superconducting junction switch, comprising: a bias signal generation module, a signal input module, a superconducting encoding array, an RL transmission filter module, a SQUID readout module, and a signal processing module; wherein, the superconducting encoding array consists of k parallel encoding branches, where k is a natural number greater than or equal to 1; the k Josephson junction units in the superconducting encoding array are configured with gradient-distributed critical current thresholds. And satisfy To form a multi-level quantization ladder for the amplitude of the analog current signal under test; the bias signal generation module is connected to the input of the superconducting encoding array and outputs a square wave bias current to control the working state of the Josephson junction unit in the superconducting encoding array; the signal under test input module is connected in parallel with the superconducting encoding array to input the analog current signal under test to the superconducting encoding array; each encoding branch of the superconducting encoding array contains a Josephson junction unit as a threshold comparator; the SQUID readout module contains k SQUID devices corresponding to the number of encoding branches, and each SQUID device is connected to the corresponding transmission coil L through mutual inductance. in Coupling; the output of the SQUID readout module is connected to the signal processing module to convert the sensed magnetic flux signal into a digital logic level output.

[0041] The k Josephson junction units in the superconducting coded array are configured with a gradient-distributed critical current threshold. And satisfy When the amplitude of the simulated current signal under test superimposed on the square wave bias current changes, the Josephson junctions of different branches successively flip from the zero-resistance superconducting state to the finite-resistance voltage state, forming a multi-level quantization ladder for the signal amplitude.

[0042] The RL transmission filter module constitutes a first-order low-pass filter, with a cutoff frequency of Due to the transmission resistance R in and transmission coil L in Decision, satisfaction Cutoff frequency Configured to a frequency much smaller than the characteristic oscillation frequency of the Josephson junction element in the finite resistance voltage state. ( ),satisfy This ensures that the attenuation of AC Josephson high-frequency oscillation noise in the readout circuit is greater than 40dB.

[0043] The Josephson junction unit and the RL transfer filter module are integrated on the same substrate; the Josephson junction adopts an Nb / Al-AlOx / Nb or Al / Al-AlOx / Al stacked structure; the transfer resistance R in Pd or Mo metal thin-film resistors are used. The Josephson junction unit and RL transmission filter module adopt a common substrate vertical integration structure, which includes a Si substrate layer and a SiO2 film layer from bottom to top. On one side of the SiO2 film layer, a Josephson junction bottom electrode, an Al-AlOx barrier layer, and a Josephson junction top electrode are stacked sequentially. On the other side, a transmission resistor R composed of a metal resistor film layer is formed. in A superconducting wiring layer is also prepared above the SiO2 film to form the transmission coil L. in The interconnections between modules and the insulation isolation layers between functional layers are also provided.

[0044] This invention utilizes a signal switching and encoding method based on a multi-bit parallel encoder with a superconducting junction switch, comprising: During the sampling phase, the square wave bias current is high: if the total current in a coding branch after superimposing the simulated current signal to be measured exceeds the critical current of the Josephson junction unit in that branch, the Josephson junction unit instantaneously switches to a finite resistance voltage state, and the simulated current signal to be measured is shunted and input to the parallel RL transmission filter module, driving the corresponding SQUID device to output a logic high level; during the reset phase, the square wave bias current is low: the Josephson junction units of all coding branches return to a zero-resistance superconducting state, the simulated current signal to be measured is short-circuited by the Josephson junction unit, the current in the RL transmission filter module decays to zero, and the corresponding SQUID device outputs a logic low level. During the sampling phase, when the Josephson junction unit is in a finite resistance voltage state, i.e., the dynamic resistance is , the effective signal current flowing through the RL transmission filter module and coupled to the SQUID device... The transfer function is ;in, The simulated current signal to be measured. ω is the signal angular frequency, and j is the imaginary unit.

[0045] The following specific examples illustrate the implementation of the present invention. Please refer to [link / reference]. Figures 1 to 5 .

[0046] This embodiment uses a 3-bit parallel superconducting encoder 1 as an example to fully illustrate the hardware composition, module interconnection, and unified working logic of the entire device. The entire device is referred to as superconducting encoder 1, or simply encoder. The entire superconducting encoder 1 consists of six core modules: bias signal generation module, under-measure signal input module, superconducting encoding array, RL transmission filtering module, SQUID readout module, and signal processing module. The superconducting encoding array contains multiple parallel encoding branches, each configured with one Josephson junction unit as a threshold comparator; the bias signal generation module outputs a square wave bias current as a global timing clock; the under-measure signal input module is connected in parallel to the array input terminal, superimposed with the under-measure analog current signal; each branch's Josephson junction unit is connected in parallel with a set of transmission filtering modules to complete noise filtering; the SQUID readout module reads the filtered signal through magnetic coupling and outputs a logic level; the signal processing module converts the thermometer code into a standard binary code output. The entire device is divided into two main working timing stages: sampling and reset, relying on the RL transmission filtering module to suppress AC Josephson high-frequency oscillation noise.

[0047] like Figure 1 As shown, Figure 1 This is a block diagram of the overall structure of the multi-parallel superconducting encoder 1 according to an embodiment of the present invention, fully demonstrating the electrical connection relationship of the six core modules of the entire device. The entire superconducting encoder 1 consists of a bias signal generation module 11, a test signal input module 13, a superconducting encoder array, an RL transmission filter module 14, a SQUID readout module 15, and a signal processing module 16. The two signals from the bias signal generation module 11 and the test signal input module 13 are fed into the superconducting encoder array. Each branch of the superconducting encoder array is connected in parallel to the RL transmission filter module 14. The RL transmission filter module 14 is magnetically coupled to the SQUID readout module 15. The SQUID readout module 15 outputs a digital level to the signal processing module 16, and finally the signal processing module 16 outputs the encoded signal to the outside through a cable.

[0048] like Figure 2 As shown, Figure 2 This diagram illustrates the principle (left) and switching operation mode (right) of the Josephson junction unit 12 switching unit in this embodiment of the invention. The left side shows the basic circuit topology of a single coded branch. The square wave bias current and the analog current signal to be measured are superimposed and then connected to the Josephson junction unit 12. The Josephson junction unit 12 is connected in parallel with the transmission resistor R. in Transmission coil L in The RL transmission filter circuit consists of a transmission coil and a SQUID device that are mutually inductively coupled. The right side shows two operating timing sequences: sampling high level and reset low level, which can intuitively demonstrate the complete workflow of single-branch threshold comparison, shunt filtering, and magnetic flux readout.

[0049] like Figure 4As shown, the core components in this embodiment—the Josephson junction unit 12 and the RL transmission filter module 14—are fabricated using integrated micro-nano technology. The fabrication process includes: providing a Si substrate 120 and growing a SiO2 film 121 on the Si substrate 120; sequentially growing a Josephson junction bottom electrode 122, an Al-AlOx barrier layer 123, and a Josephson junction top electrode 124 on one end of the SiO2 film 121; forming a Josephson junction unit 12 with a precise area (the junction area determines the critical current) through photolithography and etching processes; and growing a Pd resistor film 140 on the other end of the SiO2 film 121 to form a transmission resistor R connected in parallel with the Josephson junction unit 12. in ; Grow a superconducting wiring layer 125 to form a transmission coil L in .

[0050] like Figure 3 As shown, this embodiment constructs a 3-bit parallel superconducting encoder 1, containing three parallel encoding branches, corresponding to the "low bit," "middle bit," and "high bit" of the output logic, respectively. The key design element is the three Josephson junctions. The critical current is set as a gradient sequence, satisfying For example, setting The bias signal generation module 11 provides a high-speed square wave bias current with a frequency in the GHz range. (High level set to) The analog current signal to be measured is introduced into the signal input module 13. .

[0051] The switching and encoding method of the multi-bit parallel encoder of the present invention is as follows:

[0052] This method uses a square wave bias current as the global switching control signal. The core is to drive the Josephson junction units of each coding branch to switch rapidly between a zero-resistance superconducting state and a finite-resistance voltage state, simultaneously realizing the switching of the signal transmission path, the switching of the sampling and reset working modes, and completing the parallel quantization encoding of the simulated current under test based on the real-time switching status of each branch.

[0053] Sampling phase ( (High level): At this time, the total bias current flowing through the encoding array is If the input is the analog current signal to be measured... Then the total current Greater than and But smaller than . result: and Flip to the finite resistance voltage state, Maintaining a zero-resistance superconducting state. The corresponding SQUID 1 and SQUID 2 outputs a high level, and SQUID 3 outputs a low level. The encoded output is "011" (indicating the signal is at an intermediate level). If the input analog signal... Increase, causing the total current to exceed ,but Also flip it, outputting "111". Conversely, if The current is negative, so that the total current is less than And greater than , Flip to the finite resistance voltage state, and Maintaining a zero-resistance superconducting state. The corresponding SQUID 1 output is high, and SQUID 2 and SQUID 3 output are low. The encoded output is "001". If the input is the analog current signal to be measured... Continue to decrease, so that the total current is less than Then all Josephson junction units remain in a zero-resistance superconducting state, outputting "000". This achieves the conversion of continuously changing analog signals into discrete digital codes. It should be noted that the logic levels directly output by the superconducting encoding array are thermometer codes. Taking the three encoding branches in this embodiment as an example, as the input signal current increases, the output states are '000', '001', '011', and '111' respectively. For compatibility with general digital systems, the signal processing module needs to include a priority encoding logic to convert the above thermometer codes into standard binary two's complement.

[0054] The specific truth table mapping for converting a three-dimensional array to a two-dimensional array is as follows:

[0055] State 0: Input The original output 000 corresponds to the binary code 00;

[0056] State 1: The original output 001 corresponds to the binary code 01;

[0057] State 2: The original output 011 corresponds to the binary code 10;

[0058] State 3: The original output 111 corresponds to the binary code 11.

[0059] Furthermore, the architecture of this invention has good scalability. To achieve n-bit binary precision output, according to the architecture principle of Flash ADCs, the number k of required superconducting coding branches (i.e., Josephson junction comparators) must satisfy the formula:

[0060]

[0061] For example, achieving 4-bit binary precision requires 15 parallel branches; achieving 8-bit precision requires 255 parallel branches. This parallel architecture ensures that the system's sampling rate is not significantly affected when increasing the bit width.

[0062] To further reduce the thermal load on the cryogenic system, in a preferred embodiment of the present invention, the signal processing module (particularly the priority encoding logic for performing thermometer code to binary code conversion) can be implemented using superconducting digital logic circuits and integrated with the superconducting encoding array on the same cryogenic chip. Through this on-chip integration scheme, for The encoder has a depth of 10 bits, and the number of output cables from low temperature to room temperature can be increased from [number missing]. The number of roots (thermometer codes) has been significantly reduced to The root (binary code) is used to minimize the wiring complexity and heat leakage of the system.

[0063] Reset phase ( (Low level): The bias current returns to zero, and all Josephson junction units instantly return to the zero-resistance superconducting state. The energy in the RL loop is discharged, the system is reset, and it prepares for sampling in the next clock cycle.

[0064] Theoretical analysis of noise suppression:

[0065] To effectively suppress the AC Josephson Effect noise generated by the Josephson junction under voltage conditions, this invention designs a compact and integrated RL transmission filter module.

[0066] The RL module mainly consists of a transmission resistor ( ) and a transmission inductor ( Composed of several components, these elements are connected in series with the SQUID readout coil in the circuit topology, and together they form a parallel shunt structure with the Josephson junction unit, which acts as a switch. This RL structure essentially constitutes a first-order low-pass LR filter. The high-frequency oscillations generated by the Josephson junction (typically in the range of 100 GHz to 1 THz) act as interference sources, "seeing" a large inductive impedance in the transmission path, thus being confined within the local loop of the Josephson junction unit; while the low-frequency or DC analog signals containing the information to be measured (typically below GHz) experience very little inductive impedance and can pass through without loss. and Coupled to the SQUID device.

[0067] Based on this physical model, its cutoff frequency Defined as the impedance matching point, which satisfies:

[0068]

[0069] Set transmission resistance Transmission coil ,but .

[0070] Theoretical calculations show that: at this time ( Approximately (6000 times that of the first-order filter). Based on the characteristics of the first-order filter, the attenuation A of the high-frequency noise is:

[0071]

[0072] This attenuation is much greater than the 40 dB claimed in the claims. Therefore, the flow through the transmission coil L in and the current coupled to the SQUID device It is a smooth DC pulse (such as) Figure 5 As shown in the timing diagram, the high-frequency oscillation noise of AC Josephson is effectively filtered out, ensuring the readout accuracy of the encoder.

[0073] like Figure 5 As shown, in the sampling phase ( (High level), a voltage is generated across the Josephson junction. This voltage contains severe AC Josephson high-frequency oscillation noise (as shown in the second row of the figure). After passing through the RL transmission filter module of this invention, the current flowing through the transmission coil... (As shown in the third row of the figure) The signal is presented as a smooth signal, and the high-frequency oscillation noise of AC Josephson is effectively filtered out, thereby ensuring the stability of the SQUID device readout.

[0074] In summary, this invention provides a multi-position parallel superconducting encoder 1 based on a superconducting junction switch, which has advantages such as compact structure, high integration, and low noise. Through a process-integrated gradient threshold Josephson junction unit array and an RL transmission filter network, in-situ signal digitization under extremely low temperature conditions is achieved.

[0075] The above embodiments are merely illustrative of the technical solutions, principles, and effects of the present invention, and are not intended to limit the present invention.

Claims

1. A multi-position parallel encoder based on a superconducting junction switch, characterized in that, include: The system comprises a bias signal generation module, a test signal input module, a superconducting encoding array, an RL transmission filter module, a SQUID readout module, and a signal processing module; wherein the superconducting encoding array consists of k parallel encoding branches, where k is a natural number greater than or equal to 1. The k Josephson junction units in the superconducting coded array are configured with a gradient-distributed critical current threshold. And satisfy This allows for the formation of a multi-level quantization ladder targeting the amplitude of the analog current signal under test. The bias signal generation module is connected to the input terminal of the superconducting coding array and outputs a square wave bias current to control the working state of the Josephson junction unit in the superconducting coding array. The signal input module is connected in parallel with the superconducting encoding array to input the analog current signal to be measured into the superconducting encoding array; Each coding branch of the superconducting coding array contains a Josephson junction unit that serves as a threshold comparator. The SQUID readout module contains k SQUID devices corresponding to the number of encoded branches. Each SQUID device is connected to its corresponding transmission coil L via mutual inductance. in coupling; The output of the SQUID readout module is connected to the signal processing module to convert the sensed magnetic flux signal into a digital logic level output.

2. The multi-bit parallel encoder according to claim 1, characterized in that: The k Josephson junction units in the superconducting coded array are configured with a gradient-distributed critical current threshold. And satisfy When the amplitude of the simulated current signal under test superimposed on the square wave bias current changes, the Josephson junctions of different branches successively flip from the zero-resistance superconducting state to the finite-resistance voltage state, forming a multi-level quantization ladder for the signal amplitude.

3. The multi-bit parallel encoder according to claim 1, characterized in that: The RL transmission filtering module constitutes a first-order low-pass filter with a cutoff frequency of Due to the transmission resistance R in and transmission coil L in Decision, satisfaction The cutoff frequency It is configured to be much smaller than the characteristic oscillation frequency of the Josephson junction element in the finite resistance voltage state. ( ),satisfy This ensures that the attenuation of the AC Josephson high-frequency oscillation noise in the readout circuit is greater than 40dB.

4. The multi-bit parallel encoder according to claim 1, characterized in that: The Josephson junction unit and the RL transmission filter module are integrated on the same substrate; the Josephson junction adopts an Nb / Al-AlOx / Nb or Al / Al-AlOx / Al stacked structure; the transmission resistor R... in Pd or Mo metal thin film resistors are used.

5. The multi-bit parallel encoder according to claim 4, characterized in that: The Josephson junction unit and the RL transmission filter module adopt a common substrate vertical integration structure, which includes a Si substrate layer and a SiO2 film layer from bottom to top. On one side of the SiO2 film layer, a Josephson junction bottom electrode, an Al-AlOx barrier layer, and a Josephson junction top electrode are stacked in sequence, and on the other side, a transmission resistor R is formed by a metal resistance film layer. in A superconducting wiring layer is also prepared above the SiO2 film to form a transmission coil L. in The interconnections between modules and the insulation isolation layers between functional layers are also provided.

6. A signal switching and encoding method using a multi-bit parallel encoder as described in any one of claims 1-5, characterized in that, The method includes: During the sampling phase, the square wave bias current is at a high level: if the total current in a certain encoded branch after superimposing the analog current signal to be measured exceeds the critical current of the Josephson junction unit of that branch. The Josephson junction unit instantaneously switches to a finite resistance voltage state, and the analog current signal to be measured is shunt and input to the parallel RL transmission filter module, driving the corresponding SQUID device to output a logic high level; during the reset phase, the square wave bias current is low level: the Josephson junction units of all encoded branches return to the zero resistance superconducting state, the analog current signal to be measured is short-circuited by the Josephson junction unit, the current in the RL transmission filter module decays to zero, and the corresponding SQUID device outputs a logic low level.

7. The signal switching and encoding method of the multi-bit parallel encoder according to claim 6, characterized in that: During the sampling phase, when the Josephson junction is in a finite resistance voltage state, i.e., the dynamic resistance is , the effective signal current flowing through the RL transmission filter module and coupled to the SQUID device... The transfer function is ;in, The simulated current signal to be measured. ω is the signal angular frequency, and j is the imaginary unit.

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