LDPC decoding method and related product

Abstract

The application discloses an LDPC decoding method and related products, the method comprises the following steps: according to the check matrix of LDPC code, pre-constructing the pre-computation structure between variable nodes and check nodes; according to the received signal sequence and noise variance, calculating the prior log-likelihood ratio of each variable node in the check matrix by using fixed-point number format; reading the vector register width and the prior log-likelihood ratio fixed-point data bit width of each variable node, calculating the single batch maximum parallel processing capability value; according to the single batch maximum parallel processing capability value, performing batch loading and vectorized iterative update decoding processing on each check node and each variable node in the check matrix based on the pre-computation structure, until the iteration termination condition is met, and the decoding of the LDPC code is completed. The application greatly improves the cache hit rate and effectively eliminates the restriction of memory access delay on vector calculation speed.

Description

Technical Field

[0001] This application relates to the field of decoding technology, and in particular to an LDPC decoding method and related products. Background Technology

[0002] General-purpose LDPC decoding uses scalar serial processing per node / edge and involves a large number of branch judgments within the loop, while DSP has a wide vector parallel architecture (such as 512-bit registers, processing multiple data in a single instruction). The structural mismatch between the two leads to underloading of vector units and idle resources, making it difficult for the decoding throughput to meet the latency constraints of hundreds of microseconds.

[0003] The LDPC parity-check matrix is ​​sparse and irregular. Existing two-dimensional arrays or pointer jump storage methods make the access to node connection information random and discrete, resulting in poor locality. DSP vector loading requires continuous data alignment, which cannot be converted into burst transmission. Cache prefetching fails, data supply lags behind computation, and memory access becomes a performance bottleneck. Summary of the Invention

[0004] To address the aforementioned issues, this application provides an LDPC decoding method and related products.

[0005] The embodiments of this application disclose the following technical solutions: The first aspect of this application provides an LDPC decoding method, the method comprising: Based on the parity-check matrix of the LDPC code, a pre-computation structure between variable nodes and parity nodes is pre-constructed; the pre-computation structure includes topological connection relationships and a contiguous storage structure. Based on the received signal sequence and noise variance, the prior log-likelihood ratio of each variable node in the verification matrix is ​​calculated using a fixed-point number format. Read the vector register width and the prior log-likelihood ratio of each variable node to the fixed-point data bit width, and calculate the maximum parallel processing capability value for a single batch; Based on the maximum parallel processing capability value for a single batch, batch loading and vectorized iterative update decoding processes are performed on each check node and each variable node in the check matrix according to the pre-computation structure until the iteration termination condition is met, thus completing the decoding of the LDPC code.

[0006] Optionally, the step of performing batch loading and vectorized iterative update decoding processing on each check node and each variable node in the check matrix according to the maximum parallel processing capability value of a single batch, based on the pre-computation structure, until the iteration termination condition is met, to complete the decoding of the LDPC code, specifically includes: For any verification node: All edge messages of the verification node are loaded into the vector register. The edge messages stored in the vector register are then updated in parallel using an integrated extreme value search based on the maximum parallel processing capability value of a single batch, thus completing the update of the verification node. For any variable node: Based on all updated verification nodes connected to the variable node, the current hard decision result is obtained; Based on the current hard decision result, the total value of the checksums is obtained; the total value of the checksums is obtained by adding the checksums of all check nodes in the checksum matrix. The decoding of the LDPC code is completed when the total value of the checksum satisfies the iteration termination condition.

[0007] Optionally, loading all edge messages of the verification node into the vector register specifically includes: The length of all edge messages of the verification node in contiguous memory is directly located by the offset of the edge message storage array in the pre-computed structure; If the length is less than or equal to the preset length, then all edge messages of the verification node are directly loaded into the vector register consecutively; If the length is greater than the preset length, then all edge messages of the verification node are divided into multiple batches according to the maximum parallel processing capability value of a single batch, and loaded into the vector register in batches.

[0008] Optionally, the step of updating the side messages stored in the vector register in parallel using an integrated extreme value search based on the maximum parallel processing capability value for a single batch, thereby completing the update of the verification node, specifically includes: Combine the P edge messages loaded in the current batch into a message vector; where P is equal to the maximum parallel processing capability of a single batch. Execute the absolute value instruction on the message vector to obtain the absolute value message vector; The minimum value in the absolute value message vector is calculated in parallel within the vector register to obtain the minimum value. Each edge message in the absolute value message vector is compared with the minimum value in parallel to generate a mask vector; Determine the number of edge messages in the mask vector that are equal to a preset value, and obtain the minimum value count; The edge messages in the absolute value message vector that are equal to the minimum value are replaced with the preset maximum value to obtain the filter vector; The minimum value in the filter vector is calculated in parallel within the vector register to obtain the second smallest value; If the minimum value count is greater than the preset count threshold, then the values ​​of all edge messages in the filter vector are replaced with the minimum value to complete the update of the verification node. If the minimum value count is equal to the preset count threshold, then the value of the edge message corresponding to the minimum value is replaced with the second smallest value, and the values ​​of all edge messages in the filter vector except the edge message corresponding to the minimum value are replaced with the minimum value, thus completing the update of the verification node.

[0009] Optionally, obtaining the current hard decision result based on all updated verification nodes connected to the variable node specifically includes: All updated verification nodes connected to the variable node are located by the reverse index in the pre-computation structure, and all updated verification nodes connected to the variable node are loaded in batches according to the maximum parallel processing capability value of a single batch. After loading is complete, the variable node is updated based on all updated verification nodes connected to the variable node, and the posterior log-likelihood ratio is calculated. Hard decision calculations are performed based on the posterior log-likelihood ratio of each variable node to obtain the current hard decision result.

[0010] Optionally, obtaining the total value of the checksum based on the current hard decision result specifically includes: The current hard decision result is compared bit by bit with the previous iteration hard decision result, and the set of variable node indices where bit flips occur is recorded, denoted as the change set. The check nodes containing variable nodes in the change set are located by pre-computing the structure, and the check elements of all check nodes containing variable nodes in the change set are updated. The total sum of the checksums of all check nodes in the check matrix is ​​obtained by adding the checksums together.

[0011] Optionally, the method further includes: If the total value of the check node does not meet the iteration termination condition and the number of iterations has not reached the preset maximum number of iterations, then return to the step of loading all edge messages of the check node into the vector register; If the total value of the checksum does not meet the iteration termination condition and the number of iterations reaches the preset maximum number of iterations, then the iteration is terminated and a hard decision result is output.

[0012] A second aspect of this application provides an LDPC decoding apparatus, the LDPC decoding apparatus comprising: The construction module is used to pre-construct the pre-computation structure between variable nodes and check nodes based on the parity check matrix of the LDPC code; the pre-computation structure includes topological connection relationships and contiguous storage structure. The prior calculation module is used to calculate the prior log-likelihood ratio of each variable node in the verification matrix using a fixed-point format based on the received signal sequence and noise variance. The parallel computing module is used to read the vector register width and the prior log-likelihood ratio of each variable node to the fixed-point data bit width, and calculate the maximum parallel processing capability value for a single batch. The decoding module is used to perform batch loading and vectorized iterative update decoding processing on each check node and each variable node in the check matrix according to the maximum parallel processing capability value of a single batch, based on the pre-computation structure, until the iteration termination condition is met, and to complete the decoding of the LDPC code.

[0013] A third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the LDPC decoding method provided in the first aspect.

[0014] The fourth aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements the LDPC decoding method provided in the first aspect.

[0015] Compared with the prior art, this application has the following beneficial effects: This application includes: pre-constructing a pre-computation structure between variable nodes and check nodes based on the parity-check matrix of the LDPC code; the pre-computation structure includes topological connectivity and a continuous storage structure; calculating the prior log-likelihood ratio of each variable node in the parity-check matrix using a fixed-point format based on the received signal sequence and noise variance; reading the vector register width and the fixed-point data bit width of the prior log-likelihood ratio of each variable node to calculate the maximum parallel processing capability value for a single batch; and performing batch loading and vectorized iterative update decoding processing on each check node and each variable node in the parity-check matrix based on the pre-computation structure according to the maximum parallel processing capability value for a single batch, until the iteration termination condition is met, thus completing the decoding of the LDPC code.

[0016] This application precisely calculates the maximum parallel processing capability P of a single batch by reading the vector register width and data bit width, upgrading the decoding granularity from traditional node-by-node / edge-by-edge serial processing to batch parallel processing at the P-order level. Simultaneously, with the integration of vectorized instruction designs such as extreme value search, a large number of branch judgments are eliminated, making the algorithm control flow highly compatible with the DSP vector instruction set. As a result, previously idle vector processing units are fully utilized, significantly improving decoding throughput and meeting decoding latency constraints at the microsecond level. This application pre-constructs a pre-computation structure containing a continuous memory structure, transforming the originally random and discrete node connection information into continuous structured data. This ensures continuous data access during the decoding process, matching the DSP's continuous memory parallel access mechanism and burst transmission mode, significantly improving cache hit rate, and effectively eliminating the constraint of memory access latency on vector computation speed. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart of an LDPC decoding method provided in an embodiment of this application; Figure 2 This is a structural diagram of an LDPC decoding device provided in an embodiment of this application. Detailed Implementation

[0019] As described earlier, current general-purpose LDPC decoding uses node-by-node scalar serial processing, which is mismatched with the wide vector parallel architecture of DSPs. This results in underloaded vector units and throughput that is difficult to achieve latency in the hundreds of microseconds. The parity check matrix is ​​sparse and irregular, and the two-dimensional array storage leads to random and discrete access, which cannot match the continuous alignment vector loading requirements of DSPs. Burst transmissions and cache prefetch failures make memory access a bottleneck.

[0020] In view of the above problems, this application provides an LDPC decoding method and related products. The method includes: pre-constructing a pre-computation structure between variable nodes and check nodes based on the parity-check matrix of the LDPC code; the pre-computation structure includes topological connection relationships and a continuous storage structure; calculating the prior log-likelihood ratio of each variable node in the parity-check matrix using a fixed-point number format based on the received signal sequence and noise variance; reading the vector register width and the fixed-point data bit width of the prior log-likelihood ratio of each variable node to calculate the maximum parallel processing capability value for a single batch; and performing batch loading and vectorized iterative update decoding processing on each check node and each variable node in the parity-check matrix based on the pre-computation structure according to the maximum parallel processing capability value for a single batch, until the iteration termination condition is met, thereby completing the decoding of the LDPC code.

[0021] This application precisely calculates parallel processing capabilities, upgrading the decoding granularity from node-by-node serial to batch parallel. Combined with vectorized instruction design to eliminate branches, the algorithm is highly compatible with the DSP vector architecture, fully releasing the computing power of vector units and achieving throughput at the microsecond level. Simultaneously, this application pre-constructs a continuous pre-computation structure, transforming random discrete node connection information into continuous storage, matching the DSP's burst transmission and cache prefetching mechanisms, and eliminating memory access bottlenecks.

[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0023] Figure 1 A flowchart of an LDPC decoding method provided in an embodiment of this application is shown below. Figure 1 As shown, an LDPC decoding method includes: S101: Based on the parity check matrix of the LDPC code, pre-construct the pre-computation structure between the variable nodes and the parity check nodes.

[0024] In this embodiment, for several predefined fixed LDPC formats in the communication system, an offline preprocessing step is first performed. Let the parity check matrix of the LDPC code be H_{M×N}, where M is the number of check nodes (CN), N is the number of variable nodes (VN), and E is the number of non-zero elements in the parity check matrix H, i.e., the total number of edges in the Tanner graph.

[0025] In this step, the storage structure and index relationship of node connection information are pre-calculated according to the positions of non-zero elements in the check matrix H, so as to generate a precomputed structure that can be directly called in the online decoding stage. The precomputed structure includes a topological connection relationship and a continuous storage structure, and is specifically composed of a row compressed storage array (vns_cov, vns_offset), a column compressed storage array (cns_cov, cns_offset), an edge message offset array edge_offset, and a forward index var_pos_in_check and a reverse index check_pos_in_var.

[0026] Specifically, for each check node m (0≤m<M), the m-th row of the check matrix H is traversed, and the column indices (i.e., the variable node numbers) corresponding to all non-zero elements in this row are extracted. All column indices are connected end to end in ascending order of row numbers and continuously stored in the one-dimensional array vns_cov. At the same time, an offset array vns_offset with a length of M+1 is constructed, where vns_offset[m] records the starting position of the adjacency information of the m-th check node in vns_cov. Thus, the set of variable nodes connected to the check node m can be expressed as N(m) = {vns_cov[i] | i∈[vns_offset[m], vns_offset[m+1])}, and the degree d_m of the check node m satisfies d_m = vns_offset[m+1] - vns_offset[m]. For all check nodes, vns_offset[0] = 0 and vns_offset[M] = E are satisfied. In vns_cov, the adjacent variable node indices of the same check node are stored continuously, and the data of adjacent check nodes are connected end to end in the memory without any fragments, which integrally forms a one-dimensional linearly continuous storage structure that can effectively support the continuous loading of DSP vector instructions.

[0027] Similarly, for each variable node n (0 ≤ n < N), traverse the nth column of the check matrix H, extract the row indices (i.e., check node numbers) corresponding to all non-zero elements in this column, and sequentially store all the row indices end-to-end into the one-dimensional array cns_cov in ascending order of column numbers. Meanwhile, an offset array cns_offset with a length of N+1 is constructed, where cns_offset[n] records the starting position of the adjacency information of the nth variable node in cns_cov. Accordingly, the set of check nodes connected to variable node n can be expressed as M(n)={cns_cov[i]|i∈[cns_offset[n], cns_offset[n+1])}. For all variable nodes, cns_offset[0]=0 and cns_offset[N]=E are satisfied. The adjacent check node indices of the same variable node in cns_cov are stored continuously, and the data of adjacent variable nodes are connected end-to-end in the memory, which also forms a one-dimensional linear continuous storage structure.

[0028] As a preferred implementation of this embodiment, the method further comprises constructing a forward index var_pos_in_check and a reverse index check_pos_in_var. The forward index var_pos_in_check is used to quickly locate the specific position of the edge message of the check node in the edge message value array when a variable node and the check node are given; the reverse index check_pos_in_var is used to quickly locate the specific position of the variable node in the check node set when a check node and the variable node are given.

[0029] To illustrate the construction manner of the above storage structure more clearly, a specific example is given below. Assume that the check matrix H is: ; where M=3, N=5, E=10.

[0030] The corresponding compressed row storage (from the check node perspective) is: vns_cov = [0, 2, 4, 1, 2, 3, 0, 1, 3, 4]; vns_offset = [0, 3, 6, 10]; The non-zero elements of check node CN0 (the 0th row) are located at columns 0, 2, 4, corresponding to vns_cov[0:3]={0, 2, 4}, with a degree d_0=3; the non-zero elements of check node CN1 (the 1st row) are located at columns 1, 2, 3, corresponding to vns_cov[3:6]={1, 2, 3}, with a degree d_1=3; the non-zero elements of check node CN2 (the 2nd row) are located at columns 0, 1, 3, 4, corresponding to vns_cov[6:10]={0, 1, 3, 4}, with a degree d_2=4.

[0031] The corresponding column-compressed storage (from the perspective of variable nodes) is as follows: cns_cov = [0, 2, 1, 2, 0, 1, 1, 2, 0, 2]; cns_offset = [0, 2, 4, 7, 9, 10]; The non-zero elements of variable node VN0 (column 0) are located in rows 0 and 2, corresponding to cns_cov[0:2]={0, 2}; the non-zero elements of variable node VN1 (column 1) are located in rows 1 and 2, corresponding to cns_cov[2:4]={1, 2}; the non-zero elements of variable node VN2 (column 2) are located in rows 0, 1 and 2, corresponding to cns_cov[4:7]={0, 1, 2}; the non-zero elements of variable node VN3 (column 3) are located in rows 1 and 2, corresponding to cns_cov[7:9]={1, 2}; the non-zero elements of variable node VN4 (column 4) are located in rows 0 and 2, corresponding to cns_cov[9:10]={0, 2}.

[0032] All elements in the four arrays vns_cov, vns_offset, cns_cov, and cns_offset are stored in memory with contiguous addresses, without fragmentation or redundant padding. Taking a 512-bit vector register as an example, a single vector load instruction can load 16 32-bit LLR data from contiguous addresses at once, precisely matching the contiguous storage structure described above. The offset array allows each node to access its adjacent nodes with only one memory read, one subtraction, and one address calculation, achieving O(1) direct location without traversal search or pointer chain tracing. This pre-computed structure eliminates the need to parse the structure of the parity check matrix H during the online decoding stage. After loading the four one-dimensional arrays, iterative decoding can begin directly, and the decoding start time is independent of the number of parity check nodes M and the number of variable nodes N.

[0033] This application utilizes row-compressed storage (vns_cov / vns_offset) and column-compressed storage (cns_cov / cns_offset) to store the node connection information of the parity-check matrix with a space complexity of O(E), storing only non-zero elements. All elements in the one-dimensional array are stored in memory with contiguous addresses, eliminating fragmentation and redundant padding. Compared to the traditional O(M×N) storage method of two-dimensional arrays, this achieves over 90% storage savings on typical LDPC codes (sparseness <1%), effectively reducing the memory footprint of communication terminal equipment and making it possible to process large-scale LDPC codes with limited storage resources.

[0034] Meanwhile, the pre-computation structures are all one-dimensional linear continuous storage structures, suitable for DSP burst transmission and cache prefetching. Through the indexing mechanism of the offset array, each node's access to its adjacent edge message only requires one memory read, one subtraction, and one address calculation to complete O(1) direct positioning, reducing the original O(log d) search operation to constant time, and realizing deterministic low-latency access. The continuous data layout, combined with the DSP's vector loading instructions, allows a single vector loading operation to read up to 16 LLR data from a continuous address at once, significantly improving the cache hit rate, effectively eliminating the constraint of memory access latency on vector computation speed, and fundamentally solving the memory access bottleneck problem caused by random and discrete access modes in existing technologies.

[0035] S102: Based on the received signal sequence and noise variance, calculate the prior log-likelihood ratio of each variable node in the verification matrix using a fixed-point number format.

[0036] In this embodiment, after completing the offline preprocessing in S101, the online decoding stage begins. The first step of online decoding is initialization. Based on the received signal sequence y and the noise variance δ², the prior log-likelihood ratio (LLR) of each variable node is calculated using a fixed-point number format, serving as the initial message for iterative decoding.

[0037] Specifically, for the received signal sequence y=[y1, y2, ..., y... n ], where N is the total number of variable nodes (i.e., code length), and each received symbol y n This corresponds to one transmitted bit. In an additive white Gaussian noise (AWGN) channel, the initial LLR value for each variable node is calculated using the following formula, based on the maximum a posteriori probability criterion: ; in, This represents the nth symbol of the received signal and is the soft information value output by the demodulator; It represents the noise variance and characterizes the power of channel noise. It can be obtained in real time at the receiver using channel estimation methods (such as pilot estimation, blind estimation, etc.), or it can be determined based on empirical values ​​pre-calculated from the system signal-to-noise ratio. This represents the initial log-likelihood ratio of the nth variable node.

[0038] The physical meaning of this formula is as follows: Under AWGN channels, the LLR value is directly proportional to the amplitude of the received signal and inversely proportional to the noise variance. The larger the amplitude of the received signal y_n, the higher the reliability of that bit, and the larger the corresponding absolute value of the LLR; the larger the noise variance δ², the worse the channel conditions, the smaller the corresponding absolute value of the LLR, and the lower the initial confidence level.

[0039] In this embodiment, all LLR values ​​are represented and stored in fixed-point format to adapt to the hardware characteristics of the DSP platform. Compared to floating-point format, fixed-point format offers advantages such as faster computation speed, smaller storage space, and lower power consumption, making it more suitable for the real-time processing needs of communication terminal equipment. The bit width B of the LLR fixed-point number can be preset according to precision and dynamic range requirements. For example, this embodiment uses a 32-bit fixed-point representation, which includes a reasonable allocation of sign bits, integer bits, and decimal bits. It should be noted that the specific value of B can be adjusted according to the bit width support and performance requirements of the actual DSP platform; this application does not impose specific limitations on this.

[0040] After completing the above calculations, the initial messages from all variable nodes to the check nodes are set to the initial log-likelihood ratio, that is, the prior LLR value of each variable node is used as the first round of messages it sends to all adjacent check nodes. At the same time, the messages sent from all check nodes to variable nodes are initialized to 0, and the current iteration number t is set to 1, indicating that the decoding process starts from the first iteration.

[0041] S103: Read the vector register width and the prior log-likelihood ratio of each variable node to the fixed-point data bit width, and calculate the maximum parallel processing capability value for a single batch.

[0042] In this embodiment, after the initial LLR calculation of the variable node is completed, the key configuration step of parallel updating of the verification node is entered. The core of this step is to accurately calculate the maximum parallel processing capability of a single batch based on the hardware vector width of the target DSP and the bit width of the LLR data, thereby determining the number of side messages that can be processed simultaneously for each vector instruction, providing a quantitative basis for subsequent batch loading and parallel updates.

[0043] Specifically, the width W (in bits) of the target DSP's vector register is read. Taking a certain model of DSP vector series processor used in this embodiment as an example, its vector register width is W=512 bits, meaning a single vector register can hold 512 bits of data. Simultaneously, the fixed-point data bit width B of the LLR message is read. In this embodiment, the LLR message is represented using 32-bit fixed-point numbers, therefore B=32.

[0044] Based on the two parameters mentioned above, the maximum parallel processing capacity P of a single batch is calculated using the following formula: P = W / B; Substituting the values ​​in this embodiment: P = 512 / 32 = 16. That is, a single vector instruction can process a maximum of 16 LLR data in parallel. This means that during the check node update process, when the degree of a check node (i.e., the number of edges it connects to) does not exceed 16, all edge messages of that node can be read into the vector register at once through a single vector load instruction, and all parallel calculations can be completed through a single vector instruction; when the degree of the check node exceeds 16, the edge messages need to be divided into multiple batches of up to 16 per batch, and loaded and processed sequentially.

[0045] It should be noted that the vector register width W and the LLR fixed-point data bit width B are both inherent parameters of the DSP platform and are known constants in actual systems. The former depends on the hardware specifications of the selected DSP processor, while the latter depends on the engineering trade-off between decoding accuracy and storage overhead. This application reads the above parameters and dynamically calculates the parallel processing capability, enabling the decoding algorithm to adaptively match the vector processing capabilities of different DSP platforms without requiring a redesign of the algorithm implementation for each hardware platform.

[0046] In this embodiment, based on the calculated P=16, subsequent check node updates and variable node updates are performed in batches of a maximum of 16 data points per batch for loading and vectorization. This parallel granularity design, which precisely matches the hardware vector width, ensures maximum utilization of the DSP vector processing unit and avoids resource waste due to excessively large parallel granularity or idle processing units due to excessively small granularity.

[0047] This application dynamically calculates the maximum parallel processing capability P=W / B per batch by precisely reading the vector register width W and LLR fixed-point data bit width B of the target DSP, upgrading the decoding granularity from traditional node-by-node serial to batch parallel processing by P. Taking a 512-bit vector register and a 32-bit fixed-point LLR as an example, a single vector instruction can process 16 data simultaneously, enabling the core operations (minimum value search, sign product calculation, summation, etc.) in check node updates and variable node updates to be completed in parallel within the vector register using a single instruction, theoretically increasing the calculation speed by 16 times. Simultaneously, this parallel granularity design, precisely matching the hardware vector width, effectively avoids resource waste due to excessively large parallel granularity or idle processing units due to excessively small granularity, ensuring maximum utilization of the DSP vector processing unit.

[0048] S104: Based on the maximum parallel processing capability value for a single batch, perform batch loading and vectorized iterative update decoding processing on each check node and each variable node in the check matrix according to the pre-calculated structure until the iteration termination condition is met, and complete the decoding of the LDPC code.

[0049] In this embodiment, after the parallelism determination in S103 is completed, the process enters the core iterative processing stage of online decoding. This step performs batch loading and vectorized iterative update decoding processing on each check node and each variable node in the check matrix based on the continuous storage structure pre-generated in S101 (including the row compression arrays vns_cov / vns_offset, the column compression arrays cns_cov / cns_offset, the edge message value array and the edge message offset array edge_offset) and the maximum single-batch parallel processing capability P calculated in S103.

[0050] The entire iterative decoding process follows the normalized min-sum algorithm, and each iteration sequentially executes three sub-steps: check node update, variable node update, hard decision and incremental check update, until the iteration termination condition is satisfied.

[0051] For S104, according to the value of the maximum single-batch parallel processing capability, based on the precomputed structure, perform batch loading and vectorized iterative update decoding processing on each check node and each variable node in the check matrix respectively until the iteration termination condition is satisfied and the decoding of the LDPC code is completed, the present application provides a specific optional embodiment: For any check node m (0≤m<M), the following steps can be performed: Load all edge messages of the check node into the vector register, and perform parallel update on the edge messages stored in the vector register using integrated extremum search according to the value of the maximum single-batch parallel processing capability in the vector register to complete the update of the check node; specifically: Directly locate the length of all edge messages of the check node in the continuous memory through the offset of the edge message storage array in the precomputed structure; as described above, the edge message value array is opened as a one-dimensional array for continuously storing the LLR message values on all edges in the order of scanning non-zero elements of the check matrix H row by row, with a length of E. The edge message offset array edge_offset has a length of M+1, where edge_offset[m] represents the starting position of the first edge message of the m-th check node in the edge message value array, the d_m edge messages of the m-th check node continuously occupy the interval [edge_offset[m], edge_offset[m+1]), and edge_offset[0]=0, edge_offset[M]=E.

[0052] Using the indexing mechanism of this offset array, each node only needs three simple operations to access its adjacent edge messages: Start = edge_offset[m] to get the starting address, End = edge_offset[m+1] to get the ending address, and Neighbors = edge_value_array[Start : End-1] to read continuous data. That is, O(1) direct positioning can be completed with one memory read, one subtraction, and one address calculation, reducing the original search operation that required O(log d) to constant time, and realizing deterministic low-latency access.

[0053] After obtaining the degree of the verification node according to the above positioning method, determine the relationship between the length and the maximum parallel processing capability value P of a single batch: if the length is less than or equal to the preset length (such as the maximum parallel processing capability value P of a single batch), then directly load all edge messages of the verification node continuously into the vector register; if the length is greater than the preset length, then divide all edge messages of the verification node into multiple batches according to the maximum parallel processing capability value of a single batch, and load them into the vector register in batches.

[0054] After the edge messages are loaded, the edge messages stored in the vector register are updated in parallel using an integrated extreme value search based on the maximum parallel processing capability of a single batch. This integrated extreme value search method takes the P LLR message vectors v_msg=[m1, m2, ..., m_P] loaded in the current batch as input. In a single data traversal, it performs minimum value search, minimum value counting, second minimum value search, and decision-making for multiple minimum values ​​in parallel using DSP vector instructions. All comparison and selection operations are completed internally in the vector register using DSP vector instructions, without branch jump instructions (i.e., there are no if condition branches), fully utilizing the parallel computing capabilities of the DSP vector processing unit. The specific steps of the integrated extreme value search method are as follows: Combine the P edge messages loaded in the current batch into a message vector; where P is equal to the maximum parallel processing capability of a single batch; execute the absolute value instruction on the message vector to obtain an absolute value message vector; for example, the 16 edge messages (32-bit fixed-point numbers) loaded in the current batch are regarded as message vector v_msg = [m1, m2, ..., m16], and the absolute value instruction is executed to obtain the absolute value message vector v_abs = |v_msg|.

[0055] The minimum value in the absolute value message vector is calculated in parallel within the vector register to obtain the minimum value; for example, the global minimum value min_batch among 16 elements is calculated in parallel through the vmin minimum value calculation instruction. This process is completed entirely within the vector register without memory access or branch judgment.

[0056] Each edge message in the absolute value message vector is compared in parallel with the minimum value to generate a mask vector; the number of edge messages in the mask vector that equals a preset value is determined to obtain the minimum value count; for example, the DSP vector comparison instruction vcmp is executed to compare each element of v_abs in parallel with min_batch to generate a mask vector mask, where the position of the element equal to min_batch is 1. The number of 1s in the mask is counted by the DSP vector addition instruction vaddint to obtain the minimum value count min_count_batch.

[0057] The edge messages in the absolute value message vector that are equal to the minimum value are replaced with a preset maximum value to obtain a filter vector. The minimum value in the filter vector is calculated in parallel within the vector register to obtain the second smallest value. For example, to eliminate interference from the minimum value, the vector conditional execution instructions vcmp and vmov are executed, replacing elements in v_abs that are equal to min_batch with a preset maximum value MAX_VAL to obtain the filter vector v_filtered. The minimum value instruction vmin is then applied again to v_filtered to obtain the second smallest value second_min_batch.

[0058] If the minimum value count is greater than the preset count threshold, it indicates that there are multiple minimum values. In this case, the values ​​of the edge messages in the filter vector are all replaced with the minimum values ​​to complete the update of the verification node.

[0059] If the minimum value count equals the preset counting threshold, the value of the edge message corresponding to the minimum value is replaced with the second smallest value, and the values ​​of all edge messages in the filter vector except the edge message corresponding to the minimum value are replaced with the minimum value, thus completing the update of the verification node. This ensures the numerical stability of the algorithm and avoids the performance degradation caused by improper handling of multiple minimum values ​​in traditional methods.

[0060] This embodiment compresses the complex process of the traditional min-sum algorithm, which requires four data traversals (finding the minimum, second minimum, calculating the sign product, and calculating the output value), into a single traversal. All comparison and selection operations are completed within the vector register using DSP vector instructions (vmin, vcmp, vaddint, etc.), eliminating the need for memory access and branch judgments. A mask vector is generated using vector comparison instructions, and the minimum value count is counted. Then, the minimum value element is replaced using vector conditional execution instructions, and the vmin instruction is applied again to obtain the second minimum value. Finally, decision processing for multiple minimum value cases is performed based on the global minimum value count. This mechanism eliminates the impact of branch judgments on the instruction pipeline, avoids pipeline stalls caused by numerous if-else branches within loops in traditional methods, and significantly improves the execution efficiency of check node updates.

[0061] After completing the integrated extremum search, for each check node m and each variable node n connected thereto, that is, for each edge (m, n), the update message transmitted from the check node to the variable node is calculated using the following normalized min-sum formula: ; where t represents the current iteration number; N(m)\ndenotes the set of all variable nodes connected to check node m excluding the current variable node n; is a sign function, taking a value of +1 or -1, representing the product of the signs of each input message; = is a minimum value function, representing taking the minimum value among the absolute values; a is a normalization factor for integer input, for example, a=80 means the normalization coefficient is 0.8, which is used to appropriately scale and adjust the message amplitude to improve decoding performance. The above-mentioned sign product, minimum value extraction and normalization multiplication operations are all completed in parallel inside the vector register through DSP vector instructions.

[0062] In specific implementation, the vectorized check node update process can be summarized as: using the DSP vector load instruction to obtain the starting position with vns_offset[m : m + DSP vector[WIDTH] as the index, and read the offset information of multiple check nodes in batches; calculate the number of neighbors of each check node to determine the required number of iterations; in each iteration, continuously read the neighbor indices through the DSP vector dense load instruction, obtain the corresponding message values through the DSP vector gather instruction, and execute the min-sum operation in parallel through the DSP vector instruction; write the updated results back to the corresponding storage positions of the edge message value array continuously through the DSP vector scatter store instruction.

[0063] After completing the message update of all check nodes, the process enters the variable node update stage. For any variable node n (0≤n<N), the current hard decision result is obtained based on all updated check nodes connected to the variable node; the total syndrome value is obtained based on the current hard decision result; the total syndrome value is obtained by adding the syndromes of all check nodes in the check matrix; when the total syndrome value satisfies the iteration termination condition (for example, the total syndrome value is 0), the current hard decision result is output as the final decoded bit sequence, and the decoding of the LDPC code is completed.

[0064] Regarding obtaining the current hard decision result based on all updated check nodes connected to the variable node, the present application provides an optional embodiment: The inverted index `check_pos_in_var` in the pre-computation structure is used to locate all updated check nodes connected to the variable node, and these updated check nodes are loaded in batches according to the maximum parallel processing capability value for a single batch. The inverted index `check_pos_in_var` records the specific position of the adjacent check node information of each variable node in the column-compressed storage array, allowing the location operation to be completed in constant time.

[0065] Specifically, cns_offset[n] and cns_offset[n+1] are used to obtain the start and end positions of the adjacent check node indices of the variable node n in cns_cov, and its degree d'_n = cns_offset[n+1] - cns_offset[n]. Based on the maximum parallel processing capability P of a single batch, the degree is determined: if d'_n ≤ P, all adjacent check node indices are loaded into the vector register continuously in a single vector load instruction; if d'_n > P, the nodes are divided into multiple batches of a maximum of P, and loaded into the vector register sequentially.

[0066] After loading is complete, the variable node is updated based on all updated check nodes connected to it, and the posterior log-likelihood ratio is calculated. For example, for each batch loaded into the vector register, the accumulation operation is performed in parallel using DSP vector instructions. For the current variable node n and each check node m it connects to (i.e., for each edge (n, m)), the update message passed from the variable node to the check node is calculated using the following formula: + ; in, M(n) represents the prior LLR value of the nth variable node (i.e., the initial LLR calculated in step S102 based on the received signal and noise variance); M(n) represents the set of all check nodes connected to variable node n; M(n)m represents the set of all check nodes connected to variable node n excluding the current check node m. Let m' be the message that the m'-th check node transmits to the variable node n in the t-th iteration. The physical meaning of the above formula is that the message transmitted by the variable node n to the check node m is equal to the prior information of the variable node plus the sum of the external information transmitted by all adjacent check nodes other than check node m. This message update method that excludes itself can effectively avoid positive feedback and ensure iterative convergence.

[0067] After updating all edge messages in all variable nodes, the posterior log-likelihood ratio (PLR) of each variable node is further calculated. The posterior LLR of variable node n is equal to its prior LLR plus the sum of messages passed from all neighboring check nodes. The posterior LLR combines the initial information of the received signal with the constraint information obtained from the check nodes during the iteration process, and its confidence level increases with the number of iterations.

[0068] Hard decision calculations are performed based on the posterior log-likelihood ratio of each variable node to obtain the current hard decision result.

[0069] Regarding the calculation of the total value of the checksum based on the current hard decision result, this application provides an optional embodiment: This embodiment utilizes the incremental check update mechanism and the fast lookup capability of a one-dimensional continuous storage structure to recalculate the checksum only for check nodes affected by the changed bits, thereby significantly reducing the overhead of check sub-calculation.

[0070] Specifically, after completing the hard decision of the current iteration, the current hard decision result is compared bit by bit with the hard decision result of the previous iteration, and the set of variable node indices where bit flips occur is recorded, denoted as the change set. For the first iteration (t=1), since there is no previous hard decision result, the change set is initialized to the entire set {1, 2, ..., N}, that is, the first iteration performs full checksum calculations on all check nodes. As the iteration progresses, when the decoding gradually converges, the number of variable nodes where bit flips occur decreases successively, becoming much smaller than the total number of variable nodes N (i.e., |Δ (t) |< <N)。

[0071] The pre-computation structure locates all check nodes containing variable nodes in the changed set and updates the check functions of all check nodes containing variable nodes in the changed set. For example, the row-compressed storage array `vns_cov` and the offset array `vns_offset` in the pre-computation structure quickly locate all check nodes containing any variable node in the changed set. Since the adjacent variable node indices of the same check node are stored consecutively in `vns_cov`, and `vns_offset` provides O(1) direct location capability, for each changed variable node `n`, by querying `vns_offset` and `vns_cov`, the index set of all check nodes containing that variable node can be directly located without traversing the entire check matrix. Only the check nodes located above are recalculated; the check functions of check nodes unaffected by the changed bits remain unchanged.

[0072] For any check node m, its checksum is updated as follows: if the set of variable nodes N(m) connected to the check node is equal to the set of changes Δ... (t)There exists an intersection (i.e., N(m)∩Δ) (t) ≠ If so, the checksum of that check node will be recalculated. = , , where ⊕ represents the XOR operation; if N(m)∩Δ (t) = If no bit flips occur in any of the variable nodes connected to the check node, then the checksum of the check node remains unchanged. = This incremental update strategy means that each iteration only needs to recalculate the checksum of the check nodes affected by the changed bits, while keeping the checksums of other unaffected check nodes unchanged, effectively avoiding the redundant overhead of full calculation.

[0073] After updating the checksums of all affected check nodes, the checksums of all check nodes in the check matrix are summed to obtain the total checksum.

[0074] For cases where the total value of the checksum does not meet the iteration termination condition, this application provides an optional embodiment: If the total value of the checksum does not meet the iteration termination condition and the number of iterations has not reached the preset maximum number of iterations, then return to the step of loading all edge messages of the checksum node into the vector register.

[0075] If the total value of the checksum does not meet the iteration termination condition and the number of iterations reaches the preset maximum number of iterations, then the iteration is terminated and a hard decision result is output.

[0076] This embodiment, through the aforementioned incremental check update mechanism and combined with the fast lookup capability of a one-dimensional continuous storage structure, records the bit positions that change in each iteration and only recalculates the checksum of the affected check nodes. This ensures that the computational load of the checksum decreases dynamically as the iteration converges, while maintaining the correctness of the decoding, thereby further shortening the decoding latency.

[0077] This application achieves a theoretically optimal space complexity of O(E) through row-compressed storage (vns_cov / vns_offset) and column-compressed storage (cns_cov / cns_offset), where E is the total number of non-zero elements in the parity-check matrix H. The vns_cov and cns_cov arrays each store E index values, with a total storage overhead of 2E integer units, strictly proportional to the sparsity of the H matrix, and without redundant storage. Compared to the traditional O(M×N) storage method of two-dimensional arrays, this application achieves over 99% storage savings on typical LDPC codes (sparseness <1%), effectively reducing the memory footprint of communication terminal equipment and making it possible to process large-scale LDPC codes with limited storage resources.

[0078] All four arrays are one-dimensional linear contiguous storage structures, free of fragmentation, suitable for burst transmission and cache prefetching in DSPs. The adjacency information of the same node in vns_cov and cns_cov is stored contiguously, allowing DSP vectorized loading to retrieve the complete adjacency set at once, perfectly matching the access granularity of a 512-bit vector register. Through the indexing mechanism of the offset array, each node's access to its adjacent edge message requires only one memory read, one subtraction, and one address calculation, achieving O(1) direct location, reducing the original O(log d) search operation to constant time, and realizing deterministic low-latency access. The contiguous data layout fundamentally solves the problem of low cache hit rate caused by pointer jumps and discontinuous memory in traditional schemes, significantly improving memory access speed.

[0079] The incremental checksum update mechanism compares the current iteration's hard decision result bit-by-bit with the previous iteration's result, records the set of variable node indices where bit flips occur, and recalculates the checksum only for the affected check nodes, while keeping the checksums of other check nodes unchanged. Since the number of elements in the changed set is much smaller than the total number of variable nodes N during iterative convergence, the computational cost of the checksum decreases dynamically with iteration convergence. Compared to traditional schemes that recalculate all M check equations in each iteration, this application significantly reduces the checksum computation time.

[0080] This application utilizes offline preprocessing to complete computationally intensive tasks such as H matrix parsing and index construction entirely offline. The online decoder only needs to load the four pre-computed arrays to begin decoding, eliminating the need to parse the H matrix structure at runtime. The decoding startup time is independent of the number of verification nodes M and variable nodes N, reducing the decoder startup overhead from the traditional O(M×N) to O(1), making it particularly suitable for applications requiring rapid capture.

[0081] In summary, this application achieves deep co-design between the algorithm and DSP hardware through offline preprocessing to construct a continuous storage structure, precisely matching the DSP vector width to determine the parallel granularity, using integrated extreme value search to eliminate branch judgments, and incremental check updates to avoid full computation. The one-dimensional continuous layout of the storage structure solves the problem of irregular memory access from the bottom layer; the precise matching of the vector width ensures that the vector instructions run at full load; the integrated extreme value search fundamentally eliminates memory access latency and branch penalties; and the incremental update mechanism makes the amount of check computation dynamically decrease as the iteration converges. These four technical means support each other and advance layer by layer, forming a complete technical closed loop from data organization, computational granularity, instruction flow optimization to iteration control. Under the constraints of limited memory resources and microsecond-level decoding latency, it significantly improves the storage efficiency, memory access speed, computational throughput, and iteration efficiency of LDPC decoding, and can be widely used in communication terminal equipment with high real-time decoding requirements, such as 5G communication, satellite communication, and digital video broadcasting.

[0082] Figure 2 A structural diagram of an LDPC decoding device provided in an embodiment of this application is shown below. Figure 2 As shown, based on the LDPC decoding method provided in the preceding embodiments, this application also provides an LDPC decoding apparatus comprising: The construction module is used to pre-construct the pre-computation structure between variable nodes and check nodes based on the parity check matrix of the LDPC code; the pre-computation structure includes topological connection relationships and contiguous storage structure. The prior calculation module is used to calculate the prior log-likelihood ratio of each variable node in the verification matrix using a fixed-point format based on the received signal sequence and noise variance. The parallel computing module is used to read the vector register width and the prior log-likelihood ratio of each variable node to the fixed-point data bit width, and calculate the maximum parallel processing capability value for a single batch. The decoding module is used to perform batch loading and vectorized iterative update decoding processing on each check node and each variable node in the check matrix according to the maximum parallel processing capability value of a single batch, based on the pre-computation structure, until the iteration termination condition is met, and to complete the decoding of the LDPC code.

[0083] As an optional embodiment, the decoding module specifically includes: The verification node decoding unit is used for any verification node to: load all edge messages of the verification node into a vector register, and use integrated extreme value search to update the edge messages stored in the vector register in parallel according to the maximum parallel processing capability value of a single batch, thereby completing the update of the verification node. The variable node decoding unit is configured to, for any variable node: obtain the current hard decision result based on all updated check nodes connected to the variable node; obtain the total checksum value based on the current hard decision result; the total checksum value is obtained by adding the checksums of all check nodes in the check matrix; and complete the decoding of the LDPC code when the total checksum value satisfies the iteration termination condition.

[0084] As an optional embodiment, loading all edge messages of the verification node into the vector register specifically includes: The length of all edge messages of the verification node in contiguous memory is directly located by the offset of the edge message storage array in the pre-computed structure; If the length is less than or equal to the preset length, then all edge messages of the verification node are directly loaded into the vector register consecutively; If the length is greater than the preset length, then all edge messages of the verification node are divided into multiple batches according to the maximum parallel processing capability value of a single batch, and loaded into the vector register in batches.

[0085] As an optional embodiment, the step of updating the side messages stored in the vector register in parallel using an integrated extreme value search based on the maximum parallel processing capability value per batch to complete the update of the verification node specifically includes: Combine the P edge messages loaded in the current batch into a message vector; where P is equal to the maximum parallel processing capability of a single batch. Execute the absolute value instruction on the message vector to obtain the absolute value message vector; The minimum value in the absolute value message vector is calculated in parallel within the vector register to obtain the minimum value. Each edge message in the absolute value message vector is compared with the minimum value in parallel to generate a mask vector; Determine the number of edge messages in the mask vector that are equal to a preset value, and obtain the minimum value count; The edge messages in the absolute value message vector that are equal to the minimum value are replaced with the preset maximum value to obtain the filter vector; The minimum value in the filter vector is calculated in parallel within the vector register to obtain the second smallest value; If the minimum value count is greater than the preset count threshold, then the values ​​of all edge messages in the filter vector are replaced with the minimum value to complete the update of the verification node. If the minimum value count is equal to the preset count threshold, then the value of the edge message corresponding to the minimum value is replaced with the second smallest value, and the values ​​of all edge messages in the filter vector except the edge message corresponding to the minimum value are replaced with the minimum value, thus completing the update of the verification node.

[0086] As an optional embodiment, obtaining the current hard decision result based on all updated verification nodes connected to the variable node specifically includes: All updated verification nodes connected to the variable node are located by the reverse index in the pre-computation structure, and all updated verification nodes connected to the variable node are loaded in batches according to the maximum parallel processing capability value of a single batch. After loading is complete, the variable node is updated based on all updated verification nodes connected to the variable node, and the posterior log-likelihood ratio is calculated. Hard decision calculations are performed based on the posterior log-likelihood ratio of each variable node to obtain the current hard decision result.

[0087] As an optional embodiment, obtaining the total value of the checksum based on the current hard decision result specifically includes: The current hard decision result is compared bit by bit with the previous iteration hard decision result, and the set of variable node indices where bit flips occur is recorded, denoted as the change set. The check nodes containing variable nodes in the change set are located by pre-computing the structure, and the check elements of all check nodes containing variable nodes in the change set are updated. The total sum of the checksums of all check nodes in the check matrix is ​​obtained by adding the checksums together.

[0088] As an optional embodiment, the decoding module further includes: An iteration unit is used to return to the step of loading all edge messages of the verification node into the vector register if the total value of the verification sub-value does not meet the iteration termination condition and the number of iterations has not reached the preset maximum number of iterations; and to terminate the iteration and output a hard decision result if the total value of the verification sub-value does not meet the iteration termination condition and the number of iterations has reached the preset maximum number of iterations.

[0089] This application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the LDPC decoding method.

[0090] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements an LDPC decoding method.

[0091] This application provides a computer program product, including a computer program that, when executed by a processor, implements an LDPC decoding method.

[0092] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the device and equipment embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The device and equipment embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0093] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An LDPC decoding method, characterized in that, The method includes: Based on the parity-check matrix of the LDPC code, a pre-computation structure between variable nodes and parity nodes is pre-constructed; the pre-computation structure includes topological connection relationships and a contiguous storage structure. Based on the received signal sequence and noise variance, the prior log-likelihood ratio of each variable node in the verification matrix is ​​calculated using a fixed-point number format. Read the vector register width and the prior log-likelihood ratio of each variable node to the fixed-point data bit width, and calculate the maximum parallel processing capability value for a single batch; Based on the maximum parallel processing capability value for a single batch, batch loading and vectorized iterative update decoding processes are performed on each check node and each variable node in the check matrix according to the pre-computation structure until the iteration termination condition is met, thus completing the decoding of the LDPC code.

2. The LDPC decoding method according to claim 1, characterized in that, The process involves performing batch loading and vectorized iterative update decoding on each check node and each variable node in the check matrix according to the maximum parallel processing capability value for a single batch, based on the pre-computation structure, until the iteration termination condition is met, thus completing the decoding of the LDPC code. Specifically, this includes: For any verification node: All edge messages of the verification node are loaded into the vector register. The edge messages stored in the vector register are then updated in parallel using an integrated extreme value search based on the maximum parallel processing capability value of a single batch, thus completing the update of the verification node. For any variable node: Based on all updated verification nodes connected to the variable node, the current hard decision result is obtained; Based on the current hard decision result, the total value of the checksums is obtained; the total value of the checksums is obtained by adding the checksums of all check nodes in the checksum matrix. The decoding of the LDPC code is completed when the total value of the checksum satisfies the iteration termination condition.

3. The LDPC decoding method according to claim 2, characterized in that, The step of loading all edge messages of the verification node into the vector register specifically includes: The length of all edge messages of the verification node in contiguous memory is directly located by the offset of the edge message storage array in the pre-computed structure; If the length is less than or equal to the preset length, then all edge messages of the verification node are directly loaded into the vector register consecutively; If the length is greater than the preset length, then all edge messages of the verification node are divided into multiple batches according to the maximum parallel processing capability value of a single batch, and loaded into the vector register in batches.

4. The LDPC decoding method according to claim 2, characterized in that, The step of updating the edge messages stored in the vector register in parallel using an integrated extreme value search based on the maximum parallel processing capability value per batch, thereby completing the update of the verification node, specifically includes: Combine the P edge messages loaded in the current batch into a message vector; where P is equal to the maximum parallel processing capability of a single batch. Execute the absolute value instruction on the message vector to obtain the absolute value message vector; The minimum value in the absolute value message vector is calculated in parallel within the vector register to obtain the minimum value. Each edge message in the absolute value message vector is compared with the minimum value in parallel to generate a mask vector; Determine the number of edge messages in the mask vector that are equal to a preset value, and obtain the minimum value count; The edge messages in the absolute value message vector that are equal to the minimum value are replaced with the preset maximum value to obtain the filter vector; The minimum value in the filter vector is calculated in parallel within the vector register to obtain the second smallest value; If the minimum value count is greater than the preset count threshold, then the values ​​of all edge messages in the filter vector are replaced with the minimum value to complete the update of the verification node. If the minimum value count is equal to the preset count threshold, then the value of the edge message corresponding to the minimum value is replaced with the second smallest value, and the values ​​of all edge messages in the filter vector except the edge message corresponding to the minimum value are replaced with the minimum value, thus completing the update of the verification node.

5. The LDPC decoding method according to claim 2, characterized in that, The current hard decision result is obtained by connecting all the updated verification nodes based on the variable node, specifically including: All updated verification nodes connected to the variable node are located by the reverse index in the pre-computation structure, and all updated verification nodes connected to the variable node are loaded in batches according to the maximum parallel processing capability value of a single batch. After loading is complete, the variable node is updated based on all updated verification nodes connected to the variable node, and the posterior log-likelihood ratio is calculated. Hard decision calculations are performed based on the posterior log-likelihood ratio of each variable node to obtain the current hard decision result.

6. The LDPC decoding method according to claim 2, characterized in that, The process of obtaining the total value of the checksum based on the current hard decision result specifically includes: The current hard decision result is compared bit by bit with the previous iteration hard decision result, and the set of variable node indices where bit flips occur is recorded, denoted as the change set. The check nodes containing variable nodes in the change set are located by pre-computing the structure, and the check elements of all check nodes containing variable nodes in the change set are updated. The total sum of the checksums of all check nodes in the check matrix is ​​obtained by adding the checksums together.

7. The LDPC decoding method according to claim 2, characterized in that, The method further includes: If the total value of the check node does not meet the iteration termination condition and the number of iterations has not reached the preset maximum number of iterations, then return to the step of loading all edge messages of the check node into the vector register; If the total value of the checksum does not meet the iteration termination condition and the number of iterations reaches the preset maximum number of iterations, then the iteration is terminated and a hard decision result is output.

8. An LDPC decoding device, characterized in that, The LDPC decoding device includes: The construction module is used to pre-construct the pre-computation structure between variable nodes and check nodes based on the parity check matrix of the LDPC code; the pre-computation structure includes topological connection relationships and contiguous storage structure. The prior calculation module is used to calculate the prior log-likelihood ratio of each variable node in the verification matrix using a fixed-point format based on the received signal sequence and noise variance. The parallel computing module is used to read the vector register width and the prior log-likelihood ratio of each variable node to the fixed-point data bit width, and calculate the maximum parallel processing capability value for a single batch. The decoding module is used to perform batch loading and vectorized iterative update decoding processing on each check node and each variable node in the check matrix according to the maximum parallel processing capability value of a single batch, based on the pre-computation structure, until the iteration termination condition is met, and to complete the decoding of the LDPC code.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the LDPC decoding method according to any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the LDPC decoding method according to any one of claims 1-7.

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