An encoding method, a decoding method, a communication device, and a communication system

Abstract

The application relates to the technical field of communication, and discloses an encoding method, a decoding method, a communication device and a communication system. Based on the method, since the encoding matrix for polar encoding is determined according to a first rate matching mode, the first rate matching mode is determined according to N second code lengths corresponding to an encoding parameter and N second rate matching modes, the mode determines the first rate matching mode of the encoding matrix corresponding to a larger first code length based on smaller N second code lengths and corresponding N second rate matching modes, the flexibility of constructing the encoding matrix can be improved, thus the encoding matrix with fast polarization capability can be constructed, and the decoding performance is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a communication device, and a communication system. Background Technology

[0002] Polar codes were selected as the control channel coding scheme in the 5th generation (5G) communication standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity and have the advantages of good decoding performance and low complexity.

[0003] Currently, in polar coding, a coding matrix of size N*N is generally constructed using the mother code length N, and the information bit sequence is polar-coded using this matrix to obtain a encoded bit sequence of length N. Here, N is 2 to the power of n, and n is an integer greater than or equal to 1. Due to factors such as channel conditions and available transmission resources, the actual transmittable length E of the encoded bit sequence may not be equal to N. Therefore, rate matching is required for the encoded bit sequence of length N to obtain an encoded bit sequence of length E for transmission. Here, E is also called the code length or coding code length.

[0004] The decoding performance of polar codes is related to the rate matching method, and the decoding performance of current polar code rate matching schemes needs to be improved. Summary of the Invention

[0005] This application provides an encoding method, a decoding method, a communication device, and a communication system to improve decoding performance.

[0006] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, etc.), a component used in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device. The method includes: polar coding a first bit sequence according to an encoding matrix to obtain a second bit sequence; modulating the second bit sequence to obtain modulation symbol information; and outputting the modulation symbol information; wherein the encoding matrix includes N coupled sub-matrices, the encoding matrix is ​​determined according to encoding parameters and a first rate matching method, the encoding parameters include a first code length and a first number of information bits, the first rate matching method indicates the rate matching method for a first mother code, the first rate matching method is determined according to N second code lengths and N second rate matching methods corresponding to the encoding parameters, the N second code lengths, the N second rate matching methods and the N sub-matrices are in one-to-one correspondence, and each of the N second rate matching methods indicates the rate matching method for the second mother code corresponding to its corresponding sub-matrix.

[0007] Based on the above scheme, since the coding matrix used for polarization coding is determined according to the first rate matching method, which is determined according to the N second code lengths and N second rate matching methods corresponding to the coding parameters, this method determines the first rate matching method of the coding matrix corresponding to the larger first code length based on the smaller N second code lengths and the corresponding N second rate matching methods. This can improve the flexibility of constructing the coding matrix, and thus a coding matrix with fast polarization capability can be constructed, thereby improving the decoding performance.

[0008] Secondly, embodiments of this application provide a decoding method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, network device, etc.), a component used in the communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device. The method includes: acquiring modulation symbol information; demodulating the modulation symbol information to obtain a sequence to be decoded; and performing polarization decoding on the sequence to be decoded according to an encoding matrix to obtain a decoding result. The encoding matrix includes N coupled sub-matrices, and is determined based on encoding parameters and a first rate matching method. The encoding parameters include a first code length and a first number of information bits. The first rate matching method indicates the rate matching method for a first mother code. The first rate matching method is determined based on N second code lengths and N second rate matching methods corresponding to the encoding parameters. The N second code lengths, the N second rate matching methods, and the N sub-matrices correspond one-to-one. Each of the N second rate matching methods indicates the rate matching method for the second mother code corresponding to its corresponding sub-matrix.

[0009] Based on the above scheme, since the coding matrix used for polarization coding is determined according to the first rate matching method, which is determined according to the N second code lengths and N second rate matching methods corresponding to the coding parameters, this method determines the first rate matching method of the coding matrix corresponding to the larger first code length based on the smaller N second code lengths and the corresponding N second rate matching methods. This can improve the flexibility of constructing the coding matrix, and thus a coding matrix with fast polarization capability can be constructed, thereby improving the decoding performance.

[0010] Based on the first or second aspect mentioned above, there are one or more possible implementation methods as follows:

[0011] In one possible implementation, the length of the first mother code is 2. m m is an integer greater than 1, and the length of the second mother code is 2. t t is a positive integer, and the number of the second code length is 2. m-t .

[0012] In one possible implementation, E represents the length of the first code. This represents the function for rounding up.

[0013] In one possible implementation, each of the N second rate matching methods indicates the puncture position of the second mother code corresponding to its corresponding submatrix, and the first rate matching method is determined based on the puncture positions indicated by the N second rate matching methods.

[0014] Based on the above scheme, the puncturing method of the first mother code can be determined according to the second rate matching method of the N second mother codes, and a suitable first rate matching method can be determined, thereby constructing a coding matrix with fast polarization capability and improving decoding performance.

[0015] In one possible implementation, the first rate matching method is used to indicate that the first master code is punched at the following punching positions: The second rate matching method is used to indicate the first sequence. Punch holes in the second mother code; the lengths of the N second codes are as follows: Among them, l i ≤2 t i = 1, 2, ..., 2 m-t The first code length is equal to When the second code length is equal to l i Then the corresponding punch position of the second mother code is Furthermore, it also satisfies: Where mt≥k≥0, 0≤s<2 m-k-1 .in, The sum of the upper half code lengths used to represent the first mother code (or the sub-blocks of the first mother code of various sizes) is less than or equal to the sum of the lower half code lengths.

[0016] Based on the above scheme, the puncturing method of the first mother code can be determined according to the puncturing method of the second mother code, thus improving the flexibility of constructing the coding matrix. This allows for the construction of a coding matrix with fast polarization capability, further enhancing decoding performance. Furthermore, by limiting the sum of the upper half code lengths of the first mother code (or its various sizes of sub-blocks) to be less than or equal to the sum of the lower half code lengths, decoding accuracy can be improved, thereby enhancing decoding performance.

[0017] In one possible implementation, the first sequence is either a punched sequence or a bit index of the second mother code in natural order.

[0018] Based on the above scheme, the bit index of the second mother code, which is either a punctured sequence or a natural sequence, is pre-set, which can achieve correct puncturing and help improve decoding performance.

[0019] In one possible implementation, m = 5, t = 3, N = 4; the N second code lengths are l1 = 4, l2 = 6, l3 = 5, l4 = 7 respectively; the first code length is equal to 22, and the first information bit number is equal to 11; The first rate matching method indicates that the first mother code is punched at the following punching positions: 1,2,3,4,5,6,7,8;

[0020] Based on the above scheme, a punching method with good decoding performance can be obtained, and then a coding matrix with fast polarization capability can be constructed.

[0021] In one possible implementation, each of the N second rate matching methods indicates the shortening position of the second mother code corresponding to its corresponding submatrix, and the first rate matching method is determined based on the shortening position indicated by the N second rate matching methods.

[0022] Based on the above scheme, the shortening method of the first mother code can be determined according to the second rate matching method of N second mother codes, and a suitable first rate matching method can be determined, thereby constructing a coding matrix with fast polarization capability and improving decoding performance.

[0023] In one possible implementation, the first rate matching method is used to indicate that the first mother code is shortened according to the following shortening positions: The second rate matching information is used to indicate the sequence. The second mother code is shortened; the lengths of the N second codes are as follows: Among them, l i ≤2 t i = 1, 2, ..., 2 m-t The first code length is equal to When the second code length is equal to l i Then the corresponding shortened position of the second mother code is Furthermore, it also satisfies: Where mt≥k≥0, 0≤s<2 m-k-1 .in, The sum of the upper half code lengths used to represent the first mother code (or the sub-blocks of the first mother code of various sizes) is greater than or equal to the sum of the lower half code lengths.

[0024] In one possible implementation, the second sequence is a shortened sequence or a naturally reversed bit index of the second mother code.

[0025] Based on the above scheme, pre-setting the second sequence to be a shortened sequence or the bit index of the second mother code in natural reverse order can achieve correct shortening and help improve decoding performance.

[0026] Based on the above scheme, the shortening method of the first mother code can be determined according to the shortening method of the second mother code, thus improving the flexibility of constructing the coding matrix. This allows for the construction of a coding matrix with fast polarization capability, further enhancing decoding performance. Furthermore, by limiting the sum of the upper half code lengths of the first mother code (or its various sizes of sub-blocks) to be greater than or equal to the sum of the lower half code lengths, decoding accuracy can be improved, thereby enhancing decoding performance.

[0027] In one possible implementation, m = 4, t = 3, N = 2; the N second code lengths are l1 = 7, l2 = 4 respectively; the first code length is equal to 11, and the first information bit number is equal to 8; The first rate matching method indicates that the first mother code is shortened according to the following shortening positions: 8, 13, 14, 15, 16.

[0028] Based on the above scheme, a shortening method with good decoding performance can be obtained, and then a coding matrix with fast polarization capability can be constructed.

[0029] In one possible implementation, m = 4, t = 3, N = 2; the N second code lengths are l1 = 7, l2 = 4 respectively; the first code length is equal to 11, and the first information bit number is equal to 8; The first rate matching method indicates that the first mother code is shortened according to the following shortening positions: 8, 10, 12, 14, 16.

[0030] Based on the above scheme, a shortening method with good decoding performance can be obtained, and then a coding matrix with fast polarization capability can be constructed.

[0031] In one possible implementation, the first code length is not an integer power of 2.

[0032] In one possible implementation, the encoding parameters further include information about the N sub-matrices, which includes the size of the sub-matrices and / or the value of each element position in the sub-matrices (i.e., 0 or 1).

[0033] Based on the above scheme, non-regular kernel polar codes based on rate matching can be obtained, thus improving decoding performance.

[0034] Thirdly, this application provides a communication device that has the functions involved in implementing the first aspect or any implementation method of the first aspect. For example, the communication device includes modules, units, or means corresponding to performing the operations involved in the first aspect or any implementation method of the first aspect. The functions, units, or means can be implemented by software, or by hardware, or by hardware executing corresponding software.

[0035] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in the first aspect described above.

[0036] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store computer programs or instructions that implement the functions described in the first aspect above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first aspect above, when the computer programs or instructions are executed.

[0037] In one possible design, the communication device includes a processor and a memory, the memory of which can store computer programs or instructions that implement the functions involved in the first aspect or any implementation method of the first aspect described above. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the first aspect or any implementation method of the first aspect described above.

[0038] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the first aspect or any implementation thereof described above. Optionally, the communication device further includes a memory for storing computer programs or instructions that, when executed by the processor, implement the first aspect or any implementation thereof described above.

[0039] Understandably, the processor in the third aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0040] Fourthly, this application provides a communication device that has the functions involved in implementing the second aspect or any implementation method of the second aspect. For example, the communication device includes modules, units, or means corresponding to performing the operations involved in the second aspect or any implementation method of the second aspect. The functions, units, or means can be implemented by software, or by hardware, or by hardware executing corresponding software.

[0041] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in the second aspect or any implementation method of the second aspect described above.

[0042] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store computer programs or instructions that implement the functions described in the second aspect above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the second aspect or any implementation thereof when the computer programs or instructions are executed.

[0043] In one possible design, the communication device includes a processor and a memory, the memory of which can store computer programs or instructions for implementing the functions described in the second and / or fourth aspects above. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the second aspect or any implementation method of the second aspect above.

[0044] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the second aspect or any implementation thereof described above. Optionally, the communication device further includes a memory for storing computer programs or instructions that, when executed by the processor, implement the second aspect or any implementation thereof described above.

[0045] Understandably, the processor in the fourth aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor, or the memory and processor can be separate. In specific implementations, the memory can be integrated with the processor on the same chip, or they can be set on different chips. This application does not limit the type of memory or the way the memory and processor are set.

[0046] Fifthly, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to execute the first aspect or any possible implementation of the first aspect, and the second communication device is used to execute the second aspect or any possible implementation of the second aspect.

[0047] Sixthly, this application provides a computer-readable storage medium storing a computer program (or computer-readable instructions) in which, when a computer reads and executes some or all of the computer-readable instructions, the method in any of the possible designs in the first to second aspects described above is executed.

[0048] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM) or other optical disk storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0049] In a seventh aspect, this application provides a computer program product that, when read and executed by a computer, causes any of the possible designs in the first to second aspects described above to be performed.

[0050] Eighthly, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that any of the possible designs in the first to second aspects described above are executed. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the architecture of a communication system applicable to the embodiments of this application;

[0052] Figure 2 This is a schematic diagram of a processing flow for the information source and the information sink in an embodiment of this application;

[0053] Figure 3(a) shows an 8×8 polarization transformation matrix provided in an embodiment of this application;

[0054] Figure 3(b) is a schematic diagram of the serial cancellation decoding calculation process provided in the embodiment of this application;

[0055] Figure 3(c) is a schematic diagram of the decoding path in the serial cancellation list decoding method provided in the embodiments of this application;

[0056] Figure 4 A flowchart illustrating the encoding method provided in an embodiment of this application;

[0057] Figure 5 A schematic diagram illustrating the process of constructing the encoding matrix;

[0058] Figure 6 A schematic diagram illustrating the process of constructing the encoding matrix;

[0059] Figure 7 A schematic diagram of simulation results provided for embodiments of this application;

[0060] Figure 8 A schematic diagram illustrating the process of constructing the encoding matrix;

[0061] Figure 9 A schematic diagram of simulation results provided for embodiments of this application;

[0062] Figure 10 A schematic diagram illustrating the process of constructing the encoding matrix;

[0063] Figure 11 This is a schematic diagram of a non-regular matrix;

[0064] Figure 12This is a schematic diagram illustrating the expansion of the generator matrix provided in an embodiment of this application;

[0065] Figure 13 This is a schematic diagram illustrating the expansion of the generator matrix provided in an embodiment of this application;

[0066] Figure 14 A schematic diagram for constructing the encoding matrix;

[0067] Figure 15 A flowchart illustrating the decoding method provided in an embodiment of this application;

[0068] Figure 16 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0069] Figure 17 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0070] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0071] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, Wireless Fidelity (Wi-Fi), Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, 5G mobile communication systems (such as New Radio (NR) systems), Future Communications systems, or other similar communication systems, and are not limited thereto. The embodiments of this application use... Figure 1 The communication system shown is used as an example for description. When the technical solutions of the embodiments of this application are applied to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0072] Figure 1 This is a schematic diagram of the architecture of the communication system used in the embodiments of this application. Figure 1 As shown, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as... Figure 1 110a and 110b may also include at least one terminal device, such as Figure 1 The series consists of 120a-120j. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example... Figure 1The mobile phones included are 120a, 120e, 120f, and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e, and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can connect to micro-station 110b, connect to laptop 120g, and connect to printer 120h. Mobile phone 120j can control drone 120i.

[0073] The communication system provided in this application may also include AI network elements for implementing some or all AI-related operations. AI network elements can also be referred to as AI nodes, AI devices, AI entities, AI modules, AI models, or AI units, etc. The AI ​​network elements may be built into the network elements of the communication system. For example, an AI network element may be an AI module built into: access network equipment, core network equipment, cloud server, or operation, administration, and maintenance (OAM) to implement AI-related functions. The OAM may act as the network management system for core network equipment and / or access network equipment. Alternatively, the AI ​​network element may also be an independently configured network element in the communication system. Optionally, the terminal or its built-in chip may also include AI entities for implementing AI-related functions.

[0074] (1) Network equipment

[0075] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0076] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0077] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (such as...) Figure 1 110a in the text), can also be a micro base station or an indoor station (such as... Figure 1 In 110b), it can also be a relay node or a donor node, etc. The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0078] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0079] (2) Terminal equipment

[0080] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, onboard units (OBUs) or telematics boxes (T-BOXs)), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0081] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device that includes the functions of the terminal device.

[0082] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0083] The roles of network devices and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol; in this case, 120i is also a network device relative to 110a. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. Figure 1 110a and 110b can be referred to as communication devices with network equipment functions. Figure 1 The 120a-120j in the text can be referred to as communication devices with terminal equipment functions.

[0084] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0085] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0086] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0087] (1) Channel coding and channel decoding

[0088] Figure 2 This is a schematic diagram illustrating a processing flow between the information source and the information sink. For example... Figure 2As shown, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source coding, and then performs channel coding on the bit sequence to be encoded to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the symbol sequence to be decoded, it performs channel decoding on the symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0089] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0090] There are various channel coding methods, such as polar coding or LDPC coding. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, exhibiting good performance approaching the Shannon limit, low decoding complexity, and flexible structure.

[0091] (2) Modulation and demodulation

[0092] See Figure 2 As shown, the transmitting end can also map the encoded bit sequence to the modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and then demodulate it to obtain the symbol sequence to be decoded.

[0093] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain a modulated symbol sequence. Demodulation is the inverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0094] (3) Information bit sequence

[0095] An information bit sequence refers to a sequence of bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence is 10101100101. In this application, K represents the length of the information bit sequence. The information bits may include payload bits. Optionally, the information bits may also include check bits, such as a cyclic redundancy check (CRC) code.

[0096] (4) Code length

[0097] Code length refers to the length of the bit sequence to be transmitted obtained by encoding the information bit sequence. The code length is greater than or equal to the length of the information bit sequence. In this application, E represents the code length.

[0098] (5) Bitrate

[0099] The code rate is the ratio of the length of the information bit sequence to the code length. In this application, R represents the code rate, therefore R = K / E.

[0100] The length, code length, and code rate of the information bit sequence can be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signals, and can also be obtained or calculated by the transmitting and receiving devices. For example, the transmitting and receiving devices can determine the code length based on the coding method, the frame structure used to transmit the information bits, the number of layers, and the modulation scheme. For example, the transmitting and receiving devices can obtain the code rate based on higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or determine the code rate based on the modulation and coding scheme (MCS), or determine the code rate based on the length and code length of the information bit sequence.

[0101] (6) Rate matching

[0102] Rate matching refers to removing some bits from the encoded bit sequence without transmitting them, or repeating some bits.

[0103] The rate matching method will be further explained in three categories below.

[0104] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding punctured positions, the log-likelihood ratio (LLR) of the corresponding bit is set to 0.

[0105] Shortening: Shortening involves fixing certain bit positions in the encoded bit sequence so that they do not need to be transmitted. On the decoding side, since the corresponding "shortened" positions are known at the receiver (usually 0), the LLR of the corresponding bit is set to infinity.

[0106] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0107] Taking polar codes as an example, the encoding length (i.e., the mother code length) of a polar code is an integer power of 2. In practical applications, the required length may be a non-encoded length. In this case, it is necessary to remove some bits from the encoded bit sequence without transmitting them, or to repeatedly transmit some bits.

[0108] (7) Polar code

[0109] (7.1) Polarization coding and polarization nuclei

[0110] Referring to Figure 3(a), in the encoding process, two adjacent columns constitute a coding layer. The left column of bits represents the input bits of the coding layer, and the right column represents the output bits. For example, in the leftmost coding layer, the input bit sequence is (0, 0, 0, 0, 0, 0, 1, 1), and the output bit sequence is (0, 0, 0, 0, 0, 0, 0, 1). The operation symbols in the middle of the coding layer... This represents the XOR operation, specifically... express The bits in the current row and A single XOR operation between the bits in the row. The bits on the right represent the result of the operation. For example, in the leftmost coding layer, the first input bit (value 0) and the second input bit (value 0) are processed... The operation yields the first output bit (with a value of 0).

[0111] The polar coding process involves several polarization kernel operations. Taking Figure 3(a) as an example, the polarization kernel operation can be understood as multiplying multiple input bits by the matrix corresponding to the polarization kernel to obtain the output bits. For example, the polarization kernel in Figure 3(a) is the Arikan polarization kernel, and the matrix corresponding to this polarization kernel is... That is, in each polarization kernel operation in Figure 3(a), two input bits are multiplied by the polarization kernel to obtain two output bits. Based on Figure 3(a), the polar codes can be considered as recursively constructed. For example, taking an information bit length of K=4 and a code length of N=8, the 8-length polar code [01010101] can be seen as a coupling of two 4-length polar codes. As shown, these two 4-length polar codes are the polar codes

[0000] corresponding to u0 to u3 and

[0101] corresponding to u4 to u7, respectively. Furthermore, these two 4-length polar codes can be considered as being obtained by coupling two 2-length polar codes, which are the output bits of the four polarization kernels in Figure 3(a).

[0112] The Arikan polarization kernel is a type of regular polarization kernel. Taking a regular polarization kernel as an example, the generator matrix of a polar code can be represented as: Defined as the Kronecker product of log₂N matrices F₂, where F₂ is... The G N It can also be called an Arikan polarization nucleus or a canonical polarization nucleus of length N.

[0113] Another type of polarization kernel is the non-regular polarization kernel. A non-regular polarization kernel is constructed by arranging the polarization trellis connection method according to the channel state or the specific number of information bits K. It can accelerate polarization without increasing decoding complexity. The size of the matrix corresponding to the non-regular polarization kernel can be N*N, where N is the code length, and the value of N does not have to be an integer power of 2. The non-regular polarization kernel can be associated with the information bit length K; that is, the connection method of an N*N non-regular polarization kernel can vary for different information bit lengths. Therefore, compared to the regular polarization kernel, the non-regular polarization kernel can select the connection method according to the information bit length K to improve the reliability of K information bits, thereby achieving better coding error correction performance. In this application, the size of the matrix can refer to the dimension of the matrix, that is, the number of rows and columns of the matrix.

[0114] Among them, the non-canonical polarization nucleus corresponds to K, or in other words, the non-canonical polarization nucleus corresponds to [N,K]. The non-canonical polarization nucleus C N,K This can represent a non-canonical polarization nucleus corresponding to [N,K]. C N,K It can be composed of non-canonical polarized nuclei corresponding to [N1, K1]. and the non-canonical polarized nuclei corresponding to [N-N1, K-K1]. The coupling is obtained, where N1 and K1 are positive integers, N1 < N, K1 < K.

[0115] (7.2) Polarization Decoding

[0116] There are several methods for decoding polar codes, such as successive cancellation (SC) decoding and successive cancellation list (SCL) decoding.

[0117] The SC decoding method refers to calculating the LLR of each decoded bit sequentially based on the LLR sequence corresponding to the bit sequence to be decoded, and making a bit-by-bit decision. When the decoded bit is an information bit, if the LLR of the decoded bit is greater than 0, then the decoded bit is 0; if the LLR of the decoded bit is less than 0, then the decoded bit is 1. When the decoded bit is a fixed bit, the decoding result is set to 0 regardless of the LLR value. Figure 3(b) is a schematic diagram of the SC decoding calculation process. Taking 4 decoded bits as an example, there are 8 calculation nodes in Figure 3(b), including 4 f nodes and 4 g nodes. The f nodes and g nodes correspond to the f operation and the g operation, respectively. The operation of the f node requires the two LLR inputs on its right side, and the operation of the g node requires the two LLR inputs on its right side and the output of the previous stage as inputs. Only after the input items are calculated can the output be calculated. According to the above calculation rules, the decoded bits obtained by calculating sequentially from the right side in Figure 3(b) are ①→②→③→④, and the decoding is completed.

[0118] The SCL decoding method refers to using the LLR sequence corresponding to the bit sequence to be decoded. When decoding each information bit, the decoding results corresponding to 0 and 1 are saved as two branch decoding paths (referred to as path splitting). Figure 3(c) shows a schematic diagram of the decoding paths in the SCL decoding method. As shown in Figure 3(c), each level represents one decoded bit. If the decoding result is 0, the path is developed along the left subtree; if the decoding result is 1, the path is developed along the right subtree. When the total number of decoding paths exceeds the preset path width L (generally L = 2, 4, 8, 16, or 32), the L paths with the best path metric (PM) value are selected, saved, and the path is further developed to decode subsequent bits. The PM value is used to judge the quality of the path, and the PM value is calculated using LLR. For each level of decoded bits, the PM values ​​of the L paths are sorted in ascending order, and the correct path is selected based on the PM value. This process is repeated until the last bit is decoded.

[0119] Currently, in polar coding, a coding matrix of size N*N is generally constructed using the mother code length N, and the information bit sequence is polar-coded using this matrix to obtain a encoded bit sequence of length N. Here, N is 2 to the power of n, and n is an integer greater than or equal to 1. Due to factors such as channel conditions and available transmission resources, the actual transmittable length E of the encoded bit sequence may not be equal to N. Therefore, rate matching is required for the encoded bit sequence of length N to obtain an encoded bit sequence of length E for transmission. Here, E is also called the code length or coding code length.

[0120] The decoding performance of polar codes is related to the rate matching method, and the decoding performance of current polar code rate matching schemes needs to be improved.

[0121] To address the aforementioned issues, this application provides corresponding solutions.

[0122] The methods provided in the embodiments of this application are described in detail below. The methods provided in the embodiments of this application involve a first communication device and / or a second communication device. The first communication device is a signal transmitter, and the second communication device is a signal receiver. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component used in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device. Similarly, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.), a component used in the communication device (e.g., a processor, a chip, or a chip system, etc.), or it can be a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device. For example, the first communication device is a network device and the second communication device is a terminal device; or, the first communication device is a terminal device and the second communication device is a network device.

[0123] Figure 4 This is a flowchart illustrating an encoding method provided in an embodiment of this application. The method is an implementation method on the encoding side, and includes the following steps:

[0124] Step 401: The first communication device performs polar coding on the first bit sequence according to the coding matrix to obtain the second bit sequence.

[0125] This encoding matrix is ​​a non-regular encoding matrix, or the encoding matrix corresponding to a non-regular polarization kernel. A regular encoding matrix refers to an encoding matrix constructed from a regular polarization kernel (or Arikan polarization kernel), for example, the structure shown in Figure 3(a) is a regular polarization kernel. A non-regular encoding matrix refers to an encoding matrix other than a regular encoding matrix.

[0126] The characteristic of a regular encoding matrix is ​​that the row weight of each row is a power of 2. The characteristic of a non-regular encoding matrix is ​​that the row weight of at least one row is not a power of 2. Here, row weight refers to the number of non-zero elements in a row of the matrix.

[0127] The encoding matrix in this embodiment includes N coupled sub-matrices. This encoding matrix is ​​determined based on encoding parameters and a first rate matching method. The encoding parameters include a first code length (denoted by E) and a first number of information bits (denoted by K). Optionally, the encoding parameters also include information about the N sub-matrices, including the size of the sub-matrices and the value (i.e., 0 or 1) of each element position within the sub-matrices.

[0128] The first code length is the code length corresponding to the encoding matrix, and the number of the first information bits is the same as the length of the first bit sequence. The first code length can be an integer power of 2, or it can be a non-integer power of 2.

[0129] The first rate matching method indicates the rate matching method for the first mother code; that is, rate matching is performed on the first mother code based on the first rate matching method to obtain the encoding matrix. This first rate matching method is determined based on N second code lengths corresponding to the aforementioned encoding parameters and N second rate matching methods. Each of the N second rate matching methods indicates the rate matching method for the second mother code corresponding to the corresponding sub-matrix; that is, rate matching of the second mother code using the second rate matching method yields a sub-matrix. Coupled together, the N sub-matrices yield the aforementioned encoding matrix.

[0130] There is a one-to-one correspondence between the N second code lengths, the N second rate matching methods, and the N sub-matrices. That is, there is a one-to-one correspondence between the N second code lengths and the N second rate matching methods, and a one-to-one correspondence between the N second code lengths and the N sub-matrices.

[0131] The second rate matching method can indicate a rate matching sequence, which can then be used for rate matching. For example, if the rate matching sequence is the first sequence, it can be used for puncturing. The first sequence can be a puncturing sequence (e.g., the forward sequence of natural order or other sequences). Punching with the forward sequence of natural order is also called sequential puncturing. The first sequence can also be the bit index of the second mother code in natural order. As another example, if the rate matching sequence is the second sequence, it can be used for shortening. The second sequence can be a shortening sequence (e.g., the reverse sequence of natural order, or other sequences (e.g., bit reversal)). Shortening with the reverse sequence of natural order is also called sequential shortening. Shortening with the bit reversal is also called bit reversal shortening. Alternatively, the second sequence can also be the bit index of the second mother code in natural reverse order.

[0132] Bit reversal shortening is a shortening pattern defined by simple rules, and the determination process is as follows:

[0133] Initialize an auxiliary sequence of length Z, where the first X elements are 1s and the last ZX elements are 0s. Reverse the bit order of the auxiliary sequence to obtain a new sequence. The positions of the 0s in this new sequence are the actual shortened bit positions. Here, Z represents the length of the second mother code, and X is the length of the second code. The elements of the auxiliary sequence are represented by q. i This indicates that the elements of the new sequence are represented by p. i Let i = 0, 1, 2, ..., Z-1. And satisfy: Where n = log2Z, D(b0,b1,…,b) n-1 This represents the binary sequence b0, b1, ..., b n-1 Similarly, the operations for converting to decimal numbers are performed, D(b) n-1 ,b n-2 (b, ..., b0) represents the binary sequence b n-1 ,b n-2 The operation of converting b0 to decimal numbers. The following example illustrates this.

[0134] Assuming Z = 8, X = 5, and n = 3, the auxiliary sequence is 11111000, where q0 to q4 are all 1 and q5 to q7 are all 0. Therefore:

[0135] ①p0=p D(000) =q D(000) =q0=1

[0136] ②p1=p D(001) =q D(100) =q4=1

[0137] ③p2=pD(010) =q D(010) =q2=1

[0138] ④p3=p D(011) =q D(110) =q6=0

[0139] ⑤p4=p D(100) =q D(001) =q1=1

[0140] ⑥p5=p D(101) =q D(101) =q5=0

[0141] ⑦p6=p D(110) =q D(011) =q3=1

[0142] ⑧p7=p D(111) =q D(111) =q7=0

[0143] Since p3 = p5 = p7 = 0, the shortened bit positions are 3, 5, and 7. These shortened bit positions 3, 5, and 7 refer to the 4th, 6th, and 8th bits of the second mother code, respectively. Therefore, it can also be expressed as: the shortened bit positions of the 4th, 6th, and 8th bits of the second mother code.

[0144] Furthermore, p0, p1, p2, p3, p4, p5, p6, p7 correspond one-to-one with q0, q4, q2, q6, q1, q5, q3, q7. Therefore, a bit-reversed shortening sequence can be constructed, i.e., [7, 3, 5, 1, 6, 2, 4, 0], where the numbers in this sequence refer to the bit positions starting from 0. If described according to natural ordering, the bit-reversed shortening sequence can also be described as: [8, 4, 6, 2, 7, 3, 5, 1], where each number in this sequence refers to the order of the shortened bit position in the second mother code, i.e., the i-th shortened bit position, i = 1, 2, ..., 8.

[0145] As one implementation method, the first communication device performs polar coding on the first bit sequence according to the coding matrix. For example, the first communication device may place the first bit sequence in the information bit position and add frozen bits in the pre-frozen bit position to obtain the bit sequence to be encoded. The bit sequence to be encoded is then multiplied by the coding matrix to obtain the second bit sequence. The specific implementation method for determining the information bit position can be found in the following explanation (related to...). Figures 11-14 ).

[0146] Step 402: The first communication device modulates the second bit sequence to obtain modulation symbol information.

[0147] This application does not limit the modulation method. For specific implementation methods of modulation, please refer to the description of related technologies.

[0148] Step 403: The first communication device outputs modulation symbol information.

[0149] The output modulation symbol information here can be sent to the second communication device via the air interface, or it can be output to the transceiver of the first communication device via the input / output interface, and the transceiver can then send the corresponding signal to the second communication device via the air interface.

[0150] Based on the above scheme, since the coding matrix used for polarization coding is determined according to the first rate matching method, which is determined according to the N second code lengths and N second rate matching methods corresponding to the coding parameters, this method determines the first rate matching method of the coding matrix corresponding to the larger first code length based on the smaller N second code lengths and the corresponding N second rate matching methods. This can improve the flexibility of constructing the coding matrix, and thus a coding matrix with fast polarization capability can be constructed, thereby improving the decoding performance.

[0151] The specific implementation method for determining the first rate matching mode in the embodiments of this application will be described below.

[0152] The following uses 2 m This indicates the length of the first mother code, where m is an integer greater than 1, expressed in 2^m. t This represents the length of the second mother code, where t is a positive integer. Therefore, the number of second code lengths is 2. m-t For example, E indicates the length of the first yard. This represents the function for rounding up.

[0153] In the first implementation method, each of the N second rate matching methods indicates the shortening position of the second mother code corresponding to its submatrix, and the first rate matching method is determined based on the shortening position indicated by the N second rate matching methods.

[0154] For example, the first rate matching method is used to indicate that the first mother code is shortened according to the following shortening positions: The second rate matching information is used to indicate the sequence. The second mother code is shortened. The lengths of the N second codes are as follows: Among them, l i ≤2 t i = 1, 2, ..., 2 m-t The first yard length is equal to When the second code length is equal to l i Then the shortened position of the corresponding second mother code is Furthermore, it also satisfies: Where mt≥k≥0, 0≤s<2 m-k-1 .in, The sum of the upper half code lengths used to represent the first mother code (or the sub-blocks of the first mother code of various sizes) is greater than or equal to the sum of the lower half code lengths.

[0155] For example, the correspondence between the first code length, the first number of information bits, and N second code lengths can be pre-stored (e.g., stored as a function or table). Therefore, after determining the first code length and the first number of information bits, the size of N and the specific values ​​of the N second code lengths can be determined by looking up this correspondence. That is, after determining the first code length and the first number of information bits, the [missing information] can be determined. The value of .

[0156] For example, the second sequence is either a shortened sequence or the bit index of the naturally reversed second mother code. When the second sequence is the bit index of the naturally reversed second mother code, it can also be considered that there is no concept of a shortened sequence; instead, the second mother code is shortened from back to front. In this case, the second sequence can also be expressed as: 2 t ,2 t -1,…,1, or expressed as: 2 t -1,2 t -2,…,0.

[0157] Example 1

[0158] The first mother code has a size of 16, i.e., m = 4. The first code length E = 11, and the first information bit count K = 8. By looking up a table, it is determined that constructing the encoding matrix corresponding to this first code length and first information bit count requires two second code lengths, i.e., N = 2. One second code length has a size of l1 = 7, and the other has a size of l2 = 4. Furthermore, the second information bit count corresponding to the second code length can be calculated. For example, l1 corresponds to the second information bit count K1 = 4, and l2 corresponds to the second information bit count K2 = 4. Here, E = l1 + l2, ​​and K = K1 + K2. This can also be understood as the encoding matrix corresponding to E = 11, K = 8 being obtained by coupling the submatrix corresponding to l1 = 7, K1 = 4 and the submatrix corresponding to l2 = 4, K2 = 4; or it can be understood as the encoding matrix corresponding to E = 11, K = 8 being determined by the non-regular polarization kernel corresponding to l1 = 7, K1 = 4 and the non-regular polarization kernel corresponding to l2 = 4, K2 = 4.

[0159] With m = 4 and N = 2, t = 3. Since l1 = 7, the number of bits that need to be shortened in the second mother code is 8 - 7 = 1. Since l2 = 4, the number of bits that need to be shortened in the second mother code is 8 - 4 = 4.

[0160] Assumption The value is [8,7,6,5,4,3,2,1], which means that the shortening order of the second mother code is sequential shortening, that is, the shortening position is selected from back to front. Then the first rate matching method indicates that the first mother code (obtained by coupling two second mother codes) is shortened according to the following shortening positions: 8,13,14,15,16.

[0161] Figure 5 This is a schematic diagram illustrating the process of constructing the encoding matrix corresponding to Example 1. The non-regular polarization kernel corresponding to the encoding matrix to be constructed is represented by C. 11,8 This indicates that the non-regular polarization kernels corresponding to the two sub-matrices used to couple the encoding matrix are represented by C. 7,4 and C 4,4 This indicates that C can be obtained by shortening the last bit position (i.e., sub-channel 8, or shortened position 8) of the upper half (i.e., one of the second mother codes). 7,4 C is obtained by shortening the last 4 bits of the lower half (i.e., another second mother code) (i.e., sub-channels 8, 7, 6, 5, or shortened positions 8, 7, 6, 5). 4,4 Therefore, the determined first rate matching method indicates that the first mother code (obtained by coupling two second mother codes) is shortened at the following shortening positions: 8, 13, 14, 15, 16. Wherein, Figure 5 The dashed lines in the diagram represent sub-channels that need to be shortened.

[0162] Example 2

[0163] The first mother code has a size of 16, i.e., m = 4. The first code length E = 11, and the first information bit count K = 8. By looking up a table, it is determined that constructing the encoding matrix corresponding to this first code length and first information bit count requires two second code lengths, i.e., N = 2. One second code length has a size of l1 = 7, and the other has a size of l2 = 4. Furthermore, the second information bit count corresponding to the second code length can be calculated. Specifically, l1 corresponds to the second information bit count K1 = 4, and l2 corresponds to the second information bit count K2 = 4. Here, E = l1 + l2, ​​and K = K1 + K2. This can also be understood as the encoding matrix corresponding to E = 11, K = 8 being obtained by coupling the submatrix corresponding to l1 = 7, K1 = 4 and the submatrix corresponding to l2 = 4, K2 = 4. Alternatively, it can be understood as the encoding matrix corresponding to E = 11, K = 8 being determined by the non-regular polarization kernel corresponding to l1 = 7, K1 = 4 and the non-regular polarization kernel corresponding to l2 = 4, K2 = 4.

[0164] With m = 4 and N = 2, t = 3. Since l1 = 7, the number of bits that need to be shortened in the second mother code is 8 - 7 = 1. Since l2 = 4, the number of bits that need to be shortened in the second mother code is 8 - 4 = 4.

[0165] Assumption The shortening order of the second mother code is [8,4,6,2,7,3,5,1], which is also known as bit reversal shortening. The first rate matching method indicates that the first mother code (obtained by coupling two second mother codes) is shortened according to the following shortening positions: 8,10,12,14,16.

[0166] Figure 6 This is a schematic diagram illustrating the process of constructing the encoding matrix corresponding to Example 2. The non-regular polarization kernel corresponding to the encoding matrix to be constructed is represented by C. 11,8 This indicates that the non-regular polarization kernels corresponding to the two sub-matrices used to couple the encoding matrix are represented by C. 7,4 and C 4,4 This indicates that C can be obtained by shortening the last bit position (i.e., sub-channel 8, or shortened position 8) of the upper half (i.e., one of the second mother codes). 7,4 C is obtained by shortening the 2nd, 4th, 6th, and 8th bits of the lower half (i.e., another second mother code) (i.e., sub-channels 2, 4, 6, 8, or shortened positions 2, 4, 6, 8). 4,4 Therefore, the determined first rate matching mode indicates that the first mother code (obtained by coupling two second mother codes) is shortened at the following shortening positions: 8, 10, 12, 14, 16. Wherein, Figure 6 The dashed lines in the diagram represent sub-channels that need to be shortened.

[0167] Figure 7 This is a schematic diagram of simulation results provided for an embodiment of this application. The decoding method used is successive cancellation (SC). The horizontal axis in the diagram represents the signal-to-noise ratio (SNR), and the vertical axis represents the block error ratio (BLER). It can be seen that, using the above-mentioned... Figure 5 or Figure 6 The method shown has a smaller BLER for the same SNR compared to the existing Arikan order shortening method. Therefore, the encoding method provided in this application has better decoding performance.

[0168] In the second implementation method, each of the N second rate matching methods indicates the punching position of the second mother code corresponding to its submatrix, and the first rate matching method is determined based on the punching positions indicated by the N second rate matching methods.

[0169] For example, the first rate matching method is used to indicate that the first master code is punched at the following punching positions: The second rate matching method is used to indicate that the first sequence is followed. Punch holes in the second mother code. The lengths of the N second codes are as follows: Among them, l i ≤2 t i = 1, 2, ..., 2 m-t The first yard length is equal to When the second code length is equal to l i Then the corresponding punch position of the second mother code is Furthermore, it also satisfies: Where mt≥k≥0, 0≤s<2 m-k-1 .in, The sum of the upper half code lengths used to represent the first mother code (or the sub-blocks of the first mother code of various sizes) is less than or equal to the sum of the lower half code lengths.

[0170] For example, the correspondence between the first code length E and N second code lengths can be pre-stored (e.g., stored as a function or table). Therefore, after determining the first code length E, the size of N and the specific values ​​of the N second code lengths can be determined by looking up this correspondence. That is, after determining the first code length, it is possible to... The value of .

[0171] For example, the first sequence is either a punctured sequence or a bit index of the second mother code in natural order. When the first sequence is a bit index of the second mother code in natural order, it can be considered that there is no concept of a punctured sequence; instead, puncturing is performed on the second mother code from front to back. In this case, the first sequence can also be expressed as: 1,2,…,2 t Or expressed as 0,1,…,2 t -1. The following section will explain the implementation method two with specific examples.

[0172] Example 3

[0173] The size of the first mother code is 32, i.e., m = 5. The first code length E = 22, and the first information bit number K = 11. By looking up a table, it is determined that constructing the encoding matrix corresponding to this first code length and first information bit number requires four second code lengths, i.e., N = 4. The sizes of these four second code lengths are: l1 = 4, l2 = 6, l3 = 5, and l4 = 7. Furthermore, the second information bit number corresponding to the second code length can be calculated. Specifically, the second information bit number K1 = 0 for l1, K2 = 3 for l2, K3 = 3 for l3, and K4 = 5 for l4. Where E = l1 + l2 + l3 + l4, and K = K1 + K2 + K3 + K4. This can also be understood as follows: the encoding matrix corresponding to E=22, K=11 is obtained by coupling the submatrix corresponding to l1=4, K1=0, l2=6, K2=3, l3=5, K3=3, and l4=7, K4=5. Alternatively, the encoding matrix corresponding to E=22, K=11 is determined by the non-regular polarization kernel corresponding to l1=4, K1=0, l2=6, K2=3, l3=5, K3=3, and l4=7, K4=5.

[0174] With m = 5 and N = 4, t = 3. Since l1 = 4, the number of bits that need to be punched in the second numeric code is 8 - 4 = 4. Since l2 = 6, the number of bits that need to be punched in the second numeric code is 8 - 6 = 2. Since l3 = 5, the number of bits that need to be punched in the second numeric code is 8 - 5 = 3. Since l4 = 7, the number of bits that need to be punched in the second numeric code is 8 - 7 = 1.

[0175] Assumption The value is [1,2,3,4,5,6,7,8], which means the punching order of the second mother code is sequential punching, that is, the punching position is selected from front to back. Then the first rate matching mode indicates that the first mother code (obtained by coupling 4 second mother codes) is punched according to the following punching positions: 1,2,3,4,9,10,17,18,19,25.

[0176] Figure 8 This is a schematic diagram illustrating the process of constructing the encoding matrix corresponding to Example 3. The non-regular polarization kernel corresponding to the encoding matrix to be constructed is represented by C. 22,11 This indicates that the non-regular polarization kernels corresponding to the four sub-matrices used to couple the encoding matrix are represented by C. 4,0 C 6,3 C 5,3 and C 7,5This indicates that C is obtained by punching the 1st, 2nd, and 3rd bits (i.e., sub-channels 1, 2, 3, or puncturing positions 1, 2, 3) of the first 1 / 4 portion of the first mother code (i.e., the first second mother code). 4,0 C is obtained by punching the first and second bits (i.e., sub-channels 1 and 2, or puncturing positions 1 and 2) of the second quarter portion of the first mother code (i.e., the second second mother code). 6,3 C is obtained by punching the 1st, 2nd, and 3rd bits (i.e., sub-channels 1, 2, 3, or puncturing positions 1, 2, 3) of the third quarter portion of the first mother code (i.e., the third second mother code). 5,3 C is obtained by punching the first bit position (i.e., sub-channel 1, or puncturing position 1) of the fourth 1 / 4 part of the first mother code (i.e., the fourth second mother code). 7,5 Therefore, the determined first rate matching method indicates that the first mother code (obtained by coupling four second mother codes) is punctured at the following positions: 1, 2, 3, 4, 9, 10, 17, 18, 19, 25. Wherein, Figure 8 The dashed lines in the diagram represent sub-channels that require punching.

[0177] Example 4

[0178] The first mother code has a size of 64, i.e., m = 6. The first code length E = 36, and the first information bit number K = 17. By looking up a table, it is determined that constructing the encoding matrix corresponding to this first code length and first information bit number requires four second code lengths, i.e., N = 4. The sizes of these four second code lengths are: l1 = 8, l2 = 9, l3 = 9, and l4 = 10. E = l1 + l2 + l3 + l4. Alternatively, it can be understood that the encoding matrix corresponding to E = 36 and K = 17 is obtained by coupling the submatrix corresponding to l1 = 8, l2 = 9, l3 = 9, and l4 = 10. Or, it can be understood that the encoding matrix corresponding to E = 36 and K = 17 is determined by the non-regular polarization kernels corresponding to l1 = 8, l2 = 9, l3 = 9, and l4 = 10.

[0179] With m = 6 and N = 4, t = 4. Since l1 = 8, the number of bits that need to be punched in the second numeric code is 16 - 8 = 8. Since l2 = 9, the number of bits that need to be punched in the second numeric code is 16 - 9 = 7. Since l3 = 9, the number of bits that need to be punched in the second numeric code is 16 - 9 = 7. Since l4 = 10, the number of bits that need to be punched in the second numeric code is 16 - 10 = 6.

[0180] Assumption The value is [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16]. That is, the punching order of the second mother code is sequential punching, that is, the punching position is selected from front to back. Then the first rate matching mode indicates that the first mother code (obtained by coupling 4 second mother codes) is punched according to the following punching positions: 1~8, 17~23, 33~39, 49~54.

[0181] Figure 9 This is a schematic diagram of simulation results provided for an embodiment of this application. The decoding method used is the SC method. The horizontal axis represents SNR, and the vertical axis represents BLER. As can be seen, using the method shown in Example 4 above, compared to the prior art method using Arikan sequential puncturing, it has a smaller BLER for the same SNR. Therefore, the encoding method provided in this embodiment of the application has better decoding performance.

[0182] In the third implementation method, each of the N second rate matching methods indicates the punching position and / or shortening position of the second mother code corresponding to its submatrix. The first rate matching method is determined based on the punching position and / or shortening position indicated by the N second rate matching methods.

[0183] Using this method, each second mother code can be punched only, shortened only, or punched and shortened simultaneously.

[0184] The following section will illustrate this third implementation method with specific examples.

[0185] Example 5

[0186] The first mother code has a size of 16, i.e., m = 4. The first code length E = 11, and the first information bit count K = 8. By looking up a table, it is determined that constructing the encoding matrix corresponding to this first code length and first information bit count requires two second code lengths, i.e., N = 2. One second code length has a size of l1 = 7, and the other has a size of l2 = 4. Furthermore, the second information bit count corresponding to the second code length can be calculated. Specifically, l1 corresponds to the second information bit count K1 = 4, and l2 corresponds to the second information bit count K2 = 4. Here, E = l1 + l2, ​​and K = K1 + K2. This can also be understood as the encoding matrix corresponding to E = 11, K = 8 being obtained by coupling the submatrix corresponding to l1 = 7, K1 = 4 and the submatrix corresponding to l2 = 4, K4 = 4. Alternatively, it can be understood as the encoding matrix corresponding to E = 11, K = 8 being determined by the non-regular polarization kernel corresponding to l1 = 7, K1 = 4 and the non-regular polarization kernel corresponding to l2 = 4, K2 = 4.

[0187] With m = 4 and N = 2, t = 3. Since l1 = 7, the total number of bits that need to be punctured and / or shortened in the corresponding second mother code is 8 - 7 = 1. Since l2 = 4, the total number of bits that need to be punctured and / or shortened in the corresponding second mother code is 8 - 4 = 4.

[0188] The upper half of the first mother code uses sequential puncturing for rate matching, i.e., the puncturing sequence is [1,2,3,4,5,6,7,8], so the puncturing position is 1. The lower half of the first mother code uses sequential puncturing and sequential shortening for rate matching, where the number of puncturing bits is 1 and the number of shortening bits is 3, so the puncturing position is 1 and the shortening positions are 6,7,8. Therefore, the first rate matching method indicates that the first mother code (obtained by coupling two second mother codes) is shortened and punctured according to shortening positions 14,15,16 and puncturing positions 1,9.

[0189] Figure 10 This is a schematic diagram illustrating the process of constructing the encoding matrix corresponding to Example 5. The non-regular polarization kernel corresponding to the encoding matrix to be constructed is represented by C. 11,8 This indicates that the non-regular polarization kernels corresponding to the two sub-matrices used to couple the encoding matrix are represented by C. 7,4 and C 4,4 This indicates that C can be obtained by punching the first bit position (i.e., sub-channel 1, or puncture position 1) of the upper half (i.e., one of the second mother codes). 7,4 By punching the first bit position (i.e., sub-channel 1, or punctured position 1) of the lower half (i.e., another second mother code), and shortening the 6th, 7th, and 8th bit positions (i.e., sub-channels 6, 7, and 8, or shortened positions 6, 7, and 8), C is obtained. 4,4 Therefore, the determined first rate matching method indicates that the first mother code (obtained by coupling two second mother codes) is shortened and punctured according to shortening positions 14, 15, 16 and puncturing positions 1, 9. Wherein, Figure 10 The dashed lines in the text represent sub-channels that need to be shortened or punched.

[0190] The following section uses the second implementation method described above as an example to illustrate the process of constructing the encoding matrix after determining the first rate matching method.

[0191] Assume the length of the first mother code is 16, the number of second mother codes is N=2, the puncturing sequence is [1,5,3,7,2,6,4,8], E=11, K=7, l1=5, l2=6, the upper half of the first mother code (corresponding to one second mother code) indicates the puncturing position of the second rate matching method as 1,5,3, and the lower half of the first mother code (corresponding to another second mother code) indicates the puncturing position of the second rate matching method as 1,5. Therefore, the first rate matching method indicates the puncturing position of the first mother code as 1,3,5,9,13.

[0192] Next, based on the reliability sequence of the first mother code, the number of information bits in the sub-matrix corresponding to each second mother code is determined. The reliability sequence represents the reliability ranking of each sub-channel in the first mother code. For example, a reliability sequence of [1,2,3,5,9,4,6,10,7,11,13,8,12,14,15,16] is used. Each number in this reliability sequence represents a sub-channel (or bit position) of the first mother code, and the reliability of a later-ranked sub-channel is greater than that of an earlier-ranked sub-channel. Puncture positions 1,3,5,9,13 are removed (or pre-frozen) from the reliability sequence, resulting in the sequence [2,4,6,10,7,11,8,12,14,15,16]. Then, K information bit positions (i.e., 7 bits) are read from back to front, resulting in 7,11,8,12,14,15,16. As can be seen, since 7 and 8 are located in the upper half of the first mother code, the number of information bits (i.e., K1) of the submatrix corresponding to the upper half of the first mother code is equal to 2. Since 11, 12, 14, 15, and 16 are located in the lower half of the first mother code, the number of information bits (i.e., K2) of the submatrix corresponding to the lower half of the first mother code is equal to 5.

[0193] Then, the generator matrix corresponding to the second code length and the second number of information bits is determined. For example, Table 1 defines the correspondence between the second code length, the second number of information bits, and the generator matrix. In Table 1, l represents the second code length, and K represents the second number of information bits. It can be seen that the generator matrices given in the table include: a regular matrix (i.e., the matrix corresponding to the Arikan polarization kernel, abbreviated as Arikan), a matrix obtained by shortening the regular matrix (abbreviated as Arikan shortening), a matrix obtained by puncturing the regular matrix (abbreviated as Arikan puncturing), and other predefined non-regular matrices (e.g., G). 8,6 G 8,5 G 7,5 wait).

[0194] Table 1

[0195] l＝8 l＝7 l＝6 l＝5 l＝4 K＝8 Arikan K＝7 Arikan Arikan shortened K＝6 <![CDATA[G 8,6 ]]> Arikan shortened Arikan shortened K＝5 <![CDATA[G 8,5 ]]> <![CDATA[G 7,5 ]]> Arikan shortened Arikan shortened K＝4 Arikan Arikan punch <![CDATA[G 6,3 ]]> Arikan shortened Arikan K＝3 <![CDATA[G 8,3 ]]> Arikan shortened <![CDATA[G 6,3 ]]> <![CDATA[G 5,3 ]]> Arikan K＝2 <![CDATA[G 8,2 ]]> <![CDATA[G 7,2 ]]> <![CDATA[G 6,3 ]]> <![CDATA[G 5,2 ]]> <![CDATA[G 4,2 ]]> K＝1 Arikan Arikan punch Arikan punch Arikan punch Arikan K＝0 Arikan Arikan punch Arikan punch Arikan punch Arikan

[0196] The specific element values ​​for each non-regular matrix shown in Table 1 can be found by referring to... Figure 11 .

[0197] Based on the preceding description, the first code length E = 11 and K = 7 correspond to two generator matrices. One of these generator matrices has a second code length l1 = 5 and a second information bit count K1 = 2. By looking up Table 1, the generator matrix is ​​determined to be G. 5,2 (Hereinafter referred to as F1); The second code length l2 = 6 and the second information bit number K2 = 5 of the other generator matrix are determined by looking up Table 1. The generator matrix is ​​a generator matrix corresponding to the shortened Arikan matrix (hereinafter referred to as F2). Specifically, F2 is obtained by shortening the 8*8 Arikan matrix.

[0198] Next, the encoding matrix is ​​constructed using the generator matrices F1 and F2. (See reference) Figure 12 The generated matrix F1 is expanded into an 8x8 matrix Q1, where the punched bits in Q1 are 1, 3, and 5. Therefore, the rows and columns in Q1 corresponding to these punched bits can be called the expanded rows and expanded columns. Bits 1-5 of F1 correspond to bits 2, 4, 6, 7, and 8 of Q1, and the information bits in Q1 are 7 and 8. (Reference) Figure 13 The generator matrix F2 is expanded into an 8x8 matrix Q2, where the punched bits in Q2 are 1 and 5. Therefore, the rows and columns in Q2 corresponding to the punched bits can be called the expanded rows and columns. Bits 1-6 of F2 correspond to bits 2, 3, 4, 6, 7, and 8 of Q2, and the information bits in Q2 are 3, 4, 6, 7, and 8. Then, Q1 and Q2 are coupled into a 16x16 target matrix according to the rules of Arikan polar codes (see reference). Figure 14 Then, according to the first rate matching method, rate matching is performed on the target matrix to obtain a coding matrix with a first code length E=11 and K=7. The first rate matching method indicates that rows 1, 3, 5, 9, and 13 of the target matrix are punctured.

[0199] Figure 15 This is a flowchart illustrating a decoding method provided in an embodiment of this application. The method is an implementation method on the decoding side, and includes the following steps:

[0200] Step 1501: The second communication device acquires modulation symbol information.

[0201] For example, the second communication device receives modulation symbol information from the first communication device via an air interface, or receives a signal from the first communication device and obtains modulation symbol information based on the signal.

[0202] Step 1502: The second communication device demodulates the modulation symbol information to obtain the sequence to be decoded.

[0203] This application does not limit the demodulation method. For specific implementation methods of demodulation, please refer to the description of related technologies.

[0204] Step 1503: The second communication device performs polarization decoding on the sequence to be decoded according to the encoding matrix to obtain the decoding result.

[0205] The encoding matrix is ​​the same as the aforementioned Figure 4 The encoding matrix in the embodiments is the same, and can be referred to the foregoing description.

[0206] For example, the decoding result is the same as the aforementioned Figure 4 The first bit sequence is the same as in the embodiments, or the decoding result contains a portion of the bits in the first bit sequence.

[0207] Based on the above scheme, since the coding matrix used for polarization coding is determined according to the first rate matching method, which is determined according to the N second code lengths and N second rate matching methods corresponding to the coding parameters, this method determines the first rate matching method of the coding matrix corresponding to the larger first code length based on the smaller N second code lengths and the corresponding N second rate matching methods. This can improve the flexibility of constructing the coding matrix, and thus a coding matrix with fast polarization capability can be constructed, thereby improving the decoding performance.

[0208] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first communication device and the second communication device. It is understood that, in order to achieve the above functions, the first communication device and the second communication device may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0209] In this application embodiment, the first communication device and the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0210] When using integrated units, Figure 16A possible exemplary block diagram of the apparatus involved in an embodiment of this application is shown. For example... Figure 16 As shown, device 1600 may include a processing unit 1602 and a communication unit 1603. The processing unit 1602 is used to control and manage the operation of device 1600. The communication unit 1603 is used to support communication between device 1600 and other devices. Optionally, the communication unit 1603, also called a transceiver unit, may include a receiving unit and / or a transmitting unit, respectively used to perform receiving and transmitting operations. Device 1600 may also include a storage unit 1601 for storing program code and / or data of device 1600.

[0211] The device 1600 can be the first communication device in the above embodiments. The processing unit 1602 can support the device 1600 in performing the operations of the first communication device in the above method embodiments. Alternatively, the processing unit 1602 mainly performs the internal operations of the first communication device in the method embodiments, and the communication unit 1603 can support communication between the device 1600 and other devices.

[0212] For example, in one embodiment, processing unit 1602 is used to polarize the first bit sequence according to the encoding matrix to obtain a second bit sequence; and to modulate the second bit sequence to obtain modulation symbol information; communication unit 1603 is used to output the modulation symbol information; wherein, the encoding matrix includes N coupled sub-matrices, the encoding matrix is ​​determined according to encoding parameters and a first rate matching method, the encoding parameters include a first code length and a first number of information bits, the first rate matching method indicates the rate matching method for the first mother code, the first rate matching method is determined according to N second code lengths and N second rate matching methods corresponding to the encoding parameters, the N second code lengths, the N second rate matching methods and the N sub-matrices are in one-to-one correspondence, and each of the N second rate matching methods indicates the rate matching method for the second mother code corresponding to its corresponding sub-matrix.

[0213] The device 1600 can be the second communication device in the above embodiments. The processing unit 1602 can support the device 1600 in performing the operations of the second communication device in the above method embodiments. Alternatively, the processing unit 1602 mainly performs the internal operations of the second communication device in the method embodiments, and the communication unit 1603 can support communication between the device 1600 and other devices.

[0214] For example, in one embodiment, a communication unit 1603 is used to acquire modulation symbol information; a processing unit 1602 is used to demodulate the modulation symbol information to obtain a sequence to be decoded; and to perform polarization decoding on the sequence to be decoded according to the encoding matrix to obtain a decoding result; wherein, the encoding matrix includes N coupled sub-matrices, the encoding matrix is ​​determined according to encoding parameters and a first rate matching method, the encoding parameters include a first code length and a first number of information bits, the first rate matching method indicates the rate matching method for a first mother code, the first rate matching method is determined according to N second code lengths and N second rate matching methods corresponding to the encoding parameters, the N second code lengths, the N second rate matching methods and the N sub-matrices are in one-to-one correspondence, and each of the N second rate matching methods indicates the rate matching method for the second mother code corresponding to its corresponding sub-matrix.

[0215] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and some units can be implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations of the above methods or the various units mentioned above can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0216] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a general-purpose central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together and implemented as a System-on-a-Chip (SoC).

[0217] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0218] Based on the same technical concept, embodiments of this application also provide a communication device, which is used to implement the functions of the first or second communication device in the above embodiments. For example... Figure 17 As shown, the device can be a communication device or a component for the communication device (e.g., a processor, chip, or chip system). The component for the communication device can be a component within the communication device, or it can be independent of the communication device. The device includes a processor 1701 and a communication interface 1702, and optionally, it also includes a memory 1703. The memory 1703 can be independent of the processor 1701, or it can be integrated into the processor 1701; the specifics are not limited. It is understood that... Figure 17 Only the main components of the communication device are shown. In one possible implementation, the communication device may further include input / output devices (not shown in the figure).

[0219] The processor 1701 is used to execute the program code stored in the memory 1703, specifically to perform the actions of the aforementioned processing unit 1602, which will not be described in detail here. The communication interface 1702 is specifically used to perform the actions of the aforementioned communication unit 1603, which will not be described in detail here.

[0220] Processor 1701 can be a CPU, a digital processing unit, etc. Processor 1701 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 1702 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 1701 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of this application do not limit the specific implementation of the above-mentioned devices.

[0221] The communication interface 1702 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 1702 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Optionally, the communication interface 1702 can be an input / output interface or a chip pin.

[0222] Input / output devices, such as touchscreens, displays, and keyboards, are primarily used to receive user input data and output data to the user.

[0223] Memory 1703 is used to store programs executed by processor 1701. Memory 1703 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as cache or random-access memory (RAM). Memory 1703 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited to these.

[0224] When the communication device is powered on, the processor 1701 can read the software program in the memory 1703, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1701 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1701. The processor 1701 converts the baseband signal into data and processes the data.

[0225] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0226] This application embodiment does not limit the specific connection medium between the communication interface 1702, processor 1701, and memory 1703. This application embodiment... Figure 17 The memory 1703, processor 1701, and communication interface 1702 are connected via a bus 1704. Figure 17 The connections between other components are shown in bold lines only and are not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, Figure 17 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0227] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be:

[0228] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0229] (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions;

[0230] (3) Application-specific integrated circuit (ASIC), such as modem;

[0231] (4) Modules that can be embedded in other devices;

[0232] (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.;

[0233] (6) Others, etc.

[0234] This application provides a chip (or chip system) including a processor for implementing any of the above-described method embodiments.

[0235] This application provides a computer-readable storage medium storing a computer program or instructions that, when executed, implement any of the above-described method embodiments.

[0236] This application provides a computer program product, which includes a computer program or instructions that, when executed, implement any of the above-described method embodiments.

[0237] This application provides a communication system, including a first communication device and a second communication device in the above method embodiments.

[0238] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0239] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of this application are used to distinguish between two communication devices, and do not limit the priority or importance of these two communication devices.

[0240] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0241] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0242] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0243] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

Claims

1. An encoding method, characterized in that, include: Based on the encoding matrix, the first bit sequence is polar-coded to obtain the second bit sequence; The second bit sequence is modulated to obtain modulation symbol information; Output the modulation symbol information; The encoding matrix comprises N coupled sub-matrices. The encoding matrix is ​​determined based on encoding parameters and a first rate matching method. The encoding parameters include a first code length and a first number of information bits. The first rate matching method indicates the rate matching method for a first mother code. The first rate matching method is determined based on N second code lengths and N second rate matching methods corresponding to the encoding parameters. The N second code lengths, the N second rate matching methods, and the N sub-matrices correspond one-to-one. Each of the N second rate matching methods indicates the rate matching method for the second mother code corresponding to its corresponding sub-matrix.

2. A decoding method, characterized in that, include: Obtain modulation symbol information; The modulation symbol information is demodulated to obtain the sequence to be decoded; Based on the encoding matrix, polarization decoding is performed on the sequence to be decoded to obtain the decoding result; The encoding matrix comprises N coupled sub-matrices. The encoding matrix is ​​determined based on encoding parameters and a first rate matching method. The encoding parameters include a first code length and a first number of information bits. The first rate matching method indicates the rate matching method for a first mother code. The first rate matching method is determined based on N second code lengths and N second rate matching methods corresponding to the encoding parameters. The N second code lengths, the N second rate matching methods, and the N sub-matrices correspond one-to-one. Each of the N second rate matching methods indicates the rate matching method for the second mother code corresponding to its corresponding sub-matrix.

3. The method as described in claim 1 or 2, characterized in that, The length of the first mother code is 2. m m is an integer greater than 1, and the length of the second mother code is 2. t t is a positive integer, and the number of the second code length is 2. m-t .

4. The method as described in claim 3, characterized in that, E represents the length of the first code. This represents the function for rounding up.

5. The method as described in claim 3 or 4, characterized in that, Each of the N second rate matching methods indicates the puncture position of the second mother code corresponding to its corresponding submatrix, and the first rate matching method is determined based on the puncture positions indicated by the N second rate matching methods.

6. The method as described in claim 5, characterized in that, The first rate matching method is used to indicate that the first master code is punched at the following punching positions: The second rate matching method is used to indicate the first sequence. Punch holes in the second mother code; The N second code lengths are as follows: Among them, l i ≤2 t i = 1, 2, ..., 2 m-t ; The first code length is equal to When the second code length is equal to l i Then the corresponding punch position of the second mother code is Furthermore, it also satisfies: Where mt≥k≥0, 0≤s<2 m-k-1 .

7. The method as described in claim 6, characterized in that, The first sequence is either a punched sequence or a bit index of the second mother code in natural order.

8. The method as described in claim 6 or 7, characterized in that, m = 5, t = 3, N = 4; The N second code lengths are l1=4, l2=6, l3=5, l4=7 respectively; the first code length is 22, and the first information bit number is 11; The values ​​are [1,2,3,4,5,6,7,8]. The first rate matching mode indicates that the first master code is punched at the following punch positions: 1, 2, 3, 4, 9, 10, 17, 18, 19, 25.

9. The method as described in claim 3 or 4, characterized in that, Each of the N second rate matching methods indicates the shortening position of the second mother code corresponding to its corresponding submatrix, and the first rate matching method is determined based on the shortening position indicated by the N second rate matching methods.

10. The method as described in claim 9, characterized in that, The first rate matching method is used to indicate that the first mother code is shortened according to the following shortening positions: The second rate matching information is used to indicate the sequence. The second mother code is shortened; The N second code lengths are as follows: Among them, l i ≤2 t i = 1, 2, ..., 2 m-t ; The first code length is equal to When the second code length is equal to l i Then the corresponding shortened position of the second mother code is Furthermore, it also satisfies: Where mt≥k≥0, 0≤s<2 m-k-1 .

11. The method as described in claim 10, characterized in that, The second sequence is either a shortened sequence or a naturally reversed bit index of the second mother code.

12. The method as described in claim 10 or 11, characterized in that, m = 4, t = 3, N = 2; The N second code lengths are l1 = 7 and l2 = 4 respectively; the first code length is equal to 11 and the first information bit number is equal to 8; The result is [8,7,6,5,4,3,2,1]; The first rate matching method indicates that the first mother code is shortened at the following shortening positions: 8, 13, 14, 15, 16.

13. The method as described in claim 10 or 11, characterized in that, m = 4, t = 3, N = 2; The N second code lengths are l1 = 7 and l2 = 4 respectively; the first code length is equal to 11 and the first information bit number is equal to 8; The result is [8,4,6,2,7,3,5,1]; The first rate matching method indicates that the first mother code is shortened at the following shortening positions: 8, 10, 12, 14, 16.

14. The method according to any one of claims 1 to 11, characterized in that, The length of the first code is not a power of 2.

15. The method according to any one of claims 1 to 12, characterized in that, The encoding parameters also include information about the N sub-matrices.

16. A communication device, characterized in that, It includes a processor and an interface circuit, the processor being used to communicate with other devices through the interface circuit and to implement the method of any one of claims 1, 3 to 15, or to implement the method of any one of claims 2 to 15.

17. The apparatus as claimed in claim 16, characterized in that, The communication device further includes a memory for storing computer programs or instructions, which, when executed by the processor, implement the method of any one of claims 1, 3 to 15, or the method of any one of claims 2 to 15.

18. A computer program product, characterized in that, The computer program product includes instructions that, when executed, implement the method of any one of claims 1 to 15.

19. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed, implement the method described in any one of claims 1 to 15.

20. A chip, characterized in that, The chip includes a processor for implementing the method according to any one of claims 1 to 15.

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