A millimeter wave Doherty transmit front-end chip based on harmonic suppression antenna load modulation

Abstract

The application discloses a millimeter wave Doherty transmitting front-end chip based on harmonic suppression antenna load modulation, which contains driving amplification circuit, Wilkinson power divider, carrier amplification circuit, peak amplification circuit and double-patch antenna integrated on the same chip; the application utilizes the electromagnetic coupling effect between the two ports of the double-patch antenna, so that the double-patch antenna realizes spatial power synthesis and electromagnetic wave radiation at the same time, and realizes the active load modulation function of the Doherty power amplifier; at the same time, through the collaborative impedance design among the carrier amplification circuit, the bias network and the load modulation antenna, the loss and the parasitic effect introduced by the millimeter wave frequency band output matching network are reduced. Through the collaborative design of the power amplifier and the load modulation antenna, the antenna has the functions of spatial power synthesis, dynamic load modulation and harmonic suppression, which is beneficial to realize the millimeter wave transmitting front-end with low loss, miniaturization, high integration and high efficiency, and can be widely applied to 5G and 6G millimeter wave communication systems.

Description

Technical Field

[0001] This invention relates to the field of monolithic microwave integrated circuit technology, and in particular to a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation. Background Technology

[0002] With the development of fifth-generation (5G) and sixth-generation (6G) mobile communication technologies, the millimeter-wave band, due to its abundant spectrum resources and large system capacity, has become an important development direction for high-speed wireless communication. Modern communication systems generally employ more complex high-order digital modulation methods to improve spectrum utilization and achieve a higher peak-to-average power ratio (PAPR) for the transmitted signal. Therefore, the power amplifier in the transmitter not only needs to have high efficiency at saturated output power but also needs to maintain high efficiency over a wider power back-off range to reduce system power consumption and improve energy efficiency.

[0003] Doherty power amplifiers are widely used in wireless communication base stations and millimeter-wave transmission systems due to their large power back-off range, high back-off-to-saturation efficiency, and relatively simple circuit structure. Traditional Doherty power amplifiers typically utilize quarter-wavelength impedance transformation lines and T-junction power combining networks to achieve dynamic load modulation between the carrier power amplifier and the peak power amplifier, thereby improving back-off efficiency. To further improve performance in areas such as bandwidth, efficiency, and linearity, various impedance transformation structures and output combining networks have been proposed, such as implementations based on coupled transmission lines, LC networks, and balun transformers. However, these solutions usually require additional passive combining networks, which not only increases RF transmission loss but also results in larger sizes for quarter-wavelength transmission lines and power combining networks in the millimeter-wave band. Furthermore, quarter-wavelength transmission lines are significantly affected by dispersion effects, and their impedance transformation characteristics vary considerably with frequency, which is detrimental to low-loss, miniaturized, highly integrated, high-efficiency, and wideband designs for the transmitter front-end.

[0004] On the other hand, in traditional transmitters, antennas are typically used only as electromagnetic wave radiating units, their function mainly limited to radiating radio frequency energy into free space, without participating in the load modulation process of the power amplifier. In recent years, some research has attempted to co-design antennas and Doherty power amplifiers, using doubly-fed antennas and array antennas to replace traditional power combining networks to achieve active load modulation. However, existing antenna-load-modulated transmitter structures are mainly applied in the Sub-6GHz band, typically relying on PCB-level antenna arrays and discrete power amplifiers. The antenna, impedance matching network, and power amplifier are designed independently, and achieving the optimal load impedance of the power amplifier still depends on the external impedance matching network. Therefore, this type of design relies on a large circuit implementation space and a relatively independent RF module environment, making it difficult to directly apply to millimeter-wave monolithic integrated transmitter front-ends.

[0005] Specifically, in the millimeter-wave band, due to the shortened operating wavelength, the electromagnetic dimensions of the antenna, feed structure, and interconnect structure are comparable to the operating wavelength. Even minor structural changes can cause significant impedance and phase variations, greatly increasing design complexity. Simultaneously, millimeter-wave on-chip antennas are limited by the characteristics of the semiconductor substrate. Because chip substrates typically have high dielectric constants and extremely thin thicknesses, on-chip antennas are susceptible to surface wave propagation, reduced radiation efficiency, and limited impedance bandwidth. Simply employing traditional methods of designing antennas and power amplifiers independently makes it difficult to simultaneously meet the requirements of load modulation impedance trajectory, power amplifier efficiency, and radiation performance. Therefore, how to coordinate the characteristics of the antenna and power amplifier in a millimeter-wave on-chip integration environment, enabling the antenna to simultaneously meet the requirements of spatial power combining, dynamic load modulation, and high-efficiency power amplifier operation, has become a key technical challenge in the design of millimeter-wave antenna load-modulated transmitter front-ends.

[0006] Furthermore, millimeter-wave power amplifiers generate strong harmonic components when operating at high power. If a harmonic suppression network is implemented at the output, it will increase transmission loss and reduce amplifier efficiency. If the antenna is directly connected to the power amplifier, second and higher harmonics may excite higher-order resonant modes of the on-chip antenna, generating undesirable harmonic radiation and further affecting the load state at the power amplifier output. Therefore, on-chip load-modulated antennas not only need to achieve effective radiation and load modulation at the fundamental frequency but also need to possess harmonic suppression capabilities. Summary of the Invention

[0007] Purpose of the Invention: In view of the above, the purpose of this invention is to provide a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation, which reduces the signal transmission loss introduced by impedance transformation, matching network and power combining network in the traditional Doherty architecture, reduces the size of the entire transmitter front-end system, and improves the system integration, power and efficiency, thereby solving the technical problems of existing millimeter-wave Doherty transmitter front-ends such as large size, high loss, insufficient integration and limited efficiency improvement.

[0008] Technical Solution: To achieve the above objectives, this invention provides a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation, comprising a driver amplifier circuit, a Wilkinson power divider, a carrier amplifier circuit, a peak amplifier circuit, and a dual-patch antenna integrated on the same chip; wherein, the input terminal of the driver amplifier circuit is connected to the input terminal of the radio frequency signal, the output terminal of the driver amplifier circuit is connected to the input terminal of the Wilkinson power divider, the two output terminals of the Wilkinson power divider are respectively connected to the input terminals of the carrier amplifier circuit and the peak amplifier circuit, the output terminals of the carrier amplifier circuit and the peak amplifier circuit are respectively connected to the two input terminals of the dual-patch antenna, and the signal is spatially power synthesized by the dual-patch antenna and radiated into free space;

[0009] The dual-pattern antenna is composed of a first patch unit and a second patch unit. The dual-pattern antenna is a binary symmetrical antenna array with two coupling ports. Electromagnetic coupling exists between the two ports. When the output current of the peak amplifier circuit changes, the equivalent load impedance presented at the output of the carrier amplifier circuit is altered through the electromagnetic coupling between the two ports, thus achieving active load modulation. Simultaneously, the dual-pattern antenna has harmonic suppression capabilities, used to achieve spatial power synthesis and electromagnetic radiation of the output signals from the carrier amplifier circuit and the peak amplifier circuit.

[0010] The power stage carrier amplifier circuit, drain bias network, and dual patch antenna are designed with coordinated impedance, instead of setting an independent output matching network for the power stage carrier amplifier.

[0011] Furthermore, the first patch unit and the second patch unit of the dual-patch antenna adopt the same structure and are symmetrically arranged according to the central axis of the dual-patch antenna; wherein, the first patch unit includes a rectangular patch, a power-dividing microstrip feed line, a feed slot, a rectangular slot, and a square slot; the antenna unit has an axisymmetric structure, and the feed slot, the rectangular slot, and the square slot are all slotted on the rectangular patch; the radio frequency signal is fed in from the power-dividing microstrip feed line and fed into the rectangular patch in two, so that the radio frequency signal is loaded at the symmetrical position of the rectangular patch, and the rectangular patch transmits the electromagnetic signal into free space.

[0012] Furthermore, the rectangular patch, the power divider microstrip feed line, and the feed slot, rectangular slot, and square slot together constitute a harmonic suppression structure. By adjusting the slot structure and size to change the current path on the patch surface, the patch size is reduced while an electric field excitation conforming to the TM10 fundamental mode distribution is formed. By co-designing the feed structure, location, and electric field distribution of higher-order modes, the feed region is located in the electric field zero-point region of TM02, TM20, TM12, and TM22 modes, thereby reducing the excitation intensity of higher-order modes and achieving suppression of harmonics and parasitic resonant modes.

[0013] Furthermore, electromagnetic coupling is formed between the first patch unit and the second patch unit, and the distance between the power supply structures connecting the first patch unit and the second patch unit is less than half the wavelength corresponding to the operating frequency, so as to enhance the coupling effect between the ports.

[0014] Furthermore, the carrier amplifier circuit includes a carrier input matching network, a power stage carrier amplifier, a carrier drain bias network, and an eighth DC blocking capacitor cascaded in sequence; wherein, the input terminal of the carrier input matching network is connected to the first output terminal of the Wilkinson power divider, the output terminal of the carrier input matching network is connected to the gate of the power stage carrier amplifier, the drain of the power stage carrier amplifier is connected to the input terminal of the carrier drain bias network, the output terminal of the carrier drain bias network is connected to the eighth DC blocking capacitor, and the third output terminal of the carrier amplifier circuit is connected to the input terminal of the first patch unit of the dual patch antenna.

[0015] Furthermore, the carrier drain bias network is composed of a first equivalent parallel resonant inductor; wherein, the first equivalent parallel resonant inductor provides power to the drain of the power stage carrier amplifier and is used to resonate and compensate for the internal parasitic capacitance of the transistor.

[0016] Furthermore, the drive amplifier circuit includes a drive input matching network, a drive stage amplifier, and a drive output matching network cascaded in sequence; wherein, the input terminal of the drive input matching network is connected to the input terminal of the radio frequency signal (RF IN), the output terminal of the drive input matching network is connected to the gate of the drive stage amplifier, the drain of the drive stage amplifier is connected to the input terminal of the drive output matching network, and the output terminal of the drive output matching network is connected to the input terminal of the Wilkinson power divider.

[0017] Furthermore, the Wilkinson power divider is an equal-power output power divider; wherein, the first output terminal of the Wilkinson power divider is connected to the input terminal of the carrier amplifier circuit, and the second output terminal of the Wilkinson power divider is connected to the input terminal of the peak amplifier circuit.

[0018] Furthermore, the peak amplifier circuit includes a phase-shifting network, a peak input matching network, a power stage peak amplifier, a peak drain bias network, an eighth DC blocking capacitor, and a peak impedance transformation network cascaded in sequence. The input terminal of the phase-shifting network is connected to the second output terminal of the Wilkinson power divider; the output terminal of the phase-shifting network is connected to the input terminal of the peak input matching network; the output terminal of the peak input matching network is connected to the gate of the power stage peak amplifier; the drain of the power stage peak amplifier is connected to the input terminal of the peak drain bias network; the output terminal of the peak drain bias network is connected to the eighth DC blocking capacitor; the eighth DC blocking capacitor is connected to the input terminal of the peak impedance transformation network; and the fourth output terminal of the peak amplifier circuit is connected to the input terminal of the second patch unit of the dual patch antenna.

[0019] Furthermore, the driver stage amplifier in the drive amplifier circuit, the power stage carrier amplifier in the carrier amplifier circuit, and the power stage peak amplifier in the peak amplifier circuit are all gallium nitride high electron mobility transistors.

[0020] Beneficial effects: Compared with the prior art, the advantages of the present invention are as follows:

[0021] 1. This invention utilizes the electromagnetic coupling between the two ports of a dual-patch antenna to dynamically adjust the load impedance at the output of the power amplifier through the mutual impedance between the ports. This enables the antenna structure to also have active load modulation capabilities, realizing load modulation between the carrier power amplifier and the peak power amplifier in a Doherty power amplifier. Compared with the traditional Doherty structure, this invention uses the electromagnetic coupling between antenna elements to replace part of the traditional power combining network function, avoiding the size increase, transmission loss, and dispersion effects caused by quarter-wavelength impedance transformation lines. It is suitable for high-integration transmitter front-end designs in the millimeter-wave band.

[0022] 2. This invention utilizes a dual-patch antenna to achieve spatial power combining and electromagnetic radiation of radio frequency (RF) signals. It integrates the power combining network from the traditional Doherty structure with the antenna, reducing the RF signal transmission path and minimizing transmission loss introduced by passive networks. Furthermore, addressing the issue of strong electromagnetic coupling between the antenna, power amplifier, and matching network in millimeter-wave monolithic integrated environments, this invention employs a collaborative design between the antenna structure and the power amplifier output. This allows the antenna to not only function as a radiating element but also participate in adjusting the power amplifier's load characteristics, thereby improving the output power and efficiency performance of the transmitting front-end.

[0023] 3. This invention, through the coordinated impedance design between the carrier power amplifier, the bias network, and the load modulation antenna, enables the power transistor drain terminal to present an equivalent load impedance R close to its optimal operating state without the need for a separate output matching network. optThis reduces the losses and parasitic effects introduced by the millimeter-wave band output matching network, and improves the integration and efficiency performance of the transmitter front end.

[0024] 4. This invention optimizes the antenna feeding structure, patch current distribution, and harmonic impedance characteristics to maintain the port impedance characteristics that meet Doherty operating requirements at the fundamental frequency, while suppressing the excitation of higher-order modes at the second harmonic frequency, thus suppressing the second harmonic component of the power amplifier. Compared with traditional antenna structures that only focus on fundamental radiation performance, the antenna in this invention also functions as a load modulation network and a harmonic suppression network, which is beneficial for improving the harmonic operation of the power amplifier and increasing the efficiency of the millimeter-wave transmitting front-end.

[0025] 5. This invention integrates the power amplifier, load modulation antenna, and related RF network into a single chip design. Existing antenna load modulation structures typically employ PCB-level antenna arrays and peripheral RF connections, which suffer from long transmission paths, significant parasitic effects, and limited system integration in the millimeter-wave band. This invention reduces the impact of package interconnects, PCB traces, and additional RF connection structures on system performance, achieving a highly integrated design of the power amplifier and antenna in the millimeter-wave transmitting front-end.

[0026] 6. This invention enables end-to-end design based on GaN technology, fully leveraging the inherent advantages of GaN materials such as high breakdown electric field, high power density, and high thermal conductivity. Compared to traditional silicon-based processes, this invention provides higher equivalent isotropic radiated power (EIRP), supports higher-order modulation schemes and higher data transmission rates, and is more suitable for 5G and 6G millimeter-wave communication systems. Attached Figure Description

[0027] Figure 1 This is a circuit structure block diagram of a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation, provided in a specific embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram illustrating the specific circuit structure of a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation, as exemplified in a specific embodiment of the present invention.

[0029] Figure 3 The simulation curves of the load impedance at the output of the carrier amplifier circuit and the peak amplifier circuit provided in the specific embodiments of the present invention as a function of the back-off coefficient are shown.

[0030] Figure 4 The figure shows the simulation results of the power stage transistor load pulling, which includes a drain bias network, provided in a specific embodiment of the present invention.

[0031] Figure 5 This is a Smith circle simulation diagram of the second harmonic load impedance of the power stage transistor under saturated output provided in a specific embodiment of the present invention;

[0032] Figure 6 This invention provides a small-signal simulation and measured S-parameter diagram of a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation, as shown in a specific embodiment of the invention.

[0033] Figure 7 The above is a measured curve of the overall gain and EIRP efficiency of a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation as a function of EIRP, provided in a specific embodiment of the present invention.

[0034] Figure 8 The normalized E-plane (a) and H-plane (b) radiation patterns of a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation are provided in a specific embodiment of the present invention.

[0035] The diagram includes: a driver amplifier circuit 1, a Wilkinson power divider 2, a carrier amplifier circuit 3, a peak amplifier circuit 4, and a dual patch antenna 5; a driver input matching network 11 and a driver output matching network 12; a carrier input matching network 31, a carrier drain bias network 32, and an eighth DC blocking capacitor C8; a phase shifting network 41, a peak input matching network 42, a peak drain bias network 43, an eighth DC blocking capacitor C8, and a peak impedance transformation network 44; a first patch unit 51 and a second patch unit 52; a rectangular patch 511, a power-dividing microstrip feed line 512, a feed slot 513, a rectangular slot 514, and a square slot 515; a driver stage amplifier T1, a power stage carrier amplifier T2, and a power stage peak amplifier T3; an RF signal input terminal RF IN; the first output terminal OUT1 of the Wilkinson power divider, the second output terminal OUT2 of the Wilkinson power divider, the third output terminal OUT3 of the carrier amplifier circuit, and the fourth output terminal OUT4 of the peak amplifier circuit; and a first external power supply terminal V. g1 Second external power supply terminal V d1 Third external power supply terminal V g2 Fourth external power supply terminal V d2 Fifth external power supply terminal V g3 Sixth external power supply terminal V d3 . Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0037] See Figure 1This embodiment provides a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation, which specifically includes:

[0038] A drive amplifier circuit 1 is provided, the input terminal of which is connected to the radio frequency signal input terminal RF IN. The drive amplifier circuit 1 is composed of a drive input matching network 11, a drive stage amplifier T1, and a drive output matching network 12 cascaded in sequence. The input terminal of the drive input matching network 11 is connected to the radio frequency signal input terminal RF IN, the output terminal of the drive input matching network 11 is connected to the gate of the drive stage amplifier T1, and the drain of the drive stage amplifier T1 is connected to the input terminal of the drive output matching network 12.

[0039] Wilkinson power divider 2, the input terminal of which is connected to the output terminal of the drive amplifier circuit 1;

[0040] The carrier amplifier circuit 3 has its input terminal connected to the first output terminal OUT1 of the Wilkinson power divider 2. The carrier amplifier circuit 3 is composed of a carrier input matching network 31, a power stage carrier amplifier T2, a carrier drain bias network 32, and an eighth DC blocking capacitor C8 cascaded in sequence. The input terminal of the carrier input matching network 31 is connected to the first output terminal OUT1 of the Wilkinson power divider 2, the output terminal of the carrier input matching network 31 is connected to the gate of the power stage carrier amplifier T2, the drain of the power stage carrier amplifier T2 is connected to the input terminal of the carrier drain bias network 32, the output terminal of the carrier drain bias network 32 is connected to the eighth DC blocking capacitor C8, and the third output terminal OUT3 of the carrier amplifier circuit 3 is connected to the input terminal of the first patch unit 51 of the dual patch antenna 5.

[0041] A peak amplifier circuit 4 is provided, the input of which is connected to the second output terminal OUT2 of the Wilkinson power divider 2. The peak amplifier circuit 4 is composed of a phase shifting network 41, a peak input matching network 42, a power stage peak amplifier T3, a peak drain bias network 43, an eighth DC blocking capacitor C8, and a peak impedance transformation network 44 cascaded in sequence. The input of the phase shifting network 41 is connected to the second output terminal OUT2 of the Wilkinson power divider 2, the output of the phase shifting network 41 is connected to the input of the peak input matching network 42, the output of the peak input matching network 42 is connected to the gate of the power stage peak amplifier T3, the drain of the power stage peak amplifier T3 is connected to the input of the peak drain bias network 43, the output of the peak drain bias network 43 is connected to the eighth DC blocking capacitor C8, the eighth DC blocking capacitor C8 is connected to the input of the peak impedance transformation network 44, and the fourth output terminal OUT4 of the peak amplifier circuit 4 is connected to the input of the second patch unit 52 of the dual patch antenna 5.

[0042] Specifically, in this embodiment, the carrier drain bias network 32 is composed of a first equivalent parallel resonant inductor L1; wherein, the first equivalent parallel resonant inductor L1 provides power to the drain of the power stage carrier amplifier T2 and is used to resonate and compensate for the internal parasitic capacitance of the transistor; the output of the carrier amplifier circuit 3 does not require an independent output matching network, but through the collaborative design of the drain bias network 32 and the dual patch antenna 5, the carrier power amplifier obtains high-efficiency dynamic load impedance under different power states, realizing load modulation without the need for an independent output matching network.

[0043] The dual patch antenna 5 is composed of a first patch unit 51 and a second patch unit 52; the input terminal of the first patch unit 51 is connected to the third output terminal OUT3 of the carrier amplifier circuit, and the input terminal of the second patch unit 52 is connected to the fourth output terminal OUT4 of the peak amplifier circuit; the radio frequency signal is spatially power synthesized and radiated into free space through the dual patch antenna 5.

[0044] In this embodiment, the dual patch antenna 5 is a binary symmetrical antenna array with two coupling ports. There is an electromagnetic coupling between the two ports. After the output current of the peak amplifier circuit 4 changes, the equivalent load impedance presented at the output terminal of the carrier amplifier circuit 3 is changed through the electromagnetic coupling between the two ports, thereby realizing active load modulation. The dual patch antenna 5 is used to realize spatial power synthesis and electromagnetic radiation of the output signals of the carrier amplifier circuit 3 and the peak amplifier circuit 4.

[0045] In this embodiment, the first patch unit 51 and the second patch unit 52 of the dual-patch antenna 5 adopt the same structure and are symmetrically arranged according to the central axis of the dual-patch antenna 5. The first patch unit 51 includes a rectangular patch 511, a power-dividing microstrip feed line 512, a feed slot 513, a rectangular slot 514, and a square slot 515. The antenna unit has an axisymmetric structure, and the feed slot 513, rectangular slot 514, and square slot 515 are all slotted on the rectangular patch 511. The feed slot 513, rectangular slot 514, and square slot 515 are used to change the surface current distribution of the rectangular patch 511 and extend the RF current transmission distance. The broadcast path is adjusted to reduce the antenna resonant frequency, thereby reducing the physical size of the rectangular patch 511. The radio frequency signal is fed into the rectangular patch 511 through a power-dividing microstrip feed line 512, which is split into two feeds. The two feed ports are respectively located at positions approximately W / 4 and 3W / 4 away from the short side edge in the width direction of the rectangular patch, where W is the width of the rectangular patch. The fundamental mode TM10 of the rectangular patch is excited by symmetrical feeding, while the feeding region is located in the electric field zero region of the TM02, TM20, TM12 and TM22 modes, thereby reducing the excitation intensity of the above higher-order modes and suppressing harmonic and parasitic resonant modes.

[0046] The rectangular patch 511 serves as a structure for transmitting electromagnetic signals into free space.

[0047] The drive input matching network 11 and the first external power supply terminal V g1 The circuit connection is such that the drive output matching network 12 is connected to the second external power supply terminal V. d1 Circuit connection; the carrier input matching network 31 and the third external power supply terminal V g2 The circuit connection, wherein the carrier drain bias network 32 is connected to the fourth external power supply terminal V d2 Circuit connection; the peak input matching network 42 and the fifth external power supply terminal V g3 The circuit connection, wherein the peak drain bias network 43 is connected to the sixth external power supply terminal V d3 Circuit connection.

[0048] The driver stage amplifier T1 in the driver amplifier circuit 1, the power stage carrier amplifier T2 in the carrier amplifier circuit 3, and the power stage peak amplifier T3 in the peak amplifier circuit 4 are all gallium nitride high electron mobility transistors (GaN HEMTs). For example, a 0.15 μm gallium nitride process can be used, and the driver stage amplifier T1, power stage carrier amplifier T2, and power stage peak amplifier T3 can all employ 6×50 μm transistors.

[0049] In this embodiment, the drive input matching network 11, drive output matching network 12, Wilkinson power divider 2, carrier input matching network 31, carrier drain bias network 32, phase shifting network 41, peak input matching network 42, peak drain bias network 43, and peak impedance transformation network 44 can all adopt existing mature designs, and this invention does not impose any restrictions. Figure 2A specific circuit structure diagram is illustrated, where capacitors and resistors with the same capacitance and resistance values ​​are labeled with the same designation. The drive input matching network 11 includes capacitors (C1, C2, C3, C4, C5), microstrip lines (TL1, TL2, TL3, TL4, TL5), and resistors (R1, R2, R3). Capacitor C1 is placed at the RF input terminal to suppress DC signals. Microstrip lines TL1 and TL2 form a second-order high-pass filter matching network, and microstrip line TL3 and grounded capacitor C2 form a second-order low-pass filter matching network. These two sets constitute a bandpass filter to suppress low-frequency spurious signals and high-frequency harmonics. Resistor R1 and capacitor C3 are connected in parallel to form a stability network, and resistor R2 is used for fine-tuning circuit stability. The drive output matching network 12 includes capacitors (C4, C6, C7), microstrip lines (TL6, TL7, TL8, TL9), and resistor (R3). Microstrip line TL7 is equivalent to a parallel inductor grounded to resonate and compensate for the internal parasitic capacitance of the transistor, thus offsetting reactance. The resistor R3 is used to increase the Q value of the bias circuit, thereby increasing the bandwidth of the DC bias circuit. The Wilkinson power divider 2 includes microstrip lines (TL10, TL11) and a resistor (R4). The circuit has a symmetrical structure, and the power divider has equal power output. The resistor R4 acts as an isolation resistor to increase the isolation between the two output ports. The carrier input matching network 31 includes capacitors (C1, C2, C3, C4, C5), microstrip lines (TL1, TL2, TL3, TL4, TL13), and resistors (R1, R2, R3). The carrier drain bias network 32 includes capacitors (C4, C6, C8), microstrip lines (TL6, TL7, TL14), and a resistor (R3). The function of this network is equivalent to the first equivalent parallel resonant inductor (L1), used to resonate and compensate for the internal parasitic capacitance of the transistor, to counteract the influence of reactance, and to make the drain terminal of the carrier power amplifier transistor present the optimal load impedance R. opt The eighth DC blocking capacitor C8 is placed at the RF output to suppress DC signals; the phase-shifting network 41 includes a microstrip line (TL12), the characteristic impedance of which is 50Ω. Ω, with a length less than λ / 4, is used to adjust the phase difference of the RF signals output from the carrier amplifier circuit and the peak amplifier circuit to the dual patch antenna; the peak input matching network 42 includes capacitors (C1, C2, C3, C4, C5), microstrip lines (TL1, TL2, TL3, TL4, TL13), and resistors (R1, R2, R3); the peak drain bias network 43 includes capacitors (C4, C6, C8), microstrip lines (TL6, TL7, TL14), and resistors (R3), and the function of this network is also equivalent to the first equivalent parallel resonant inductor (L1); the peak impedance transformation network 44 includes capacitor (C9) and microstrip line (TL15). Capacitor C9 and parallel microstrip line TL15 are grounded to form a second-order high-pass filter matching network, which is used to match the equivalent load impedance of the peak amplifier circuit output in saturation state to the input impedance of the second patch unit.

[0050] Specifically, in this embodiment, electromagnetic coupling is formed between the first patch unit 51 and the second patch unit 52 of the dual patch antenna 5. The two microstrip feed lines connecting the first patch unit 51 and the second patch unit 52 are symmetrically arranged with a center-to-center distance of about one-quarter of the free space wavelength to enhance the near-field electromagnetic coupling between the ports. The coupling effect between the antenna units is characterized by mutual impedance.

[0051] Specifically, in this embodiment, the peak amplifier circuit 4 achieves active load modulation of the carrier amplifier circuit 3 through electromagnetic coupling between the two ports of the dual patch antenna 5, and the equivalent load impedance presented at the output of the carrier amplifier circuit 3 satisfies the following relationship:

[0052] (1)

[0053] Among them, Z in1 Z is the equivalent load impedance at the output of carrier amplifier circuit 3. 11 Z is the self-impedance of port 51 of the first patch cell. 12 Let Z be the coupling mutual impedance between the two surface mount units, I1 be the current at port 51 of the first surface mount unit, and I2 be the current at port 52 of the second surface mount unit. According to equation (1), the current I2 at port 52 of the second surface mount unit will pass through the mutual impedance Z. 12 Change the equivalent load impedance Z at the output of carrier amplifier circuit 3 in1 This allows for active load modulation.

[0054] Specifically, in this embodiment, the dual-patch antenna 5 is a symmetrical reciprocal two-port network, and its port impedance satisfies the following relationship:

[0055] (2)

[0056] (3)

[0057] Specifically, in this embodiment, the Wilkinson power divider 2 is a 1:1 equal power divider, and the phase-shifting network 41 is implemented by microstrip lines to perform phase compensation on the output signal of the peak amplifier circuit 4, so that the RF signal output by the peak amplifier circuit 4 and the RF signal output by the carrier amplifier circuit 3 satisfy an orthogonal phase relationship. Equation (1) is transformed into

[0058] (4)

[0059] Equation (4) illustrates the equivalent load impedance and mutual impedance Z presented at the output terminal of carrier amplifier circuit 3. 12 Directly related;

[0060] Specifically, in this embodiment, in the fallback state, i.e., when the peak power amplifier is not turned on, the port current I2 of the second patch unit 51 is 0. Theoretical analysis shows that the equivalent load impedance Z presented at the output of the carrier amplifier circuit 3 is... in1 2*R opt That is, corresponding to Z 11 2*R opt , where R opt This is the optimal load impedance for the power amplifier tube.

[0061] Specifically, in this embodiment, under saturation conditions, i.e., when both the carrier power amplifier and the peak power amplifier are saturated, theoretical analysis shows that the equivalent load impedance Z presented at the output of the carrier amplifier circuit 3 is... in1 For R opt That is, corresponding to Z 12 -j*R opt .

[0062] In this embodiment, the equivalent load impedance at the output of the peak amplifier circuit 4 is also affected by the port current of the first patch unit 51. Based on the above-mentioned equal amplitude and phase orthogonal relationship of the output RF signals of the carrier amplifier circuit 3 and the peak amplifier circuit 4, and equations (2)-(3), theoretical analysis shows that the equivalent load impedance Z of the peak amplifier circuit under saturation state is Z. in2 3*R opt .

[0063] Specifically, in this embodiment, the transistor size is 6×50 μm, and under a specific bias voltage, the optimal load impedance R is... opt The Ω is 100. The backoff coefficient, used as a normalization parameter, represents the backoff state. A backoff coefficient of 0 represents a power backoff of 6 dB, and a backoff coefficient of 1 represents saturated power output. The backoff coefficient from 0 to 1 represents the process of the peak power amplifier going from off to saturated output. Figure 3 Simulation curves showing the load impedance at the output of the carrier amplifier circuit and the peak amplifier circuit as a function of the backoff coefficient are presented. It can be seen that the dual patch antenna achieves load modulation of the carrier power amplifier. As the peak power amplifier current increases, the load impedance at the output of the carrier power amplifier is pulled from 155.31+j*52.6 Ω to 105-j*12.24 Ω, which is consistent with the load pulling process of the carrier power amplifier in Doherty power amplifier theory. The load impedance at the output of the peak power amplifier changes from approximately infinite to 198.37+j*184 Ω, which is consistent with the theoretical trend that the load impedance tends to infinity when the peak amplifier circuit is off, and that the equivalent load impedance gradually decreases as the peak current increases during the on-state.

[0064] Specifically, in this embodiment, to simplify the circuit, the drive amplifier circuit, carrier amplifier circuit, and peak amplifier circuit all use the same topology. The input matching networks of all three use bandpass filter matching networks to suppress low-frequency spurious signals and high-frequency harmonics while achieving broadband impedance matching, ensuring circuit stability. The drain bias networks of all three adopt a structure with an inductor loaded and connected to ground at the transistor drain node. This inductor, along with the internal parasitic capacitance of the transistor, forms a resonant compensation to counteract the capacitive effect caused by the parasitic capacitance, resulting in the transistor output exhibiting the optimal load impedance R. opt This enables high-efficiency power transmission.

[0065] Specifically, in this embodiment, the dual-pattern antenna increases the current transmission path and reduces the overall antenna size by opening feed slots, rectangular slots, and square slots on the rectangular patch. The radio frequency signal is fed in from a power-divided microstrip feeder, which adopts a one-to-two feeding structure. The two feeding branches are connected to the one-quarter and three-quarters positions in the width direction of the rectangular patch, respectively. That is, the two feeding points are located at approximately W / 4 and 3W / 4 from the short edge of the rectangular patch, respectively, where W is the width of the rectangular patch. The fundamental mode TM10 of the rectangular patch is excited by symmetrical feeding, and the excitation intensity of higher-order modes such as TM02, TM20, TM12, and TM22 is reduced by utilizing the electric field zero position corresponding to the higher-order modes, thereby achieving harmonic suppression function.

[0066] Figure 4 The simulation results show the load pulling of a power stage transistor including a drain bias network; from Figure 4 It can be seen that the input impedance of the first patch element of the load-modulated antenna in the fundamental frequency band (27.8-28.4 GHz) lies within the overlap range of the high PAE region and the high output power region in the load-pulling results, corresponding to a PAE of 45.4-50.4% and an output power of 30.9-31.9 dBm. Since the carrier amplifier circuit does not have an independent output matching network, this result demonstrates that through the coordinated design of the drain bias network and the load-modulated antenna, the drain terminal of the power stage transistor can achieve a load impedance close to its optimal operating state. This verifies the feasibility of using dual patch antennas to participate in the load impedance adjustment of the power amplifier, achieving high-efficiency, high-power output without the need for a traditional output matching network.

[0067] Figure 5 Smith circle simulation plot of the second harmonic load impedance of the power stage transistor at saturation output; from Figure 5It can be seen that the load impedance of the power stage transistor in the second harmonic band (56-60 GHz) is located near the Smith circle open point, while the power-added efficiency (PAE) and output power gradually decrease from the upper edge to the lower right corner (in the direction of the arrow). This indicates that the harmonic suppression dual-patch antenna proposed in this embodiment, by adjusting the second harmonic impedance of the antenna port, pulls the second harmonic load of the power stage transistor to a better range of PAE and output power, thereby optimizing the second harmonic impedance, improving the power-added efficiency of the power stage transistor, and thus improving the efficiency of the overall system.

[0068] To verify the reliability of this implementation scheme, this embodiment also underwent tape-out and testing. Specific simulation and measurement results are as follows: Figures 6-8 As shown, specifically in this embodiment, the rectangular patch has a length of 1598 μm and a width of 2547 μm. The feed slot size is 530 μm × 80 μm, the rectangular slot size is 240 μm × 370 μm, and the square slot size is 160 μm × 160 μm. The two branches of the power-dividing microstrip feed line are of equal length and symmetrical about the patch axis. The two feed points are located at distances of 744.5 μm and 1795 μm from the short edge of the rectangular patch, which are approximately 0.29 and 0.70 times the width of the rectangular patch, respectively. The distance between the centers of the two patch unit microstrip feed lines is 2750 μm, which is approximately one-quarter of the free space wavelength.

[0069] Figure 6 The diagram shows the small-signal simulation and measured S-parameters of the Doherty transmitter front-end chip in this embodiment. It can be seen that the maximum total gain of this example is 10.9 dB at 28.2 GHz and the 3-dB bandwidth is 0.7 GHz. This indicates that the integrated Doherty power amplifier and antenna in this embodiment can achieve good signal transmission performance and has the advantages of miniaturization, compact structure and high integration.

[0070] Figure 7 The figures show the measured curves of the overall gain and EIRP efficiency of the Doherty transmitter front-end chip in this embodiment as a function of EIRP. It can be seen that the operating frequency range of this embodiment is 28.0-28.4 GHz. The measured saturated EIRP in this frequency band is 33.6-34.2 dBm, and the corresponding saturated EIRP efficiency is 34.8-45.0%. The EIRP efficiency at 6-dB OBO is 18.1-39.3%, and the measured saturated gain is 7.5-8.7 dB. The optimal performance frequency is 28.2 GHz, exhibiting good Doherty backoff characteristics. This indicates that the dual-patch antenna has multiple functions such as active load modulation, spatial power combining, and electromagnetic radiation, verifying the effectiveness of the integrated design scheme of Doherty transmitter front-end based on harmonic suppression antenna load modulation.

[0071] Figure 8 The normalized E-plane (a) and H-plane (b) radiation patterns of a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation in this embodiment are shown in the simulation and actual measurements. It can be seen that the test results and simulation results are consistent to a certain extent and show good radiation characteristics.

[0072] In summary, this invention provides a millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation. By designing a dual-pattern antenna structure with dual-port electromagnetic coupling characteristics, dynamic load modulation between the carrier amplifier circuit and the peak amplifier circuit is achieved through the mutual impedance between the antenna ports. This allows the antenna to perform both electromagnetic radiation and spatial power combining and active load modulation functions. Furthermore, through the coordinated impedance design between the power stage carrier amplifier, bias network, and load modulation antenna, this invention enables the antenna to participate in the power amplifier load state adjustment, reducing the additional losses and parasitic effects caused by the independent power combining network and output matching network in traditional Doherty structures. Simultaneously, by optimizing the antenna feed structure and harmonic impedance characteristics, the second harmonic of the power amplifier is suppressed while maintaining the fundamental frequency load modulation characteristics, improving the harmonic operating state of the power amplifier and enhancing the efficiency and performance of the transmitter front-end. This invention integrates a Doherty power amplifier and a load-modulated antenna on a single chip, overcoming the limitation that traditional PCB-level antenna load-modulated structures are difficult to apply to millimeter-wave monolithic integration environments. It reduces millimeter-wave RF interconnect paths and the transmission losses they introduce, improving system integration, power, and efficiency. It is suitable for high-efficiency, low-loss, miniaturized, and highly integrated transmission front-end applications in 5G and 6G millimeter-wave communication systems.

[0073] Any aspects of this invention not described in detail are well-known to those skilled in the art.

[0074] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation, characterized in that, The system includes a drive amplifier circuit (1), a Wilkinson power divider (2), a carrier amplifier circuit (3), a peak amplifier circuit (4), and a dual patch antenna (5) integrated on the same chip. The input terminal of the drive amplifier circuit (1) is connected to the input terminal of the radio frequency signal, the output terminal of the drive amplifier circuit (1) is connected to the input terminal of the Wilkinson power divider (2), the two output terminals of the Wilkinson power divider (2) are respectively connected to the input terminals of the carrier amplifier circuit (3) and the peak amplifier circuit (4), the output terminals of the carrier amplifier circuit (3) and the peak amplifier circuit (4) are respectively connected to the two input terminals of the dual patch antenna (5), and the signal is spatially power synthesized by the dual patch antenna (5) and radiated into free space. The dual patch antenna (5) is composed of a first patch unit (51) and a second patch unit (52); wherein, the dual patch antenna (5) is a binary symmetrical antenna array with two coupling ports, and there is an electromagnetic coupling between the two ports. After the output current of the peak amplifier circuit (4) changes, the equivalent load impedance presented at the output terminal of the carrier amplifier circuit (3) is changed through the electromagnetic coupling between the two ports, thereby realizing active load modulation; at the same time, the dual patch antenna (5) has a harmonic suppression function, which is used to realize the spatial power synthesis and electromagnetic radiation of the output signals of the carrier amplifier circuit (3) and the peak amplifier circuit (4); The power stage carrier amplifier, drain bias network (32), and dual patch antenna (5) in the carrier amplifier circuit (3) are designed with coordinated impedance, instead of setting the output matching network of the power stage carrier amplifier independently.

2. The millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, The first patch unit (51) and the second patch unit (52) of the dual patch antenna (5) adopt the same structure and are symmetrically arranged according to the central axis of the dual patch antenna (5); wherein, the first patch unit (51) includes a rectangular patch (511), a power divider microstrip feed line (512), a feed slot (513), a rectangular slot (514) and a square slot (515); the antenna unit is an axisymmetric structure, and the feed slot (513), the rectangular slot (514) and the square slot (515) are all slotted on the rectangular patch (511); the radio frequency signal is fed in from the power divider microstrip feed line (512) and fed into the rectangular patch (511) by splitting it into two, so that the radio frequency signal is loaded at the symmetrical position of the rectangular patch (511), and the rectangular patch (511) transmits the electromagnetic signal into free space.

3. The millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, The rectangular patch (511), the power divider microstrip feed line (512), and the feed slots (513), rectangular slots (514), and square slots (515) together constitute a harmonic suppression structure. By adjusting the slot structure and size, the current path on the patch surface is changed, thereby reducing the patch size while forming an electric field excitation that conforms to the TM10 fundamental mode distribution. By co-designing the feed structure, position, and electric field distribution of higher-order modes, the feed region is located in the electric field zero-point region of TM02, TM20, TM12, and TM22 modes, thereby reducing the excitation intensity of higher-order modes and achieving suppression of harmonics and parasitic resonance modes.

4. The millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, Electromagnetic coupling is formed between the first patch unit (51) and the second patch unit (52), and the distance between the power supply structures connecting the first patch unit (51) and the second patch unit (52) is less than half of the wavelength corresponding to the operating frequency, so as to enhance the coupling effect between the ports.

5. A millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, The carrier amplifier circuit (3) includes a carrier input matching network (31), a power stage carrier amplifier (T2), a carrier drain bias network (32), and an eighth DC blocking capacitor (C8) cascaded in sequence. The input terminal of the carrier input matching network (31) is connected to the first output terminal (OUT1) of the Wilkinson power divider (2), the output terminal of the carrier input matching network (31) is connected to the gate of the power stage carrier amplifier (T2), the drain of the power stage carrier amplifier (T2) is connected to the input terminal of the carrier drain bias network (32), the output terminal of the carrier drain bias network (32) is connected to the eighth DC blocking capacitor (C8), and the third output terminal (OUT3) of the carrier amplifier circuit (3) is connected to the input terminal of the first patch unit (51) of the dual patch antenna (5).

6. A millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, The carrier drain bias network (32) is composed of a first equivalent parallel resonant inductor (L1); wherein, the first equivalent parallel resonant inductor (L1) provides power to the drain of the power stage carrier amplifier (T2) and is used to resonate and compensate for the internal parasitic capacitance of the transistor.

7. A millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, The drive amplifier circuit (1) includes a drive input matching network (11), a drive stage amplifier (T1), and a drive output matching network (12) cascaded in sequence; wherein, the input terminal of the drive input matching network (11) is connected to the input terminal of the radio frequency signal (RF IN), the output terminal of the drive input matching network (11) is connected to the gate of the drive stage amplifier (T1), the drain of the drive stage amplifier (T1) is connected to the input terminal of the drive output matching network (12), and the output terminal of the drive output matching network (12) is connected to the input terminal of the Wilkinson power divider (2).

8. A millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, The Wilkinson power divider (2) is an equal power output power divider; wherein, the first output terminal (OUT1) of the Wilkinson power divider (2) is connected to the input terminal of the carrier amplifier circuit (3), and the second output terminal (OUT2) of the Wilkinson power divider (2) is connected to the input terminal of the peak amplifier circuit (4).

9. A millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, The peak amplifier circuit (4) includes a phase-shifting network (41), a peak input matching network (42), a power stage peak amplifier (T3), a peak drain bias network (43), an eighth DC blocking capacitor (C8), and a peak impedance transformation network (44) cascaded in sequence. The input terminal of the phase-shifting network (41) is connected to the second output terminal (OUT2) of the Wilkinson power divider (2), the output terminal of the phase-shifting network (41) is connected to the input terminal of the peak input matching network (42), the output terminal of the peak input matching network (42) is connected to the gate of the power stage peak amplifier (T3), the drain of the power stage peak amplifier (T3) is connected to the input terminal of the peak drain bias network (43), the output terminal of the peak drain bias network (43) is connected to the eighth DC blocking capacitor (C8), the eighth DC blocking capacitor (C8) is connected to the input terminal of the peak impedance transformation network (44), and the fourth output terminal (OUT4) of the peak amplifier circuit (4) is connected to the input terminal of the second patch unit (52) of the dual patch antenna (5).

10. A millimeter-wave Doherty transmitter front-end chip based on harmonic suppression antenna load modulation according to claim 1, characterized in that, The drive stage amplifier (T1) in the drive amplifier circuit (1), the power stage carrier amplifier (T2) in the carrier amplifier circuit (3), and the power stage peak amplifier (T3) in the peak amplifier circuit (4) are all gallium nitride high electron mobility transistors.

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